1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include "hwmgr.h" 25 #include "vega10_hwmgr.h" 26 #include "vega10_powertune.h" 27 #include "vega10_ppsmc.h" 28 #include "vega10_inc.h" 29 #include "pp_debug.h" 30 #include "soc15_common.h" 31 32 static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] = 33 { 34 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 35 * Offset Mask Shift Value 36 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 37 */ 38 /* DIDT_SQ */ 39 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853 }, 40 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153 }, 41 42 /* DIDT_TD */ 43 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde }, 44 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde }, 45 46 /* DIDT_TCP */ 47 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde }, 48 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde }, 49 50 /* DIDT_DB */ 51 { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde }, 52 { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde }, 53 54 { 0xFFFFFFFF } /* End of list */ 55 }; 56 57 static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] = 58 { 59 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 60 * Offset Mask Shift Value 61 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 62 */ 63 /*DIDT_SQ_CTRL3 */ 64 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, 65 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 66 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK, DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, 67 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 68 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, 69 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, 70 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 71 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 72 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, 73 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK, DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, 74 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, 75 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, 76 77 /*DIDT_TCP_CTRL3 */ 78 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, 79 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 80 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK, DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, 81 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 82 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, 83 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, 84 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 85 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 86 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, 87 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, 88 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, 89 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, 90 91 /*DIDT_TD_CTRL3 */ 92 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, 93 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 94 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__THROTTLE_POLICY_MASK, DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, 95 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 96 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, 97 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, 98 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 99 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 100 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, 101 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, 102 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, 103 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, 104 105 /*DIDT_DB_CTRL3 */ 106 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, 107 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 108 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__THROTTLE_POLICY_MASK, DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, 109 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 110 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, 111 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, 112 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 113 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 114 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, 115 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK, DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, 116 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, 117 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, 118 119 { 0xFFFFFFFF } /* End of list */ 120 }; 121 122 static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] = 123 { 124 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 125 * Offset Mask Shift Value 126 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 127 */ 128 /* DIDT_SQ */ 129 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853 }, 130 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, 131 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000 }, 132 133 /* DIDT_TD */ 134 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff }, 135 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, 136 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, 137 138 /* DIDT_TCP */ 139 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde }, 140 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, 141 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, 142 143 /* DIDT_DB */ 144 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK, DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde }, 145 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, 146 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, 147 148 { 0xFFFFFFFF } /* End of list */ 149 }; 150 151 static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] = 152 { 153 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 154 * Offset Mask Shift Value 155 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 156 */ 157 /* DIDT_SQ */ 158 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000 }, 159 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff }, 160 /* DIDT_TD */ 161 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000 }, 162 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff }, 163 /* DIDT_TCP */ 164 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000 }, 165 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff }, 166 /* DIDT_DB */ 167 { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MIN_POWER_MASK, DIDT_DB_CTRL1__MIN_POWER__SHIFT, 0x0000 }, 168 { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MAX_POWER_MASK, DIDT_DB_CTRL1__MAX_POWER__SHIFT, 0xffff }, 169 170 { 0xFFFFFFFF } /* End of list */ 171 }; 172 173 174 static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] = 175 { 176 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 177 * Offset Mask Shift Value 178 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 179 */ 180 /* DIDT_SQ */ 181 { ixDIDT_SQ_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B363B1A }, 182 { ixDIDT_SQ_WEIGHT4_7, 0xFFFFFFFF, 0, 0x270B2432 }, 183 { ixDIDT_SQ_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000018 }, 184 185 /* DIDT_TD */ 186 { ixDIDT_TD_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B1D220F }, 187 { ixDIDT_TD_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00007558 }, 188 { ixDIDT_TD_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 }, 189 190 /* DIDT_TCP */ 191 { ixDIDT_TCP_WEIGHT0_3, 0xFFFFFFFF, 0, 0x5ACE160D }, 192 { ixDIDT_TCP_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00000000 }, 193 { ixDIDT_TCP_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 }, 194 195 /* DIDT_DB */ 196 { ixDIDT_DB_WEIGHT0_3, 0xFFFFFFFF, 0, 0x0E152A0F }, 197 { ixDIDT_DB_WEIGHT4_7, 0xFFFFFFFF, 0, 0x09061813 }, 198 { ixDIDT_DB_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000013 }, 199 200 { 0xFFFFFFFF } /* End of list */ 201 }; 202 203 static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] = 204 { 205 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 206 * Offset Mask Shift Value 207 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 208 */ 209 /* DIDT_SQ */ 210 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 211 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 212 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, 213 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 214 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, 215 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, 216 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, 217 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, 218 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, 219 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, 220 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, 221 /* DIDT_TD */ 222 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 223 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 224 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, 225 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 226 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, 227 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, 228 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, 229 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, 230 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, 231 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, 232 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, 233 /* DIDT_TCP */ 234 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 235 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 236 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, 237 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 238 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, 239 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, 240 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, 241 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, 242 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, 243 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, 244 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, 245 /* DIDT_DB */ 246 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 247 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 248 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, 249 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 250 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, 251 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, 252 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, 253 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, 254 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, 255 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, 256 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, 257 258 { 0xFFFFFFFF } /* End of list */ 259 }; 260 261 262 static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] = 263 { 264 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 265 * Offset Mask Shift Value 266 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 267 */ 268 /* DIDT_SQ */ 269 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 }, 270 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 }, 271 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, 272 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, 273 274 /* DIDT_TD */ 275 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 }, 276 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 }, 277 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, 278 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, 279 280 /* DIDT_TCP */ 281 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 }, 282 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 }, 283 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, 284 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, 285 286 /* DIDT_DB */ 287 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 }, 288 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 }, 289 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, 290 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, 291 292 { 0xFFFFFFFF } /* End of list */ 293 }; 294 295 static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] = 296 { 297 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 298 * Offset Mask Shift Value 299 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 300 */ 301 /* DIDT_SQ_STALL_PATTERN_1_2 */ 302 { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, 303 { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, 304 305 /* DIDT_SQ_STALL_PATTERN_3_4 */ 306 { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, 307 { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, 308 309 /* DIDT_SQ_STALL_PATTERN_5_6 */ 310 { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, 311 { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, 312 313 /* DIDT_SQ_STALL_PATTERN_7 */ 314 { ixDIDT_SQ_STALL_PATTERN_7, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, 315 316 /* DIDT_TCP_STALL_PATTERN_1_2 */ 317 { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, 318 { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, 319 320 /* DIDT_TCP_STALL_PATTERN_3_4 */ 321 { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, 322 { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, 323 324 /* DIDT_TCP_STALL_PATTERN_5_6 */ 325 { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, 326 { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, 327 328 /* DIDT_TCP_STALL_PATTERN_7 */ 329 { ixDIDT_TCP_STALL_PATTERN_7, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, 330 331 /* DIDT_TD_STALL_PATTERN_1_2 */ 332 { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, 333 { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, 334 335 /* DIDT_TD_STALL_PATTERN_3_4 */ 336 { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, 337 { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, 338 339 /* DIDT_TD_STALL_PATTERN_5_6 */ 340 { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, 341 { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, 342 343 /* DIDT_TD_STALL_PATTERN_7 */ 344 { ixDIDT_TD_STALL_PATTERN_7, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, 345 346 /* DIDT_DB_STALL_PATTERN_1_2 */ 347 { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, 348 { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, 349 350 /* DIDT_DB_STALL_PATTERN_3_4 */ 351 { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, 352 { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, 353 354 /* DIDT_DB_STALL_PATTERN_5_6 */ 355 { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, 356 { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, 357 358 /* DIDT_DB_STALL_PATTERN_7 */ 359 { ixDIDT_DB_STALL_PATTERN_7, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, 360 361 { 0xFFFFFFFF } /* End of list */ 362 }; 363 364 static const struct vega10_didt_config_reg SELCacConfig_Vega10[] = 365 { 366 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 367 * Offset Mask Shift Value 368 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 369 */ 370 /* SQ */ 371 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060021 }, 372 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860021 }, 373 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060021 }, 374 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860021 }, 375 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060021 }, 376 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860021 }, 377 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060021 }, 378 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860021 }, 379 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060021 }, 380 /* TD */ 381 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0020 }, 382 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0020 }, 383 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0020 }, 384 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0020 }, 385 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0020 }, 386 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x028E0020 }, 387 /* TCP */ 388 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x001c0020 }, 389 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x009c0020 }, 390 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x011c0020 }, 391 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x019c0020 }, 392 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x021c0020 }, 393 /* DB */ 394 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00200008 }, 395 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00820008 }, 396 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01020008 }, 397 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01820008 }, 398 399 { 0xFFFFFFFF } /* End of list */ 400 }; 401 402 403 static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] = 404 { 405 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 406 * Offset Mask Shift Value 407 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 408 */ 409 /* SQ */ 410 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00030001 }, 411 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x000F0007 }, 412 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x003F001F }, 413 { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x0000007F }, 414 /* TD */ 415 { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 }, 416 { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 417 { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 418 { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 419 /* TCP */ 420 { ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 }, 421 { ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 422 { ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 423 { ixDIDT_TCP_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 424 /* DB */ 425 { ixDIDT_DB_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 }, 426 { ixDIDT_DB_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 427 { ixDIDT_DB_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 428 { ixDIDT_DB_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 429 430 { 0xFFFFFFFF } /* End of list */ 431 }; 432 433 static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] = 434 { 435 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 436 * Offset Mask Shift Value 437 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 438 */ 439 /* SQ */ 440 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 }, 441 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 442 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 443 { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 444 /* TD */ 445 { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 }, 446 { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 447 { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 448 { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 449 450 { 0xFFFFFFFF } /* End of list */ 451 }; 452 453 static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] = 454 { 455 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 456 * Offset Mask Shift Value 457 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 458 */ 459 /* SQ */ 460 { ixDIDT_SQ_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, 461 { ixDIDT_SQ_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 }, 462 { ixDIDT_SQ_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 }, 463 { ixDIDT_SQ_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 }, 464 /* TD */ 465 { ixDIDT_TD_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, 466 { ixDIDT_TD_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 }, 467 { ixDIDT_TD_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 }, 468 { ixDIDT_TD_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 }, 469 /* TCP */ 470 { ixDIDT_TCP_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, 471 { ixDIDT_TCP_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 }, 472 { ixDIDT_TCP_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 }, 473 { ixDIDT_TCP_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 }, 474 /* DB */ 475 { ixDIDT_DB_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, 476 477 { 0xFFFFFFFF } /* End of list */ 478 }; 479 480 static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] = 481 { 482 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 483 * Offset Mask Shift Value 484 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 485 */ 486 { ixDIDT_SQ_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0x0000010E }, 487 { ixDIDT_TD_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF }, 488 { ixDIDT_TCP_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF }, 489 { ixDIDT_DB_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF }, 490 491 { 0xFFFFFFFF } /* End of list */ 492 }; 493 494 static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] = 495 { 496 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 497 * Offset Mask Shift Value 498 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 499 */ 500 /* SQ */ 501 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 502 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, 503 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 504 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 505 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 506 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 }, 507 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 508 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 509 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 510 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 511 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 512 513 { 0xFFFFFFFF } /* End of list */ 514 }; 515 516 static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] = 517 { 518 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 519 * Offset Mask Shift Value 520 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 521 */ 522 /* SQ */ 523 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, 524 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 525 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 526 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 527 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0004 }, 528 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0006 }, 529 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 530 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 531 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 532 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, 533 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 534 535 { 0xFFFFFFFF } /* End of list */ 536 }; 537 538 static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] = 539 { 540 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 541 * Offset Mask Shift Value 542 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 543 */ 544 /* SQ */ 545 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 546 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 547 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 548 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, 549 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 }, 550 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000C }, 551 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 552 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 553 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 554 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 555 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, 556 557 /* TD */ 558 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 559 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 560 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 561 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, 562 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 }, 563 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E }, 564 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 565 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 566 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 567 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 568 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, 569 570 { 0xFFFFFFFF } /* End of list */ 571 }; 572 573 static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] = 574 { 575 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 576 * Offset Mask Shift Value 577 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 578 */ 579 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT, 0x0000 }, 580 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT, 0x0000 }, 581 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT, 0x0000 }, 582 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT, 0x0000 }, 583 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT, 0x0000 }, 584 585 { 0xFFFFFFFF } /* End of list */ 586 }; 587 588 static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] = 589 { 590 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 591 * Offset Mask Shift Value 592 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 593 */ 594 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK, GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 595 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__PHASE_OFFSET_MASK, GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 596 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_SW_RST_MASK, GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT, 0x0000 }, 597 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 598 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 599 { 0xFFFFFFFF } /* End of list */ 600 }; 601 602 603 static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[] = 604 { 605 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 606 * Offset Mask Shift Value 607 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 608 */ 609 /* SQ EDC STALL PATTERNs */ 610 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT, 0x0101 }, 611 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT, 0x0101 }, 612 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT, 0x1111 }, 613 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT, 0x1111 }, 614 615 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT, 0x1515 }, 616 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT, 0x1515 }, 617 618 { ixDIDT_SQ_EDC_STALL_PATTERN_7, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT, 0x5555 }, 619 620 { 0xFFFFFFFF } /* End of list */ 621 }; 622 623 static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] = 624 { 625 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 626 * Offset Mask Shift Value 627 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 628 */ 629 /* SQ EDC STALL DELAYs */ 630 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT, 0x0000 }, 631 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT, 0x0000 }, 632 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT, 0x0000 }, 633 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT, 0x0000 }, 634 635 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT, 0x0000 }, 636 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT, 0x0000 }, 637 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT, 0x0000 }, 638 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT, 0x0000 }, 639 640 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT, 0x0000 }, 641 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT, 0x0000 }, 642 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 }, 643 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 }, 644 645 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 }, 646 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 }, 647 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 }, 648 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 }, 649 650 { 0xFFFFFFFF } /* End of list */ 651 }; 652 653 #if 0 654 static const struct vega10_didt_config_reg PSMSEEDCThresholdConfig_Vega10[] = 655 { 656 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 657 * Offset Mask Shift Value 658 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 659 */ 660 /* SQ EDC THRESHOLD */ 661 { ixDIDT_SQ_EDC_THRESHOLD, DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK, DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT, 0x0000 }, 662 663 { 0xFFFFFFFF } /* End of list */ 664 }; 665 #endif 666 667 static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] = 668 { 669 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 670 * Offset Mask Shift Value 671 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 672 */ 673 /* SQ EDC CTRL */ 674 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 675 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, 676 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 677 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 678 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 679 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 }, 680 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 681 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 682 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 683 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 684 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 685 686 { 0xFFFFFFFF } /* End of list */ 687 }; 688 689 static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] = 690 { 691 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 692 * Offset Mask Shift Value 693 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 694 */ 695 /* SQ EDC CTRL */ 696 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, 697 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 698 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 699 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 700 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 701 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E }, 702 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 703 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0001 }, 704 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0003 }, 705 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, 706 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 707 708 { 0xFFFFFFFF } /* End of list */ 709 }; 710 711 #if 0 712 static const struct vega10_didt_config_reg PSMGCEDCThresholdConfig_vega10[] = 713 { 714 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 715 * Offset Mask Shift Value 716 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 717 */ 718 { mmGC_EDC_THRESHOLD, GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK, GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT, 0x0000000 }, 719 720 { 0xFFFFFFFF } /* End of list */ 721 }; 722 #endif 723 724 static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] = 725 { 726 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 727 * Offset Mask Shift Value 728 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 729 */ 730 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT, 0x0001 }, 731 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT, 0x0384 }, 732 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT, 0x0001 }, 733 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK, GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT, 0x0001 }, 734 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT, 0x0001 }, 735 736 { 0xFFFFFFFF } /* End of list */ 737 }; 738 739 static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] = 740 { 741 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 742 * Offset Mask Shift Value 743 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 744 */ 745 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 746 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, 747 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 748 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 749 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 750 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 751 752 { 0xFFFFFFFF } /* End of list */ 753 }; 754 755 static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] = 756 { 757 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 758 * Offset Mask Shift Value 759 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 760 */ 761 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, 762 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 763 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 764 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 765 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 766 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 767 768 { 0xFFFFFFFF } /* End of list */ 769 }; 770 771 static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[]= 772 { 773 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 774 * Offset Mask Shift Value 775 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 776 */ 777 { 0x16A02, 0xFFFFFFFF, 0x0, 0x0000005F }, 778 { 0x16A05, 0xFFFFFFFF, 0x0, 0x00000001 }, 779 { 0x16A06, 0x00000001, 0x0, 0x02000000 }, 780 { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 }, 781 782 { 0xFFFFFFFF } /* End of list */ 783 }; 784 785 static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] = 786 { 787 /* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 788 * Offset Mask Shift Value 789 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 790 */ 791 { 0x16A05, 0xFFFFFFFF, 0x18, 0x00000001 }, 792 { 0x16A05, 0xFFFFFFFF, 0x8, 0x00000003 }, 793 { 0x16A05, 0xFFFFFFFF, 0xa, 0x00000006 }, 794 { 0x16A05, 0xFFFFFFFF, 0x7, 0x00000000 }, 795 { 0x16A06, 0xFFFFFFFF, 0x18, 0x00000001 }, 796 { 0x16A06, 0xFFFFFFFF, 0x19, 0x00000001 }, 797 { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 }, 798 799 { 0xFFFFFFFF } /* End of list */ 800 }; 801 802 static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type) 803 { 804 uint32_t data; 805 806 PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL); 807 808 while (config_regs->offset != 0xFFFFFFFF) { 809 switch (reg_type) { 810 case VEGA10_CONFIGREG_DIDT: 811 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); 812 data &= ~config_regs->mask; 813 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 814 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data); 815 break; 816 case VEGA10_CONFIGREG_GCCAC: 817 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); 818 data &= ~config_regs->mask; 819 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 820 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data); 821 break; 822 case VEGA10_CONFIGREG_SECAC: 823 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset); 824 data &= ~config_regs->mask; 825 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 826 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data); 827 break; 828 default: 829 return -EINVAL; 830 } 831 832 config_regs++; 833 } 834 835 return 0; 836 } 837 838 static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs) 839 { 840 uint32_t data; 841 842 while (config_regs->offset != 0xFFFFFFFF) { 843 data = cgs_read_register(hwmgr->device, config_regs->offset); 844 data &= ~config_regs->mask; 845 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 846 cgs_write_register(hwmgr->device, config_regs->offset, data); 847 config_regs++; 848 } 849 850 return 0; 851 } 852 853 static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) 854 { 855 uint32_t data; 856 uint32_t en = (enable ? 1 : 0); 857 uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; 858 859 if (PP_CAP(PHM_PlatformCaps_SQRamping)) { 860 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 861 DIDT_SQ_CTRL0, DIDT_CTRL_EN, en); 862 didt_block_info &= ~SQ_Enable_MASK; 863 didt_block_info |= en << SQ_Enable_SHIFT; 864 } 865 866 if (PP_CAP(PHM_PlatformCaps_DBRamping)) { 867 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 868 DIDT_DB_CTRL0, DIDT_CTRL_EN, en); 869 didt_block_info &= ~DB_Enable_MASK; 870 didt_block_info |= en << DB_Enable_SHIFT; 871 } 872 873 if (PP_CAP(PHM_PlatformCaps_TDRamping)) { 874 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 875 DIDT_TD_CTRL0, DIDT_CTRL_EN, en); 876 didt_block_info &= ~TD_Enable_MASK; 877 didt_block_info |= en << TD_Enable_SHIFT; 878 } 879 880 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) { 881 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 882 DIDT_TCP_CTRL0, DIDT_CTRL_EN, en); 883 didt_block_info &= ~TCP_Enable_MASK; 884 didt_block_info |= en << TCP_Enable_SHIFT; 885 } 886 887 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { 888 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 889 DIDT_DBR_CTRL0, DIDT_CTRL_EN, en); 890 } 891 892 if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) { 893 if (PP_CAP(PHM_PlatformCaps_SQRamping)) { 894 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL); 895 data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en); 896 data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en); 897 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data); 898 } 899 900 if (PP_CAP(PHM_PlatformCaps_DBRamping)) { 901 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL); 902 data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en); 903 data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en); 904 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data); 905 } 906 907 if (PP_CAP(PHM_PlatformCaps_TDRamping)) { 908 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL); 909 data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en); 910 data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en); 911 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data); 912 } 913 914 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) { 915 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL); 916 data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en); 917 data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en); 918 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data); 919 } 920 921 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { 922 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL); 923 data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en); 924 data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en); 925 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data); 926 } 927 } 928 929 /* For Vega10, SMC does not support any mask yet. */ 930 if (enable) 931 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); 932 933 } 934 935 static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) 936 { 937 struct amdgpu_device *adev = hwmgr->adev; 938 int result; 939 uint32_t num_se = 0, count, data; 940 941 num_se = adev->gfx.config.max_shader_engines; 942 943 adev->gfx.rlc.funcs->enter_safe_mode(adev); 944 945 mutex_lock(&adev->grbm_idx_mutex); 946 for (count = 0; count < num_se; count++) { 947 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 948 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 949 950 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); 951 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); 952 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT); 953 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT); 954 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT); 955 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT); 956 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); 957 result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC); 958 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT); 959 960 if (0 != result) 961 break; 962 } 963 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 964 mutex_unlock(&adev->grbm_idx_mutex); 965 966 vega10_didt_set_mask(hwmgr, true); 967 968 adev->gfx.rlc.funcs->exit_safe_mode(adev); 969 970 return 0; 971 } 972 973 static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) 974 { 975 struct amdgpu_device *adev = hwmgr->adev; 976 977 adev->gfx.rlc.funcs->enter_safe_mode(adev); 978 979 vega10_didt_set_mask(hwmgr, false); 980 981 adev->gfx.rlc.funcs->exit_safe_mode(adev); 982 983 return 0; 984 } 985 986 static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) 987 { 988 struct amdgpu_device *adev = hwmgr->adev; 989 int result; 990 uint32_t num_se = 0, count, data; 991 992 num_se = adev->gfx.config.max_shader_engines; 993 994 adev->gfx.rlc.funcs->enter_safe_mode(adev); 995 996 mutex_lock(&adev->grbm_idx_mutex); 997 for (count = 0; count < num_se; count++) { 998 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 999 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1000 1001 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); 1002 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); 1003 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT); 1004 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT); 1005 if (0 != result) 1006 break; 1007 } 1008 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1009 mutex_unlock(&adev->grbm_idx_mutex); 1010 1011 vega10_didt_set_mask(hwmgr, true); 1012 1013 adev->gfx.rlc.funcs->exit_safe_mode(adev); 1014 1015 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10); 1016 if (PP_CAP(PHM_PlatformCaps_GCEDC)) 1017 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10); 1018 1019 if (PP_CAP(PHM_PlatformCaps_PSM)) 1020 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10); 1021 1022 return 0; 1023 } 1024 1025 static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) 1026 { 1027 struct amdgpu_device *adev = hwmgr->adev; 1028 uint32_t data; 1029 1030 adev->gfx.rlc.funcs->enter_safe_mode(adev); 1031 1032 vega10_didt_set_mask(hwmgr, false); 1033 1034 adev->gfx.rlc.funcs->exit_safe_mode(adev); 1035 1036 if (PP_CAP(PHM_PlatformCaps_GCEDC)) { 1037 data = 0x00000000; 1038 cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data); 1039 } 1040 1041 if (PP_CAP(PHM_PlatformCaps_PSM)) 1042 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); 1043 1044 return 0; 1045 } 1046 1047 static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) 1048 { 1049 struct amdgpu_device *adev = hwmgr->adev; 1050 int result; 1051 uint32_t num_se = 0, count, data; 1052 1053 num_se = adev->gfx.config.max_shader_engines; 1054 1055 adev->gfx.rlc.funcs->enter_safe_mode(adev); 1056 1057 mutex_lock(&adev->grbm_idx_mutex); 1058 for (count = 0; count < num_se; count++) { 1059 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1060 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1061 result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1062 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1063 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1064 result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1065 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1066 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1067 1068 if (0 != result) 1069 break; 1070 } 1071 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1072 mutex_unlock(&adev->grbm_idx_mutex); 1073 1074 vega10_didt_set_mask(hwmgr, true); 1075 1076 adev->gfx.rlc.funcs->exit_safe_mode(adev); 1077 1078 return 0; 1079 } 1080 1081 static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr) 1082 { 1083 struct amdgpu_device *adev = hwmgr->adev; 1084 1085 adev->gfx.rlc.funcs->enter_safe_mode(adev); 1086 1087 vega10_didt_set_mask(hwmgr, false); 1088 1089 adev->gfx.rlc.funcs->exit_safe_mode(adev); 1090 1091 return 0; 1092 } 1093 1094 static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 1095 { 1096 struct amdgpu_device *adev = hwmgr->adev; 1097 int result = 0; 1098 uint32_t num_se = 0; 1099 uint32_t count, data; 1100 1101 num_se = adev->gfx.config.max_shader_engines; 1102 1103 adev->gfx.rlc.funcs->enter_safe_mode(adev); 1104 1105 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); 1106 1107 mutex_lock(&adev->grbm_idx_mutex); 1108 for (count = 0; count < num_se; count++) { 1109 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1110 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1111 result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1112 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1113 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1114 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1115 1116 if (0 != result) 1117 break; 1118 } 1119 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1120 mutex_unlock(&adev->grbm_idx_mutex); 1121 1122 vega10_didt_set_mask(hwmgr, true); 1123 1124 adev->gfx.rlc.funcs->exit_safe_mode(adev); 1125 1126 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10); 1127 1128 if (PP_CAP(PHM_PlatformCaps_GCEDC)) { 1129 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10); 1130 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10); 1131 } 1132 1133 if (PP_CAP(PHM_PlatformCaps_PSM)) 1134 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10); 1135 1136 return 0; 1137 } 1138 1139 static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 1140 { 1141 struct amdgpu_device *adev = hwmgr->adev; 1142 uint32_t data; 1143 1144 adev->gfx.rlc.funcs->enter_safe_mode(adev); 1145 1146 vega10_didt_set_mask(hwmgr, false); 1147 1148 adev->gfx.rlc.funcs->exit_safe_mode(adev); 1149 1150 if (PP_CAP(PHM_PlatformCaps_GCEDC)) { 1151 data = 0x00000000; 1152 cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data); 1153 } 1154 1155 if (PP_CAP(PHM_PlatformCaps_PSM)) 1156 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); 1157 1158 return 0; 1159 } 1160 1161 static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) 1162 { 1163 struct amdgpu_device *adev = hwmgr->adev; 1164 int result; 1165 1166 adev->gfx.rlc.funcs->enter_safe_mode(adev); 1167 1168 mutex_lock(&adev->grbm_idx_mutex); 1169 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1170 mutex_unlock(&adev->grbm_idx_mutex); 1171 1172 result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1173 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1174 if (0 != result) 1175 return result; 1176 1177 vega10_didt_set_mask(hwmgr, false); 1178 1179 adev->gfx.rlc.funcs->exit_safe_mode(adev); 1180 1181 return 0; 1182 } 1183 1184 static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) 1185 { 1186 int result; 1187 1188 result = vega10_disable_se_edc_config(hwmgr); 1189 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result); 1190 1191 return 0; 1192 } 1193 1194 int vega10_enable_didt_config(struct pp_hwmgr *hwmgr) 1195 { 1196 int result = 0; 1197 struct vega10_hwmgr *data = hwmgr->backend; 1198 1199 if (data->smu_features[GNLD_DIDT].supported) { 1200 if (data->smu_features[GNLD_DIDT].enabled) 1201 PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n"); 1202 1203 switch (data->registry_data.didt_mode) { 1204 case 0: 1205 result = vega10_enable_cac_driving_se_didt_config(hwmgr); 1206 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result); 1207 break; 1208 case 2: 1209 result = vega10_enable_psm_gc_didt_config(hwmgr); 1210 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result); 1211 break; 1212 case 3: 1213 result = vega10_enable_se_edc_config(hwmgr); 1214 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result); 1215 break; 1216 case 1: 1217 case 4: 1218 case 5: 1219 result = vega10_enable_psm_gc_edc_config(hwmgr); 1220 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result); 1221 break; 1222 case 6: 1223 result = vega10_enable_se_edc_force_stall_config(hwmgr); 1224 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result); 1225 break; 1226 default: 1227 result = -EINVAL; 1228 break; 1229 } 1230 1231 if (0 == result) { 1232 result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap); 1233 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result); 1234 data->smu_features[GNLD_DIDT].enabled = true; 1235 } 1236 } 1237 1238 return result; 1239 } 1240 1241 int vega10_disable_didt_config(struct pp_hwmgr *hwmgr) 1242 { 1243 int result = 0; 1244 struct vega10_hwmgr *data = hwmgr->backend; 1245 1246 if (data->smu_features[GNLD_DIDT].supported) { 1247 if (!data->smu_features[GNLD_DIDT].enabled) 1248 PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n"); 1249 1250 switch (data->registry_data.didt_mode) { 1251 case 0: 1252 result = vega10_disable_cac_driving_se_didt_config(hwmgr); 1253 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result); 1254 break; 1255 case 2: 1256 result = vega10_disable_psm_gc_didt_config(hwmgr); 1257 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result); 1258 break; 1259 case 3: 1260 result = vega10_disable_se_edc_config(hwmgr); 1261 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result); 1262 break; 1263 case 1: 1264 case 4: 1265 case 5: 1266 result = vega10_disable_psm_gc_edc_config(hwmgr); 1267 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result); 1268 break; 1269 case 6: 1270 result = vega10_disable_se_edc_force_stall_config(hwmgr); 1271 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result); 1272 break; 1273 default: 1274 result = -EINVAL; 1275 break; 1276 } 1277 1278 if (0 == result) { 1279 result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap); 1280 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result); 1281 data->smu_features[GNLD_DIDT].enabled = false; 1282 } 1283 } 1284 1285 return result; 1286 } 1287 1288 void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 1289 { 1290 struct vega10_hwmgr *data = hwmgr->backend; 1291 struct phm_ppt_v2_information *table_info = 1292 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1293 struct phm_tdp_table *tdp_table = table_info->tdp_table; 1294 PPTable_t *table = &(data->smc_state_table.pp_table); 1295 1296 table->SocketPowerLimit = cpu_to_le16( 1297 tdp_table->usMaximumPowerDeliveryLimit); 1298 table->TdcLimit = cpu_to_le16(tdp_table->usTDC); 1299 table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit); 1300 table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge); 1301 table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot); 1302 table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM); 1303 table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc); 1304 table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd); 1305 table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1); 1306 table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2); 1307 table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx); 1308 table->LoadLineResistance = 1309 hwmgr->platform_descriptor.LoadLineSlope * 256; 1310 table->FitLimit = 0; /* Not used for Vega10 */ 1311 1312 table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address; 1313 table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address; 1314 table->Vr_I2C_address = tdp_table->ucVr_I2C_address; 1315 table->Plx_I2C_address = tdp_table->ucPlx_I2C_address; 1316 1317 table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line; 1318 table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA; 1319 1320 table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line; 1321 table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA; 1322 1323 table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line; 1324 table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA; 1325 } 1326 1327 int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) 1328 { 1329 struct vega10_hwmgr *data = hwmgr->backend; 1330 1331 if (data->registry_data.enable_pkg_pwr_tracking_feature) 1332 smum_send_msg_to_smc_with_parameter(hwmgr, 1333 PPSMC_MSG_SetPptLimit, n); 1334 1335 return 0; 1336 } 1337 1338 int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) 1339 { 1340 struct vega10_hwmgr *data = hwmgr->backend; 1341 struct phm_ppt_v2_information *table_info = 1342 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1343 struct phm_tdp_table *tdp_table = table_info->tdp_table; 1344 int result = 0; 1345 1346 hwmgr->default_power_limit = hwmgr->power_limit = 1347 (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit); 1348 1349 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 1350 if (data->smu_features[GNLD_PPT].supported) 1351 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 1352 true, data->smu_features[GNLD_PPT].smu_feature_bitmap), 1353 "Attempt to enable PPT feature Failed!", 1354 data->smu_features[GNLD_PPT].supported = false); 1355 1356 if (data->smu_features[GNLD_TDC].supported) 1357 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 1358 true, data->smu_features[GNLD_TDC].smu_feature_bitmap), 1359 "Attempt to enable PPT feature Failed!", 1360 data->smu_features[GNLD_TDC].supported = false); 1361 1362 result = vega10_set_power_limit(hwmgr, hwmgr->power_limit); 1363 PP_ASSERT_WITH_CODE(!result, 1364 "Failed to set Default Power Limit in SMC!", 1365 return result); 1366 } 1367 1368 return result; 1369 } 1370 1371 int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) 1372 { 1373 struct vega10_hwmgr *data = hwmgr->backend; 1374 1375 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 1376 if (data->smu_features[GNLD_PPT].supported) 1377 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 1378 false, data->smu_features[GNLD_PPT].smu_feature_bitmap), 1379 "Attempt to disable PPT feature Failed!", 1380 data->smu_features[GNLD_PPT].supported = false); 1381 1382 if (data->smu_features[GNLD_TDC].supported) 1383 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 1384 false, data->smu_features[GNLD_TDC].smu_feature_bitmap), 1385 "Attempt to disable PPT feature Failed!", 1386 data->smu_features[GNLD_TDC].supported = false); 1387 } 1388 1389 return 0; 1390 } 1391 1392 static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, 1393 uint32_t adjust_percent) 1394 { 1395 smum_send_msg_to_smc_with_parameter(hwmgr, 1396 PPSMC_MSG_OverDriveSetPercentage, adjust_percent); 1397 } 1398 1399 int vega10_power_control_set_level(struct pp_hwmgr *hwmgr) 1400 { 1401 int adjust_percent; 1402 1403 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 1404 adjust_percent = 1405 hwmgr->platform_descriptor.TDPAdjustmentPolarity ? 1406 hwmgr->platform_descriptor.TDPAdjustment : 1407 (-1 * hwmgr->platform_descriptor.TDPAdjustment); 1408 vega10_set_overdrive_target_percentage(hwmgr, 1409 (uint32_t)adjust_percent); 1410 } 1411 return 0; 1412 } 1413