1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2017 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef _VEGA12_HWMGR_H_ 25*b843c749SSergey Zigachev #define _VEGA12_HWMGR_H_ 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include "hwmgr.h" 28*b843c749SSergey Zigachev #include "vega12/smu9_driver_if.h" 29*b843c749SSergey Zigachev #include "ppatomfwctrl.h" 30*b843c749SSergey Zigachev 31*b843c749SSergey Zigachev #define VEGA12_MAX_HARDWARE_POWERLEVELS 2 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev #define WaterMarksExist 1 34*b843c749SSergey Zigachev #define WaterMarksLoaded 2 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev #define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS 16 37*b843c749SSergey Zigachev #define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8 38*b843c749SSergey Zigachev #define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8 39*b843c749SSergey Zigachev #define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS 4 40*b843c749SSergey Zigachev 41*b843c749SSergey Zigachev enum 42*b843c749SSergey Zigachev { 43*b843c749SSergey Zigachev GNLD_DPM_PREFETCHER = 0, 44*b843c749SSergey Zigachev GNLD_DPM_GFXCLK, 45*b843c749SSergey Zigachev GNLD_DPM_UCLK, 46*b843c749SSergey Zigachev GNLD_DPM_SOCCLK, 47*b843c749SSergey Zigachev GNLD_DPM_UVD, 48*b843c749SSergey Zigachev GNLD_DPM_VCE, 49*b843c749SSergey Zigachev GNLD_ULV, 50*b843c749SSergey Zigachev GNLD_DPM_MP0CLK, 51*b843c749SSergey Zigachev GNLD_DPM_LINK, 52*b843c749SSergey Zigachev GNLD_DPM_DCEFCLK, 53*b843c749SSergey Zigachev GNLD_DS_GFXCLK, 54*b843c749SSergey Zigachev GNLD_DS_SOCCLK, 55*b843c749SSergey Zigachev GNLD_DS_LCLK, 56*b843c749SSergey Zigachev GNLD_PPT, 57*b843c749SSergey Zigachev GNLD_TDC, 58*b843c749SSergey Zigachev GNLD_THERMAL, 59*b843c749SSergey Zigachev GNLD_GFX_PER_CU_CG, 60*b843c749SSergey Zigachev GNLD_RM, 61*b843c749SSergey Zigachev GNLD_DS_DCEFCLK, 62*b843c749SSergey Zigachev GNLD_ACDC, 63*b843c749SSergey Zigachev GNLD_VR0HOT, 64*b843c749SSergey Zigachev GNLD_VR1HOT, 65*b843c749SSergey Zigachev GNLD_FW_CTF, 66*b843c749SSergey Zigachev GNLD_LED_DISPLAY, 67*b843c749SSergey Zigachev GNLD_FAN_CONTROL, 68*b843c749SSergey Zigachev GNLD_DIDT, 69*b843c749SSergey Zigachev GNLD_GFXOFF, 70*b843c749SSergey Zigachev GNLD_CG, 71*b843c749SSergey Zigachev GNLD_ACG, 72*b843c749SSergey Zigachev 73*b843c749SSergey Zigachev GNLD_FEATURES_MAX 74*b843c749SSergey Zigachev }; 75*b843c749SSergey Zigachev 76*b843c749SSergey Zigachev 77*b843c749SSergey Zigachev #define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1) 78*b843c749SSergey Zigachev 79*b843c749SSergey Zigachev #define SMC_DPM_FEATURES 0x30F 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev struct smu_features { 82*b843c749SSergey Zigachev bool supported; 83*b843c749SSergey Zigachev bool enabled; 84*b843c749SSergey Zigachev bool allowed; 85*b843c749SSergey Zigachev uint32_t smu_feature_id; 86*b843c749SSergey Zigachev uint64_t smu_feature_bitmap; 87*b843c749SSergey Zigachev }; 88*b843c749SSergey Zigachev 89*b843c749SSergey Zigachev struct vega12_dpm_level { 90*b843c749SSergey Zigachev bool enabled; 91*b843c749SSergey Zigachev uint32_t value; 92*b843c749SSergey Zigachev uint32_t param1; 93*b843c749SSergey Zigachev }; 94*b843c749SSergey Zigachev 95*b843c749SSergey Zigachev #define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5 96*b843c749SSergey Zigachev #define MAX_REGULAR_DPM_NUMBER 16 97*b843c749SSergey Zigachev #define MAX_PCIE_CONF 2 98*b843c749SSergey Zigachev #define VEGA12_MINIMUM_ENGINE_CLOCK 2500 99*b843c749SSergey Zigachev 100*b843c749SSergey Zigachev struct vega12_dpm_state { 101*b843c749SSergey Zigachev uint32_t soft_min_level; 102*b843c749SSergey Zigachev uint32_t soft_max_level; 103*b843c749SSergey Zigachev uint32_t hard_min_level; 104*b843c749SSergey Zigachev uint32_t hard_max_level; 105*b843c749SSergey Zigachev }; 106*b843c749SSergey Zigachev 107*b843c749SSergey Zigachev struct vega12_single_dpm_table { 108*b843c749SSergey Zigachev uint32_t count; 109*b843c749SSergey Zigachev struct vega12_dpm_state dpm_state; 110*b843c749SSergey Zigachev struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 111*b843c749SSergey Zigachev }; 112*b843c749SSergey Zigachev 113*b843c749SSergey Zigachev struct vega12_odn_dpm_control { 114*b843c749SSergey Zigachev uint32_t count; 115*b843c749SSergey Zigachev uint32_t entries[MAX_REGULAR_DPM_NUMBER]; 116*b843c749SSergey Zigachev }; 117*b843c749SSergey Zigachev 118*b843c749SSergey Zigachev struct vega12_pcie_table { 119*b843c749SSergey Zigachev uint16_t count; 120*b843c749SSergey Zigachev uint8_t pcie_gen[MAX_PCIE_CONF]; 121*b843c749SSergey Zigachev uint8_t pcie_lane[MAX_PCIE_CONF]; 122*b843c749SSergey Zigachev uint32_t lclk[MAX_PCIE_CONF]; 123*b843c749SSergey Zigachev }; 124*b843c749SSergey Zigachev 125*b843c749SSergey Zigachev struct vega12_dpm_table { 126*b843c749SSergey Zigachev struct vega12_single_dpm_table soc_table; 127*b843c749SSergey Zigachev struct vega12_single_dpm_table gfx_table; 128*b843c749SSergey Zigachev struct vega12_single_dpm_table mem_table; 129*b843c749SSergey Zigachev struct vega12_single_dpm_table eclk_table; 130*b843c749SSergey Zigachev struct vega12_single_dpm_table vclk_table; 131*b843c749SSergey Zigachev struct vega12_single_dpm_table dclk_table; 132*b843c749SSergey Zigachev struct vega12_single_dpm_table dcef_table; 133*b843c749SSergey Zigachev struct vega12_single_dpm_table pixel_table; 134*b843c749SSergey Zigachev struct vega12_single_dpm_table display_table; 135*b843c749SSergey Zigachev struct vega12_single_dpm_table phy_table; 136*b843c749SSergey Zigachev struct vega12_pcie_table pcie_table; 137*b843c749SSergey Zigachev }; 138*b843c749SSergey Zigachev 139*b843c749SSergey Zigachev #define VEGA12_MAX_LEAKAGE_COUNT 8 140*b843c749SSergey Zigachev struct vega12_leakage_voltage { 141*b843c749SSergey Zigachev uint16_t count; 142*b843c749SSergey Zigachev uint16_t leakage_id[VEGA12_MAX_LEAKAGE_COUNT]; 143*b843c749SSergey Zigachev uint16_t actual_voltage[VEGA12_MAX_LEAKAGE_COUNT]; 144*b843c749SSergey Zigachev }; 145*b843c749SSergey Zigachev 146*b843c749SSergey Zigachev struct vega12_display_timing { 147*b843c749SSergey Zigachev uint32_t min_clock_in_sr; 148*b843c749SSergey Zigachev uint32_t num_existing_displays; 149*b843c749SSergey Zigachev }; 150*b843c749SSergey Zigachev 151*b843c749SSergey Zigachev struct vega12_dpmlevel_enable_mask { 152*b843c749SSergey Zigachev uint32_t uvd_dpm_enable_mask; 153*b843c749SSergey Zigachev uint32_t vce_dpm_enable_mask; 154*b843c749SSergey Zigachev uint32_t samu_dpm_enable_mask; 155*b843c749SSergey Zigachev uint32_t sclk_dpm_enable_mask; 156*b843c749SSergey Zigachev uint32_t mclk_dpm_enable_mask; 157*b843c749SSergey Zigachev }; 158*b843c749SSergey Zigachev 159*b843c749SSergey Zigachev struct vega12_vbios_boot_state { 160*b843c749SSergey Zigachev bool bsoc_vddc_lock; 161*b843c749SSergey Zigachev uint8_t uc_cooling_id; 162*b843c749SSergey Zigachev uint16_t vddc; 163*b843c749SSergey Zigachev uint16_t vddci; 164*b843c749SSergey Zigachev uint16_t mvddc; 165*b843c749SSergey Zigachev uint16_t vdd_gfx; 166*b843c749SSergey Zigachev uint32_t gfx_clock; 167*b843c749SSergey Zigachev uint32_t mem_clock; 168*b843c749SSergey Zigachev uint32_t soc_clock; 169*b843c749SSergey Zigachev uint32_t dcef_clock; 170*b843c749SSergey Zigachev uint32_t eclock; 171*b843c749SSergey Zigachev uint32_t dclock; 172*b843c749SSergey Zigachev uint32_t vclock; 173*b843c749SSergey Zigachev }; 174*b843c749SSergey Zigachev 175*b843c749SSergey Zigachev #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 176*b843c749SSergey Zigachev #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 177*b843c749SSergey Zigachev #define DPMTABLE_UPDATE_SCLK 0x00000004 178*b843c749SSergey Zigachev #define DPMTABLE_UPDATE_MCLK 0x00000008 179*b843c749SSergey Zigachev #define DPMTABLE_OD_UPDATE_VDDC 0x00000010 180*b843c749SSergey Zigachev 181*b843c749SSergey Zigachev struct vega12_smc_state_table { 182*b843c749SSergey Zigachev uint32_t soc_boot_level; 183*b843c749SSergey Zigachev uint32_t gfx_boot_level; 184*b843c749SSergey Zigachev uint32_t dcef_boot_level; 185*b843c749SSergey Zigachev uint32_t mem_boot_level; 186*b843c749SSergey Zigachev uint32_t uvd_boot_level; 187*b843c749SSergey Zigachev uint32_t vce_boot_level; 188*b843c749SSergey Zigachev uint32_t gfx_max_level; 189*b843c749SSergey Zigachev uint32_t mem_max_level; 190*b843c749SSergey Zigachev uint8_t vr_hot_gpio; 191*b843c749SSergey Zigachev uint8_t ac_dc_gpio; 192*b843c749SSergey Zigachev uint8_t therm_out_gpio; 193*b843c749SSergey Zigachev uint8_t therm_out_polarity; 194*b843c749SSergey Zigachev uint8_t therm_out_mode; 195*b843c749SSergey Zigachev PPTable_t pp_table; 196*b843c749SSergey Zigachev Watermarks_t water_marks_table; 197*b843c749SSergey Zigachev AvfsDebugTable_t avfs_debug_table; 198*b843c749SSergey Zigachev AvfsFuseOverride_t avfs_fuse_override_table; 199*b843c749SSergey Zigachev SmuMetrics_t smu_metrics; 200*b843c749SSergey Zigachev DriverSmuConfig_t driver_smu_config; 201*b843c749SSergey Zigachev DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint; 202*b843c749SSergey Zigachev OverDriveTable_t overdrive_table; 203*b843c749SSergey Zigachev }; 204*b843c749SSergey Zigachev 205*b843c749SSergey Zigachev struct vega12_mclk_latency_entries { 206*b843c749SSergey Zigachev uint32_t frequency; 207*b843c749SSergey Zigachev uint32_t latency; 208*b843c749SSergey Zigachev }; 209*b843c749SSergey Zigachev 210*b843c749SSergey Zigachev struct vega12_mclk_latency_table { 211*b843c749SSergey Zigachev uint32_t count; 212*b843c749SSergey Zigachev struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 213*b843c749SSergey Zigachev }; 214*b843c749SSergey Zigachev 215*b843c749SSergey Zigachev struct vega12_registry_data { 216*b843c749SSergey Zigachev uint64_t disallowed_features; 217*b843c749SSergey Zigachev uint8_t ac_dc_switch_gpio_support; 218*b843c749SSergey Zigachev uint8_t acg_loop_support; 219*b843c749SSergey Zigachev uint8_t clock_stretcher_support; 220*b843c749SSergey Zigachev uint8_t db_ramping_support; 221*b843c749SSergey Zigachev uint8_t didt_mode; 222*b843c749SSergey Zigachev uint8_t didt_support; 223*b843c749SSergey Zigachev uint8_t edc_didt_support; 224*b843c749SSergey Zigachev uint8_t force_dpm_high; 225*b843c749SSergey Zigachev uint8_t fuzzy_fan_control_support; 226*b843c749SSergey Zigachev uint8_t mclk_dpm_key_disabled; 227*b843c749SSergey Zigachev uint8_t od_state_in_dc_support; 228*b843c749SSergey Zigachev uint8_t pcie_lane_override; 229*b843c749SSergey Zigachev uint8_t pcie_speed_override; 230*b843c749SSergey Zigachev uint32_t pcie_clock_override; 231*b843c749SSergey Zigachev uint8_t pcie_dpm_key_disabled; 232*b843c749SSergey Zigachev uint8_t dcefclk_dpm_key_disabled; 233*b843c749SSergey Zigachev uint8_t prefetcher_dpm_key_disabled; 234*b843c749SSergey Zigachev uint8_t quick_transition_support; 235*b843c749SSergey Zigachev uint8_t regulator_hot_gpio_support; 236*b843c749SSergey Zigachev uint8_t master_deep_sleep_support; 237*b843c749SSergey Zigachev uint8_t gfx_clk_deep_sleep_support; 238*b843c749SSergey Zigachev uint8_t sclk_deep_sleep_support; 239*b843c749SSergey Zigachev uint8_t lclk_deep_sleep_support; 240*b843c749SSergey Zigachev uint8_t dce_fclk_deep_sleep_support; 241*b843c749SSergey Zigachev uint8_t sclk_dpm_key_disabled; 242*b843c749SSergey Zigachev uint8_t sclk_throttle_low_notification; 243*b843c749SSergey Zigachev uint8_t skip_baco_hardware; 244*b843c749SSergey Zigachev uint8_t socclk_dpm_key_disabled; 245*b843c749SSergey Zigachev uint8_t sq_ramping_support; 246*b843c749SSergey Zigachev uint8_t tcp_ramping_support; 247*b843c749SSergey Zigachev uint8_t td_ramping_support; 248*b843c749SSergey Zigachev uint8_t dbr_ramping_support; 249*b843c749SSergey Zigachev uint8_t gc_didt_support; 250*b843c749SSergey Zigachev uint8_t psm_didt_support; 251*b843c749SSergey Zigachev uint8_t thermal_support; 252*b843c749SSergey Zigachev uint8_t fw_ctf_enabled; 253*b843c749SSergey Zigachev uint8_t led_dpm_enabled; 254*b843c749SSergey Zigachev uint8_t fan_control_support; 255*b843c749SSergey Zigachev uint8_t ulv_support; 256*b843c749SSergey Zigachev uint8_t odn_feature_enable; 257*b843c749SSergey Zigachev uint8_t disable_water_mark; 258*b843c749SSergey Zigachev uint8_t disable_workload_policy; 259*b843c749SSergey Zigachev uint32_t force_workload_policy_mask; 260*b843c749SSergey Zigachev uint8_t disable_3d_fs_detection; 261*b843c749SSergey Zigachev uint8_t disable_pp_tuning; 262*b843c749SSergey Zigachev uint8_t disable_xlpp_tuning; 263*b843c749SSergey Zigachev uint32_t perf_ui_tuning_profile_turbo; 264*b843c749SSergey Zigachev uint32_t perf_ui_tuning_profile_powerSave; 265*b843c749SSergey Zigachev uint32_t perf_ui_tuning_profile_xl; 266*b843c749SSergey Zigachev uint16_t zrpm_stop_temp; 267*b843c749SSergey Zigachev uint16_t zrpm_start_temp; 268*b843c749SSergey Zigachev uint32_t stable_pstate_sclk_dpm_percentage; 269*b843c749SSergey Zigachev uint8_t fps_support; 270*b843c749SSergey Zigachev uint8_t vr0hot; 271*b843c749SSergey Zigachev uint8_t vr1hot; 272*b843c749SSergey Zigachev uint8_t disable_auto_wattman; 273*b843c749SSergey Zigachev uint32_t auto_wattman_debug; 274*b843c749SSergey Zigachev uint32_t auto_wattman_sample_period; 275*b843c749SSergey Zigachev uint8_t auto_wattman_threshold; 276*b843c749SSergey Zigachev uint8_t log_avfs_param; 277*b843c749SSergey Zigachev uint8_t enable_enginess; 278*b843c749SSergey Zigachev uint8_t custom_fan_support; 279*b843c749SSergey Zigachev uint8_t disable_pcc_limit_control; 280*b843c749SSergey Zigachev }; 281*b843c749SSergey Zigachev 282*b843c749SSergey Zigachev struct vega12_odn_clock_voltage_dependency_table { 283*b843c749SSergey Zigachev uint32_t count; 284*b843c749SSergey Zigachev struct phm_ppt_v1_clock_voltage_dependency_record 285*b843c749SSergey Zigachev entries[MAX_REGULAR_DPM_NUMBER]; 286*b843c749SSergey Zigachev }; 287*b843c749SSergey Zigachev 288*b843c749SSergey Zigachev struct vega12_odn_dpm_table { 289*b843c749SSergey Zigachev struct vega12_odn_dpm_control control_gfxclk_state; 290*b843c749SSergey Zigachev struct vega12_odn_dpm_control control_memclk_state; 291*b843c749SSergey Zigachev struct phm_odn_clock_levels odn_core_clock_dpm_levels; 292*b843c749SSergey Zigachev struct phm_odn_clock_levels odn_memory_clock_dpm_levels; 293*b843c749SSergey Zigachev struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_sclk; 294*b843c749SSergey Zigachev struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_mclk; 295*b843c749SSergey Zigachev struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_socclk; 296*b843c749SSergey Zigachev uint32_t odn_mclk_min_limit; 297*b843c749SSergey Zigachev }; 298*b843c749SSergey Zigachev 299*b843c749SSergey Zigachev struct vega12_odn_fan_table { 300*b843c749SSergey Zigachev uint32_t target_fan_speed; 301*b843c749SSergey Zigachev uint32_t target_temperature; 302*b843c749SSergey Zigachev uint32_t min_performance_clock; 303*b843c749SSergey Zigachev uint32_t min_fan_limit; 304*b843c749SSergey Zigachev bool force_fan_pwm; 305*b843c749SSergey Zigachev }; 306*b843c749SSergey Zigachev 307*b843c749SSergey Zigachev struct vega12_clock_range { 308*b843c749SSergey Zigachev uint32_t ACMax; 309*b843c749SSergey Zigachev uint32_t ACMin; 310*b843c749SSergey Zigachev uint32_t DCMax; 311*b843c749SSergey Zigachev }; 312*b843c749SSergey Zigachev 313*b843c749SSergey Zigachev struct vega12_hwmgr { 314*b843c749SSergey Zigachev struct vega12_dpm_table dpm_table; 315*b843c749SSergey Zigachev struct vega12_dpm_table golden_dpm_table; 316*b843c749SSergey Zigachev struct vega12_registry_data registry_data; 317*b843c749SSergey Zigachev struct vega12_vbios_boot_state vbios_boot_state; 318*b843c749SSergey Zigachev struct vega12_mclk_latency_table mclk_latency_table; 319*b843c749SSergey Zigachev 320*b843c749SSergey Zigachev struct vega12_leakage_voltage vddc_leakage; 321*b843c749SSergey Zigachev 322*b843c749SSergey Zigachev uint32_t vddc_control; 323*b843c749SSergey Zigachev struct pp_atomfwctrl_voltage_table vddc_voltage_table; 324*b843c749SSergey Zigachev uint32_t mvdd_control; 325*b843c749SSergey Zigachev struct pp_atomfwctrl_voltage_table mvdd_voltage_table; 326*b843c749SSergey Zigachev uint32_t vddci_control; 327*b843c749SSergey Zigachev struct pp_atomfwctrl_voltage_table vddci_voltage_table; 328*b843c749SSergey Zigachev 329*b843c749SSergey Zigachev uint32_t active_auto_throttle_sources; 330*b843c749SSergey Zigachev uint32_t water_marks_bitmap; 331*b843c749SSergey Zigachev 332*b843c749SSergey Zigachev struct vega12_odn_dpm_table odn_dpm_table; 333*b843c749SSergey Zigachev struct vega12_odn_fan_table odn_fan_table; 334*b843c749SSergey Zigachev 335*b843c749SSergey Zigachev /* ---- General data ---- */ 336*b843c749SSergey Zigachev uint8_t need_update_dpm_table; 337*b843c749SSergey Zigachev 338*b843c749SSergey Zigachev bool cac_enabled; 339*b843c749SSergey Zigachev bool battery_state; 340*b843c749SSergey Zigachev bool is_tlu_enabled; 341*b843c749SSergey Zigachev bool avfs_exist; 342*b843c749SSergey Zigachev 343*b843c749SSergey Zigachev uint32_t low_sclk_interrupt_threshold; 344*b843c749SSergey Zigachev 345*b843c749SSergey Zigachev uint32_t total_active_cus; 346*b843c749SSergey Zigachev 347*b843c749SSergey Zigachev struct vega12_display_timing display_timing; 348*b843c749SSergey Zigachev 349*b843c749SSergey Zigachev /* ---- Vega12 Dyn Register Settings ---- */ 350*b843c749SSergey Zigachev 351*b843c749SSergey Zigachev uint32_t debug_settings; 352*b843c749SSergey Zigachev uint32_t lowest_uclk_reserved_for_ulv; 353*b843c749SSergey Zigachev uint32_t gfxclk_average_alpha; 354*b843c749SSergey Zigachev uint32_t socclk_average_alpha; 355*b843c749SSergey Zigachev uint32_t uclk_average_alpha; 356*b843c749SSergey Zigachev uint32_t gfx_activity_average_alpha; 357*b843c749SSergey Zigachev uint32_t display_voltage_mode; 358*b843c749SSergey Zigachev uint32_t dcef_clk_quad_eqn_a; 359*b843c749SSergey Zigachev uint32_t dcef_clk_quad_eqn_b; 360*b843c749SSergey Zigachev uint32_t dcef_clk_quad_eqn_c; 361*b843c749SSergey Zigachev uint32_t disp_clk_quad_eqn_a; 362*b843c749SSergey Zigachev uint32_t disp_clk_quad_eqn_b; 363*b843c749SSergey Zigachev uint32_t disp_clk_quad_eqn_c; 364*b843c749SSergey Zigachev uint32_t pixel_clk_quad_eqn_a; 365*b843c749SSergey Zigachev uint32_t pixel_clk_quad_eqn_b; 366*b843c749SSergey Zigachev uint32_t pixel_clk_quad_eqn_c; 367*b843c749SSergey Zigachev uint32_t phy_clk_quad_eqn_a; 368*b843c749SSergey Zigachev uint32_t phy_clk_quad_eqn_b; 369*b843c749SSergey Zigachev uint32_t phy_clk_quad_eqn_c; 370*b843c749SSergey Zigachev 371*b843c749SSergey Zigachev /* ---- Thermal Temperature Setting ---- */ 372*b843c749SSergey Zigachev struct vega12_dpmlevel_enable_mask dpm_level_enable_mask; 373*b843c749SSergey Zigachev 374*b843c749SSergey Zigachev /* ---- Power Gating States ---- */ 375*b843c749SSergey Zigachev bool uvd_power_gated; 376*b843c749SSergey Zigachev bool vce_power_gated; 377*b843c749SSergey Zigachev bool samu_power_gated; 378*b843c749SSergey Zigachev bool need_long_memory_training; 379*b843c749SSergey Zigachev 380*b843c749SSergey Zigachev /* Internal settings to apply the application power optimization parameters */ 381*b843c749SSergey Zigachev bool apply_optimized_settings; 382*b843c749SSergey Zigachev uint32_t disable_dpm_mask; 383*b843c749SSergey Zigachev 384*b843c749SSergey Zigachev /* ---- Overdrive next setting ---- */ 385*b843c749SSergey Zigachev uint32_t apply_overdrive_next_settings_mask; 386*b843c749SSergey Zigachev 387*b843c749SSergey Zigachev /* ---- Workload Mask ---- */ 388*b843c749SSergey Zigachev uint32_t workload_mask; 389*b843c749SSergey Zigachev 390*b843c749SSergey Zigachev /* ---- SMU9 ---- */ 391*b843c749SSergey Zigachev uint32_t smu_version; 392*b843c749SSergey Zigachev struct smu_features smu_features[GNLD_FEATURES_MAX]; 393*b843c749SSergey Zigachev struct vega12_smc_state_table smc_state_table; 394*b843c749SSergey Zigachev 395*b843c749SSergey Zigachev struct vega12_clock_range clk_range[PPCLK_COUNT]; 396*b843c749SSergey Zigachev 397*b843c749SSergey Zigachev /* ---- Gfxoff ---- */ 398*b843c749SSergey Zigachev bool gfxoff_controlled_by_driver; 399*b843c749SSergey Zigachev }; 400*b843c749SSergey Zigachev 401*b843c749SSergey Zigachev #define VEGA12_DPM2_NEAR_TDP_DEC 10 402*b843c749SSergey Zigachev #define VEGA12_DPM2_ABOVE_SAFE_INC 5 403*b843c749SSergey Zigachev #define VEGA12_DPM2_BELOW_SAFE_INC 20 404*b843c749SSergey Zigachev 405*b843c749SSergey Zigachev #define VEGA12_DPM2_LTA_WINDOW_SIZE 7 406*b843c749SSergey Zigachev 407*b843c749SSergey Zigachev #define VEGA12_DPM2_LTS_TRUNCATE 0 408*b843c749SSergey Zigachev 409*b843c749SSergey Zigachev #define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT 80 410*b843c749SSergey Zigachev 411*b843c749SSergey Zigachev #define VEGA12_DPM2_MAXPS_PERCENT_M 90 412*b843c749SSergey Zigachev #define VEGA12_DPM2_MAXPS_PERCENT_H 90 413*b843c749SSergey Zigachev 414*b843c749SSergey Zigachev #define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN 50 415*b843c749SSergey Zigachev 416*b843c749SSergey Zigachev #define VEGA12_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 417*b843c749SSergey Zigachev #define VEGA12_DPM2_SQ_RAMP_MIN_POWER 0x12 418*b843c749SSergey Zigachev #define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 419*b843c749SSergey Zigachev #define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E 420*b843c749SSergey Zigachev #define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF 421*b843c749SSergey Zigachev 422*b843c749SSergey Zigachev #define VEGA12_VOLTAGE_CONTROL_NONE 0x0 423*b843c749SSergey Zigachev #define VEGA12_VOLTAGE_CONTROL_BY_GPIO 0x1 424*b843c749SSergey Zigachev #define VEGA12_VOLTAGE_CONTROL_BY_SVID2 0x2 425*b843c749SSergey Zigachev #define VEGA12_VOLTAGE_CONTROL_MERGED 0x3 426*b843c749SSergey Zigachev /* To convert to Q8.8 format for firmware */ 427*b843c749SSergey Zigachev #define VEGA12_Q88_FORMAT_CONVERSION_UNIT 256 428*b843c749SSergey Zigachev 429*b843c749SSergey Zigachev #define VEGA12_UNUSED_GPIO_PIN 0x7F 430*b843c749SSergey Zigachev 431*b843c749SSergey Zigachev #define VEGA12_THERM_OUT_MODE_DISABLE 0x0 432*b843c749SSergey Zigachev #define VEGA12_THERM_OUT_MODE_THERM_ONLY 0x1 433*b843c749SSergey Zigachev #define VEGA12_THERM_OUT_MODE_THERM_VRHOT 0x2 434*b843c749SSergey Zigachev 435*b843c749SSergey Zigachev #define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff 436*b843c749SSergey Zigachev #define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff 437*b843c749SSergey Zigachev 438*b843c749SSergey Zigachev #define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 439*b843c749SSergey Zigachev #define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 440*b843c749SSergey Zigachev #define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 441*b843c749SSergey Zigachev #define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 442*b843c749SSergey Zigachev #define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT 0xffffffff 443*b843c749SSergey Zigachev #define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff 444*b843c749SSergey Zigachev #define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff 445*b843c749SSergey Zigachev 446*b843c749SSergey Zigachev #define VEGA12_UMD_PSTATE_GFXCLK_LEVEL 0x3 447*b843c749SSergey Zigachev #define VEGA12_UMD_PSTATE_SOCCLK_LEVEL 0x3 448*b843c749SSergey Zigachev #define VEGA12_UMD_PSTATE_MCLK_LEVEL 0x2 449*b843c749SSergey Zigachev #define VEGA12_UMD_PSTATE_UVDCLK_LEVEL 0x3 450*b843c749SSergey Zigachev #define VEGA12_UMD_PSTATE_VCEMCLK_LEVEL 0x3 451*b843c749SSergey Zigachev 452*b843c749SSergey Zigachev int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); 453*b843c749SSergey Zigachev 454*b843c749SSergey Zigachev #endif /* _VEGA12_HWMGR_H_ */ 455