1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/fb.h> 26 27 #include "vega12/smu9_driver_if.h" 28 #include "vega12_processpptables.h" 29 #include "ppatomfwctrl.h" 30 #include "atomfirmware.h" 31 #include "pp_debug.h" 32 #include "cgs_common.h" 33 #include "vega12_pptable.h" 34 35 static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable, 36 enum phm_platform_caps cap) 37 { 38 if (enable) 39 phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap); 40 else 41 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap); 42 } 43 44 static const void *get_powerplay_table(struct pp_hwmgr *hwmgr) 45 { 46 int index = GetIndexIntoMasterDataTable(powerplayinfo); 47 48 u16 size; 49 u8 frev, crev; 50 const void *table_address = hwmgr->soft_pp_table; 51 52 if (!table_address) { 53 table_address = (ATOM_Vega12_POWERPLAYTABLE *) 54 smu_atom_get_data_table(hwmgr->adev, index, 55 &size, &frev, &crev); 56 57 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ 58 hwmgr->soft_pp_table_size = size; 59 } 60 61 return table_address; 62 } 63 64 static int check_powerplay_tables( 65 struct pp_hwmgr *hwmgr, 66 const ATOM_Vega12_POWERPLAYTABLE *powerplay_table) 67 { 68 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >= 69 ATOM_VEGA12_TABLE_REVISION_VEGA12), 70 "Unsupported PPTable format!", return -1); 71 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0, 72 "Invalid PowerPlay Table!", return -1); 73 74 return 0; 75 } 76 77 static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps) 78 { 79 set_hw_cap( 80 hwmgr, 81 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_POWERPLAY), 82 PHM_PlatformCaps_PowerPlaySupport); 83 84 set_hw_cap( 85 hwmgr, 86 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_SBIOSPOWERSOURCE), 87 PHM_PlatformCaps_BiosPowerSourceControl); 88 89 set_hw_cap( 90 hwmgr, 91 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BACO), 92 PHM_PlatformCaps_BACO); 93 94 set_hw_cap( 95 hwmgr, 96 0 != (powerplay_caps & ATOM_VEGA12_PP_PLATFORM_CAP_BAMACO), 97 PHM_PlatformCaps_BAMACO); 98 99 return 0; 100 } 101 102 static int copy_clock_limits_array( 103 struct pp_hwmgr *hwmgr, 104 uint32_t **pptable_info_array, 105 const uint32_t *pptable_array) 106 { 107 uint32_t array_size, i; 108 uint32_t *table; 109 110 array_size = sizeof(uint32_t) * ATOM_VEGA12_PPCLOCK_COUNT; 111 112 table = kzalloc(array_size, GFP_KERNEL); 113 if (NULL == table) 114 return -ENOMEM; 115 116 for (i = 0; i < ATOM_VEGA12_PPCLOCK_COUNT; i++) 117 table[i] = pptable_array[i]; 118 119 *pptable_info_array = table; 120 121 return 0; 122 } 123 124 static int copy_overdrive_settings_limits_array( 125 struct pp_hwmgr *hwmgr, 126 uint32_t **pptable_info_array, 127 const uint32_t *pptable_array) 128 { 129 uint32_t array_size, i; 130 uint32_t *table; 131 132 array_size = sizeof(uint32_t) * ATOM_VEGA12_ODSETTING_COUNT; 133 134 table = kzalloc(array_size, GFP_KERNEL); 135 if (NULL == table) 136 return -ENOMEM; 137 138 for (i = 0; i < ATOM_VEGA12_ODSETTING_COUNT; i++) 139 table[i] = pptable_array[i]; 140 141 *pptable_info_array = table; 142 143 return 0; 144 } 145 146 static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable) 147 { 148 struct pp_atomfwctrl_smc_dpm_parameters smc_dpm_table; 149 150 PP_ASSERT_WITH_CODE( 151 pp_atomfwctrl_get_smc_dpm_information(hwmgr, &smc_dpm_table) == 0, 152 "[appendVbiosPPTable] Failed to retrieve Smc Dpm Table from VBIOS!", 153 return -1); 154 155 ppsmc_pptable->Liquid1_I2C_address = smc_dpm_table.liquid1_i2c_address; 156 ppsmc_pptable->Liquid2_I2C_address = smc_dpm_table.liquid2_i2c_address; 157 ppsmc_pptable->Vr_I2C_address = smc_dpm_table.vr_i2c_address; 158 ppsmc_pptable->Plx_I2C_address = smc_dpm_table.plx_i2c_address; 159 160 ppsmc_pptable->Liquid_I2C_LineSCL = smc_dpm_table.liquid_i2c_linescl; 161 ppsmc_pptable->Liquid_I2C_LineSDA = smc_dpm_table.liquid_i2c_linesda; 162 ppsmc_pptable->Vr_I2C_LineSCL = smc_dpm_table.vr_i2c_linescl; 163 ppsmc_pptable->Vr_I2C_LineSDA = smc_dpm_table.vr_i2c_linesda; 164 165 ppsmc_pptable->Plx_I2C_LineSCL = smc_dpm_table.plx_i2c_linescl; 166 ppsmc_pptable->Plx_I2C_LineSDA = smc_dpm_table.plx_i2c_linesda; 167 ppsmc_pptable->VrSensorPresent = smc_dpm_table.vrsensorpresent; 168 ppsmc_pptable->LiquidSensorPresent = smc_dpm_table.liquidsensorpresent; 169 170 ppsmc_pptable->MaxVoltageStepGfx = smc_dpm_table.maxvoltagestepgfx; 171 ppsmc_pptable->MaxVoltageStepSoc = smc_dpm_table.maxvoltagestepsoc; 172 173 ppsmc_pptable->VddGfxVrMapping = smc_dpm_table.vddgfxvrmapping; 174 ppsmc_pptable->VddSocVrMapping = smc_dpm_table.vddsocvrmapping; 175 ppsmc_pptable->VddMem0VrMapping = smc_dpm_table.vddmem0vrmapping; 176 ppsmc_pptable->VddMem1VrMapping = smc_dpm_table.vddmem1vrmapping; 177 178 ppsmc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table.gfxulvphasesheddingmask; 179 ppsmc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table.soculvphasesheddingmask; 180 181 ppsmc_pptable->GfxMaxCurrent = smc_dpm_table.gfxmaxcurrent; 182 ppsmc_pptable->GfxOffset = smc_dpm_table.gfxoffset; 183 ppsmc_pptable->Padding_TelemetryGfx = smc_dpm_table.padding_telemetrygfx; 184 185 ppsmc_pptable->SocMaxCurrent = smc_dpm_table.socmaxcurrent; 186 ppsmc_pptable->SocOffset = smc_dpm_table.socoffset; 187 ppsmc_pptable->Padding_TelemetrySoc = smc_dpm_table.padding_telemetrysoc; 188 189 ppsmc_pptable->Mem0MaxCurrent = smc_dpm_table.mem0maxcurrent; 190 ppsmc_pptable->Mem0Offset = smc_dpm_table.mem0offset; 191 ppsmc_pptable->Padding_TelemetryMem0 = smc_dpm_table.padding_telemetrymem0; 192 193 ppsmc_pptable->Mem1MaxCurrent = smc_dpm_table.mem1maxcurrent; 194 ppsmc_pptable->Mem1Offset = smc_dpm_table.mem1offset; 195 ppsmc_pptable->Padding_TelemetryMem1 = smc_dpm_table.padding_telemetrymem1; 196 197 ppsmc_pptable->AcDcGpio = smc_dpm_table.acdcgpio; 198 ppsmc_pptable->AcDcPolarity = smc_dpm_table.acdcpolarity; 199 ppsmc_pptable->VR0HotGpio = smc_dpm_table.vr0hotgpio; 200 ppsmc_pptable->VR0HotPolarity = smc_dpm_table.vr0hotpolarity; 201 202 ppsmc_pptable->VR1HotGpio = smc_dpm_table.vr1hotgpio; 203 ppsmc_pptable->VR1HotPolarity = smc_dpm_table.vr1hotpolarity; 204 ppsmc_pptable->Padding1 = smc_dpm_table.padding1; 205 ppsmc_pptable->Padding2 = smc_dpm_table.padding2; 206 207 ppsmc_pptable->LedPin0 = smc_dpm_table.ledpin0; 208 ppsmc_pptable->LedPin1 = smc_dpm_table.ledpin1; 209 ppsmc_pptable->LedPin2 = smc_dpm_table.ledpin2; 210 211 ppsmc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table.pllgfxclkspreadenabled; 212 ppsmc_pptable->PllGfxclkSpreadPercent = smc_dpm_table.pllgfxclkspreadpercent; 213 ppsmc_pptable->PllGfxclkSpreadFreq = smc_dpm_table.pllgfxclkspreadfreq; 214 215 ppsmc_pptable->UclkSpreadEnabled = 0; 216 ppsmc_pptable->UclkSpreadPercent = smc_dpm_table.uclkspreadpercent; 217 ppsmc_pptable->UclkSpreadFreq = smc_dpm_table.uclkspreadfreq; 218 219 ppsmc_pptable->SocclkSpreadEnabled = 0; 220 ppsmc_pptable->SocclkSpreadPercent = smc_dpm_table.socclkspreadpercent; 221 ppsmc_pptable->SocclkSpreadFreq = smc_dpm_table.socclkspreadfreq; 222 223 ppsmc_pptable->AcgGfxclkSpreadEnabled = smc_dpm_table.acggfxclkspreadenabled; 224 ppsmc_pptable->AcgGfxclkSpreadPercent = smc_dpm_table.acggfxclkspreadpercent; 225 ppsmc_pptable->AcgGfxclkSpreadFreq = smc_dpm_table.acggfxclkspreadfreq; 226 227 ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address; 228 229 ppsmc_pptable->Vr2_I2C_address = smc_dpm_table.Vr2_I2C_address; 230 231 return 0; 232 } 233 234 #define VEGA12_ENGINECLOCK_HARDMAX 198000 235 static int init_powerplay_table_information( 236 struct pp_hwmgr *hwmgr, 237 const ATOM_Vega12_POWERPLAYTABLE *powerplay_table) 238 { 239 struct phm_ppt_v3_information *pptable_information = 240 (struct phm_ppt_v3_information *)hwmgr->pptable; 241 uint32_t disable_power_control = 0; 242 int result; 243 244 hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType; 245 pptable_information->uc_thermal_controller_type = powerplay_table->ucThermalControllerType; 246 247 set_hw_cap(hwmgr, 248 ATOM_VEGA12_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType, 249 PHM_PlatformCaps_ThermalController); 250 251 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl); 252 253 if (powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX] > VEGA12_ENGINECLOCK_HARDMAX) 254 hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX; 255 else 256 hwmgr->platform_descriptor.overdriveLimit.engineClock = powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_GFXCLKFMAX]; 257 hwmgr->platform_descriptor.overdriveLimit.memoryClock = powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_UCLKFMAX]; 258 259 copy_overdrive_settings_limits_array(hwmgr, &pptable_information->od_settings_max, powerplay_table->ODSettingsMax); 260 copy_overdrive_settings_limits_array(hwmgr, &pptable_information->od_settings_min, powerplay_table->ODSettingsMin); 261 262 /* hwmgr->platformDescriptor.minOverdriveVDDC = 0; 263 hwmgr->platformDescriptor.maxOverdriveVDDC = 0; 264 hwmgr->platformDescriptor.overdriveVDDCStep = 0; */ 265 266 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 267 && hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0) 268 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport); 269 270 pptable_information->us_small_power_limit1 = powerplay_table->usSmallPowerLimit1; 271 pptable_information->us_small_power_limit2 = powerplay_table->usSmallPowerLimit2; 272 pptable_information->us_boost_power_limit = powerplay_table->usBoostPowerLimit; 273 pptable_information->us_od_turbo_power_limit = powerplay_table->usODTurboPowerLimit; 274 pptable_information->us_od_powersave_power_limit = powerplay_table->usODPowerSavePowerLimit; 275 276 pptable_information->us_software_shutdown_temp = powerplay_table->usSoftwareShutdownTemp; 277 278 hwmgr->platform_descriptor.TDPODLimit = (uint16_t)powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE]; 279 280 disable_power_control = 0; 281 if (!disable_power_control) { 282 /* enable TDP overdrive (PowerControl) feature as well if supported */ 283 if (hwmgr->platform_descriptor.TDPODLimit) 284 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 285 PHM_PlatformCaps_PowerControl); 286 } 287 288 copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockMax); 289 copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockMin); 290 291 pptable_information->smc_pptable = (PPTable_t *)kmalloc(sizeof(PPTable_t), M_DRM, GFP_KERNEL); 292 if (pptable_information->smc_pptable == NULL) 293 return -ENOMEM; 294 295 memcpy(pptable_information->smc_pptable, &(powerplay_table->smcPPTable), sizeof(PPTable_t)); 296 297 result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable)); 298 299 return result; 300 } 301 302 int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr); 303 int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr) 304 { 305 int result = 0; 306 const ATOM_Vega12_POWERPLAYTABLE *powerplay_table; 307 308 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL); 309 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), 310 "Failed to allocate hwmgr->pptable!", return -ENOMEM); 311 312 powerplay_table = get_powerplay_table(hwmgr); 313 PP_ASSERT_WITH_CODE((powerplay_table != NULL), 314 "Missing PowerPlay Table!", return -1); 315 316 result = check_powerplay_tables(hwmgr, powerplay_table); 317 PP_ASSERT_WITH_CODE((result == 0), 318 "check_powerplay_tables failed", return result); 319 320 result = set_platform_caps(hwmgr, 321 le32_to_cpu(powerplay_table->ulPlatformCaps)); 322 PP_ASSERT_WITH_CODE((result == 0), 323 "set_platform_caps failed", return result); 324 325 result = init_powerplay_table_information(hwmgr, powerplay_table); 326 PP_ASSERT_WITH_CODE((result == 0), 327 "init_powerplay_table_information failed", return result); 328 329 return result; 330 } 331 332 static int vega12_pp_tables_uninitialize(struct pp_hwmgr *hwmgr) 333 { 334 struct phm_ppt_v3_information *pp_table_info = 335 (struct phm_ppt_v3_information *)(hwmgr->pptable); 336 337 kfree(pp_table_info->power_saving_clock_max); 338 pp_table_info->power_saving_clock_max = NULL; 339 340 kfree(pp_table_info->power_saving_clock_min); 341 pp_table_info->power_saving_clock_min = NULL; 342 343 kfree(pp_table_info->od_settings_max); 344 pp_table_info->od_settings_max = NULL; 345 346 kfree(pp_table_info->od_settings_min); 347 pp_table_info->od_settings_min = NULL; 348 349 kfree(pp_table_info->smc_pptable); 350 pp_table_info->smc_pptable = NULL; 351 352 kfree(hwmgr->pptable); 353 hwmgr->pptable = NULL; 354 355 return 0; 356 } 357 358 const struct pp_table_func vega12_pptable_funcs = { 359 .pptable_init = vega12_pp_tables_initialize, 360 .pptable_fini = vega12_pp_tables_uninitialize, 361 }; 362 363 #if 0 364 static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr, 365 uint16_t classification, uint16_t classification2) 366 { 367 uint32_t result = 0; 368 369 if (classification & ATOM_PPLIB_CLASSIFICATION_BOOT) 370 result |= PP_StateClassificationFlag_Boot; 371 372 if (classification & ATOM_PPLIB_CLASSIFICATION_THERMAL) 373 result |= PP_StateClassificationFlag_Thermal; 374 375 if (classification & ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE) 376 result |= PP_StateClassificationFlag_LimitedPowerSource; 377 378 if (classification & ATOM_PPLIB_CLASSIFICATION_REST) 379 result |= PP_StateClassificationFlag_Rest; 380 381 if (classification & ATOM_PPLIB_CLASSIFICATION_FORCED) 382 result |= PP_StateClassificationFlag_Forced; 383 384 if (classification & ATOM_PPLIB_CLASSIFICATION_ACPI) 385 result |= PP_StateClassificationFlag_ACPI; 386 387 if (classification2 & ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2) 388 result |= PP_StateClassificationFlag_LimitedPowerSource_2; 389 390 return result; 391 } 392 393 int vega12_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, 394 uint32_t entry_index, struct pp_power_state *power_state, 395 int (*call_back_func)(struct pp_hwmgr *, void *, 396 struct pp_power_state *, void *, uint32_t)) 397 { 398 int result = 0; 399 const ATOM_Vega12_State_Array *state_arrays; 400 const ATOM_Vega12_State *state_entry; 401 const ATOM_Vega12_POWERPLAYTABLE *pp_table = 402 get_powerplay_table(hwmgr); 403 404 PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!", 405 return -1;); 406 power_state->classification.bios_index = entry_index; 407 408 if (pp_table->sHeader.format_revision >= 409 ATOM_Vega12_TABLE_REVISION_VEGA12) { 410 state_arrays = (ATOM_Vega12_State_Array *) 411 (((unsigned long)pp_table) + 412 le16_to_cpu(pp_table->usStateArrayOffset)); 413 414 PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0, 415 "Invalid PowerPlay Table State Array Offset.", 416 return -1); 417 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0, 418 "Invalid PowerPlay Table State Array.", 419 return -1); 420 PP_ASSERT_WITH_CODE((entry_index <= state_arrays->ucNumEntries), 421 "Invalid PowerPlay Table State Array Entry.", 422 return -1); 423 424 state_entry = &(state_arrays->states[entry_index]); 425 426 result = call_back_func(hwmgr, (void *)state_entry, power_state, 427 (void *)pp_table, 428 make_classification_flags(hwmgr, 429 le16_to_cpu(state_entry->usClassification), 430 le16_to_cpu(state_entry->usClassification2))); 431 } 432 433 if (!result && (power_state->classification.flags & 434 PP_StateClassificationFlag_Boot)) 435 result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware)); 436 437 return result; 438 } 439 #endif 440