1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev #ifndef PP_POWERSTATE_H 24*b843c749SSergey Zigachev #define PP_POWERSTATE_H 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev struct pp_hw_power_state { 27*b843c749SSergey Zigachev unsigned int magic; 28*b843c749SSergey Zigachev }; 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev struct pp_power_state; 31*b843c749SSergey Zigachev 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev #define PP_INVALID_POWER_STATE_ID (0) 34*b843c749SSergey Zigachev 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev /* 37*b843c749SSergey Zigachev * An item of a list containing Power States. 38*b843c749SSergey Zigachev */ 39*b843c749SSergey Zigachev 40*b843c749SSergey Zigachev struct PP_StateLinkedList { 41*b843c749SSergey Zigachev struct pp_power_state *next; 42*b843c749SSergey Zigachev struct pp_power_state *prev; 43*b843c749SSergey Zigachev }; 44*b843c749SSergey Zigachev 45*b843c749SSergey Zigachev 46*b843c749SSergey Zigachev enum PP_StateUILabel { 47*b843c749SSergey Zigachev PP_StateUILabel_None, 48*b843c749SSergey Zigachev PP_StateUILabel_Battery, 49*b843c749SSergey Zigachev PP_StateUILabel_MiddleLow, 50*b843c749SSergey Zigachev PP_StateUILabel_Balanced, 51*b843c749SSergey Zigachev PP_StateUILabel_MiddleHigh, 52*b843c749SSergey Zigachev PP_StateUILabel_Performance, 53*b843c749SSergey Zigachev PP_StateUILabel_BACO 54*b843c749SSergey Zigachev }; 55*b843c749SSergey Zigachev 56*b843c749SSergey Zigachev enum PP_StateClassificationFlag { 57*b843c749SSergey Zigachev PP_StateClassificationFlag_Boot = 0x0001, 58*b843c749SSergey Zigachev PP_StateClassificationFlag_Thermal = 0x0002, 59*b843c749SSergey Zigachev PP_StateClassificationFlag_LimitedPowerSource = 0x0004, 60*b843c749SSergey Zigachev PP_StateClassificationFlag_Rest = 0x0008, 61*b843c749SSergey Zigachev PP_StateClassificationFlag_Forced = 0x0010, 62*b843c749SSergey Zigachev PP_StateClassificationFlag_User3DPerformance = 0x0020, 63*b843c749SSergey Zigachev PP_StateClassificationFlag_User2DPerformance = 0x0040, 64*b843c749SSergey Zigachev PP_StateClassificationFlag_3DPerformance = 0x0080, 65*b843c749SSergey Zigachev PP_StateClassificationFlag_ACOverdriveTemplate = 0x0100, 66*b843c749SSergey Zigachev PP_StateClassificationFlag_Uvd = 0x0200, 67*b843c749SSergey Zigachev PP_StateClassificationFlag_3DPerformanceLow = 0x0400, 68*b843c749SSergey Zigachev PP_StateClassificationFlag_ACPI = 0x0800, 69*b843c749SSergey Zigachev PP_StateClassificationFlag_HD2 = 0x1000, 70*b843c749SSergey Zigachev PP_StateClassificationFlag_UvdHD = 0x2000, 71*b843c749SSergey Zigachev PP_StateClassificationFlag_UvdSD = 0x4000, 72*b843c749SSergey Zigachev PP_StateClassificationFlag_UserDCPerformance = 0x8000, 73*b843c749SSergey Zigachev PP_StateClassificationFlag_DCOverdriveTemplate = 0x10000, 74*b843c749SSergey Zigachev PP_StateClassificationFlag_BACO = 0x20000, 75*b843c749SSergey Zigachev PP_StateClassificationFlag_LimitedPowerSource_2 = 0x40000, 76*b843c749SSergey Zigachev PP_StateClassificationFlag_ULV = 0x80000, 77*b843c749SSergey Zigachev PP_StateClassificationFlag_UvdMVC = 0x100000, 78*b843c749SSergey Zigachev }; 79*b843c749SSergey Zigachev 80*b843c749SSergey Zigachev typedef unsigned int PP_StateClassificationFlags; 81*b843c749SSergey Zigachev 82*b843c749SSergey Zigachev struct PP_StateClassificationBlock { 83*b843c749SSergey Zigachev enum PP_StateUILabel ui_label; 84*b843c749SSergey Zigachev enum PP_StateClassificationFlag flags; 85*b843c749SSergey Zigachev int bios_index; 86*b843c749SSergey Zigachev bool temporary_state; 87*b843c749SSergey Zigachev bool to_be_deleted; 88*b843c749SSergey Zigachev }; 89*b843c749SSergey Zigachev 90*b843c749SSergey Zigachev struct PP_StatePcieBlock { 91*b843c749SSergey Zigachev unsigned int lanes; 92*b843c749SSergey Zigachev }; 93*b843c749SSergey Zigachev 94*b843c749SSergey Zigachev enum PP_RefreshrateSource { 95*b843c749SSergey Zigachev PP_RefreshrateSource_EDID, 96*b843c749SSergey Zigachev PP_RefreshrateSource_Explicit 97*b843c749SSergey Zigachev }; 98*b843c749SSergey Zigachev 99*b843c749SSergey Zigachev struct PP_StateDisplayBlock { 100*b843c749SSergey Zigachev bool disableFrameModulation; 101*b843c749SSergey Zigachev bool limitRefreshrate; 102*b843c749SSergey Zigachev enum PP_RefreshrateSource refreshrateSource; 103*b843c749SSergey Zigachev int explicitRefreshrate; 104*b843c749SSergey Zigachev int edidRefreshrateIndex; 105*b843c749SSergey Zigachev bool enableVariBright; 106*b843c749SSergey Zigachev }; 107*b843c749SSergey Zigachev 108*b843c749SSergey Zigachev struct PP_StateMemroyBlock { 109*b843c749SSergey Zigachev bool dllOff; 110*b843c749SSergey Zigachev uint8_t m3arb; 111*b843c749SSergey Zigachev uint8_t unused[3]; 112*b843c749SSergey Zigachev }; 113*b843c749SSergey Zigachev 114*b843c749SSergey Zigachev struct PP_StateSoftwareAlgorithmBlock { 115*b843c749SSergey Zigachev bool disableLoadBalancing; 116*b843c749SSergey Zigachev bool enableSleepForTimestamps; 117*b843c749SSergey Zigachev }; 118*b843c749SSergey Zigachev 119*b843c749SSergey Zigachev #define PP_TEMPERATURE_UNITS_PER_CENTIGRADES 1000 120*b843c749SSergey Zigachev 121*b843c749SSergey Zigachev /** 122*b843c749SSergey Zigachev * Type to hold a temperature range. 123*b843c749SSergey Zigachev */ 124*b843c749SSergey Zigachev struct PP_TemperatureRange { 125*b843c749SSergey Zigachev int min; 126*b843c749SSergey Zigachev int max; 127*b843c749SSergey Zigachev }; 128*b843c749SSergey Zigachev 129*b843c749SSergey Zigachev struct PP_StateValidationBlock { 130*b843c749SSergey Zigachev bool singleDisplayOnly; 131*b843c749SSergey Zigachev bool disallowOnDC; 132*b843c749SSergey Zigachev uint8_t supportedPowerLevels; 133*b843c749SSergey Zigachev }; 134*b843c749SSergey Zigachev 135*b843c749SSergey Zigachev struct PP_UVD_CLOCKS { 136*b843c749SSergey Zigachev uint32_t VCLK; 137*b843c749SSergey Zigachev uint32_t DCLK; 138*b843c749SSergey Zigachev }; 139*b843c749SSergey Zigachev 140*b843c749SSergey Zigachev /** 141*b843c749SSergey Zigachev * Structure to hold a PowerPlay Power State. 142*b843c749SSergey Zigachev */ 143*b843c749SSergey Zigachev struct pp_power_state { 144*b843c749SSergey Zigachev uint32_t id; 145*b843c749SSergey Zigachev struct PP_StateLinkedList orderedList; 146*b843c749SSergey Zigachev struct PP_StateLinkedList allStatesList; 147*b843c749SSergey Zigachev 148*b843c749SSergey Zigachev struct PP_StateClassificationBlock classification; 149*b843c749SSergey Zigachev struct PP_StateValidationBlock validation; 150*b843c749SSergey Zigachev struct PP_StatePcieBlock pcie; 151*b843c749SSergey Zigachev struct PP_StateDisplayBlock display; 152*b843c749SSergey Zigachev struct PP_StateMemroyBlock memory; 153*b843c749SSergey Zigachev struct PP_TemperatureRange temperatures; 154*b843c749SSergey Zigachev struct PP_StateSoftwareAlgorithmBlock software; 155*b843c749SSergey Zigachev struct PP_UVD_CLOCKS uvd_clocks; 156*b843c749SSergey Zigachev struct pp_hw_power_state hardware; 157*b843c749SSergey Zigachev }; 158*b843c749SSergey Zigachev 159*b843c749SSergey Zigachev enum PP_MMProfilingState { 160*b843c749SSergey Zigachev PP_MMProfilingState_NA = 0, 161*b843c749SSergey Zigachev PP_MMProfilingState_Started, 162*b843c749SSergey Zigachev PP_MMProfilingState_Stopped 163*b843c749SSergey Zigachev }; 164*b843c749SSergey Zigachev 165*b843c749SSergey Zigachev struct pp_clock_engine_request { 166*b843c749SSergey Zigachev unsigned long client_type; 167*b843c749SSergey Zigachev unsigned long ctx_id; 168*b843c749SSergey Zigachev uint64_t context_handle; 169*b843c749SSergey Zigachev unsigned long sclk; 170*b843c749SSergey Zigachev unsigned long sclk_hard_min; 171*b843c749SSergey Zigachev unsigned long mclk; 172*b843c749SSergey Zigachev unsigned long iclk; 173*b843c749SSergey Zigachev unsigned long evclk; 174*b843c749SSergey Zigachev unsigned long ecclk; 175*b843c749SSergey Zigachev unsigned long ecclk_hard_min; 176*b843c749SSergey Zigachev unsigned long vclk; 177*b843c749SSergey Zigachev unsigned long dclk; 178*b843c749SSergey Zigachev unsigned long sclk_over_drive; 179*b843c749SSergey Zigachev unsigned long mclk_over_drive; 180*b843c749SSergey Zigachev unsigned long sclk_threshold; 181*b843c749SSergey Zigachev unsigned long flag; 182*b843c749SSergey Zigachev unsigned long vclk_ceiling; 183*b843c749SSergey Zigachev unsigned long dclk_ceiling; 184*b843c749SSergey Zigachev unsigned long num_cus; 185*b843c749SSergey Zigachev unsigned long pm_flag; 186*b843c749SSergey Zigachev enum PP_MMProfilingState mm_profiling_state; 187*b843c749SSergey Zigachev }; 188*b843c749SSergey Zigachev 189*b843c749SSergey Zigachev #endif 190