1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2013 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef SMU7_H 25*b843c749SSergey Zigachev #define SMU7_H 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #pragma pack(push, 1) 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #define SMU7_CONTEXT_ID_SMC 1 30*b843c749SSergey Zigachev #define SMU7_CONTEXT_ID_VBIOS 2 31*b843c749SSergey Zigachev 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev #define SMU7_CONTEXT_ID_SMC 1 34*b843c749SSergey Zigachev #define SMU7_CONTEXT_ID_VBIOS 2 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_VDDC 8 37*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_VDDCI 4 38*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_MVDD 4 39*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_VDDNB 8 40*b843c749SSergey Zigachev 41*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV 42*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS // MCLK Levels DPM 43*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS // LCLK Levels 44*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes. 45*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_UVD 8 // VCLK/DCLK levels for UVD. 46*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_VCE 8 // ECLK levels for VCE. 47*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_ACP 8 // ACLK levels for ACP. 48*b843c749SSergey Zigachev #define SMU7_MAX_LEVELS_SAMU 8 // SAMCLK levels for SAMU. 49*b843c749SSergey Zigachev #define SMU7_MAX_ENTRIES_SMIO 32 // Number of entries in SMIO table. 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev #define DPM_NO_LIMIT 0 52*b843c749SSergey Zigachev #define DPM_NO_UP 1 53*b843c749SSergey Zigachev #define DPM_GO_DOWN 2 54*b843c749SSergey Zigachev #define DPM_GO_UP 3 55*b843c749SSergey Zigachev 56*b843c749SSergey Zigachev #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 57*b843c749SSergey Zigachev #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 58*b843c749SSergey Zigachev 59*b843c749SSergey Zigachev #define GPIO_CLAMP_MODE_VRHOT 1 60*b843c749SSergey Zigachev #define GPIO_CLAMP_MODE_THERM 2 61*b843c749SSergey Zigachev #define GPIO_CLAMP_MODE_DC 4 62*b843c749SSergey Zigachev 63*b843c749SSergey Zigachev #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 64*b843c749SSergey Zigachev #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 65*b843c749SSergey Zigachev #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 66*b843c749SSergey Zigachev #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 67*b843c749SSergey Zigachev #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 68*b843c749SSergey Zigachev #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 69*b843c749SSergey Zigachev #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 70*b843c749SSergey Zigachev #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 71*b843c749SSergey Zigachev #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 72*b843c749SSergey Zigachev #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 73*b843c749SSergey Zigachev #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 74*b843c749SSergey Zigachev #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 75*b843c749SSergey Zigachev #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 76*b843c749SSergey Zigachev #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 77*b843c749SSergey Zigachev #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 78*b843c749SSergey Zigachev #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 79*b843c749SSergey Zigachev #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 80*b843c749SSergey Zigachev #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 81*b843c749SSergey Zigachev #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 82*b843c749SSergey Zigachev #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 83*b843c749SSergey Zigachev 84*b843c749SSergey Zigachev 85*b843c749SSergey Zigachev /* Voltage Regulator Configuration */ 86*b843c749SSergey Zigachev /* VR Config info is contained in dpmTable */ 87*b843c749SSergey Zigachev 88*b843c749SSergey Zigachev #define VRCONF_VDDC_MASK 0x000000FF 89*b843c749SSergey Zigachev #define VRCONF_VDDC_SHIFT 0 90*b843c749SSergey Zigachev #define VRCONF_VDDGFX_MASK 0x0000FF00 91*b843c749SSergey Zigachev #define VRCONF_VDDGFX_SHIFT 8 92*b843c749SSergey Zigachev #define VRCONF_VDDCI_MASK 0x00FF0000 93*b843c749SSergey Zigachev #define VRCONF_VDDCI_SHIFT 16 94*b843c749SSergey Zigachev #define VRCONF_MVDD_MASK 0xFF000000 95*b843c749SSergey Zigachev #define VRCONF_MVDD_SHIFT 24 96*b843c749SSergey Zigachev 97*b843c749SSergey Zigachev #define VR_MERGED_WITH_VDDC 0 98*b843c749SSergey Zigachev #define VR_SVI2_PLANE_1 1 99*b843c749SSergey Zigachev #define VR_SVI2_PLANE_2 2 100*b843c749SSergey Zigachev #define VR_SMIO_PATTERN_1 3 101*b843c749SSergey Zigachev #define VR_SMIO_PATTERN_2 4 102*b843c749SSergey Zigachev #define VR_STATIC_VOLTAGE 5 103*b843c749SSergey Zigachev 104*b843c749SSergey Zigachev struct SMU7_PIDController 105*b843c749SSergey Zigachev { 106*b843c749SSergey Zigachev uint32_t Ki; 107*b843c749SSergey Zigachev int32_t LFWindupUL; 108*b843c749SSergey Zigachev int32_t LFWindupLL; 109*b843c749SSergey Zigachev uint32_t StatePrecision; 110*b843c749SSergey Zigachev uint32_t LfPrecision; 111*b843c749SSergey Zigachev uint32_t LfOffset; 112*b843c749SSergey Zigachev uint32_t MaxState; 113*b843c749SSergey Zigachev uint32_t MaxLfFraction; 114*b843c749SSergey Zigachev uint32_t StateShift; 115*b843c749SSergey Zigachev }; 116*b843c749SSergey Zigachev 117*b843c749SSergey Zigachev typedef struct SMU7_PIDController SMU7_PIDController; 118*b843c749SSergey Zigachev 119*b843c749SSergey Zigachev // ------------------------------------------------------------------------------------------------------------------------- 120*b843c749SSergey Zigachev #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 121*b843c749SSergey Zigachev 122*b843c749SSergey Zigachev #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 123*b843c749SSergey Zigachev #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 124*b843c749SSergey Zigachev #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 125*b843c749SSergey Zigachev #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 126*b843c749SSergey Zigachev #define SMU7_UVD_DPM_CONFIG_MASK 0x10 127*b843c749SSergey Zigachev #define SMU7_VCE_DPM_CONFIG_MASK 0x20 128*b843c749SSergey Zigachev #define SMU7_ACP_DPM_CONFIG_MASK 0x40 129*b843c749SSergey Zigachev #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 130*b843c749SSergey Zigachev #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 131*b843c749SSergey Zigachev 132*b843c749SSergey Zigachev #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 133*b843c749SSergey Zigachev #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 134*b843c749SSergey Zigachev #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 135*b843c749SSergey Zigachev #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 136*b843c749SSergey Zigachev #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 137*b843c749SSergey Zigachev #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 138*b843c749SSergey Zigachev 139*b843c749SSergey Zigachev struct SMU7_Firmware_Header 140*b843c749SSergey Zigachev { 141*b843c749SSergey Zigachev uint32_t Digest[5]; 142*b843c749SSergey Zigachev uint32_t Version; 143*b843c749SSergey Zigachev uint32_t HeaderSize; 144*b843c749SSergey Zigachev uint32_t Flags; 145*b843c749SSergey Zigachev uint32_t EntryPoint; 146*b843c749SSergey Zigachev uint32_t CodeSize; 147*b843c749SSergey Zigachev uint32_t ImageSize; 148*b843c749SSergey Zigachev 149*b843c749SSergey Zigachev uint32_t Rtos; 150*b843c749SSergey Zigachev uint32_t SoftRegisters; 151*b843c749SSergey Zigachev uint32_t DpmTable; 152*b843c749SSergey Zigachev uint32_t FanTable; 153*b843c749SSergey Zigachev uint32_t CacConfigTable; 154*b843c749SSergey Zigachev uint32_t CacStatusTable; 155*b843c749SSergey Zigachev 156*b843c749SSergey Zigachev uint32_t mcRegisterTable; 157*b843c749SSergey Zigachev 158*b843c749SSergey Zigachev uint32_t mcArbDramTimingTable; 159*b843c749SSergey Zigachev 160*b843c749SSergey Zigachev uint32_t PmFuseTable; 161*b843c749SSergey Zigachev uint32_t Globals; 162*b843c749SSergey Zigachev uint32_t Reserved[42]; 163*b843c749SSergey Zigachev uint32_t Signature; 164*b843c749SSergey Zigachev }; 165*b843c749SSergey Zigachev 166*b843c749SSergey Zigachev typedef struct SMU7_Firmware_Header SMU7_Firmware_Header; 167*b843c749SSergey Zigachev 168*b843c749SSergey Zigachev #define SMU7_FIRMWARE_HEADER_LOCATION 0x20000 169*b843c749SSergey Zigachev 170*b843c749SSergey Zigachev enum DisplayConfig { 171*b843c749SSergey Zigachev PowerDown = 1, 172*b843c749SSergey Zigachev DP54x4, 173*b843c749SSergey Zigachev DP54x2, 174*b843c749SSergey Zigachev DP54x1, 175*b843c749SSergey Zigachev DP27x4, 176*b843c749SSergey Zigachev DP27x2, 177*b843c749SSergey Zigachev DP27x1, 178*b843c749SSergey Zigachev HDMI297, 179*b843c749SSergey Zigachev HDMI162, 180*b843c749SSergey Zigachev LVDS, 181*b843c749SSergey Zigachev DP324x4, 182*b843c749SSergey Zigachev DP324x2, 183*b843c749SSergey Zigachev DP324x1 184*b843c749SSergey Zigachev }; 185*b843c749SSergey Zigachev 186*b843c749SSergey Zigachev #pragma pack(pop) 187*b843c749SSergey Zigachev 188*b843c749SSergey Zigachev #endif 189*b843c749SSergey Zigachev 190