1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev #ifndef SMU71_H 24*b843c749SSergey Zigachev #define SMU71_H 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #if !defined(SMC_MICROCODE) 27*b843c749SSergey Zigachev #pragma pack(push, 1) 28*b843c749SSergey Zigachev #endif 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define SMU__NUM_PCIE_DPM_LEVELS 8 31*b843c749SSergey Zigachev #define SMU__NUM_SCLK_DPM_STATE 8 32*b843c749SSergey Zigachev #define SMU__NUM_MCLK_DPM_LEVELS 4 33*b843c749SSergey Zigachev #define SMU__VARIANT__ICELAND 1 34*b843c749SSergey Zigachev #define SMU__DGPU_ONLY 1 35*b843c749SSergey Zigachev #define SMU__DYNAMIC_MCARB_SETTINGS 1 36*b843c749SSergey Zigachev 37*b843c749SSergey Zigachev enum SID_OPTION { 38*b843c749SSergey Zigachev SID_OPTION_HI, 39*b843c749SSergey Zigachev SID_OPTION_LO, 40*b843c749SSergey Zigachev SID_OPTION_COUNT 41*b843c749SSergey Zigachev }; 42*b843c749SSergey Zigachev 43*b843c749SSergey Zigachev typedef struct { 44*b843c749SSergey Zigachev uint32_t high; 45*b843c749SSergey Zigachev uint32_t low; 46*b843c749SSergey Zigachev } data_64_t; 47*b843c749SSergey Zigachev 48*b843c749SSergey Zigachev typedef struct { 49*b843c749SSergey Zigachev data_64_t high; 50*b843c749SSergey Zigachev data_64_t low; 51*b843c749SSergey Zigachev } data_128_t; 52*b843c749SSergey Zigachev 53*b843c749SSergey Zigachev #define SMU7_CONTEXT_ID_SMC 1 54*b843c749SSergey Zigachev #define SMU7_CONTEXT_ID_VBIOS 2 55*b843c749SSergey Zigachev 56*b843c749SSergey Zigachev #define SMU71_MAX_LEVELS_VDDC 8 57*b843c749SSergey Zigachev #define SMU71_MAX_LEVELS_VDDCI 4 58*b843c749SSergey Zigachev #define SMU71_MAX_LEVELS_MVDD 4 59*b843c749SSergey Zigachev #define SMU71_MAX_LEVELS_VDDNB 8 60*b843c749SSergey Zigachev 61*b843c749SSergey Zigachev #define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE 62*b843c749SSergey Zigachev #define SMU71_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS 63*b843c749SSergey Zigachev #define SMU71_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS 64*b843c749SSergey Zigachev #define SMU71_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS 65*b843c749SSergey Zigachev #define SMU71_MAX_ENTRIES_SMIO 32 66*b843c749SSergey Zigachev 67*b843c749SSergey Zigachev #define DPM_NO_LIMIT 0 68*b843c749SSergey Zigachev #define DPM_NO_UP 1 69*b843c749SSergey Zigachev #define DPM_GO_DOWN 2 70*b843c749SSergey Zigachev #define DPM_GO_UP 3 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev #define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0 73*b843c749SSergey Zigachev #define SMU7_FIRST_DPM_MEMORY_LEVEL 0 74*b843c749SSergey Zigachev 75*b843c749SSergey Zigachev #define GPIO_CLAMP_MODE_VRHOT 1 76*b843c749SSergey Zigachev #define GPIO_CLAMP_MODE_THERM 2 77*b843c749SSergey Zigachev #define GPIO_CLAMP_MODE_DC 4 78*b843c749SSergey Zigachev 79*b843c749SSergey Zigachev #define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0 80*b843c749SSergey Zigachev #define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT) 81*b843c749SSergey Zigachev #define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3 82*b843c749SSergey Zigachev #define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT) 83*b843c749SSergey Zigachev #define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6 84*b843c749SSergey Zigachev #define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT) 85*b843c749SSergey Zigachev #define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9 86*b843c749SSergey Zigachev #define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT) 87*b843c749SSergey Zigachev #define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12 88*b843c749SSergey Zigachev #define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT) 89*b843c749SSergey Zigachev #define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15 90*b843c749SSergey Zigachev #define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT) 91*b843c749SSergey Zigachev #define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18 92*b843c749SSergey Zigachev #define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT) 93*b843c749SSergey Zigachev #define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21 94*b843c749SSergey Zigachev #define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT) 95*b843c749SSergey Zigachev #define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24 96*b843c749SSergey Zigachev #define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT) 97*b843c749SSergey Zigachev #define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27 98*b843c749SSergey Zigachev #define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT) 99*b843c749SSergey Zigachev 100*b843c749SSergey Zigachev 101*b843c749SSergey Zigachev #if defined SMU__DGPU_ONLY 102*b843c749SSergey Zigachev #define SMU71_DTE_ITERATIONS 5 103*b843c749SSergey Zigachev #define SMU71_DTE_SOURCES 3 104*b843c749SSergey Zigachev #define SMU71_DTE_SINKS 1 105*b843c749SSergey Zigachev #define SMU71_NUM_CPU_TES 0 106*b843c749SSergey Zigachev #define SMU71_NUM_GPU_TES 1 107*b843c749SSergey Zigachev #define SMU71_NUM_NON_TES 2 108*b843c749SSergey Zigachev 109*b843c749SSergey Zigachev #endif 110*b843c749SSergey Zigachev 111*b843c749SSergey Zigachev #if defined SMU__FUSION_ONLY 112*b843c749SSergey Zigachev #define SMU7_DTE_ITERATIONS 5 113*b843c749SSergey Zigachev #define SMU7_DTE_SOURCES 5 114*b843c749SSergey Zigachev #define SMU7_DTE_SINKS 3 115*b843c749SSergey Zigachev #define SMU7_NUM_CPU_TES 2 116*b843c749SSergey Zigachev #define SMU7_NUM_GPU_TES 1 117*b843c749SSergey Zigachev #define SMU7_NUM_NON_TES 2 118*b843c749SSergey Zigachev 119*b843c749SSergey Zigachev #endif 120*b843c749SSergey Zigachev 121*b843c749SSergey Zigachev struct SMU71_PIDController 122*b843c749SSergey Zigachev { 123*b843c749SSergey Zigachev uint32_t Ki; 124*b843c749SSergey Zigachev int32_t LFWindupUpperLim; 125*b843c749SSergey Zigachev int32_t LFWindupLowerLim; 126*b843c749SSergey Zigachev uint32_t StatePrecision; 127*b843c749SSergey Zigachev uint32_t LfPrecision; 128*b843c749SSergey Zigachev uint32_t LfOffset; 129*b843c749SSergey Zigachev uint32_t MaxState; 130*b843c749SSergey Zigachev uint32_t MaxLfFraction; 131*b843c749SSergey Zigachev uint32_t StateShift; 132*b843c749SSergey Zigachev }; 133*b843c749SSergey Zigachev 134*b843c749SSergey Zigachev typedef struct SMU71_PIDController SMU71_PIDController; 135*b843c749SSergey Zigachev 136*b843c749SSergey Zigachev struct SMU7_LocalDpmScoreboard 137*b843c749SSergey Zigachev { 138*b843c749SSergey Zigachev uint32_t PercentageBusy; 139*b843c749SSergey Zigachev 140*b843c749SSergey Zigachev int32_t PIDError; 141*b843c749SSergey Zigachev int32_t PIDIntegral; 142*b843c749SSergey Zigachev int32_t PIDOutput; 143*b843c749SSergey Zigachev 144*b843c749SSergey Zigachev uint32_t SigmaDeltaAccum; 145*b843c749SSergey Zigachev uint32_t SigmaDeltaOutput; 146*b843c749SSergey Zigachev uint32_t SigmaDeltaLevel; 147*b843c749SSergey Zigachev 148*b843c749SSergey Zigachev uint32_t UtilizationSetpoint; 149*b843c749SSergey Zigachev 150*b843c749SSergey Zigachev uint8_t TdpClampMode; 151*b843c749SSergey Zigachev uint8_t TdcClampMode; 152*b843c749SSergey Zigachev uint8_t ThermClampMode; 153*b843c749SSergey Zigachev uint8_t VoltageBusy; 154*b843c749SSergey Zigachev 155*b843c749SSergey Zigachev int8_t CurrLevel; 156*b843c749SSergey Zigachev int8_t TargLevel; 157*b843c749SSergey Zigachev uint8_t LevelChangeInProgress; 158*b843c749SSergey Zigachev uint8_t UpHyst; 159*b843c749SSergey Zigachev 160*b843c749SSergey Zigachev uint8_t DownHyst; 161*b843c749SSergey Zigachev uint8_t VoltageDownHyst; 162*b843c749SSergey Zigachev uint8_t DpmEnable; 163*b843c749SSergey Zigachev uint8_t DpmRunning; 164*b843c749SSergey Zigachev 165*b843c749SSergey Zigachev uint8_t DpmForce; 166*b843c749SSergey Zigachev uint8_t DpmForceLevel; 167*b843c749SSergey Zigachev uint8_t DisplayWatermark; 168*b843c749SSergey Zigachev uint8_t McArbIndex; 169*b843c749SSergey Zigachev 170*b843c749SSergey Zigachev uint32_t MinimumPerfSclk; 171*b843c749SSergey Zigachev 172*b843c749SSergey Zigachev uint8_t AcpiReq; 173*b843c749SSergey Zigachev uint8_t AcpiAck; 174*b843c749SSergey Zigachev uint8_t GfxClkSlow; 175*b843c749SSergey Zigachev uint8_t GpioClampMode; 176*b843c749SSergey Zigachev 177*b843c749SSergey Zigachev uint8_t FpsFilterWeight; 178*b843c749SSergey Zigachev uint8_t EnabledLevelsChange; 179*b843c749SSergey Zigachev uint8_t DteClampMode; 180*b843c749SSergey Zigachev uint8_t FpsClampMode; 181*b843c749SSergey Zigachev 182*b843c749SSergey Zigachev uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_GRAPHICS]; 183*b843c749SSergey Zigachev uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_GRAPHICS]; 184*b843c749SSergey Zigachev 185*b843c749SSergey Zigachev void (*TargetStateCalculator)(uint8_t); 186*b843c749SSergey Zigachev void (*SavedTargetStateCalculator)(uint8_t); 187*b843c749SSergey Zigachev 188*b843c749SSergey Zigachev uint16_t AutoDpmInterval; 189*b843c749SSergey Zigachev uint16_t AutoDpmRange; 190*b843c749SSergey Zigachev 191*b843c749SSergey Zigachev uint8_t FpsEnabled; 192*b843c749SSergey Zigachev uint8_t MaxPerfLevel; 193*b843c749SSergey Zigachev uint8_t AllowLowClkInterruptToHost; 194*b843c749SSergey Zigachev uint8_t FpsRunning; 195*b843c749SSergey Zigachev 196*b843c749SSergey Zigachev uint32_t MaxAllowedFrequency; 197*b843c749SSergey Zigachev }; 198*b843c749SSergey Zigachev 199*b843c749SSergey Zigachev typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard; 200*b843c749SSergey Zigachev 201*b843c749SSergey Zigachev #define SMU7_MAX_VOLTAGE_CLIENTS 12 202*b843c749SSergey Zigachev 203*b843c749SSergey Zigachev struct SMU7_VoltageScoreboard 204*b843c749SSergey Zigachev { 205*b843c749SSergey Zigachev uint16_t CurrentVoltage; 206*b843c749SSergey Zigachev uint16_t HighestVoltage; 207*b843c749SSergey Zigachev uint16_t MaxVid; 208*b843c749SSergey Zigachev uint8_t HighestVidOffset; 209*b843c749SSergey Zigachev uint8_t CurrentVidOffset; 210*b843c749SSergey Zigachev #if defined (SMU__DGPU_ONLY) 211*b843c749SSergey Zigachev uint8_t CurrentPhases; 212*b843c749SSergey Zigachev uint8_t HighestPhases; 213*b843c749SSergey Zigachev #else 214*b843c749SSergey Zigachev uint8_t AvsOffset; 215*b843c749SSergey Zigachev uint8_t AvsOffsetApplied; 216*b843c749SSergey Zigachev #endif 217*b843c749SSergey Zigachev uint8_t ControllerBusy; 218*b843c749SSergey Zigachev uint8_t CurrentVid; 219*b843c749SSergey Zigachev uint16_t RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS]; 220*b843c749SSergey Zigachev #if defined (SMU__DGPU_ONLY) 221*b843c749SSergey Zigachev uint8_t RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS]; 222*b843c749SSergey Zigachev #endif 223*b843c749SSergey Zigachev uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS]; 224*b843c749SSergey Zigachev uint8_t TargetIndex; 225*b843c749SSergey Zigachev uint8_t Delay; 226*b843c749SSergey Zigachev uint8_t ControllerEnable; 227*b843c749SSergey Zigachev uint8_t ControllerRunning; 228*b843c749SSergey Zigachev uint16_t CurrentStdVoltageHiSidd; 229*b843c749SSergey Zigachev uint16_t CurrentStdVoltageLoSidd; 230*b843c749SSergey Zigachev #if defined (SMU__DGPU_ONLY) 231*b843c749SSergey Zigachev uint16_t RequestedVddci; 232*b843c749SSergey Zigachev uint16_t CurrentVddci; 233*b843c749SSergey Zigachev uint16_t HighestVddci; 234*b843c749SSergey Zigachev uint8_t CurrentVddciVid; 235*b843c749SSergey Zigachev uint8_t TargetVddciIndex; 236*b843c749SSergey Zigachev #endif 237*b843c749SSergey Zigachev }; 238*b843c749SSergey Zigachev 239*b843c749SSergey Zigachev typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard; 240*b843c749SSergey Zigachev 241*b843c749SSergey Zigachev // ------------------------------------------------------------------------------------------------------------------------- 242*b843c749SSergey Zigachev #define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */ 243*b843c749SSergey Zigachev 244*b843c749SSergey Zigachev struct SMU7_PCIeLinkSpeedScoreboard 245*b843c749SSergey Zigachev { 246*b843c749SSergey Zigachev uint8_t DpmEnable; 247*b843c749SSergey Zigachev uint8_t DpmRunning; 248*b843c749SSergey Zigachev uint8_t DpmForce; 249*b843c749SSergey Zigachev uint8_t DpmForceLevel; 250*b843c749SSergey Zigachev 251*b843c749SSergey Zigachev uint8_t CurrentLinkSpeed; 252*b843c749SSergey Zigachev uint8_t EnabledLevelsChange; 253*b843c749SSergey Zigachev uint16_t AutoDpmInterval; 254*b843c749SSergey Zigachev 255*b843c749SSergey Zigachev uint16_t AutoDpmRange; 256*b843c749SSergey Zigachev uint16_t AutoDpmCount; 257*b843c749SSergey Zigachev 258*b843c749SSergey Zigachev uint8_t DpmMode; 259*b843c749SSergey Zigachev uint8_t AcpiReq; 260*b843c749SSergey Zigachev uint8_t AcpiAck; 261*b843c749SSergey Zigachev uint8_t CurrentLinkLevel; 262*b843c749SSergey Zigachev 263*b843c749SSergey Zigachev }; 264*b843c749SSergey Zigachev 265*b843c749SSergey Zigachev typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard; 266*b843c749SSergey Zigachev 267*b843c749SSergey Zigachev // -------------------------------------------------------- CAC table ------------------------------------------------------ 268*b843c749SSergey Zigachev #define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 269*b843c749SSergey Zigachev #define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16 270*b843c749SSergey Zigachev 271*b843c749SSergey Zigachev #define SMU7_SCALE_I 7 272*b843c749SSergey Zigachev #define SMU7_SCALE_R 12 273*b843c749SSergey Zigachev 274*b843c749SSergey Zigachev struct SMU7_PowerScoreboard 275*b843c749SSergey Zigachev { 276*b843c749SSergey Zigachev uint16_t MinVoltage; 277*b843c749SSergey Zigachev uint16_t MaxVoltage; 278*b843c749SSergey Zigachev 279*b843c749SSergey Zigachev uint32_t AvgGpuPower; 280*b843c749SSergey Zigachev 281*b843c749SSergey Zigachev uint16_t VddcLeakagePower[SID_OPTION_COUNT]; 282*b843c749SSergey Zigachev uint16_t VddcSclkConstantPower[SID_OPTION_COUNT]; 283*b843c749SSergey Zigachev uint16_t VddcSclkDynamicPower[SID_OPTION_COUNT]; 284*b843c749SSergey Zigachev uint16_t VddcNonSclkDynamicPower[SID_OPTION_COUNT]; 285*b843c749SSergey Zigachev uint16_t VddcTotalPower[SID_OPTION_COUNT]; 286*b843c749SSergey Zigachev uint16_t VddcTotalCurrent[SID_OPTION_COUNT]; 287*b843c749SSergey Zigachev uint16_t VddcLoadVoltage[SID_OPTION_COUNT]; 288*b843c749SSergey Zigachev uint16_t VddcNoLoadVoltage[SID_OPTION_COUNT]; 289*b843c749SSergey Zigachev 290*b843c749SSergey Zigachev uint16_t DisplayPhyPower; 291*b843c749SSergey Zigachev uint16_t PciePhyPower; 292*b843c749SSergey Zigachev 293*b843c749SSergey Zigachev uint16_t VddciTotalPower; 294*b843c749SSergey Zigachev uint16_t Vddr1TotalPower; 295*b843c749SSergey Zigachev 296*b843c749SSergey Zigachev uint32_t RocPower; 297*b843c749SSergey Zigachev 298*b843c749SSergey Zigachev uint32_t last_power; 299*b843c749SSergey Zigachev uint32_t enableWinAvg; 300*b843c749SSergey Zigachev 301*b843c749SSergey Zigachev uint32_t lkg_acc; 302*b843c749SSergey Zigachev uint16_t VoltLkgeScaler; 303*b843c749SSergey Zigachev uint16_t TempLkgeScaler; 304*b843c749SSergey Zigachev 305*b843c749SSergey Zigachev uint32_t uvd_cac_dclk; 306*b843c749SSergey Zigachev uint32_t uvd_cac_vclk; 307*b843c749SSergey Zigachev uint32_t vce_cac_eclk; 308*b843c749SSergey Zigachev uint32_t samu_cac_samclk; 309*b843c749SSergey Zigachev uint32_t display_cac_dispclk; 310*b843c749SSergey Zigachev uint32_t acp_cac_aclk; 311*b843c749SSergey Zigachev uint32_t unb_cac; 312*b843c749SSergey Zigachev 313*b843c749SSergey Zigachev uint32_t WinTime; 314*b843c749SSergey Zigachev 315*b843c749SSergey Zigachev uint16_t GpuPwr_MAWt; 316*b843c749SSergey Zigachev uint16_t FilteredVddcTotalPower; 317*b843c749SSergey Zigachev 318*b843c749SSergey Zigachev uint8_t CalculationRepeats; 319*b843c749SSergey Zigachev uint8_t WaterfallUp; 320*b843c749SSergey Zigachev uint8_t WaterfallDown; 321*b843c749SSergey Zigachev uint8_t WaterfallLimit; 322*b843c749SSergey Zigachev }; 323*b843c749SSergey Zigachev 324*b843c749SSergey Zigachev typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard; 325*b843c749SSergey Zigachev 326*b843c749SSergey Zigachev // -------------------------------------------------------------------------------------------------- 327*b843c749SSergey Zigachev 328*b843c749SSergey Zigachev struct SMU7_ThermalScoreboard 329*b843c749SSergey Zigachev { 330*b843c749SSergey Zigachev int16_t GpuLimit; 331*b843c749SSergey Zigachev int16_t GpuHyst; 332*b843c749SSergey Zigachev uint16_t CurrGnbTemp; 333*b843c749SSergey Zigachev uint16_t FilteredGnbTemp; 334*b843c749SSergey Zigachev uint8_t ControllerEnable; 335*b843c749SSergey Zigachev uint8_t ControllerRunning; 336*b843c749SSergey Zigachev uint8_t WaterfallUp; 337*b843c749SSergey Zigachev uint8_t WaterfallDown; 338*b843c749SSergey Zigachev uint8_t WaterfallLimit; 339*b843c749SSergey Zigachev uint8_t padding[3]; 340*b843c749SSergey Zigachev }; 341*b843c749SSergey Zigachev 342*b843c749SSergey Zigachev typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard; 343*b843c749SSergey Zigachev 344*b843c749SSergey Zigachev // For FeatureEnables: 345*b843c749SSergey Zigachev #define SMU7_SCLK_DPM_CONFIG_MASK 0x01 346*b843c749SSergey Zigachev #define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02 347*b843c749SSergey Zigachev #define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04 348*b843c749SSergey Zigachev #define SMU7_MCLK_DPM_CONFIG_MASK 0x08 349*b843c749SSergey Zigachev #define SMU7_UVD_DPM_CONFIG_MASK 0x10 350*b843c749SSergey Zigachev #define SMU7_VCE_DPM_CONFIG_MASK 0x20 351*b843c749SSergey Zigachev #define SMU7_ACP_DPM_CONFIG_MASK 0x40 352*b843c749SSergey Zigachev #define SMU7_SAMU_DPM_CONFIG_MASK 0x80 353*b843c749SSergey Zigachev #define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100 354*b843c749SSergey Zigachev 355*b843c749SSergey Zigachev #define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001 356*b843c749SSergey Zigachev #define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002 357*b843c749SSergey Zigachev #define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100 358*b843c749SSergey Zigachev #define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200 359*b843c749SSergey Zigachev #define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000 360*b843c749SSergey Zigachev #define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000 361*b843c749SSergey Zigachev 362*b843c749SSergey Zigachev // All 'soft registers' should be uint32_t. 363*b843c749SSergey Zigachev struct SMU71_SoftRegisters 364*b843c749SSergey Zigachev { 365*b843c749SSergey Zigachev uint32_t RefClockFrequency; 366*b843c749SSergey Zigachev uint32_t PmTimerPeriod; 367*b843c749SSergey Zigachev uint32_t FeatureEnables; 368*b843c749SSergey Zigachev #if defined (SMU__DGPU_ONLY) 369*b843c749SSergey Zigachev uint32_t PreVBlankGap; 370*b843c749SSergey Zigachev uint32_t VBlankTimeout; 371*b843c749SSergey Zigachev uint32_t TrainTimeGap; 372*b843c749SSergey Zigachev uint32_t MvddSwitchTime; 373*b843c749SSergey Zigachev uint32_t LongestAcpiTrainTime; 374*b843c749SSergey Zigachev uint32_t AcpiDelay; 375*b843c749SSergey Zigachev uint32_t G5TrainTime; 376*b843c749SSergey Zigachev uint32_t DelayMpllPwron; 377*b843c749SSergey Zigachev uint32_t VoltageChangeTimeout; 378*b843c749SSergey Zigachev #endif 379*b843c749SSergey Zigachev uint32_t HandshakeDisables; 380*b843c749SSergey Zigachev 381*b843c749SSergey Zigachev uint8_t DisplayPhy1Config; 382*b843c749SSergey Zigachev uint8_t DisplayPhy2Config; 383*b843c749SSergey Zigachev uint8_t DisplayPhy3Config; 384*b843c749SSergey Zigachev uint8_t DisplayPhy4Config; 385*b843c749SSergey Zigachev 386*b843c749SSergey Zigachev uint8_t DisplayPhy5Config; 387*b843c749SSergey Zigachev uint8_t DisplayPhy6Config; 388*b843c749SSergey Zigachev uint8_t DisplayPhy7Config; 389*b843c749SSergey Zigachev uint8_t DisplayPhy8Config; 390*b843c749SSergey Zigachev 391*b843c749SSergey Zigachev uint32_t AverageGraphicsActivity; 392*b843c749SSergey Zigachev uint32_t AverageMemoryActivity; 393*b843c749SSergey Zigachev uint32_t AverageGioActivity; 394*b843c749SSergey Zigachev 395*b843c749SSergey Zigachev uint8_t SClkDpmEnabledLevels; 396*b843c749SSergey Zigachev uint8_t MClkDpmEnabledLevels; 397*b843c749SSergey Zigachev uint8_t LClkDpmEnabledLevels; 398*b843c749SSergey Zigachev uint8_t PCIeDpmEnabledLevels; 399*b843c749SSergey Zigachev 400*b843c749SSergey Zigachev uint32_t DRAM_LOG_ADDR_H; 401*b843c749SSergey Zigachev uint32_t DRAM_LOG_ADDR_L; 402*b843c749SSergey Zigachev uint32_t DRAM_LOG_PHY_ADDR_H; 403*b843c749SSergey Zigachev uint32_t DRAM_LOG_PHY_ADDR_L; 404*b843c749SSergey Zigachev uint32_t DRAM_LOG_BUFF_SIZE; 405*b843c749SSergey Zigachev uint32_t UlvEnterCount; 406*b843c749SSergey Zigachev uint32_t UlvTime; 407*b843c749SSergey Zigachev uint32_t UcodeLoadStatus; 408*b843c749SSergey Zigachev uint8_t DPMFreezeAndForced; 409*b843c749SSergey Zigachev uint8_t Activity_Weight; 410*b843c749SSergey Zigachev uint8_t Reserved8[2]; 411*b843c749SSergey Zigachev uint32_t Reserved; 412*b843c749SSergey Zigachev }; 413*b843c749SSergey Zigachev 414*b843c749SSergey Zigachev typedef struct SMU71_SoftRegisters SMU71_SoftRegisters; 415*b843c749SSergey Zigachev 416*b843c749SSergey Zigachev struct SMU71_Firmware_Header 417*b843c749SSergey Zigachev { 418*b843c749SSergey Zigachev uint32_t Digest[5]; 419*b843c749SSergey Zigachev uint32_t Version; 420*b843c749SSergey Zigachev uint32_t HeaderSize; 421*b843c749SSergey Zigachev uint32_t Flags; 422*b843c749SSergey Zigachev uint32_t EntryPoint; 423*b843c749SSergey Zigachev uint32_t CodeSize; 424*b843c749SSergey Zigachev uint32_t ImageSize; 425*b843c749SSergey Zigachev 426*b843c749SSergey Zigachev uint32_t Rtos; 427*b843c749SSergey Zigachev uint32_t SoftRegisters; 428*b843c749SSergey Zigachev uint32_t DpmTable; 429*b843c749SSergey Zigachev uint32_t FanTable; 430*b843c749SSergey Zigachev uint32_t CacConfigTable; 431*b843c749SSergey Zigachev uint32_t CacStatusTable; 432*b843c749SSergey Zigachev 433*b843c749SSergey Zigachev uint32_t mcRegisterTable; 434*b843c749SSergey Zigachev 435*b843c749SSergey Zigachev uint32_t mcArbDramTimingTable; 436*b843c749SSergey Zigachev 437*b843c749SSergey Zigachev uint32_t PmFuseTable; 438*b843c749SSergey Zigachev uint32_t Globals; 439*b843c749SSergey Zigachev uint32_t UvdDpmTable; 440*b843c749SSergey Zigachev uint32_t AcpDpmTable; 441*b843c749SSergey Zigachev uint32_t VceDpmTable; 442*b843c749SSergey Zigachev uint32_t SamuDpmTable; 443*b843c749SSergey Zigachev uint32_t UlvSettings; 444*b843c749SSergey Zigachev uint32_t Reserved[37]; 445*b843c749SSergey Zigachev uint32_t Signature; 446*b843c749SSergey Zigachev }; 447*b843c749SSergey Zigachev 448*b843c749SSergey Zigachev typedef struct SMU71_Firmware_Header SMU71_Firmware_Header; 449*b843c749SSergey Zigachev 450*b843c749SSergey Zigachev struct SMU7_HystController_Data 451*b843c749SSergey Zigachev { 452*b843c749SSergey Zigachev uint8_t waterfall_up; 453*b843c749SSergey Zigachev uint8_t waterfall_down; 454*b843c749SSergey Zigachev uint8_t pstate; 455*b843c749SSergey Zigachev uint8_t clamp_mode; 456*b843c749SSergey Zigachev }; 457*b843c749SSergey Zigachev 458*b843c749SSergey Zigachev typedef struct SMU7_HystController_Data SMU7_HystController_Data; 459*b843c749SSergey Zigachev 460*b843c749SSergey Zigachev #define SMU71_FIRMWARE_HEADER_LOCATION 0x20000 461*b843c749SSergey Zigachev 462*b843c749SSergey Zigachev enum DisplayConfig { 463*b843c749SSergey Zigachev PowerDown = 1, 464*b843c749SSergey Zigachev DP54x4, 465*b843c749SSergey Zigachev DP54x2, 466*b843c749SSergey Zigachev DP54x1, 467*b843c749SSergey Zigachev DP27x4, 468*b843c749SSergey Zigachev DP27x2, 469*b843c749SSergey Zigachev DP27x1, 470*b843c749SSergey Zigachev HDMI297, 471*b843c749SSergey Zigachev HDMI162, 472*b843c749SSergey Zigachev LVDS, 473*b843c749SSergey Zigachev DP324x4, 474*b843c749SSergey Zigachev DP324x2, 475*b843c749SSergey Zigachev DP324x1 476*b843c749SSergey Zigachev }; 477*b843c749SSergey Zigachev 478*b843c749SSergey Zigachev //#define SX_BLOCK_COUNT 8 479*b843c749SSergey Zigachev //#define MC_BLOCK_COUNT 1 480*b843c749SSergey Zigachev //#define CPL_BLOCK_COUNT 27 481*b843c749SSergey Zigachev 482*b843c749SSergey Zigachev #if defined SMU__VARIANT__ICELAND 483*b843c749SSergey Zigachev #define SX_BLOCK_COUNT 8 484*b843c749SSergey Zigachev #define MC_BLOCK_COUNT 1 485*b843c749SSergey Zigachev #define CPL_BLOCK_COUNT 29 486*b843c749SSergey Zigachev #endif 487*b843c749SSergey Zigachev 488*b843c749SSergey Zigachev struct SMU7_Local_Cac { 489*b843c749SSergey Zigachev uint8_t BlockId; 490*b843c749SSergey Zigachev uint8_t SignalId; 491*b843c749SSergey Zigachev uint8_t Threshold; 492*b843c749SSergey Zigachev uint8_t Padding; 493*b843c749SSergey Zigachev }; 494*b843c749SSergey Zigachev 495*b843c749SSergey Zigachev typedef struct SMU7_Local_Cac SMU7_Local_Cac; 496*b843c749SSergey Zigachev 497*b843c749SSergey Zigachev struct SMU7_Local_Cac_Table { 498*b843c749SSergey Zigachev SMU7_Local_Cac SxLocalCac[SX_BLOCK_COUNT]; 499*b843c749SSergey Zigachev SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT]; 500*b843c749SSergey Zigachev SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT]; 501*b843c749SSergey Zigachev }; 502*b843c749SSergey Zigachev 503*b843c749SSergey Zigachev typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table; 504*b843c749SSergey Zigachev 505*b843c749SSergey Zigachev #if !defined(SMC_MICROCODE) 506*b843c749SSergey Zigachev #pragma pack(pop) 507*b843c749SSergey Zigachev #endif 508*b843c749SSergey Zigachev 509*b843c749SSergey Zigachev #endif 510*b843c749SSergey Zigachev 511