1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2017 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef SMU72_DISCRETE_H 25*b843c749SSergey Zigachev #define SMU72_DISCRETE_H 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include "smu72.h" 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #if !defined(SMC_MICROCODE) 30*b843c749SSergey Zigachev #pragma pack(push, 1) 31*b843c749SSergey Zigachev #endif 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev struct SMIO_Pattern { 34*b843c749SSergey Zigachev uint16_t Voltage; 35*b843c749SSergey Zigachev uint8_t Smio; 36*b843c749SSergey Zigachev uint8_t padding; 37*b843c749SSergey Zigachev }; 38*b843c749SSergey Zigachev 39*b843c749SSergey Zigachev typedef struct SMIO_Pattern SMIO_Pattern; 40*b843c749SSergey Zigachev 41*b843c749SSergey Zigachev struct SMIO_Table { 42*b843c749SSergey Zigachev SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; 43*b843c749SSergey Zigachev }; 44*b843c749SSergey Zigachev 45*b843c749SSergey Zigachev typedef struct SMIO_Table SMIO_Table; 46*b843c749SSergey Zigachev 47*b843c749SSergey Zigachev struct SMU72_Discrete_GraphicsLevel { 48*b843c749SSergey Zigachev SMU_VoltageLevel MinVoltage; 49*b843c749SSergey Zigachev 50*b843c749SSergey Zigachev uint32_t SclkFrequency; 51*b843c749SSergey Zigachev 52*b843c749SSergey Zigachev uint8_t pcieDpmLevel; 53*b843c749SSergey Zigachev uint8_t DeepSleepDivId; 54*b843c749SSergey Zigachev uint16_t ActivityLevel; 55*b843c749SSergey Zigachev 56*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl3; 57*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl4; 58*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum; 59*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum2; 60*b843c749SSergey Zigachev uint32_t CcPwrDynRm; 61*b843c749SSergey Zigachev uint32_t CcPwrDynRm1; 62*b843c749SSergey Zigachev uint8_t SclkDid; 63*b843c749SSergey Zigachev uint8_t DisplayWatermark; 64*b843c749SSergey Zigachev uint8_t EnabledForActivity; 65*b843c749SSergey Zigachev uint8_t EnabledForThrottle; 66*b843c749SSergey Zigachev uint8_t UpHyst; 67*b843c749SSergey Zigachev uint8_t DownHyst; 68*b843c749SSergey Zigachev uint8_t VoltageDownHyst; 69*b843c749SSergey Zigachev uint8_t PowerThrottle; 70*b843c749SSergey Zigachev }; 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel; 73*b843c749SSergey Zigachev 74*b843c749SSergey Zigachev struct SMU72_Discrete_ACPILevel { 75*b843c749SSergey Zigachev uint32_t Flags; 76*b843c749SSergey Zigachev SMU_VoltageLevel MinVoltage; 77*b843c749SSergey Zigachev uint32_t SclkFrequency; 78*b843c749SSergey Zigachev uint8_t SclkDid; 79*b843c749SSergey Zigachev uint8_t DisplayWatermark; 80*b843c749SSergey Zigachev uint8_t DeepSleepDivId; 81*b843c749SSergey Zigachev uint8_t padding; 82*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl; 83*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl2; 84*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl3; 85*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl4; 86*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum; 87*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum2; 88*b843c749SSergey Zigachev uint32_t CcPwrDynRm; 89*b843c749SSergey Zigachev uint32_t CcPwrDynRm1; 90*b843c749SSergey Zigachev }; 91*b843c749SSergey Zigachev 92*b843c749SSergey Zigachev typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel; 93*b843c749SSergey Zigachev 94*b843c749SSergey Zigachev struct SMU72_Discrete_Ulv { 95*b843c749SSergey Zigachev uint32_t CcPwrDynRm; 96*b843c749SSergey Zigachev uint32_t CcPwrDynRm1; 97*b843c749SSergey Zigachev uint16_t VddcOffset; 98*b843c749SSergey Zigachev uint8_t VddcOffsetVid; 99*b843c749SSergey Zigachev uint8_t VddcPhase; 100*b843c749SSergey Zigachev uint32_t Reserved; 101*b843c749SSergey Zigachev }; 102*b843c749SSergey Zigachev 103*b843c749SSergey Zigachev typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv; 104*b843c749SSergey Zigachev 105*b843c749SSergey Zigachev struct SMU72_Discrete_MemoryLevel { 106*b843c749SSergey Zigachev SMU_VoltageLevel MinVoltage; 107*b843c749SSergey Zigachev uint32_t MinMvdd; 108*b843c749SSergey Zigachev 109*b843c749SSergey Zigachev uint32_t MclkFrequency; 110*b843c749SSergey Zigachev 111*b843c749SSergey Zigachev uint8_t EdcReadEnable; 112*b843c749SSergey Zigachev uint8_t EdcWriteEnable; 113*b843c749SSergey Zigachev uint8_t RttEnable; 114*b843c749SSergey Zigachev uint8_t StutterEnable; 115*b843c749SSergey Zigachev 116*b843c749SSergey Zigachev uint8_t StrobeEnable; 117*b843c749SSergey Zigachev uint8_t StrobeRatio; 118*b843c749SSergey Zigachev uint8_t EnabledForThrottle; 119*b843c749SSergey Zigachev uint8_t EnabledForActivity; 120*b843c749SSergey Zigachev 121*b843c749SSergey Zigachev uint8_t UpHyst; 122*b843c749SSergey Zigachev uint8_t DownHyst; 123*b843c749SSergey Zigachev uint8_t VoltageDownHyst; 124*b843c749SSergey Zigachev uint8_t padding; 125*b843c749SSergey Zigachev 126*b843c749SSergey Zigachev uint16_t ActivityLevel; 127*b843c749SSergey Zigachev uint8_t DisplayWatermark; 128*b843c749SSergey Zigachev uint8_t padding1; 129*b843c749SSergey Zigachev 130*b843c749SSergey Zigachev uint32_t MpllFuncCntl; 131*b843c749SSergey Zigachev uint32_t MpllFuncCntl_1; 132*b843c749SSergey Zigachev uint32_t MpllFuncCntl_2; 133*b843c749SSergey Zigachev uint32_t MpllAdFuncCntl; 134*b843c749SSergey Zigachev uint32_t MpllDqFuncCntl; 135*b843c749SSergey Zigachev uint32_t MclkPwrmgtCntl; 136*b843c749SSergey Zigachev uint32_t DllCntl; 137*b843c749SSergey Zigachev uint32_t MpllSs1; 138*b843c749SSergey Zigachev uint32_t MpllSs2; 139*b843c749SSergey Zigachev }; 140*b843c749SSergey Zigachev 141*b843c749SSergey Zigachev typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel; 142*b843c749SSergey Zigachev 143*b843c749SSergey Zigachev struct SMU72_Discrete_LinkLevel { 144*b843c749SSergey Zigachev uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */ 145*b843c749SSergey Zigachev uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */ 146*b843c749SSergey Zigachev uint8_t EnabledForActivity; 147*b843c749SSergey Zigachev uint8_t SPC; 148*b843c749SSergey Zigachev uint32_t DownThreshold; 149*b843c749SSergey Zigachev uint32_t UpThreshold; 150*b843c749SSergey Zigachev uint32_t Reserved; 151*b843c749SSergey Zigachev }; 152*b843c749SSergey Zigachev 153*b843c749SSergey Zigachev typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel; 154*b843c749SSergey Zigachev 155*b843c749SSergey Zigachev /* MC ARB DRAM Timing registers. */ 156*b843c749SSergey Zigachev struct SMU72_Discrete_MCArbDramTimingTableEntry { 157*b843c749SSergey Zigachev uint32_t McArbDramTiming; 158*b843c749SSergey Zigachev uint32_t McArbDramTiming2; 159*b843c749SSergey Zigachev uint8_t McArbBurstTime; 160*b843c749SSergey Zigachev uint8_t padding[3]; 161*b843c749SSergey Zigachev }; 162*b843c749SSergey Zigachev 163*b843c749SSergey Zigachev typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry; 164*b843c749SSergey Zigachev 165*b843c749SSergey Zigachev struct SMU72_Discrete_MCArbDramTimingTable { 166*b843c749SSergey Zigachev SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 167*b843c749SSergey Zigachev }; 168*b843c749SSergey Zigachev 169*b843c749SSergey Zigachev typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable; 170*b843c749SSergey Zigachev 171*b843c749SSergey Zigachev /* UVD VCLK/DCLK state (level) definition. */ 172*b843c749SSergey Zigachev struct SMU72_Discrete_UvdLevel { 173*b843c749SSergey Zigachev uint32_t VclkFrequency; 174*b843c749SSergey Zigachev uint32_t DclkFrequency; 175*b843c749SSergey Zigachev SMU_VoltageLevel MinVoltage; 176*b843c749SSergey Zigachev uint8_t VclkDivider; 177*b843c749SSergey Zigachev uint8_t DclkDivider; 178*b843c749SSergey Zigachev uint8_t padding[2]; 179*b843c749SSergey Zigachev }; 180*b843c749SSergey Zigachev 181*b843c749SSergey Zigachev typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel; 182*b843c749SSergey Zigachev 183*b843c749SSergey Zigachev /* Clocks for other external blocks (VCE, ACP, SAMU). */ 184*b843c749SSergey Zigachev struct SMU72_Discrete_ExtClkLevel { 185*b843c749SSergey Zigachev uint32_t Frequency; 186*b843c749SSergey Zigachev SMU_VoltageLevel MinVoltage; 187*b843c749SSergey Zigachev uint8_t Divider; 188*b843c749SSergey Zigachev uint8_t padding[3]; 189*b843c749SSergey Zigachev }; 190*b843c749SSergey Zigachev 191*b843c749SSergey Zigachev typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel; 192*b843c749SSergey Zigachev 193*b843c749SSergey Zigachev struct SMU72_Discrete_StateInfo { 194*b843c749SSergey Zigachev uint32_t SclkFrequency; 195*b843c749SSergey Zigachev uint32_t MclkFrequency; 196*b843c749SSergey Zigachev uint32_t VclkFrequency; 197*b843c749SSergey Zigachev uint32_t DclkFrequency; 198*b843c749SSergey Zigachev uint32_t SamclkFrequency; 199*b843c749SSergey Zigachev uint32_t AclkFrequency; 200*b843c749SSergey Zigachev uint32_t EclkFrequency; 201*b843c749SSergey Zigachev uint16_t MvddVoltage; 202*b843c749SSergey Zigachev uint16_t padding16; 203*b843c749SSergey Zigachev uint8_t DisplayWatermark; 204*b843c749SSergey Zigachev uint8_t McArbIndex; 205*b843c749SSergey Zigachev uint8_t McRegIndex; 206*b843c749SSergey Zigachev uint8_t SeqIndex; 207*b843c749SSergey Zigachev uint8_t SclkDid; 208*b843c749SSergey Zigachev int8_t SclkIndex; 209*b843c749SSergey Zigachev int8_t MclkIndex; 210*b843c749SSergey Zigachev uint8_t PCIeGen; 211*b843c749SSergey Zigachev 212*b843c749SSergey Zigachev }; 213*b843c749SSergey Zigachev 214*b843c749SSergey Zigachev typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo; 215*b843c749SSergey Zigachev 216*b843c749SSergey Zigachev struct SMU72_Discrete_DpmTable { 217*b843c749SSergey Zigachev /* Multi-DPM controller settings */ 218*b843c749SSergey Zigachev SMU72_PIDController GraphicsPIDController; 219*b843c749SSergey Zigachev SMU72_PIDController MemoryPIDController; 220*b843c749SSergey Zigachev SMU72_PIDController LinkPIDController; 221*b843c749SSergey Zigachev 222*b843c749SSergey Zigachev uint32_t SystemFlags; 223*b843c749SSergey Zigachev 224*b843c749SSergey Zigachev /* SMIO masks for voltage and phase controls */ 225*b843c749SSergey Zigachev uint32_t VRConfig; 226*b843c749SSergey Zigachev uint32_t SmioMask1; 227*b843c749SSergey Zigachev uint32_t SmioMask2; 228*b843c749SSergey Zigachev SMIO_Table SmioTable1; 229*b843c749SSergey Zigachev SMIO_Table SmioTable2; 230*b843c749SSergey Zigachev 231*b843c749SSergey Zigachev uint32_t VddcLevelCount; 232*b843c749SSergey Zigachev uint32_t VddciLevelCount; 233*b843c749SSergey Zigachev uint32_t VddGfxLevelCount; 234*b843c749SSergey Zigachev uint32_t MvddLevelCount; 235*b843c749SSergey Zigachev 236*b843c749SSergey Zigachev uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC]; 237*b843c749SSergey Zigachev uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX]; 238*b843c749SSergey Zigachev uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI]; 239*b843c749SSergey Zigachev 240*b843c749SSergey Zigachev uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX]; 241*b843c749SSergey Zigachev uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX]; 242*b843c749SSergey Zigachev uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX]; 243*b843c749SSergey Zigachev 244*b843c749SSergey Zigachev uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC]; 245*b843c749SSergey Zigachev uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC]; 246*b843c749SSergey Zigachev uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC]; 247*b843c749SSergey Zigachev 248*b843c749SSergey Zigachev uint8_t GraphicsDpmLevelCount; 249*b843c749SSergey Zigachev uint8_t MemoryDpmLevelCount; 250*b843c749SSergey Zigachev uint8_t LinkLevelCount; 251*b843c749SSergey Zigachev uint8_t MasterDeepSleepControl; 252*b843c749SSergey Zigachev 253*b843c749SSergey Zigachev uint8_t UvdLevelCount; 254*b843c749SSergey Zigachev uint8_t VceLevelCount; 255*b843c749SSergey Zigachev uint8_t AcpLevelCount; 256*b843c749SSergey Zigachev uint8_t SamuLevelCount; 257*b843c749SSergey Zigachev 258*b843c749SSergey Zigachev uint8_t ThermOutGpio; 259*b843c749SSergey Zigachev uint8_t ThermOutPolarity; 260*b843c749SSergey Zigachev uint8_t ThermOutMode; 261*b843c749SSergey Zigachev uint8_t DPMFreezeAndForced; 262*b843c749SSergey Zigachev uint32_t Reserved[4]; 263*b843c749SSergey Zigachev 264*b843c749SSergey Zigachev /* State table entries for each DPM state */ 265*b843c749SSergey Zigachev SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS]; 266*b843c749SSergey Zigachev SMU72_Discrete_MemoryLevel MemoryACPILevel; 267*b843c749SSergey Zigachev SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY]; 268*b843c749SSergey Zigachev SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK]; 269*b843c749SSergey Zigachev SMU72_Discrete_ACPILevel ACPILevel; 270*b843c749SSergey Zigachev SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD]; 271*b843c749SSergey Zigachev SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE]; 272*b843c749SSergey Zigachev SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP]; 273*b843c749SSergey Zigachev SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU]; 274*b843c749SSergey Zigachev SMU72_Discrete_Ulv Ulv; 275*b843c749SSergey Zigachev 276*b843c749SSergey Zigachev uint32_t SclkStepSize; 277*b843c749SSergey Zigachev uint32_t Smio[SMU72_MAX_ENTRIES_SMIO]; 278*b843c749SSergey Zigachev 279*b843c749SSergey Zigachev uint8_t UvdBootLevel; 280*b843c749SSergey Zigachev uint8_t VceBootLevel; 281*b843c749SSergey Zigachev uint8_t AcpBootLevel; 282*b843c749SSergey Zigachev uint8_t SamuBootLevel; 283*b843c749SSergey Zigachev 284*b843c749SSergey Zigachev uint8_t GraphicsBootLevel; 285*b843c749SSergey Zigachev uint8_t GraphicsVoltageChangeEnable; 286*b843c749SSergey Zigachev uint8_t GraphicsThermThrottleEnable; 287*b843c749SSergey Zigachev uint8_t GraphicsInterval; 288*b843c749SSergey Zigachev 289*b843c749SSergey Zigachev uint8_t VoltageInterval; 290*b843c749SSergey Zigachev uint8_t ThermalInterval; 291*b843c749SSergey Zigachev uint16_t TemperatureLimitHigh; 292*b843c749SSergey Zigachev 293*b843c749SSergey Zigachev uint16_t TemperatureLimitLow; 294*b843c749SSergey Zigachev uint8_t MemoryBootLevel; 295*b843c749SSergey Zigachev uint8_t MemoryVoltageChangeEnable; 296*b843c749SSergey Zigachev 297*b843c749SSergey Zigachev uint16_t BootMVdd; 298*b843c749SSergey Zigachev uint8_t MemoryInterval; 299*b843c749SSergey Zigachev uint8_t MemoryThermThrottleEnable; 300*b843c749SSergey Zigachev 301*b843c749SSergey Zigachev uint16_t VoltageResponseTime; 302*b843c749SSergey Zigachev uint16_t PhaseResponseTime; 303*b843c749SSergey Zigachev 304*b843c749SSergey Zigachev uint8_t PCIeBootLinkLevel; 305*b843c749SSergey Zigachev uint8_t PCIeGenInterval; 306*b843c749SSergey Zigachev uint8_t DTEInterval; 307*b843c749SSergey Zigachev uint8_t DTEMode; 308*b843c749SSergey Zigachev 309*b843c749SSergey Zigachev uint8_t SVI2Enable; 310*b843c749SSergey Zigachev uint8_t VRHotGpio; 311*b843c749SSergey Zigachev uint8_t AcDcGpio; 312*b843c749SSergey Zigachev uint8_t ThermGpio; 313*b843c749SSergey Zigachev 314*b843c749SSergey Zigachev uint16_t PPM_PkgPwrLimit; 315*b843c749SSergey Zigachev uint16_t PPM_TemperatureLimit; 316*b843c749SSergey Zigachev 317*b843c749SSergey Zigachev uint16_t DefaultTdp; 318*b843c749SSergey Zigachev uint16_t TargetTdp; 319*b843c749SSergey Zigachev 320*b843c749SSergey Zigachev uint16_t FpsHighThreshold; 321*b843c749SSergey Zigachev uint16_t FpsLowThreshold; 322*b843c749SSergey Zigachev 323*b843c749SSergey Zigachev uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; 324*b843c749SSergey Zigachev uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS]; 325*b843c749SSergey Zigachev 326*b843c749SSergey Zigachev uint8_t DTEAmbientTempBase; 327*b843c749SSergey Zigachev uint8_t DTETjOffset; 328*b843c749SSergey Zigachev uint8_t GpuTjMax; 329*b843c749SSergey Zigachev uint8_t GpuTjHyst; 330*b843c749SSergey Zigachev 331*b843c749SSergey Zigachev SMU_VoltageLevel BootVoltage; 332*b843c749SSergey Zigachev 333*b843c749SSergey Zigachev uint32_t BAPM_TEMP_GRADIENT; 334*b843c749SSergey Zigachev 335*b843c749SSergey Zigachev uint32_t LowSclkInterruptThreshold; 336*b843c749SSergey Zigachev uint32_t VddGfxReChkWait; 337*b843c749SSergey Zigachev 338*b843c749SSergey Zigachev uint8_t ClockStretcherAmount; 339*b843c749SSergey Zigachev 340*b843c749SSergey Zigachev uint8_t Sclk_CKS_masterEn0_7; 341*b843c749SSergey Zigachev uint8_t Sclk_CKS_masterEn8_15; 342*b843c749SSergey Zigachev uint8_t padding[1]; 343*b843c749SSergey Zigachev 344*b843c749SSergey Zigachev uint8_t Sclk_voltageOffset[8]; 345*b843c749SSergey Zigachev 346*b843c749SSergey Zigachev SMU_ClockStretcherDataTable ClockStretcherDataTable; 347*b843c749SSergey Zigachev SMU_CKS_LOOKUPTable CKS_LOOKUPTable; 348*b843c749SSergey Zigachev }; 349*b843c749SSergey Zigachev 350*b843c749SSergey Zigachev typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable; 351*b843c749SSergey Zigachev 352*b843c749SSergey Zigachev /* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */ 353*b843c749SSergey Zigachev #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16 354*b843c749SSergey Zigachev #define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */ 355*b843c749SSergey Zigachev 356*b843c749SSergey Zigachev struct SMU72_Discrete_MCRegisterAddress { 357*b843c749SSergey Zigachev uint16_t s0; 358*b843c749SSergey Zigachev uint16_t s1; 359*b843c749SSergey Zigachev }; 360*b843c749SSergey Zigachev 361*b843c749SSergey Zigachev typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress; 362*b843c749SSergey Zigachev 363*b843c749SSergey Zigachev struct SMU72_Discrete_MCRegisterSet { 364*b843c749SSergey Zigachev uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 365*b843c749SSergey Zigachev }; 366*b843c749SSergey Zigachev 367*b843c749SSergey Zigachev typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet; 368*b843c749SSergey Zigachev 369*b843c749SSergey Zigachev struct SMU72_Discrete_MCRegisters { 370*b843c749SSergey Zigachev uint8_t last; 371*b843c749SSergey Zigachev uint8_t reserved[3]; 372*b843c749SSergey Zigachev SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE]; 373*b843c749SSergey Zigachev SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT]; 374*b843c749SSergey Zigachev }; 375*b843c749SSergey Zigachev 376*b843c749SSergey Zigachev typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters; 377*b843c749SSergey Zigachev 378*b843c749SSergey Zigachev 379*b843c749SSergey Zigachev /* --------------------------------------------------- Fan Table ----------------------------------------------------------- */ 380*b843c749SSergey Zigachev 381*b843c749SSergey Zigachev struct SMU72_Discrete_FanTable { 382*b843c749SSergey Zigachev uint16_t FdoMode; 383*b843c749SSergey Zigachev int16_t TempMin; 384*b843c749SSergey Zigachev int16_t TempMed; 385*b843c749SSergey Zigachev int16_t TempMax; 386*b843c749SSergey Zigachev int16_t Slope1; 387*b843c749SSergey Zigachev int16_t Slope2; 388*b843c749SSergey Zigachev int16_t FdoMin; 389*b843c749SSergey Zigachev int16_t HystUp; 390*b843c749SSergey Zigachev int16_t HystDown; 391*b843c749SSergey Zigachev int16_t HystSlope; 392*b843c749SSergey Zigachev int16_t TempRespLim; 393*b843c749SSergey Zigachev int16_t TempCurr; 394*b843c749SSergey Zigachev int16_t SlopeCurr; 395*b843c749SSergey Zigachev int16_t PwmCurr; 396*b843c749SSergey Zigachev uint32_t RefreshPeriod; 397*b843c749SSergey Zigachev int16_t FdoMax; 398*b843c749SSergey Zigachev uint8_t TempSrc; 399*b843c749SSergey Zigachev int8_t FanControl_GL_Flag; 400*b843c749SSergey Zigachev }; 401*b843c749SSergey Zigachev 402*b843c749SSergey Zigachev typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable; 403*b843c749SSergey Zigachev 404*b843c749SSergey Zigachev #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 405*b843c749SSergey Zigachev #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 406*b843c749SSergey Zigachev 407*b843c749SSergey Zigachev struct SMU7_MclkDpmScoreboard { 408*b843c749SSergey Zigachev 409*b843c749SSergey Zigachev uint32_t PercentageBusy; 410*b843c749SSergey Zigachev 411*b843c749SSergey Zigachev int32_t PIDError; 412*b843c749SSergey Zigachev int32_t PIDIntegral; 413*b843c749SSergey Zigachev int32_t PIDOutput; 414*b843c749SSergey Zigachev 415*b843c749SSergey Zigachev uint32_t SigmaDeltaAccum; 416*b843c749SSergey Zigachev uint32_t SigmaDeltaOutput; 417*b843c749SSergey Zigachev uint32_t SigmaDeltaLevel; 418*b843c749SSergey Zigachev 419*b843c749SSergey Zigachev uint32_t UtilizationSetpoint; 420*b843c749SSergey Zigachev 421*b843c749SSergey Zigachev uint8_t TdpClampMode; 422*b843c749SSergey Zigachev uint8_t TdcClampMode; 423*b843c749SSergey Zigachev uint8_t ThermClampMode; 424*b843c749SSergey Zigachev uint8_t VoltageBusy; 425*b843c749SSergey Zigachev 426*b843c749SSergey Zigachev int8_t CurrLevel; 427*b843c749SSergey Zigachev int8_t TargLevel; 428*b843c749SSergey Zigachev uint8_t LevelChangeInProgress; 429*b843c749SSergey Zigachev uint8_t UpHyst; 430*b843c749SSergey Zigachev 431*b843c749SSergey Zigachev uint8_t DownHyst; 432*b843c749SSergey Zigachev uint8_t VoltageDownHyst; 433*b843c749SSergey Zigachev uint8_t DpmEnable; 434*b843c749SSergey Zigachev uint8_t DpmRunning; 435*b843c749SSergey Zigachev 436*b843c749SSergey Zigachev uint8_t DpmForce; 437*b843c749SSergey Zigachev uint8_t DpmForceLevel; 438*b843c749SSergey Zigachev uint8_t DisplayWatermark; 439*b843c749SSergey Zigachev uint8_t McArbIndex; 440*b843c749SSergey Zigachev 441*b843c749SSergey Zigachev uint32_t MinimumPerfMclk; 442*b843c749SSergey Zigachev 443*b843c749SSergey Zigachev uint8_t AcpiReq; 444*b843c749SSergey Zigachev uint8_t AcpiAck; 445*b843c749SSergey Zigachev uint8_t MclkSwitchInProgress; 446*b843c749SSergey Zigachev uint8_t MclkSwitchCritical; 447*b843c749SSergey Zigachev 448*b843c749SSergey Zigachev uint8_t IgnoreVBlank; 449*b843c749SSergey Zigachev uint8_t TargetMclkIndex; 450*b843c749SSergey Zigachev uint8_t TargetMvddIndex; 451*b843c749SSergey Zigachev uint8_t MclkSwitchResult; 452*b843c749SSergey Zigachev 453*b843c749SSergey Zigachev uint16_t VbiFailureCount; 454*b843c749SSergey Zigachev uint8_t VbiWaitCounter; 455*b843c749SSergey Zigachev uint8_t EnabledLevelsChange; 456*b843c749SSergey Zigachev 457*b843c749SSergey Zigachev uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY]; 458*b843c749SSergey Zigachev uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY]; 459*b843c749SSergey Zigachev 460*b843c749SSergey Zigachev void (*TargetStateCalculator)(uint8_t); 461*b843c749SSergey Zigachev void (*SavedTargetStateCalculator)(uint8_t); 462*b843c749SSergey Zigachev 463*b843c749SSergey Zigachev uint16_t AutoDpmInterval; 464*b843c749SSergey Zigachev uint16_t AutoDpmRange; 465*b843c749SSergey Zigachev 466*b843c749SSergey Zigachev uint16_t VbiTimeoutCount; 467*b843c749SSergey Zigachev uint16_t MclkSwitchingTime; 468*b843c749SSergey Zigachev 469*b843c749SSergey Zigachev uint8_t fastSwitch; 470*b843c749SSergey Zigachev uint8_t Save_PIC_VDDGFX_EXIT; 471*b843c749SSergey Zigachev uint8_t Save_PIC_VDDGFX_ENTER; 472*b843c749SSergey Zigachev uint8_t padding; 473*b843c749SSergey Zigachev 474*b843c749SSergey Zigachev }; 475*b843c749SSergey Zigachev 476*b843c749SSergey Zigachev typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; 477*b843c749SSergey Zigachev 478*b843c749SSergey Zigachev struct SMU7_UlvScoreboard { 479*b843c749SSergey Zigachev uint8_t EnterUlv; 480*b843c749SSergey Zigachev uint8_t ExitUlv; 481*b843c749SSergey Zigachev uint8_t UlvActive; 482*b843c749SSergey Zigachev uint8_t WaitingForUlv; 483*b843c749SSergey Zigachev uint8_t UlvEnable; 484*b843c749SSergey Zigachev uint8_t UlvRunning; 485*b843c749SSergey Zigachev uint8_t UlvMasterEnable; 486*b843c749SSergey Zigachev uint8_t padding; 487*b843c749SSergey Zigachev uint32_t UlvAbortedCount; 488*b843c749SSergey Zigachev uint32_t UlvTimeStamp; 489*b843c749SSergey Zigachev }; 490*b843c749SSergey Zigachev 491*b843c749SSergey Zigachev typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; 492*b843c749SSergey Zigachev 493*b843c749SSergey Zigachev struct VddgfxSavedRegisters { 494*b843c749SSergey Zigachev uint32_t GPU_DBG[3]; 495*b843c749SSergey Zigachev uint32_t MEC_BaseAddress_Hi; 496*b843c749SSergey Zigachev uint32_t MEC_BaseAddress_Lo; 497*b843c749SSergey Zigachev uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; 498*b843c749SSergey Zigachev uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; 499*b843c749SSergey Zigachev uint32_t CP_INT_CNTL; 500*b843c749SSergey Zigachev }; 501*b843c749SSergey Zigachev 502*b843c749SSergey Zigachev typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; 503*b843c749SSergey Zigachev 504*b843c749SSergey Zigachev struct SMU7_VddGfxScoreboard { 505*b843c749SSergey Zigachev uint8_t VddGfxEnable; 506*b843c749SSergey Zigachev uint8_t VddGfxActive; 507*b843c749SSergey Zigachev uint8_t VPUResetOccured; 508*b843c749SSergey Zigachev uint8_t padding; 509*b843c749SSergey Zigachev 510*b843c749SSergey Zigachev uint32_t VddGfxEnteredCount; 511*b843c749SSergey Zigachev uint32_t VddGfxAbortedCount; 512*b843c749SSergey Zigachev 513*b843c749SSergey Zigachev uint32_t VddGfxVid; 514*b843c749SSergey Zigachev 515*b843c749SSergey Zigachev VddgfxSavedRegisters SavedRegisters; 516*b843c749SSergey Zigachev }; 517*b843c749SSergey Zigachev 518*b843c749SSergey Zigachev typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; 519*b843c749SSergey Zigachev 520*b843c749SSergey Zigachev struct SMU7_TdcLimitScoreboard { 521*b843c749SSergey Zigachev uint8_t Enable; 522*b843c749SSergey Zigachev uint8_t Running; 523*b843c749SSergey Zigachev uint16_t Alpha; 524*b843c749SSergey Zigachev uint32_t FilteredIddc; 525*b843c749SSergey Zigachev uint32_t IddcLimit; 526*b843c749SSergey Zigachev uint32_t IddcHyst; 527*b843c749SSergey Zigachev SMU7_HystController_Data HystControllerData; 528*b843c749SSergey Zigachev }; 529*b843c749SSergey Zigachev 530*b843c749SSergey Zigachev typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; 531*b843c749SSergey Zigachev 532*b843c749SSergey Zigachev struct SMU7_PkgPwrLimitScoreboard { 533*b843c749SSergey Zigachev uint8_t Enable; 534*b843c749SSergey Zigachev uint8_t Running; 535*b843c749SSergey Zigachev uint16_t Alpha; 536*b843c749SSergey Zigachev uint32_t FilteredPkgPwr; 537*b843c749SSergey Zigachev uint32_t Limit; 538*b843c749SSergey Zigachev uint32_t Hyst; 539*b843c749SSergey Zigachev uint32_t LimitFromDriver; 540*b843c749SSergey Zigachev SMU7_HystController_Data HystControllerData; 541*b843c749SSergey Zigachev }; 542*b843c749SSergey Zigachev 543*b843c749SSergey Zigachev typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; 544*b843c749SSergey Zigachev 545*b843c749SSergey Zigachev struct SMU7_BapmScoreboard { 546*b843c749SSergey Zigachev uint32_t source_powers[SMU72_DTE_SOURCES]; 547*b843c749SSergey Zigachev uint32_t source_powers_last[SMU72_DTE_SOURCES]; 548*b843c749SSergey Zigachev int32_t entity_temperatures[SMU72_NUM_GPU_TES]; 549*b843c749SSergey Zigachev int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES]; 550*b843c749SSergey Zigachev int32_t Limit; 551*b843c749SSergey Zigachev int32_t Hyst; 552*b843c749SSergey Zigachev int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2]; 553*b843c749SSergey Zigachev int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS]; 554*b843c749SSergey Zigachev uint16_t ConfigTDPPowerScalar; 555*b843c749SSergey Zigachev uint16_t FanSpeedPowerScalar; 556*b843c749SSergey Zigachev uint16_t OverDrivePowerScalar; 557*b843c749SSergey Zigachev uint16_t OverDriveLimitScalar; 558*b843c749SSergey Zigachev uint16_t FinalPowerScalar; 559*b843c749SSergey Zigachev uint8_t VariantID; 560*b843c749SSergey Zigachev uint8_t spare997; 561*b843c749SSergey Zigachev 562*b843c749SSergey Zigachev SMU7_HystController_Data HystControllerData; 563*b843c749SSergey Zigachev 564*b843c749SSergey Zigachev int32_t temperature_gradient_slope; 565*b843c749SSergey Zigachev int32_t temperature_gradient; 566*b843c749SSergey Zigachev uint32_t measured_temperature; 567*b843c749SSergey Zigachev }; 568*b843c749SSergey Zigachev 569*b843c749SSergey Zigachev 570*b843c749SSergey Zigachev typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; 571*b843c749SSergey Zigachev 572*b843c749SSergey Zigachev struct SMU7_AcpiScoreboard { 573*b843c749SSergey Zigachev uint32_t SavedInterruptMask[2]; 574*b843c749SSergey Zigachev uint8_t LastACPIRequest; 575*b843c749SSergey Zigachev uint8_t CgBifResp; 576*b843c749SSergey Zigachev uint8_t RequestType; 577*b843c749SSergey Zigachev uint8_t Padding; 578*b843c749SSergey Zigachev SMU72_Discrete_ACPILevel D0Level; 579*b843c749SSergey Zigachev }; 580*b843c749SSergey Zigachev 581*b843c749SSergey Zigachev typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 582*b843c749SSergey Zigachev 583*b843c749SSergey Zigachev struct SMU72_Discrete_PmFuses { 584*b843c749SSergey Zigachev /* dw1 */ 585*b843c749SSergey Zigachev uint8_t SviLoadLineEn; 586*b843c749SSergey Zigachev uint8_t SviLoadLineVddC; 587*b843c749SSergey Zigachev uint8_t SviLoadLineTrimVddC; 588*b843c749SSergey Zigachev uint8_t SviLoadLineOffsetVddC; 589*b843c749SSergey Zigachev 590*b843c749SSergey Zigachev /* dw2 */ 591*b843c749SSergey Zigachev uint16_t TDC_VDDC_PkgLimit; 592*b843c749SSergey Zigachev uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 593*b843c749SSergey Zigachev uint8_t TDC_MAWt; 594*b843c749SSergey Zigachev 595*b843c749SSergey Zigachev /* dw3 */ 596*b843c749SSergey Zigachev uint8_t TdcWaterfallCtl; 597*b843c749SSergey Zigachev uint8_t LPMLTemperatureMin; 598*b843c749SSergey Zigachev uint8_t LPMLTemperatureMax; 599*b843c749SSergey Zigachev uint8_t Reserved; 600*b843c749SSergey Zigachev 601*b843c749SSergey Zigachev /* dw4-dw7 */ 602*b843c749SSergey Zigachev uint8_t LPMLTemperatureScaler[16]; 603*b843c749SSergey Zigachev 604*b843c749SSergey Zigachev /* dw8-dw9 */ 605*b843c749SSergey Zigachev int16_t FuzzyFan_ErrorSetDelta; 606*b843c749SSergey Zigachev int16_t FuzzyFan_ErrorRateSetDelta; 607*b843c749SSergey Zigachev int16_t FuzzyFan_PwmSetDelta; 608*b843c749SSergey Zigachev uint16_t Reserved6; 609*b843c749SSergey Zigachev 610*b843c749SSergey Zigachev /* dw10-dw14 */ 611*b843c749SSergey Zigachev uint8_t GnbLPML[16]; 612*b843c749SSergey Zigachev 613*b843c749SSergey Zigachev /* dw15 */ 614*b843c749SSergey Zigachev uint8_t GnbLPMLMaxVid; 615*b843c749SSergey Zigachev uint8_t GnbLPMLMinVid; 616*b843c749SSergey Zigachev uint8_t Reserved1[2]; 617*b843c749SSergey Zigachev 618*b843c749SSergey Zigachev /* dw16 */ 619*b843c749SSergey Zigachev uint16_t BapmVddCBaseLeakageHiSidd; 620*b843c749SSergey Zigachev uint16_t BapmVddCBaseLeakageLoSidd; 621*b843c749SSergey Zigachev }; 622*b843c749SSergey Zigachev 623*b843c749SSergey Zigachev typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses; 624*b843c749SSergey Zigachev 625*b843c749SSergey Zigachev struct SMU7_Discrete_Log_Header_Table { 626*b843c749SSergey Zigachev uint32_t version; 627*b843c749SSergey Zigachev uint32_t asic_id; 628*b843c749SSergey Zigachev uint16_t flags; 629*b843c749SSergey Zigachev uint16_t entry_size; 630*b843c749SSergey Zigachev uint32_t total_size; 631*b843c749SSergey Zigachev uint32_t num_of_entries; 632*b843c749SSergey Zigachev uint8_t type; 633*b843c749SSergey Zigachev uint8_t mode; 634*b843c749SSergey Zigachev uint8_t filler_0[2]; 635*b843c749SSergey Zigachev uint32_t filler_1[2]; 636*b843c749SSergey Zigachev }; 637*b843c749SSergey Zigachev 638*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; 639*b843c749SSergey Zigachev 640*b843c749SSergey Zigachev struct SMU7_Discrete_Log_Cntl { 641*b843c749SSergey Zigachev uint8_t Enabled; 642*b843c749SSergey Zigachev uint8_t Type; 643*b843c749SSergey Zigachev uint8_t padding[2]; 644*b843c749SSergey Zigachev uint32_t BufferSize; 645*b843c749SSergey Zigachev uint32_t SamplesLogged; 646*b843c749SSergey Zigachev uint32_t SampleSize; 647*b843c749SSergey Zigachev uint32_t AddrL; 648*b843c749SSergey Zigachev uint32_t AddrH; 649*b843c749SSergey Zigachev }; 650*b843c749SSergey Zigachev 651*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; 652*b843c749SSergey Zigachev 653*b843c749SSergey Zigachev #define CAC_ACC_NW_NUM_OF_SIGNALS 87 654*b843c749SSergey Zigachev 655*b843c749SSergey Zigachev struct SMU7_Discrete_Cac_Collection_Table { 656*b843c749SSergey Zigachev uint32_t temperature; 657*b843c749SSergey Zigachev uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 658*b843c749SSergey Zigachev }; 659*b843c749SSergey Zigachev 660*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; 661*b843c749SSergey Zigachev 662*b843c749SSergey Zigachev struct SMU7_Discrete_Cac_Verification_Table { 663*b843c749SSergey Zigachev uint32_t VddcTotalPower; 664*b843c749SSergey Zigachev uint32_t VddcLeakagePower; 665*b843c749SSergey Zigachev uint32_t VddcConstantPower; 666*b843c749SSergey Zigachev uint32_t VddcGfxDynamicPower; 667*b843c749SSergey Zigachev uint32_t VddcUvdDynamicPower; 668*b843c749SSergey Zigachev uint32_t VddcVceDynamicPower; 669*b843c749SSergey Zigachev uint32_t VddcAcpDynamicPower; 670*b843c749SSergey Zigachev uint32_t VddcPcieDynamicPower; 671*b843c749SSergey Zigachev uint32_t VddcDceDynamicPower; 672*b843c749SSergey Zigachev uint32_t VddcCurrent; 673*b843c749SSergey Zigachev uint32_t VddcVoltage; 674*b843c749SSergey Zigachev uint32_t VddciTotalPower; 675*b843c749SSergey Zigachev uint32_t VddciLeakagePower; 676*b843c749SSergey Zigachev uint32_t VddciConstantPower; 677*b843c749SSergey Zigachev uint32_t VddciDynamicPower; 678*b843c749SSergey Zigachev uint32_t Vddr1TotalPower; 679*b843c749SSergey Zigachev uint32_t Vddr1LeakagePower; 680*b843c749SSergey Zigachev uint32_t Vddr1ConstantPower; 681*b843c749SSergey Zigachev uint32_t Vddr1DynamicPower; 682*b843c749SSergey Zigachev uint32_t spare[4]; 683*b843c749SSergey Zigachev uint32_t temperature; 684*b843c749SSergey Zigachev }; 685*b843c749SSergey Zigachev 686*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; 687*b843c749SSergey Zigachev 688*b843c749SSergey Zigachev struct SMU7_Discrete_Pm_Status_Table { 689*b843c749SSergey Zigachev /* Thermal entities */ 690*b843c749SSergey Zigachev int32_t T_meas_max; 691*b843c749SSergey Zigachev int32_t T_meas_acc; 692*b843c749SSergey Zigachev int32_t T_calc_max; 693*b843c749SSergey Zigachev int32_t T_calc_acc; 694*b843c749SSergey Zigachev uint32_t P_scalar_acc; 695*b843c749SSergey Zigachev uint32_t P_calc_max; 696*b843c749SSergey Zigachev uint32_t P_calc_acc; 697*b843c749SSergey Zigachev 698*b843c749SSergey Zigachev /*Voltage domains */ 699*b843c749SSergey Zigachev uint32_t I_calc_max; 700*b843c749SSergey Zigachev uint32_t I_calc_acc; 701*b843c749SSergey Zigachev uint32_t I_calc_acc_vddci; 702*b843c749SSergey Zigachev uint32_t V_calc_noload_acc; 703*b843c749SSergey Zigachev uint32_t V_calc_load_acc; 704*b843c749SSergey Zigachev uint32_t V_calc_noload_acc_vddci; 705*b843c749SSergey Zigachev uint32_t P_meas_acc; 706*b843c749SSergey Zigachev uint32_t V_meas_noload_acc; 707*b843c749SSergey Zigachev uint32_t V_meas_load_acc; 708*b843c749SSergey Zigachev uint32_t I_meas_acc; 709*b843c749SSergey Zigachev uint32_t P_meas_acc_vddci; 710*b843c749SSergey Zigachev uint32_t V_meas_noload_acc_vddci; 711*b843c749SSergey Zigachev uint32_t V_meas_load_acc_vddci; 712*b843c749SSergey Zigachev uint32_t I_meas_acc_vddci; 713*b843c749SSergey Zigachev 714*b843c749SSergey Zigachev /*Frequency */ 715*b843c749SSergey Zigachev uint16_t Sclk_dpm_residency[8]; 716*b843c749SSergey Zigachev uint16_t Uvd_dpm_residency[8]; 717*b843c749SSergey Zigachev uint16_t Vce_dpm_residency[8]; 718*b843c749SSergey Zigachev uint16_t Mclk_dpm_residency[4]; 719*b843c749SSergey Zigachev 720*b843c749SSergey Zigachev /*Chip */ 721*b843c749SSergey Zigachev uint32_t P_vddci_acc; 722*b843c749SSergey Zigachev uint32_t P_vddr1_acc; 723*b843c749SSergey Zigachev uint32_t P_nte1_acc; 724*b843c749SSergey Zigachev uint32_t PkgPwr_max; 725*b843c749SSergey Zigachev uint32_t PkgPwr_acc; 726*b843c749SSergey Zigachev uint32_t MclkSwitchingTime_max; 727*b843c749SSergey Zigachev uint32_t MclkSwitchingTime_acc; 728*b843c749SSergey Zigachev uint32_t FanPwm_acc; 729*b843c749SSergey Zigachev uint32_t FanRpm_acc; 730*b843c749SSergey Zigachev 731*b843c749SSergey Zigachev uint32_t AccCnt; 732*b843c749SSergey Zigachev }; 733*b843c749SSergey Zigachev 734*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; 735*b843c749SSergey Zigachev 736*b843c749SSergey Zigachev /*FIXME THESE NEED TO BE UPDATED */ 737*b843c749SSergey Zigachev #define SMU7_SCLK_CAC 0x561 738*b843c749SSergey Zigachev #define SMU7_MCLK_CAC 0xF9 739*b843c749SSergey Zigachev #define SMU7_VCLK_CAC 0x2DE 740*b843c749SSergey Zigachev #define SMU7_DCLK_CAC 0x2DE 741*b843c749SSergey Zigachev #define SMU7_ECLK_CAC 0x25E 742*b843c749SSergey Zigachev #define SMU7_ACLK_CAC 0x25E 743*b843c749SSergey Zigachev #define SMU7_SAMCLK_CAC 0x25E 744*b843c749SSergey Zigachev #define SMU7_DISPCLK_CAC 0x100 745*b843c749SSergey Zigachev #define SMU7_CAC_CONSTANT 0x2EE3430 746*b843c749SSergey Zigachev #define SMU7_CAC_CONSTANT_SHIFT 18 747*b843c749SSergey Zigachev 748*b843c749SSergey Zigachev #define SMU7_VDDCI_MCLK_CONST 1765 749*b843c749SSergey Zigachev #define SMU7_VDDCI_MCLK_CONST_SHIFT 16 750*b843c749SSergey Zigachev #define SMU7_VDDCI_VDDCI_CONST 50958 751*b843c749SSergey Zigachev #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 752*b843c749SSergey Zigachev #define SMU7_VDDCI_CONST 11781 753*b843c749SSergey Zigachev 754*b843c749SSergey Zigachev #define SMU7_12C_VDDCI_MCLK_CONST 1623 755*b843c749SSergey Zigachev #define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15 756*b843c749SSergey Zigachev #define SMU7_12C_VDDCI_VDDCI_CONST 40088 757*b843c749SSergey Zigachev #define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13 758*b843c749SSergey Zigachev #define SMU7_12C_VDDCI_CONST 20856 759*b843c749SSergey Zigachev 760*b843c749SSergey Zigachev #define SMU7_VDDCI_STROBE_PWR 1331 761*b843c749SSergey Zigachev 762*b843c749SSergey Zigachev #define SMU7_VDDR1_CONST 693 763*b843c749SSergey Zigachev #define SMU7_VDDR1_CAC_WEIGHT 20 764*b843c749SSergey Zigachev #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 765*b843c749SSergey Zigachev #define SMU7_VDDR1_STROBE_PWR 512 766*b843c749SSergey Zigachev 767*b843c749SSergey Zigachev #define SMU7_AREA_COEFF_UVD 0xA78 768*b843c749SSergey Zigachev #define SMU7_AREA_COEFF_VCE 0x190A 769*b843c749SSergey Zigachev #define SMU7_AREA_COEFF_ACP 0x22D1 770*b843c749SSergey Zigachev #define SMU7_AREA_COEFF_SAMU 0x534 771*b843c749SSergey Zigachev 772*b843c749SSergey Zigachev /*ThermOutMode values */ 773*b843c749SSergey Zigachev #define SMU7_THERM_OUT_MODE_DISABLE 0x0 774*b843c749SSergey Zigachev #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 775*b843c749SSergey Zigachev #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 776*b843c749SSergey Zigachev 777*b843c749SSergey Zigachev #if !defined(SMC_MICROCODE) 778*b843c749SSergey Zigachev #pragma pack(pop) 779*b843c749SSergey Zigachev #endif 780*b843c749SSergey Zigachev 781*b843c749SSergey Zigachev 782*b843c749SSergey Zigachev #endif 783*b843c749SSergey Zigachev 784