1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev #ifndef _SMU73_DISCRETE_H_ 24*b843c749SSergey Zigachev #define _SMU73_DISCRETE_H_ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #include "smu73.h" 27*b843c749SSergey Zigachev 28*b843c749SSergey Zigachev #pragma pack(push, 1) 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev struct SMIO_Pattern 31*b843c749SSergey Zigachev { 32*b843c749SSergey Zigachev uint16_t Voltage; 33*b843c749SSergey Zigachev uint8_t Smio; 34*b843c749SSergey Zigachev uint8_t padding; 35*b843c749SSergey Zigachev }; 36*b843c749SSergey Zigachev 37*b843c749SSergey Zigachev typedef struct SMIO_Pattern SMIO_Pattern; 38*b843c749SSergey Zigachev 39*b843c749SSergey Zigachev struct SMIO_Table 40*b843c749SSergey Zigachev { 41*b843c749SSergey Zigachev SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; 42*b843c749SSergey Zigachev }; 43*b843c749SSergey Zigachev 44*b843c749SSergey Zigachev typedef struct SMIO_Table SMIO_Table; 45*b843c749SSergey Zigachev 46*b843c749SSergey Zigachev struct SMU73_Discrete_GraphicsLevel { 47*b843c749SSergey Zigachev uint32_t MinVoltage; 48*b843c749SSergey Zigachev 49*b843c749SSergey Zigachev uint32_t SclkFrequency; 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev uint8_t pcieDpmLevel; 52*b843c749SSergey Zigachev uint8_t DeepSleepDivId; 53*b843c749SSergey Zigachev uint16_t ActivityLevel; 54*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl3; 55*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl4; 56*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum; 57*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum2; 58*b843c749SSergey Zigachev uint32_t CcPwrDynRm; 59*b843c749SSergey Zigachev uint32_t CcPwrDynRm1; 60*b843c749SSergey Zigachev uint8_t SclkDid; 61*b843c749SSergey Zigachev uint8_t DisplayWatermark; 62*b843c749SSergey Zigachev uint8_t EnabledForActivity; 63*b843c749SSergey Zigachev uint8_t EnabledForThrottle; 64*b843c749SSergey Zigachev uint8_t UpHyst; 65*b843c749SSergey Zigachev uint8_t DownHyst; 66*b843c749SSergey Zigachev uint8_t VoltageDownHyst; 67*b843c749SSergey Zigachev uint8_t PowerThrottle; 68*b843c749SSergey Zigachev }; 69*b843c749SSergey Zigachev 70*b843c749SSergey Zigachev typedef struct SMU73_Discrete_GraphicsLevel SMU73_Discrete_GraphicsLevel; 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev struct SMU73_Discrete_ACPILevel { 73*b843c749SSergey Zigachev uint32_t Flags; 74*b843c749SSergey Zigachev uint32_t MinVoltage; 75*b843c749SSergey Zigachev uint32_t SclkFrequency; 76*b843c749SSergey Zigachev uint8_t SclkDid; 77*b843c749SSergey Zigachev uint8_t DisplayWatermark; 78*b843c749SSergey Zigachev uint8_t DeepSleepDivId; 79*b843c749SSergey Zigachev uint8_t padding; 80*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl; 81*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl2; 82*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl3; 83*b843c749SSergey Zigachev uint32_t CgSpllFuncCntl4; 84*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum; 85*b843c749SSergey Zigachev uint32_t SpllSpreadSpectrum2; 86*b843c749SSergey Zigachev uint32_t CcPwrDynRm; 87*b843c749SSergey Zigachev uint32_t CcPwrDynRm1; 88*b843c749SSergey Zigachev }; 89*b843c749SSergey Zigachev 90*b843c749SSergey Zigachev typedef struct SMU73_Discrete_ACPILevel SMU73_Discrete_ACPILevel; 91*b843c749SSergey Zigachev 92*b843c749SSergey Zigachev struct SMU73_Discrete_Ulv { 93*b843c749SSergey Zigachev uint32_t CcPwrDynRm; 94*b843c749SSergey Zigachev uint32_t CcPwrDynRm1; 95*b843c749SSergey Zigachev uint16_t VddcOffset; 96*b843c749SSergey Zigachev uint8_t VddcOffsetVid; 97*b843c749SSergey Zigachev uint8_t VddcPhase; 98*b843c749SSergey Zigachev uint32_t Reserved; 99*b843c749SSergey Zigachev }; 100*b843c749SSergey Zigachev 101*b843c749SSergey Zigachev typedef struct SMU73_Discrete_Ulv SMU73_Discrete_Ulv; 102*b843c749SSergey Zigachev 103*b843c749SSergey Zigachev struct SMU73_Discrete_MemoryLevel 104*b843c749SSergey Zigachev { 105*b843c749SSergey Zigachev uint32_t MinVoltage; 106*b843c749SSergey Zigachev uint32_t MinMvdd; 107*b843c749SSergey Zigachev 108*b843c749SSergey Zigachev uint32_t MclkFrequency; 109*b843c749SSergey Zigachev 110*b843c749SSergey Zigachev uint8_t StutterEnable; 111*b843c749SSergey Zigachev uint8_t FreqRange; 112*b843c749SSergey Zigachev uint8_t EnabledForThrottle; 113*b843c749SSergey Zigachev uint8_t EnabledForActivity; 114*b843c749SSergey Zigachev 115*b843c749SSergey Zigachev uint8_t UpHyst; 116*b843c749SSergey Zigachev uint8_t DownHyst; 117*b843c749SSergey Zigachev uint8_t VoltageDownHyst; 118*b843c749SSergey Zigachev uint8_t padding; 119*b843c749SSergey Zigachev 120*b843c749SSergey Zigachev uint16_t ActivityLevel; 121*b843c749SSergey Zigachev uint8_t DisplayWatermark; 122*b843c749SSergey Zigachev uint8_t MclkDivider; 123*b843c749SSergey Zigachev }; 124*b843c749SSergey Zigachev 125*b843c749SSergey Zigachev typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel; 126*b843c749SSergey Zigachev 127*b843c749SSergey Zigachev struct SMU73_Discrete_LinkLevel 128*b843c749SSergey Zigachev { 129*b843c749SSergey Zigachev uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 130*b843c749SSergey Zigachev uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 131*b843c749SSergey Zigachev uint8_t EnabledForActivity; 132*b843c749SSergey Zigachev uint8_t SPC; 133*b843c749SSergey Zigachev uint32_t DownThreshold; 134*b843c749SSergey Zigachev uint32_t UpThreshold; 135*b843c749SSergey Zigachev uint32_t Reserved; 136*b843c749SSergey Zigachev }; 137*b843c749SSergey Zigachev 138*b843c749SSergey Zigachev typedef struct SMU73_Discrete_LinkLevel SMU73_Discrete_LinkLevel; 139*b843c749SSergey Zigachev 140*b843c749SSergey Zigachev 141*b843c749SSergey Zigachev // MC ARB DRAM Timing registers. 142*b843c749SSergey Zigachev struct SMU73_Discrete_MCArbDramTimingTableEntry 143*b843c749SSergey Zigachev { 144*b843c749SSergey Zigachev uint32_t McArbDramTiming; 145*b843c749SSergey Zigachev uint32_t McArbDramTiming2; 146*b843c749SSergey Zigachev uint8_t McArbBurstTime; 147*b843c749SSergey Zigachev uint8_t TRRDS; 148*b843c749SSergey Zigachev uint8_t TRRDL; 149*b843c749SSergey Zigachev uint8_t padding; 150*b843c749SSergey Zigachev }; 151*b843c749SSergey Zigachev 152*b843c749SSergey Zigachev typedef struct SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MCArbDramTimingTableEntry; 153*b843c749SSergey Zigachev 154*b843c749SSergey Zigachev struct SMU73_Discrete_MCArbDramTimingTable 155*b843c749SSergey Zigachev { 156*b843c749SSergey Zigachev SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 157*b843c749SSergey Zigachev }; 158*b843c749SSergey Zigachev 159*b843c749SSergey Zigachev typedef struct SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTable; 160*b843c749SSergey Zigachev 161*b843c749SSergey Zigachev // UVD VCLK/DCLK state (level) definition. 162*b843c749SSergey Zigachev struct SMU73_Discrete_UvdLevel 163*b843c749SSergey Zigachev { 164*b843c749SSergey Zigachev uint32_t VclkFrequency; 165*b843c749SSergey Zigachev uint32_t DclkFrequency; 166*b843c749SSergey Zigachev uint32_t MinVoltage; 167*b843c749SSergey Zigachev uint8_t VclkDivider; 168*b843c749SSergey Zigachev uint8_t DclkDivider; 169*b843c749SSergey Zigachev uint8_t padding[2]; 170*b843c749SSergey Zigachev }; 171*b843c749SSergey Zigachev 172*b843c749SSergey Zigachev typedef struct SMU73_Discrete_UvdLevel SMU73_Discrete_UvdLevel; 173*b843c749SSergey Zigachev 174*b843c749SSergey Zigachev // Clocks for other external blocks (VCE, ACP, SAMU). 175*b843c749SSergey Zigachev struct SMU73_Discrete_ExtClkLevel 176*b843c749SSergey Zigachev { 177*b843c749SSergey Zigachev uint32_t Frequency; 178*b843c749SSergey Zigachev uint32_t MinVoltage; 179*b843c749SSergey Zigachev uint8_t Divider; 180*b843c749SSergey Zigachev uint8_t padding[3]; 181*b843c749SSergey Zigachev }; 182*b843c749SSergey Zigachev 183*b843c749SSergey Zigachev typedef struct SMU73_Discrete_ExtClkLevel SMU73_Discrete_ExtClkLevel; 184*b843c749SSergey Zigachev 185*b843c749SSergey Zigachev struct SMU73_Discrete_StateInfo 186*b843c749SSergey Zigachev { 187*b843c749SSergey Zigachev uint32_t SclkFrequency; 188*b843c749SSergey Zigachev uint32_t MclkFrequency; 189*b843c749SSergey Zigachev uint32_t VclkFrequency; 190*b843c749SSergey Zigachev uint32_t DclkFrequency; 191*b843c749SSergey Zigachev uint32_t SamclkFrequency; 192*b843c749SSergey Zigachev uint32_t AclkFrequency; 193*b843c749SSergey Zigachev uint32_t EclkFrequency; 194*b843c749SSergey Zigachev uint16_t MvddVoltage; 195*b843c749SSergey Zigachev uint16_t padding16; 196*b843c749SSergey Zigachev uint8_t DisplayWatermark; 197*b843c749SSergey Zigachev uint8_t McArbIndex; 198*b843c749SSergey Zigachev uint8_t McRegIndex; 199*b843c749SSergey Zigachev uint8_t SeqIndex; 200*b843c749SSergey Zigachev uint8_t SclkDid; 201*b843c749SSergey Zigachev int8_t SclkIndex; 202*b843c749SSergey Zigachev int8_t MclkIndex; 203*b843c749SSergey Zigachev uint8_t PCIeGen; 204*b843c749SSergey Zigachev 205*b843c749SSergey Zigachev }; 206*b843c749SSergey Zigachev 207*b843c749SSergey Zigachev typedef struct SMU73_Discrete_StateInfo SMU73_Discrete_StateInfo; 208*b843c749SSergey Zigachev 209*b843c749SSergey Zigachev struct SMU73_Discrete_DpmTable 210*b843c749SSergey Zigachev { 211*b843c749SSergey Zigachev // Multi-DPM controller settings 212*b843c749SSergey Zigachev SMU73_PIDController GraphicsPIDController; 213*b843c749SSergey Zigachev SMU73_PIDController MemoryPIDController; 214*b843c749SSergey Zigachev SMU73_PIDController LinkPIDController; 215*b843c749SSergey Zigachev 216*b843c749SSergey Zigachev uint32_t SystemFlags; 217*b843c749SSergey Zigachev 218*b843c749SSergey Zigachev // SMIO masks for voltage and phase controls 219*b843c749SSergey Zigachev uint32_t VRConfig; 220*b843c749SSergey Zigachev uint32_t SmioMask1; 221*b843c749SSergey Zigachev uint32_t SmioMask2; 222*b843c749SSergey Zigachev SMIO_Table SmioTable1; 223*b843c749SSergey Zigachev SMIO_Table SmioTable2; 224*b843c749SSergey Zigachev 225*b843c749SSergey Zigachev uint32_t MvddLevelCount; 226*b843c749SSergey Zigachev 227*b843c749SSergey Zigachev 228*b843c749SSergey Zigachev uint8_t BapmVddcVidHiSidd [SMU73_MAX_LEVELS_VDDC]; 229*b843c749SSergey Zigachev uint8_t BapmVddcVidLoSidd [SMU73_MAX_LEVELS_VDDC]; 230*b843c749SSergey Zigachev uint8_t BapmVddcVidHiSidd2 [SMU73_MAX_LEVELS_VDDC]; 231*b843c749SSergey Zigachev 232*b843c749SSergey Zigachev uint8_t GraphicsDpmLevelCount; 233*b843c749SSergey Zigachev uint8_t MemoryDpmLevelCount; 234*b843c749SSergey Zigachev uint8_t LinkLevelCount; 235*b843c749SSergey Zigachev uint8_t MasterDeepSleepControl; 236*b843c749SSergey Zigachev 237*b843c749SSergey Zigachev uint8_t UvdLevelCount; 238*b843c749SSergey Zigachev uint8_t VceLevelCount; 239*b843c749SSergey Zigachev uint8_t AcpLevelCount; 240*b843c749SSergey Zigachev uint8_t SamuLevelCount; 241*b843c749SSergey Zigachev 242*b843c749SSergey Zigachev uint8_t ThermOutGpio; 243*b843c749SSergey Zigachev uint8_t ThermOutPolarity; 244*b843c749SSergey Zigachev uint8_t ThermOutMode; 245*b843c749SSergey Zigachev uint8_t BootPhases; 246*b843c749SSergey Zigachev uint32_t Reserved[4]; 247*b843c749SSergey Zigachev 248*b843c749SSergey Zigachev // State table entries for each DPM state 249*b843c749SSergey Zigachev SMU73_Discrete_GraphicsLevel GraphicsLevel [SMU73_MAX_LEVELS_GRAPHICS]; 250*b843c749SSergey Zigachev SMU73_Discrete_MemoryLevel MemoryACPILevel; 251*b843c749SSergey Zigachev SMU73_Discrete_MemoryLevel MemoryLevel [SMU73_MAX_LEVELS_MEMORY]; 252*b843c749SSergey Zigachev SMU73_Discrete_LinkLevel LinkLevel [SMU73_MAX_LEVELS_LINK]; 253*b843c749SSergey Zigachev SMU73_Discrete_ACPILevel ACPILevel; 254*b843c749SSergey Zigachev SMU73_Discrete_UvdLevel UvdLevel [SMU73_MAX_LEVELS_UVD]; 255*b843c749SSergey Zigachev SMU73_Discrete_ExtClkLevel VceLevel [SMU73_MAX_LEVELS_VCE]; 256*b843c749SSergey Zigachev SMU73_Discrete_ExtClkLevel AcpLevel [SMU73_MAX_LEVELS_ACP]; 257*b843c749SSergey Zigachev SMU73_Discrete_ExtClkLevel SamuLevel [SMU73_MAX_LEVELS_SAMU]; 258*b843c749SSergey Zigachev SMU73_Discrete_Ulv Ulv; 259*b843c749SSergey Zigachev 260*b843c749SSergey Zigachev uint32_t SclkStepSize; 261*b843c749SSergey Zigachev uint32_t Smio [SMU73_MAX_ENTRIES_SMIO]; 262*b843c749SSergey Zigachev 263*b843c749SSergey Zigachev uint8_t UvdBootLevel; 264*b843c749SSergey Zigachev uint8_t VceBootLevel; 265*b843c749SSergey Zigachev uint8_t AcpBootLevel; 266*b843c749SSergey Zigachev uint8_t SamuBootLevel; 267*b843c749SSergey Zigachev 268*b843c749SSergey Zigachev uint8_t GraphicsBootLevel; 269*b843c749SSergey Zigachev uint8_t GraphicsVoltageChangeEnable; 270*b843c749SSergey Zigachev uint8_t GraphicsThermThrottleEnable; 271*b843c749SSergey Zigachev uint8_t GraphicsInterval; 272*b843c749SSergey Zigachev 273*b843c749SSergey Zigachev uint8_t VoltageInterval; 274*b843c749SSergey Zigachev uint8_t ThermalInterval; 275*b843c749SSergey Zigachev uint16_t TemperatureLimitHigh; 276*b843c749SSergey Zigachev 277*b843c749SSergey Zigachev uint16_t TemperatureLimitLow; 278*b843c749SSergey Zigachev uint8_t MemoryBootLevel; 279*b843c749SSergey Zigachev uint8_t MemoryVoltageChangeEnable; 280*b843c749SSergey Zigachev 281*b843c749SSergey Zigachev uint16_t BootMVdd; 282*b843c749SSergey Zigachev uint8_t MemoryInterval; 283*b843c749SSergey Zigachev uint8_t MemoryThermThrottleEnable; 284*b843c749SSergey Zigachev 285*b843c749SSergey Zigachev uint16_t VoltageResponseTime; 286*b843c749SSergey Zigachev uint16_t PhaseResponseTime; 287*b843c749SSergey Zigachev 288*b843c749SSergey Zigachev uint8_t PCIeBootLinkLevel; 289*b843c749SSergey Zigachev uint8_t PCIeGenInterval; 290*b843c749SSergey Zigachev uint8_t DTEInterval; 291*b843c749SSergey Zigachev uint8_t DTEMode; 292*b843c749SSergey Zigachev 293*b843c749SSergey Zigachev uint8_t SVI2Enable; 294*b843c749SSergey Zigachev uint8_t VRHotGpio; 295*b843c749SSergey Zigachev uint8_t AcDcGpio; 296*b843c749SSergey Zigachev uint8_t ThermGpio; 297*b843c749SSergey Zigachev 298*b843c749SSergey Zigachev uint16_t PPM_PkgPwrLimit; 299*b843c749SSergey Zigachev uint16_t PPM_TemperatureLimit; 300*b843c749SSergey Zigachev 301*b843c749SSergey Zigachev uint16_t DefaultTdp; 302*b843c749SSergey Zigachev uint16_t TargetTdp; 303*b843c749SSergey Zigachev 304*b843c749SSergey Zigachev uint16_t FpsHighThreshold; 305*b843c749SSergey Zigachev uint16_t FpsLowThreshold; 306*b843c749SSergey Zigachev 307*b843c749SSergey Zigachev uint16_t TemperatureLimitEdge; 308*b843c749SSergey Zigachev uint16_t TemperatureLimitHotspot; 309*b843c749SSergey Zigachev uint16_t TemperatureLimitLiquid1; 310*b843c749SSergey Zigachev uint16_t TemperatureLimitLiquid2; 311*b843c749SSergey Zigachev uint16_t TemperatureLimitVrVddc; 312*b843c749SSergey Zigachev uint16_t TemperatureLimitVrMvdd; 313*b843c749SSergey Zigachev uint16_t TemperatureLimitPlx; 314*b843c749SSergey Zigachev 315*b843c749SSergey Zigachev uint16_t FanGainEdge; 316*b843c749SSergey Zigachev uint16_t FanGainHotspot; 317*b843c749SSergey Zigachev uint16_t FanGainLiquid; 318*b843c749SSergey Zigachev uint16_t FanGainVrVddc; 319*b843c749SSergey Zigachev uint16_t FanGainVrMvdd; 320*b843c749SSergey Zigachev uint16_t FanGainPlx; 321*b843c749SSergey Zigachev uint16_t FanGainHbm; 322*b843c749SSergey Zigachev 323*b843c749SSergey Zigachev uint8_t Liquid1_I2C_address; 324*b843c749SSergey Zigachev uint8_t Liquid2_I2C_address; 325*b843c749SSergey Zigachev uint8_t Vr_I2C_address; 326*b843c749SSergey Zigachev uint8_t Plx_I2C_address; 327*b843c749SSergey Zigachev 328*b843c749SSergey Zigachev uint8_t GeminiMode; 329*b843c749SSergey Zigachev uint8_t spare17[3]; 330*b843c749SSergey Zigachev uint32_t GeminiApertureHigh; 331*b843c749SSergey Zigachev uint32_t GeminiApertureLow; 332*b843c749SSergey Zigachev 333*b843c749SSergey Zigachev uint8_t Liquid_I2C_LineSCL; 334*b843c749SSergey Zigachev uint8_t Liquid_I2C_LineSDA; 335*b843c749SSergey Zigachev uint8_t Vr_I2C_LineSCL; 336*b843c749SSergey Zigachev uint8_t Vr_I2C_LineSDA; 337*b843c749SSergey Zigachev uint8_t Plx_I2C_LineSCL; 338*b843c749SSergey Zigachev uint8_t Plx_I2C_LineSDA; 339*b843c749SSergey Zigachev 340*b843c749SSergey Zigachev uint8_t spare1253[2]; 341*b843c749SSergey Zigachev uint32_t spare123[2]; 342*b843c749SSergey Zigachev 343*b843c749SSergey Zigachev uint8_t DTEAmbientTempBase; 344*b843c749SSergey Zigachev uint8_t DTETjOffset; 345*b843c749SSergey Zigachev uint8_t GpuTjMax; 346*b843c749SSergey Zigachev uint8_t GpuTjHyst; 347*b843c749SSergey Zigachev 348*b843c749SSergey Zigachev uint16_t BootVddc; 349*b843c749SSergey Zigachev uint16_t BootVddci; 350*b843c749SSergey Zigachev 351*b843c749SSergey Zigachev uint32_t BAPM_TEMP_GRADIENT; 352*b843c749SSergey Zigachev 353*b843c749SSergey Zigachev uint32_t LowSclkInterruptThreshold; 354*b843c749SSergey Zigachev uint32_t VddGfxReChkWait; 355*b843c749SSergey Zigachev 356*b843c749SSergey Zigachev uint8_t ClockStretcherAmount; 357*b843c749SSergey Zigachev uint8_t Sclk_CKS_masterEn0_7; 358*b843c749SSergey Zigachev uint8_t Sclk_CKS_masterEn8_15; 359*b843c749SSergey Zigachev uint8_t DPMFreezeAndForced; 360*b843c749SSergey Zigachev 361*b843c749SSergey Zigachev uint8_t Sclk_voltageOffset[8]; 362*b843c749SSergey Zigachev 363*b843c749SSergey Zigachev SMU_ClockStretcherDataTable ClockStretcherDataTable; 364*b843c749SSergey Zigachev SMU_CKS_LOOKUPTable CKS_LOOKUPTable; 365*b843c749SSergey Zigachev }; 366*b843c749SSergey Zigachev 367*b843c749SSergey Zigachev typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable; 368*b843c749SSergey Zigachev 369*b843c749SSergey Zigachev 370*b843c749SSergey Zigachev // --------------------------------------------------- Fan Table ----------------------------------------------------------- 371*b843c749SSergey Zigachev struct SMU73_Discrete_FanTable 372*b843c749SSergey Zigachev { 373*b843c749SSergey Zigachev uint16_t FdoMode; 374*b843c749SSergey Zigachev int16_t TempMin; 375*b843c749SSergey Zigachev int16_t TempMed; 376*b843c749SSergey Zigachev int16_t TempMax; 377*b843c749SSergey Zigachev int16_t Slope1; 378*b843c749SSergey Zigachev int16_t Slope2; 379*b843c749SSergey Zigachev int16_t FdoMin; 380*b843c749SSergey Zigachev int16_t HystUp; 381*b843c749SSergey Zigachev int16_t HystDown; 382*b843c749SSergey Zigachev int16_t HystSlope; 383*b843c749SSergey Zigachev int16_t TempRespLim; 384*b843c749SSergey Zigachev int16_t TempCurr; 385*b843c749SSergey Zigachev int16_t SlopeCurr; 386*b843c749SSergey Zigachev int16_t PwmCurr; 387*b843c749SSergey Zigachev uint32_t RefreshPeriod; 388*b843c749SSergey Zigachev int16_t FdoMax; 389*b843c749SSergey Zigachev uint8_t TempSrc; 390*b843c749SSergey Zigachev int8_t Padding; 391*b843c749SSergey Zigachev }; 392*b843c749SSergey Zigachev 393*b843c749SSergey Zigachev typedef struct SMU73_Discrete_FanTable SMU73_Discrete_FanTable; 394*b843c749SSergey Zigachev 395*b843c749SSergey Zigachev #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 396*b843c749SSergey Zigachev #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 397*b843c749SSergey Zigachev 398*b843c749SSergey Zigachev 399*b843c749SSergey Zigachev 400*b843c749SSergey Zigachev struct SMU7_MclkDpmScoreboard 401*b843c749SSergey Zigachev { 402*b843c749SSergey Zigachev 403*b843c749SSergey Zigachev uint32_t PercentageBusy; 404*b843c749SSergey Zigachev 405*b843c749SSergey Zigachev int32_t PIDError; 406*b843c749SSergey Zigachev int32_t PIDIntegral; 407*b843c749SSergey Zigachev int32_t PIDOutput; 408*b843c749SSergey Zigachev 409*b843c749SSergey Zigachev uint32_t SigmaDeltaAccum; 410*b843c749SSergey Zigachev uint32_t SigmaDeltaOutput; 411*b843c749SSergey Zigachev uint32_t SigmaDeltaLevel; 412*b843c749SSergey Zigachev 413*b843c749SSergey Zigachev uint32_t UtilizationSetpoint; 414*b843c749SSergey Zigachev 415*b843c749SSergey Zigachev uint8_t TdpClampMode; 416*b843c749SSergey Zigachev uint8_t TdcClampMode; 417*b843c749SSergey Zigachev uint8_t ThermClampMode; 418*b843c749SSergey Zigachev uint8_t VoltageBusy; 419*b843c749SSergey Zigachev 420*b843c749SSergey Zigachev int8_t CurrLevel; 421*b843c749SSergey Zigachev int8_t TargLevel; 422*b843c749SSergey Zigachev uint8_t LevelChangeInProgress; 423*b843c749SSergey Zigachev uint8_t UpHyst; 424*b843c749SSergey Zigachev 425*b843c749SSergey Zigachev uint8_t DownHyst; 426*b843c749SSergey Zigachev uint8_t VoltageDownHyst; 427*b843c749SSergey Zigachev uint8_t DpmEnable; 428*b843c749SSergey Zigachev uint8_t DpmRunning; 429*b843c749SSergey Zigachev 430*b843c749SSergey Zigachev uint8_t DpmForce; 431*b843c749SSergey Zigachev uint8_t DpmForceLevel; 432*b843c749SSergey Zigachev uint8_t DisplayWatermark; 433*b843c749SSergey Zigachev uint8_t McArbIndex; 434*b843c749SSergey Zigachev 435*b843c749SSergey Zigachev uint32_t MinimumPerfMclk; 436*b843c749SSergey Zigachev 437*b843c749SSergey Zigachev uint8_t AcpiReq; 438*b843c749SSergey Zigachev uint8_t AcpiAck; 439*b843c749SSergey Zigachev uint8_t MclkSwitchInProgress; 440*b843c749SSergey Zigachev uint8_t MclkSwitchCritical; 441*b843c749SSergey Zigachev 442*b843c749SSergey Zigachev uint8_t IgnoreVBlank; 443*b843c749SSergey Zigachev uint8_t TargetMclkIndex; 444*b843c749SSergey Zigachev uint8_t TargetMvddIndex; 445*b843c749SSergey Zigachev uint8_t MclkSwitchResult; 446*b843c749SSergey Zigachev 447*b843c749SSergey Zigachev uint16_t VbiFailureCount; 448*b843c749SSergey Zigachev uint8_t VbiWaitCounter; 449*b843c749SSergey Zigachev uint8_t EnabledLevelsChange; 450*b843c749SSergey Zigachev 451*b843c749SSergey Zigachev uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_MEMORY]; 452*b843c749SSergey Zigachev uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_MEMORY]; 453*b843c749SSergey Zigachev 454*b843c749SSergey Zigachev void (*TargetStateCalculator)(uint8_t); 455*b843c749SSergey Zigachev void (*SavedTargetStateCalculator)(uint8_t); 456*b843c749SSergey Zigachev 457*b843c749SSergey Zigachev uint16_t AutoDpmInterval; 458*b843c749SSergey Zigachev uint16_t AutoDpmRange; 459*b843c749SSergey Zigachev 460*b843c749SSergey Zigachev uint16_t VbiTimeoutCount; 461*b843c749SSergey Zigachev uint16_t MclkSwitchingTime; 462*b843c749SSergey Zigachev 463*b843c749SSergey Zigachev uint8_t fastSwitch; 464*b843c749SSergey Zigachev uint8_t Save_PIC_VDDGFX_EXIT; 465*b843c749SSergey Zigachev uint8_t Save_PIC_VDDGFX_ENTER; 466*b843c749SSergey Zigachev uint8_t padding; 467*b843c749SSergey Zigachev 468*b843c749SSergey Zigachev }; 469*b843c749SSergey Zigachev 470*b843c749SSergey Zigachev typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; 471*b843c749SSergey Zigachev 472*b843c749SSergey Zigachev struct SMU7_UlvScoreboard 473*b843c749SSergey Zigachev { 474*b843c749SSergey Zigachev uint8_t EnterUlv; 475*b843c749SSergey Zigachev uint8_t ExitUlv; 476*b843c749SSergey Zigachev uint8_t UlvActive; 477*b843c749SSergey Zigachev uint8_t WaitingForUlv; 478*b843c749SSergey Zigachev uint8_t UlvEnable; 479*b843c749SSergey Zigachev uint8_t UlvRunning; 480*b843c749SSergey Zigachev uint8_t UlvMasterEnable; 481*b843c749SSergey Zigachev uint8_t padding; 482*b843c749SSergey Zigachev uint32_t UlvAbortedCount; 483*b843c749SSergey Zigachev uint32_t UlvTimeStamp; 484*b843c749SSergey Zigachev }; 485*b843c749SSergey Zigachev 486*b843c749SSergey Zigachev typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; 487*b843c749SSergey Zigachev 488*b843c749SSergey Zigachev struct VddgfxSavedRegisters 489*b843c749SSergey Zigachev { 490*b843c749SSergey Zigachev uint32_t GPU_DBG[3]; 491*b843c749SSergey Zigachev uint32_t MEC_BaseAddress_Hi; 492*b843c749SSergey Zigachev uint32_t MEC_BaseAddress_Lo; 493*b843c749SSergey Zigachev uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; 494*b843c749SSergey Zigachev uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; 495*b843c749SSergey Zigachev uint32_t CP_INT_CNTL; 496*b843c749SSergey Zigachev }; 497*b843c749SSergey Zigachev 498*b843c749SSergey Zigachev typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; 499*b843c749SSergey Zigachev 500*b843c749SSergey Zigachev struct SMU7_VddGfxScoreboard 501*b843c749SSergey Zigachev { 502*b843c749SSergey Zigachev uint8_t VddGfxEnable; 503*b843c749SSergey Zigachev uint8_t VddGfxActive; 504*b843c749SSergey Zigachev uint8_t VPUResetOccured; 505*b843c749SSergey Zigachev uint8_t padding; 506*b843c749SSergey Zigachev 507*b843c749SSergey Zigachev uint32_t VddGfxEnteredCount; 508*b843c749SSergey Zigachev uint32_t VddGfxAbortedCount; 509*b843c749SSergey Zigachev 510*b843c749SSergey Zigachev uint32_t VddGfxVid; 511*b843c749SSergey Zigachev 512*b843c749SSergey Zigachev VddgfxSavedRegisters SavedRegisters; 513*b843c749SSergey Zigachev }; 514*b843c749SSergey Zigachev 515*b843c749SSergey Zigachev typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; 516*b843c749SSergey Zigachev 517*b843c749SSergey Zigachev struct SMU7_TdcLimitScoreboard { 518*b843c749SSergey Zigachev uint8_t Enable; 519*b843c749SSergey Zigachev uint8_t Running; 520*b843c749SSergey Zigachev uint16_t Alpha; 521*b843c749SSergey Zigachev uint32_t FilteredIddc; 522*b843c749SSergey Zigachev uint32_t IddcLimit; 523*b843c749SSergey Zigachev uint32_t IddcHyst; 524*b843c749SSergey Zigachev SMU7_HystController_Data HystControllerData; 525*b843c749SSergey Zigachev }; 526*b843c749SSergey Zigachev 527*b843c749SSergey Zigachev typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; 528*b843c749SSergey Zigachev 529*b843c749SSergey Zigachev struct SMU7_PkgPwrLimitScoreboard { 530*b843c749SSergey Zigachev uint8_t Enable; 531*b843c749SSergey Zigachev uint8_t Running; 532*b843c749SSergey Zigachev uint16_t Alpha; 533*b843c749SSergey Zigachev uint32_t FilteredPkgPwr; 534*b843c749SSergey Zigachev uint32_t Limit; 535*b843c749SSergey Zigachev uint32_t Hyst; 536*b843c749SSergey Zigachev uint32_t LimitFromDriver; 537*b843c749SSergey Zigachev SMU7_HystController_Data HystControllerData; 538*b843c749SSergey Zigachev }; 539*b843c749SSergey Zigachev 540*b843c749SSergey Zigachev typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; 541*b843c749SSergey Zigachev 542*b843c749SSergey Zigachev struct SMU7_BapmScoreboard { 543*b843c749SSergey Zigachev uint32_t source_powers[SMU73_DTE_SOURCES]; 544*b843c749SSergey Zigachev uint32_t source_powers_last[SMU73_DTE_SOURCES]; 545*b843c749SSergey Zigachev int32_t entity_temperatures[SMU73_NUM_GPU_TES]; 546*b843c749SSergey Zigachev int32_t initial_entity_temperatures[SMU73_NUM_GPU_TES]; 547*b843c749SSergey Zigachev int32_t Limit; 548*b843c749SSergey Zigachev int32_t Hyst; 549*b843c749SSergey Zigachev int32_t therm_influence_coeff_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS * 2]; 550*b843c749SSergey Zigachev int32_t therm_node_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS]; 551*b843c749SSergey Zigachev uint16_t ConfigTDPPowerScalar; 552*b843c749SSergey Zigachev uint16_t FanSpeedPowerScalar; 553*b843c749SSergey Zigachev uint16_t OverDrivePowerScalar; 554*b843c749SSergey Zigachev uint16_t OverDriveLimitScalar; 555*b843c749SSergey Zigachev uint16_t FinalPowerScalar; 556*b843c749SSergey Zigachev uint8_t VariantID; 557*b843c749SSergey Zigachev uint8_t spare997; 558*b843c749SSergey Zigachev 559*b843c749SSergey Zigachev SMU7_HystController_Data HystControllerData; 560*b843c749SSergey Zigachev 561*b843c749SSergey Zigachev int32_t temperature_gradient_slope; 562*b843c749SSergey Zigachev int32_t temperature_gradient; 563*b843c749SSergey Zigachev uint32_t measured_temperature; 564*b843c749SSergey Zigachev }; 565*b843c749SSergey Zigachev 566*b843c749SSergey Zigachev 567*b843c749SSergey Zigachev typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; 568*b843c749SSergey Zigachev 569*b843c749SSergey Zigachev struct SMU7_AcpiScoreboard { 570*b843c749SSergey Zigachev uint32_t SavedInterruptMask[2]; 571*b843c749SSergey Zigachev uint8_t LastACPIRequest; 572*b843c749SSergey Zigachev uint8_t CgBifResp; 573*b843c749SSergey Zigachev uint8_t RequestType; 574*b843c749SSergey Zigachev uint8_t Padding; 575*b843c749SSergey Zigachev SMU73_Discrete_ACPILevel D0Level; 576*b843c749SSergey Zigachev }; 577*b843c749SSergey Zigachev 578*b843c749SSergey Zigachev typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 579*b843c749SSergey Zigachev 580*b843c749SSergey Zigachev struct SMU_QuadraticCoeffs { 581*b843c749SSergey Zigachev int32_t m1; 582*b843c749SSergey Zigachev uint32_t b; 583*b843c749SSergey Zigachev 584*b843c749SSergey Zigachev int16_t m2; 585*b843c749SSergey Zigachev uint8_t m1_shift; 586*b843c749SSergey Zigachev uint8_t m2_shift; 587*b843c749SSergey Zigachev }; 588*b843c749SSergey Zigachev 589*b843c749SSergey Zigachev typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs; 590*b843c749SSergey Zigachev 591*b843c749SSergey Zigachev struct SMU73_Discrete_PmFuses { 592*b843c749SSergey Zigachev /* dw0-dw1 */ 593*b843c749SSergey Zigachev uint8_t BapmVddCVidHiSidd[8]; 594*b843c749SSergey Zigachev 595*b843c749SSergey Zigachev /* dw2-dw3 */ 596*b843c749SSergey Zigachev uint8_t BapmVddCVidLoSidd[8]; 597*b843c749SSergey Zigachev 598*b843c749SSergey Zigachev /* dw4-dw5 */ 599*b843c749SSergey Zigachev uint8_t VddCVid[8]; 600*b843c749SSergey Zigachev 601*b843c749SSergey Zigachev /* dw1*/ 602*b843c749SSergey Zigachev uint8_t SviLoadLineEn; 603*b843c749SSergey Zigachev uint8_t SviLoadLineVddC; 604*b843c749SSergey Zigachev uint8_t SviLoadLineTrimVddC; 605*b843c749SSergey Zigachev uint8_t SviLoadLineOffsetVddC; 606*b843c749SSergey Zigachev 607*b843c749SSergey Zigachev /* dw2 */ 608*b843c749SSergey Zigachev uint16_t TDC_VDDC_PkgLimit; 609*b843c749SSergey Zigachev uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 610*b843c749SSergey Zigachev uint8_t TDC_MAWt; 611*b843c749SSergey Zigachev 612*b843c749SSergey Zigachev /* dw3 */ 613*b843c749SSergey Zigachev uint8_t TdcWaterfallCtl; 614*b843c749SSergey Zigachev uint8_t LPMLTemperatureMin; 615*b843c749SSergey Zigachev uint8_t LPMLTemperatureMax; 616*b843c749SSergey Zigachev uint8_t Reserved; 617*b843c749SSergey Zigachev 618*b843c749SSergey Zigachev /* dw4-dw7 */ 619*b843c749SSergey Zigachev uint8_t LPMLTemperatureScaler[16]; 620*b843c749SSergey Zigachev 621*b843c749SSergey Zigachev /* dw8-dw9 */ 622*b843c749SSergey Zigachev int16_t FuzzyFan_ErrorSetDelta; 623*b843c749SSergey Zigachev int16_t FuzzyFan_ErrorRateSetDelta; 624*b843c749SSergey Zigachev int16_t FuzzyFan_PwmSetDelta; 625*b843c749SSergey Zigachev uint16_t Reserved6; 626*b843c749SSergey Zigachev 627*b843c749SSergey Zigachev /* dw10-dw14 */ 628*b843c749SSergey Zigachev uint8_t GnbLPML[16]; 629*b843c749SSergey Zigachev 630*b843c749SSergey Zigachev /* dw15 */ 631*b843c749SSergey Zigachev uint8_t GnbLPMLMaxVid; 632*b843c749SSergey Zigachev uint8_t GnbLPMLMinVid; 633*b843c749SSergey Zigachev uint8_t Reserved1[2]; 634*b843c749SSergey Zigachev 635*b843c749SSergey Zigachev /* dw16 */ 636*b843c749SSergey Zigachev uint16_t BapmVddCBaseLeakageHiSidd; 637*b843c749SSergey Zigachev uint16_t BapmVddCBaseLeakageLoSidd; 638*b843c749SSergey Zigachev 639*b843c749SSergey Zigachev /* AVFS */ 640*b843c749SSergey Zigachev uint16_t VFT_Temp[3]; 641*b843c749SSergey Zigachev uint16_t padding; 642*b843c749SSergey Zigachev 643*b843c749SSergey Zigachev SMU_QuadraticCoeffs VFT_ATE[3]; 644*b843c749SSergey Zigachev 645*b843c749SSergey Zigachev SMU_QuadraticCoeffs AVFS_GB; 646*b843c749SSergey Zigachev SMU_QuadraticCoeffs ATE_ACBTC_GB; 647*b843c749SSergey Zigachev 648*b843c749SSergey Zigachev SMU_QuadraticCoeffs P2V; 649*b843c749SSergey Zigachev 650*b843c749SSergey Zigachev uint32_t PsmCharzFreq; 651*b843c749SSergey Zigachev 652*b843c749SSergey Zigachev uint16_t InversionVoltage; 653*b843c749SSergey Zigachev uint16_t PsmCharzTemp; 654*b843c749SSergey Zigachev 655*b843c749SSergey Zigachev uint32_t EnabledAvfsModules; 656*b843c749SSergey Zigachev }; 657*b843c749SSergey Zigachev 658*b843c749SSergey Zigachev typedef struct SMU73_Discrete_PmFuses SMU73_Discrete_PmFuses; 659*b843c749SSergey Zigachev 660*b843c749SSergey Zigachev struct SMU7_Discrete_Log_Header_Table { 661*b843c749SSergey Zigachev uint32_t version; 662*b843c749SSergey Zigachev uint32_t asic_id; 663*b843c749SSergey Zigachev uint16_t flags; 664*b843c749SSergey Zigachev uint16_t entry_size; 665*b843c749SSergey Zigachev uint32_t total_size; 666*b843c749SSergey Zigachev uint32_t num_of_entries; 667*b843c749SSergey Zigachev uint8_t type; 668*b843c749SSergey Zigachev uint8_t mode; 669*b843c749SSergey Zigachev uint8_t filler_0[2]; 670*b843c749SSergey Zigachev uint32_t filler_1[2]; 671*b843c749SSergey Zigachev }; 672*b843c749SSergey Zigachev 673*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; 674*b843c749SSergey Zigachev 675*b843c749SSergey Zigachev struct SMU7_Discrete_Log_Cntl { 676*b843c749SSergey Zigachev uint8_t Enabled; 677*b843c749SSergey Zigachev uint8_t Type; 678*b843c749SSergey Zigachev uint8_t padding[2]; 679*b843c749SSergey Zigachev uint32_t BufferSize; 680*b843c749SSergey Zigachev uint32_t SamplesLogged; 681*b843c749SSergey Zigachev uint32_t SampleSize; 682*b843c749SSergey Zigachev uint32_t AddrL; 683*b843c749SSergey Zigachev uint32_t AddrH; 684*b843c749SSergey Zigachev }; 685*b843c749SSergey Zigachev 686*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; 687*b843c749SSergey Zigachev 688*b843c749SSergey Zigachev #define CAC_ACC_NW_NUM_OF_SIGNALS 87 689*b843c749SSergey Zigachev 690*b843c749SSergey Zigachev struct SMU7_Discrete_Cac_Collection_Table { 691*b843c749SSergey Zigachev uint32_t temperature; 692*b843c749SSergey Zigachev uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 693*b843c749SSergey Zigachev }; 694*b843c749SSergey Zigachev 695*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; 696*b843c749SSergey Zigachev 697*b843c749SSergey Zigachev struct SMU7_Discrete_Cac_Verification_Table { 698*b843c749SSergey Zigachev uint32_t VddcTotalPower; 699*b843c749SSergey Zigachev uint32_t VddcLeakagePower; 700*b843c749SSergey Zigachev uint32_t VddcConstantPower; 701*b843c749SSergey Zigachev uint32_t VddcGfxDynamicPower; 702*b843c749SSergey Zigachev uint32_t VddcUvdDynamicPower; 703*b843c749SSergey Zigachev uint32_t VddcVceDynamicPower; 704*b843c749SSergey Zigachev uint32_t VddcAcpDynamicPower; 705*b843c749SSergey Zigachev uint32_t VddcPcieDynamicPower; 706*b843c749SSergey Zigachev uint32_t VddcDceDynamicPower; 707*b843c749SSergey Zigachev uint32_t VddcCurrent; 708*b843c749SSergey Zigachev uint32_t VddcVoltage; 709*b843c749SSergey Zigachev uint32_t VddciTotalPower; 710*b843c749SSergey Zigachev uint32_t VddciLeakagePower; 711*b843c749SSergey Zigachev uint32_t VddciConstantPower; 712*b843c749SSergey Zigachev uint32_t VddciDynamicPower; 713*b843c749SSergey Zigachev uint32_t Vddr1TotalPower; 714*b843c749SSergey Zigachev uint32_t Vddr1LeakagePower; 715*b843c749SSergey Zigachev uint32_t Vddr1ConstantPower; 716*b843c749SSergey Zigachev uint32_t Vddr1DynamicPower; 717*b843c749SSergey Zigachev uint32_t spare[4]; 718*b843c749SSergey Zigachev uint32_t temperature; 719*b843c749SSergey Zigachev }; 720*b843c749SSergey Zigachev 721*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; 722*b843c749SSergey Zigachev 723*b843c749SSergey Zigachev struct SMU7_Discrete_Pm_Status_Table { 724*b843c749SSergey Zigachev //Thermal entities 725*b843c749SSergey Zigachev int32_t T_meas_max[SMU73_THERMAL_INPUT_LOOP_COUNT]; 726*b843c749SSergey Zigachev int32_t T_meas_acc[SMU73_THERMAL_INPUT_LOOP_COUNT]; 727*b843c749SSergey Zigachev int32_t T_meas_acc_cnt[SMU73_THERMAL_INPUT_LOOP_COUNT]; 728*b843c749SSergey Zigachev uint32_t T_hbm_acc; 729*b843c749SSergey Zigachev 730*b843c749SSergey Zigachev //Voltage domains 731*b843c749SSergey Zigachev uint32_t I_calc_max; 732*b843c749SSergey Zigachev uint32_t I_calc_acc; 733*b843c749SSergey Zigachev uint32_t P_meas_acc; 734*b843c749SSergey Zigachev uint32_t V_meas_load_acc; 735*b843c749SSergey Zigachev uint32_t I_meas_acc; 736*b843c749SSergey Zigachev uint32_t P_meas_acc_vddci; 737*b843c749SSergey Zigachev uint32_t V_meas_load_acc_vddci; 738*b843c749SSergey Zigachev uint32_t I_meas_acc_vddci; 739*b843c749SSergey Zigachev 740*b843c749SSergey Zigachev //Frequency 741*b843c749SSergey Zigachev uint16_t Sclk_dpm_residency[8]; 742*b843c749SSergey Zigachev uint16_t Uvd_dpm_residency[8]; 743*b843c749SSergey Zigachev uint16_t Vce_dpm_residency[8]; 744*b843c749SSergey Zigachev 745*b843c749SSergey Zigachev //Chip 746*b843c749SSergey Zigachev uint32_t P_roc_acc; 747*b843c749SSergey Zigachev uint32_t PkgPwr_max; 748*b843c749SSergey Zigachev uint32_t PkgPwr_acc; 749*b843c749SSergey Zigachev uint32_t MclkSwitchingTime_max; 750*b843c749SSergey Zigachev uint32_t MclkSwitchingTime_acc; 751*b843c749SSergey Zigachev uint32_t FanPwm_acc; 752*b843c749SSergey Zigachev uint32_t FanRpm_acc; 753*b843c749SSergey Zigachev uint32_t Gfx_busy_acc; 754*b843c749SSergey Zigachev uint32_t Mc_busy_acc; 755*b843c749SSergey Zigachev uint32_t Fps_acc; 756*b843c749SSergey Zigachev 757*b843c749SSergey Zigachev uint32_t AccCnt; 758*b843c749SSergey Zigachev }; 759*b843c749SSergey Zigachev 760*b843c749SSergey Zigachev typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; 761*b843c749SSergey Zigachev 762*b843c749SSergey Zigachev //FIXME THESE NEED TO BE UPDATED 763*b843c749SSergey Zigachev #define SMU7_SCLK_CAC 0x561 764*b843c749SSergey Zigachev #define SMU7_MCLK_CAC 0xF9 765*b843c749SSergey Zigachev #define SMU7_VCLK_CAC 0x2DE 766*b843c749SSergey Zigachev #define SMU7_DCLK_CAC 0x2DE 767*b843c749SSergey Zigachev #define SMU7_ECLK_CAC 0x25E 768*b843c749SSergey Zigachev #define SMU7_ACLK_CAC 0x25E 769*b843c749SSergey Zigachev #define SMU7_SAMCLK_CAC 0x25E 770*b843c749SSergey Zigachev #define SMU7_DISPCLK_CAC 0x100 771*b843c749SSergey Zigachev #define SMU7_CAC_CONSTANT 0x2EE3430 772*b843c749SSergey Zigachev #define SMU7_CAC_CONSTANT_SHIFT 18 773*b843c749SSergey Zigachev 774*b843c749SSergey Zigachev #define SMU7_VDDCI_MCLK_CONST 1765 775*b843c749SSergey Zigachev #define SMU7_VDDCI_MCLK_CONST_SHIFT 16 776*b843c749SSergey Zigachev #define SMU7_VDDCI_VDDCI_CONST 50958 777*b843c749SSergey Zigachev #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 778*b843c749SSergey Zigachev #define SMU7_VDDCI_CONST 11781 779*b843c749SSergey Zigachev #define SMU7_VDDCI_STROBE_PWR 1331 780*b843c749SSergey Zigachev 781*b843c749SSergey Zigachev #define SMU7_VDDR1_CONST 693 782*b843c749SSergey Zigachev #define SMU7_VDDR1_CAC_WEIGHT 20 783*b843c749SSergey Zigachev #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 784*b843c749SSergey Zigachev #define SMU7_VDDR1_STROBE_PWR 512 785*b843c749SSergey Zigachev 786*b843c749SSergey Zigachev #define SMU7_AREA_COEFF_UVD 0xA78 787*b843c749SSergey Zigachev #define SMU7_AREA_COEFF_VCE 0x190A 788*b843c749SSergey Zigachev #define SMU7_AREA_COEFF_ACP 0x22D1 789*b843c749SSergey Zigachev #define SMU7_AREA_COEFF_SAMU 0x534 790*b843c749SSergey Zigachev 791*b843c749SSergey Zigachev //ThermOutMode values 792*b843c749SSergey Zigachev #define SMU7_THERM_OUT_MODE_DISABLE 0x0 793*b843c749SSergey Zigachev #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 794*b843c749SSergey Zigachev #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 795*b843c749SSergey Zigachev 796*b843c749SSergey Zigachev #pragma pack(pop) 797*b843c749SSergey Zigachev 798*b843c749SSergey Zigachev #endif 799*b843c749SSergey Zigachev 800