1 /*
2  * Copyright 2013 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef SMU7_FUSION_H
25 #define SMU7_FUSION_H
26 
27 #include "smu7.h"
28 
29 #pragma pack(push, 1)
30 
31 #define SMU7_DTE_ITERATIONS 5
32 #define SMU7_DTE_SOURCES 5
33 #define SMU7_DTE_SINKS 3
34 #define SMU7_NUM_CPU_TES 2
35 #define SMU7_NUM_GPU_TES 1
36 #define SMU7_NUM_NON_TES 2
37 
38 // All 'soft registers' should be uint32_t.
39 struct SMU7_SoftRegisters
40 {
41     uint32_t        RefClockFrequency;
42     uint32_t        PmTimerP;
43     uint32_t        FeatureEnables;
44     uint32_t        HandshakeDisables;
45 
46     uint8_t         DisplayPhy1Config;
47     uint8_t         DisplayPhy2Config;
48     uint8_t         DisplayPhy3Config;
49     uint8_t         DisplayPhy4Config;
50 
51     uint8_t         DisplayPhy5Config;
52     uint8_t         DisplayPhy6Config;
53     uint8_t         DisplayPhy7Config;
54     uint8_t         DisplayPhy8Config;
55 
56     uint32_t        AverageGraphicsA;
57     uint32_t        AverageMemoryA;
58     uint32_t        AverageGioA;
59 
60     uint8_t         SClkDpmEnabledLevels;
61     uint8_t         MClkDpmEnabledLevels;
62     uint8_t         LClkDpmEnabledLevels;
63     uint8_t         PCIeDpmEnabledLevels;
64 
65     uint8_t         UVDDpmEnabledLevels;
66     uint8_t         SAMUDpmEnabledLevels;
67     uint8_t         ACPDpmEnabledLevels;
68     uint8_t         VCEDpmEnabledLevels;
69 
70     uint32_t        DRAM_LOG_ADDR_H;
71     uint32_t        DRAM_LOG_ADDR_L;
72     uint32_t        DRAM_LOG_PHY_ADDR_H;
73     uint32_t        DRAM_LOG_PHY_ADDR_L;
74     uint32_t        DRAM_LOG_BUFF_SIZE;
75     uint32_t        UlvEnterC;
76     uint32_t        UlvTime;
77     uint32_t        Reserved[3];
78 
79 };
80 
81 typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;
82 
83 struct SMU7_Fusion_GraphicsLevel
84 {
85     uint32_t    MinVddNb;
86 
87     uint32_t    SclkFrequency;
88 
89     uint8_t     Vid;
90     uint8_t     VidOffset;
91     uint16_t    AT;
92 
93     uint8_t     PowerThrottle;
94     uint8_t     GnbSlow;
95     uint8_t     ForceNbPs1;
96     uint8_t     SclkDid;
97 
98     uint8_t     DisplayWatermark;
99     uint8_t     EnabledForActivity;
100     uint8_t     EnabledForThrottle;
101     uint8_t     UpH;
102 
103     uint8_t     DownH;
104     uint8_t     VoltageDownH;
105     uint8_t     DeepSleepDivId;
106 
107     uint8_t     ClkBypassCntl;
108 
109     uint32_t    reserved;
110 };
111 
112 typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;
113 
114 struct SMU7_Fusion_GIOLevel
115 {
116     uint8_t     EnabledForActivity;
117     uint8_t     LclkDid;
118     uint8_t     Vid;
119     uint8_t     VoltageDownH;
120 
121     uint32_t    MinVddNb;
122 
123     uint16_t    ResidencyCounter;
124     uint8_t     UpH;
125     uint8_t     DownH;
126 
127     uint32_t    LclkFrequency;
128 
129     uint8_t     ActivityLevel;
130     uint8_t     EnabledForThrottle;
131 
132     uint8_t     ClkBypassCntl;
133 
134     uint8_t     padding;
135 };
136 
137 typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;
138 
139 // UVD VCLK/DCLK state (level) definition.
140 struct SMU7_Fusion_UvdLevel
141 {
142     uint32_t VclkFrequency;
143     uint32_t DclkFrequency;
144     uint16_t MinVddNb;
145     uint8_t  VclkDivider;
146     uint8_t  DclkDivider;
147 
148     uint8_t     VClkBypassCntl;
149     uint8_t     DClkBypassCntl;
150 
151     uint8_t     padding[2];
152 
153 };
154 
155 typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;
156 
157 // Clocks for other external blocks (VCE, ACP, SAMU).
158 struct SMU7_Fusion_ExtClkLevel
159 {
160     uint32_t Frequency;
161     uint16_t MinVoltage;
162     uint8_t  Divider;
163     uint8_t  ClkBypassCntl;
164 
165     uint32_t Reserved;
166 };
167 typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;
168 
169 struct SMU7_Fusion_ACPILevel
170 {
171     uint32_t    Flags;
172     uint32_t    MinVddNb;
173     uint32_t    SclkFrequency;
174     uint8_t     SclkDid;
175     uint8_t     GnbSlow;
176     uint8_t     ForceNbPs1;
177     uint8_t     DisplayWatermark;
178     uint8_t     DeepSleepDivId;
179     uint8_t     padding[3];
180 };
181 
182 typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;
183 
184 struct SMU7_Fusion_NbDpm
185 {
186     uint8_t DpmXNbPsHi;
187     uint8_t DpmXNbPsLo;
188     uint8_t Dpm0PgNbPsHi;
189     uint8_t Dpm0PgNbPsLo;
190     uint8_t EnablePsi1;
191     uint8_t SkipDPM0;
192     uint8_t SkipPG;
193     uint8_t Hysteresis;
194     uint8_t EnableDpmPstatePoll;
195     uint8_t padding[3];
196 };
197 
198 typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;
199 
200 struct SMU7_Fusion_StateInfo
201 {
202     uint32_t SclkFrequency;
203     uint32_t LclkFrequency;
204     uint32_t VclkFrequency;
205     uint32_t DclkFrequency;
206     uint32_t SamclkFrequency;
207     uint32_t AclkFrequency;
208     uint32_t EclkFrequency;
209     uint8_t  DisplayWatermark;
210     uint8_t  McArbIndex;
211     int8_t   SclkIndex;
212     int8_t   MclkIndex;
213 };
214 
215 typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;
216 
217 struct SMU7_Fusion_DpmTable
218 {
219     uint32_t                            SystemFlags;
220 
221     SMU7_PIDController                  GraphicsPIDController;
222     SMU7_PIDController                  GioPIDController;
223 
224     uint8_t                            GraphicsDpmLevelCount;
225     uint8_t                            GIOLevelCount;
226     uint8_t                            UvdLevelCount;
227     uint8_t                            VceLevelCount;
228 
229     uint8_t                            AcpLevelCount;
230     uint8_t                            SamuLevelCount;
231     uint16_t                           FpsHighT;
232 
233     SMU7_Fusion_GraphicsLevel         GraphicsLevel           [SMU__NUM_SCLK_DPM_STATE];
234     SMU7_Fusion_ACPILevel             ACPILevel;
235     SMU7_Fusion_UvdLevel              UvdLevel                [SMU7_MAX_LEVELS_UVD];
236     SMU7_Fusion_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
237     SMU7_Fusion_ExtClkLevel           AcpLevel                [SMU7_MAX_LEVELS_ACP];
238     SMU7_Fusion_ExtClkLevel           SamuLevel               [SMU7_MAX_LEVELS_SAMU];
239 
240     uint8_t                           UvdBootLevel;
241     uint8_t                           VceBootLevel;
242     uint8_t                           AcpBootLevel;
243     uint8_t                           SamuBootLevel;
244     uint8_t                           UVDInterval;
245     uint8_t                           VCEInterval;
246     uint8_t                           ACPInterval;
247     uint8_t                           SAMUInterval;
248 
249     uint8_t                           GraphicsBootLevel;
250     uint8_t                           GraphicsInterval;
251     uint8_t                           GraphicsThermThrottleEnable;
252     uint8_t                           GraphicsVoltageChangeEnable;
253 
254     uint8_t                           GraphicsClkSlowEnable;
255     uint8_t                           GraphicsClkSlowDivider;
256     uint16_t                          FpsLowT;
257 
258     uint32_t                          DisplayCac;
259     uint32_t                          LowSclkInterruptT;
260 
261     uint32_t                          DRAM_LOG_ADDR_H;
262     uint32_t                          DRAM_LOG_ADDR_L;
263     uint32_t                          DRAM_LOG_PHY_ADDR_H;
264     uint32_t                          DRAM_LOG_PHY_ADDR_L;
265     uint32_t                          DRAM_LOG_BUFF_SIZE;
266 
267 };
268 
269 struct SMU7_Fusion_GIODpmTable
270 {
271 
272     SMU7_Fusion_GIOLevel              GIOLevel                [SMU7_MAX_LEVELS_GIO];
273 
274     SMU7_PIDController                GioPIDController;
275 
276     uint32_t                          GIOLevelCount;
277 
278     uint8_t                           Enable;
279     uint8_t                           GIOVoltageChangeEnable;
280     uint8_t                           GIOBootLevel;
281     uint8_t                           padding;
282     uint8_t                           padding1[2];
283     uint8_t                           TargetState;
284     uint8_t                           CurrenttState;
285     uint8_t                           ThrottleOnHtc;
286     uint8_t                           ThermThrottleStatus;
287     uint8_t                           ThermThrottleTempSelect;
288     uint8_t                           ThermThrottleEnable;
289     uint16_t                          TemperatureLimitHigh;
290     uint16_t                          TemperatureLimitLow;
291 
292 };
293 
294 typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;
295 typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;
296 
297 #pragma pack(pop)
298 
299 #endif
300 
301