1 /*
2  * Copyright 2018 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include "smumgr.h"
25 #include "vega10_inc.h"
26 #include "soc15_common.h"
27 #include "pp_debug.h"
28 
29 
30 /* MP Apertures */
31 #define MP0_Public                  0x03800000
32 #define MP0_SRAM                    0x03900000
33 #define MP1_Public                  0x03b00000
34 #define MP1_SRAM                    0x03c00004
35 
36 #define smnMP1_FIRMWARE_FLAGS                                                                           0x3010028
37 
38 bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr);
39 bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr)
40 {
41 	struct amdgpu_device *adev = hwmgr->adev;
42 	uint32_t mp1_fw_flags;
43 
44 	WREG32_SOC15(NBIF, 0, mmPCIE_INDEX2,
45 			(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)));
46 
47 	mp1_fw_flags = RREG32_SOC15(NBIF, 0, mmPCIE_DATA2);
48 
49 	if (mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK)
50 		return true;
51 
52 	return false;
53 }
54 
55 /*
56  * Check if SMC has responded to previous message.
57  *
58  * @param    smumgr  the address of the powerplay hardware manager.
59  * @return   TRUE    SMC has responded, FALSE otherwise.
60  */
61 static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr)
62 {
63 	struct amdgpu_device *adev = hwmgr->adev;
64 	uint32_t reg;
65 	uint32_t ret;
66 
67 	reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
68 
69 	ret = phm_wait_for_register_unequal(hwmgr, reg,
70 			0, MP1_C2PMSG_90__CONTENT_MASK);
71 
72 	if (ret)
73 		pr_err("No response from smu\n");
74 
75 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
76 }
77 
78 /*
79  * Send a message to the SMC, and do not wait for its response.
80  * @param    smumgr  the address of the powerplay hardware manager.
81  * @param    msg the message to send.
82  * @return   Always return 0.
83  */
84 static int smu9_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
85 						uint16_t msg)
86 {
87 	struct amdgpu_device *adev = hwmgr->adev;
88 
89 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_66, msg);
90 
91 	return 0;
92 }
93 
94 /*
95  * Send a message to the SMC, and wait for its response.
96  * @param    hwmgr  the address of the powerplay hardware manager.
97  * @param    msg the message to send.
98  * @return   Always return 0.
99  */
100 int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
101 int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
102 {
103 	struct amdgpu_device *adev = hwmgr->adev;
104 	uint32_t ret;
105 
106 	smu9_wait_for_response(hwmgr);
107 
108 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
109 
110 	smu9_send_msg_to_smc_without_waiting(hwmgr, msg);
111 
112 	ret = smu9_wait_for_response(hwmgr);
113 	if (ret != 1)
114 		pr_err("Failed to send message: 0x%x, ret value: 0x%x\n", msg, ret);
115 
116 	return 0;
117 }
118 
119 /*
120  * Send a message to the SMC with parameter
121  * @param    hwmgr:  the address of the powerplay hardware manager.
122  * @param    msg: the message to send.
123  * @param    parameter: the parameter to send
124  * @return   Always return 0.
125  */
126 int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
127 					uint16_t msg, uint32_t parameter);
128 int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
129 					uint16_t msg, uint32_t parameter)
130 {
131 	struct amdgpu_device *adev = hwmgr->adev;
132 	uint32_t ret;
133 
134 	smu9_wait_for_response(hwmgr);
135 
136 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);
137 
138 	WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82, parameter);
139 
140 	smu9_send_msg_to_smc_without_waiting(hwmgr, msg);
141 
142 	ret = smu9_wait_for_response(hwmgr);
143 	if (ret != 1)
144 		pr_err("Failed message: 0x%x, input parameter: 0x%x, error code: 0x%x\n", msg, parameter, ret);
145 
146 	return 0;
147 }
148 
149 uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr);
150 uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr)
151 {
152 	struct amdgpu_device *adev = hwmgr->adev;
153 
154 	return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_82);
155 }
156