1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include <linux/gfp.h> 28 29 #include "smumgr.h" 30 #include "tonga_smumgr.h" 31 #include "smu_ucode_xfer_vi.h" 32 #include "tonga_ppsmc.h" 33 #include "smu/smu_7_1_2_d.h" 34 #include "smu/smu_7_1_2_sh_mask.h" 35 #include "cgs_common.h" 36 #include "smu7_smumgr.h" 37 38 #include "smu7_dyn_defaults.h" 39 40 #include "smu7_hwmgr.h" 41 #include "hardwaremanager.h" 42 #include "ppatomctrl.h" 43 44 #include "atombios.h" 45 46 #include "pppcielanes.h" 47 #include "pp_endian.h" 48 49 #include "gmc/gmc_8_1_d.h" 50 #include "gmc/gmc_8_1_sh_mask.h" 51 52 #include "bif/bif_5_0_d.h" 53 #include "bif/bif_5_0_sh_mask.h" 54 55 #include "dce/dce_10_0_d.h" 56 #include "dce/dce_10_0_sh_mask.h" 57 58 #define POWERTUNE_DEFAULT_SET_MAX 1 59 #define MC_CG_ARB_FREQ_F1 0x0b 60 #define VDDC_VDDCI_DELTA 200 61 62 63 static const struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { 64 /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, 65 * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT 66 */ 67 {1, 0xF, 0xFD, 0x19, 68 5, 45, 0, 0xB0000, 69 {0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 70 0xC9, 0xC9, 0x2F, 0x4D, 0x61}, 71 {0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 72 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4} 73 }, 74 }; 75 76 /* [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */ 77 static const uint16_t tonga_clock_stretcher_lookup_table[2][4] = { 78 {600, 1050, 3, 0}, 79 {600, 1050, 6, 1} 80 }; 81 82 /* [FF, SS] type, [] 4 voltage ranges, 83 * and [Floor Freq, Boundary Freq, VID min , VID max] 84 */ 85 static const uint32_t tonga_clock_stretcher_ddt_table[2][4][4] = { 86 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, 87 { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } 88 }; 89 90 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] */ 91 static const uint8_t tonga_clock_stretch_amount_conversion[2][6] = { 92 {0, 1, 3, 2, 4, 5}, 93 {0, 2, 4, 5, 6, 5} 94 }; 95 96 static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr) 97 { 98 int result; 99 100 /* Assert reset */ 101 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 102 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 103 104 result = smu7_upload_smu_firmware_image(hwmgr); 105 if (result) 106 return result; 107 108 /* Clear status */ 109 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 110 ixSMU_STATUS, 0); 111 112 /* Enable clock */ 113 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 114 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 115 116 /* De-assert reset */ 117 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 118 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 119 120 /* Set SMU Auto Start */ 121 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 122 SMU_INPUT_DATA, AUTO_START, 1); 123 124 /* Clear firmware interrupt enable flag */ 125 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 126 ixFIRMWARE_FLAGS, 0); 127 128 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, 129 RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1); 130 131 /** 132 * Call Test SMU message with 0x20000 offset to trigger SMU start 133 */ 134 smu7_send_msg_to_smc_offset(hwmgr); 135 136 /* Wait for done bit to be set */ 137 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, 138 SMU_STATUS, SMU_DONE, 0); 139 140 /* Check pass/failed indicator */ 141 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 142 CGS_IND_REG__SMC, SMU_STATUS, SMU_PASS)) { 143 pr_err("SMU Firmware start failed\n"); 144 return -EINVAL; 145 } 146 147 /* Wait for firmware to initialize */ 148 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, 149 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 150 151 return 0; 152 } 153 154 static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr) 155 { 156 int result = 0; 157 158 /* wait for smc boot up */ 159 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, 160 RCU_UC_EVENTS, boot_seq_done, 0); 161 162 /*Clear firmware interrupt enable flag*/ 163 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 164 ixFIRMWARE_FLAGS, 0); 165 166 167 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 168 SMC_SYSCON_RESET_CNTL, rst_reg, 1); 169 170 result = smu7_upload_smu_firmware_image(hwmgr); 171 172 if (result != 0) 173 return result; 174 175 /* Set smc instruct start point at 0x0 */ 176 smu7_program_jump_on_start(hwmgr); 177 178 179 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 180 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); 181 182 /*De-assert reset*/ 183 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 184 SMC_SYSCON_RESET_CNTL, rst_reg, 0); 185 186 /* Wait for firmware to initialize */ 187 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, 188 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1); 189 190 return result; 191 } 192 193 static int tonga_start_smu(struct pp_hwmgr *hwmgr) 194 { 195 int result; 196 197 /* Only start SMC if SMC RAM is not running */ 198 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) { 199 /*Check if SMU is running in protected mode*/ 200 if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 201 SMU_FIRMWARE, SMU_MODE)) { 202 result = tonga_start_in_non_protection_mode(hwmgr); 203 if (result) 204 return result; 205 } else { 206 result = tonga_start_in_protection_mode(hwmgr); 207 if (result) 208 return result; 209 } 210 } 211 212 result = smu7_request_smu_load_fw(hwmgr); 213 214 return result; 215 } 216 217 static int tonga_smu_init(struct pp_hwmgr *hwmgr) 218 { 219 struct tonga_smumgr *tonga_priv = NULL; 220 221 tonga_priv = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL); 222 if (tonga_priv == NULL) 223 return -ENOMEM; 224 225 hwmgr->smu_backend = tonga_priv; 226 227 if (smu7_init(hwmgr)) { 228 kfree(tonga_priv); 229 return -EINVAL; 230 } 231 232 return 0; 233 } 234 235 236 static int tonga_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, 237 phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table, 238 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) 239 { 240 uint32_t i = 0; 241 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 242 struct phm_ppt_v1_information *pptable_info = 243 (struct phm_ppt_v1_information *)(hwmgr->pptable); 244 245 /* clock - voltage dependency table is empty table */ 246 if (allowed_clock_voltage_table->count == 0) 247 return -EINVAL; 248 249 for (i = 0; i < allowed_clock_voltage_table->count; i++) { 250 /* find first sclk bigger than request */ 251 if (allowed_clock_voltage_table->entries[i].clk >= clock) { 252 voltage->VddGfx = phm_get_voltage_index( 253 pptable_info->vddgfx_lookup_table, 254 allowed_clock_voltage_table->entries[i].vddgfx); 255 voltage->Vddc = phm_get_voltage_index( 256 pptable_info->vddc_lookup_table, 257 allowed_clock_voltage_table->entries[i].vddc); 258 259 if (allowed_clock_voltage_table->entries[i].vddci) 260 voltage->Vddci = 261 phm_get_voltage_id(&data->vddci_voltage_table, allowed_clock_voltage_table->entries[i].vddci); 262 else 263 voltage->Vddci = 264 phm_get_voltage_id(&data->vddci_voltage_table, 265 allowed_clock_voltage_table->entries[i].vddc - VDDC_VDDCI_DELTA); 266 267 268 if (allowed_clock_voltage_table->entries[i].mvdd) 269 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd; 270 271 voltage->Phases = 1; 272 return 0; 273 } 274 } 275 276 /* sclk is bigger than max sclk in the dependence table */ 277 voltage->VddGfx = phm_get_voltage_index(pptable_info->vddgfx_lookup_table, 278 allowed_clock_voltage_table->entries[i-1].vddgfx); 279 voltage->Vddc = phm_get_voltage_index(pptable_info->vddc_lookup_table, 280 allowed_clock_voltage_table->entries[i-1].vddc); 281 282 if (allowed_clock_voltage_table->entries[i-1].vddci) 283 voltage->Vddci = phm_get_voltage_id(&data->vddci_voltage_table, 284 allowed_clock_voltage_table->entries[i-1].vddci); 285 286 if (allowed_clock_voltage_table->entries[i-1].mvdd) 287 *mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd; 288 289 return 0; 290 } 291 292 static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr, 293 SMU72_Discrete_DpmTable *table) 294 { 295 unsigned int count; 296 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 297 298 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { 299 table->VddcLevelCount = data->vddc_voltage_table.count; 300 for (count = 0; count < table->VddcLevelCount; count++) { 301 table->VddcTable[count] = 302 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE); 303 } 304 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount); 305 } 306 return 0; 307 } 308 309 static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr, 310 SMU72_Discrete_DpmTable *table) 311 { 312 unsigned int count; 313 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 314 315 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { 316 table->VddGfxLevelCount = data->vddgfx_voltage_table.count; 317 for (count = 0; count < data->vddgfx_voltage_table.count; count++) { 318 table->VddGfxTable[count] = 319 PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE); 320 } 321 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount); 322 } 323 return 0; 324 } 325 326 static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr, 327 SMU72_Discrete_DpmTable *table) 328 { 329 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 330 uint32_t count; 331 332 table->VddciLevelCount = data->vddci_voltage_table.count; 333 for (count = 0; count < table->VddciLevelCount; count++) { 334 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { 335 table->VddciTable[count] = 336 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); 337 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 338 table->SmioTable1.Pattern[count].Voltage = 339 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); 340 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */ 341 table->SmioTable1.Pattern[count].Smio = 342 (uint8_t) count; 343 table->Smio[count] |= 344 data->vddci_voltage_table.entries[count].smio_low; 345 table->VddciTable[count] = 346 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE); 347 } 348 } 349 350 table->SmioMask1 = data->vddci_voltage_table.mask_low; 351 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount); 352 353 return 0; 354 } 355 356 static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, 357 SMU72_Discrete_DpmTable *table) 358 { 359 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 360 uint32_t count; 361 362 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { 363 table->MvddLevelCount = data->mvdd_voltage_table.count; 364 for (count = 0; count < table->MvddLevelCount; count++) { 365 table->SmioTable2.Pattern[count].Voltage = 366 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE); 367 /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/ 368 table->SmioTable2.Pattern[count].Smio = 369 (uint8_t) count; 370 table->Smio[count] |= 371 data->mvdd_voltage_table.entries[count].smio_low; 372 } 373 table->SmioMask2 = data->mvdd_voltage_table.mask_low; 374 375 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount); 376 } 377 378 return 0; 379 } 380 381 static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr, 382 SMU72_Discrete_DpmTable *table) 383 { 384 uint32_t count; 385 uint8_t index = 0; 386 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 387 struct phm_ppt_v1_information *pptable_info = 388 (struct phm_ppt_v1_information *)(hwmgr->pptable); 389 struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = 390 pptable_info->vddgfx_lookup_table; 391 struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = 392 pptable_info->vddc_lookup_table; 393 394 /* table is already swapped, so in order to use the value from it 395 * we need to swap it back. 396 */ 397 uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount); 398 uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount); 399 400 for (count = 0; count < vddc_level_count; count++) { 401 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */ 402 index = phm_get_voltage_index(vddc_lookup_table, 403 data->vddc_voltage_table.entries[count].value); 404 table->BapmVddcVidLoSidd[count] = 405 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low); 406 table->BapmVddcVidHiSidd[count] = 407 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid); 408 table->BapmVddcVidHiSidd2[count] = 409 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high); 410 } 411 412 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 413 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */ 414 for (count = 0; count < vddgfx_level_count; count++) { 415 index = phm_get_voltage_index(vddgfx_lookup_table, 416 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid)); 417 table->BapmVddGfxVidHiSidd2[count] = 418 convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high); 419 } 420 } else { 421 for (count = 0; count < vddc_level_count; count++) { 422 index = phm_get_voltage_index(vddc_lookup_table, 423 data->vddc_voltage_table.entries[count].value); 424 table->BapmVddGfxVidLoSidd[count] = 425 convert_to_vid(vddc_lookup_table->entries[index].us_cac_low); 426 table->BapmVddGfxVidHiSidd[count] = 427 convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid); 428 table->BapmVddGfxVidHiSidd2[count] = 429 convert_to_vid(vddc_lookup_table->entries[index].us_cac_high); 430 } 431 } 432 433 return 0; 434 } 435 436 static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, 437 SMU72_Discrete_DpmTable *table) 438 { 439 int result; 440 441 result = tonga_populate_smc_vddc_table(hwmgr, table); 442 PP_ASSERT_WITH_CODE(!result, 443 "can not populate VDDC voltage table to SMC", 444 return -EINVAL); 445 446 result = tonga_populate_smc_vdd_ci_table(hwmgr, table); 447 PP_ASSERT_WITH_CODE(!result, 448 "can not populate VDDCI voltage table to SMC", 449 return -EINVAL); 450 451 result = tonga_populate_smc_vdd_gfx_table(hwmgr, table); 452 PP_ASSERT_WITH_CODE(!result, 453 "can not populate VDDGFX voltage table to SMC", 454 return -EINVAL); 455 456 result = tonga_populate_smc_mvdd_table(hwmgr, table); 457 PP_ASSERT_WITH_CODE(!result, 458 "can not populate MVDD voltage table to SMC", 459 return -EINVAL); 460 461 result = tonga_populate_cac_tables(hwmgr, table); 462 PP_ASSERT_WITH_CODE(!result, 463 "can not populate CAC voltage tables to SMC", 464 return -EINVAL); 465 466 return 0; 467 } 468 469 static int tonga_populate_ulv_level(struct pp_hwmgr *hwmgr, 470 struct SMU72_Discrete_Ulv *state) 471 { 472 struct phm_ppt_v1_information *table_info = 473 (struct phm_ppt_v1_information *)(hwmgr->pptable); 474 475 state->CcPwrDynRm = 0; 476 state->CcPwrDynRm1 = 0; 477 478 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset; 479 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset * 480 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1); 481 482 state->VddcPhase = 1; 483 484 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm); 485 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1); 486 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset); 487 488 return 0; 489 } 490 491 static int tonga_populate_ulv_state(struct pp_hwmgr *hwmgr, 492 struct SMU72_Discrete_DpmTable *table) 493 { 494 return tonga_populate_ulv_level(hwmgr, &table->Ulv); 495 } 496 497 static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table) 498 { 499 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 500 struct smu7_dpm_table *dpm_table = &data->dpm_table; 501 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 502 uint32_t i; 503 504 /* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */ 505 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { 506 table->LinkLevel[i].PcieGenSpeed = 507 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; 508 table->LinkLevel[i].PcieLaneCount = 509 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); 510 table->LinkLevel[i].EnabledForActivity = 511 1; 512 table->LinkLevel[i].SPC = 513 (uint8_t)(data->pcie_spc_cap & 0xff); 514 table->LinkLevel[i].DownThreshold = 515 PP_HOST_TO_SMC_UL(5); 516 table->LinkLevel[i].UpThreshold = 517 PP_HOST_TO_SMC_UL(30); 518 } 519 520 smu_data->smc_state_table.LinkLevelCount = 521 (uint8_t)dpm_table->pcie_speed_table.count; 522 data->dpm_level_enable_mask.pcie_dpm_enable_mask = 523 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); 524 525 return 0; 526 } 527 528 static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, 529 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) 530 { 531 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 532 pp_atomctrl_clock_dividers_vi dividers; 533 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; 534 uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; 535 uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; 536 uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; 537 uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; 538 uint32_t reference_clock; 539 uint32_t reference_divider; 540 uint32_t fbdiv; 541 int result; 542 543 /* get the engine clock dividers for this clock value*/ 544 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); 545 546 PP_ASSERT_WITH_CODE(result == 0, 547 "Error retrieving Engine Clock dividers from VBIOS.", return result); 548 549 /* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/ 550 reference_clock = atomctrl_get_reference_clock(hwmgr); 551 552 reference_divider = 1 + dividers.uc_pll_ref_div; 553 554 /* low 14 bits is fraction and high 12 bits is divider*/ 555 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; 556 557 /* SPLL_FUNC_CNTL setup*/ 558 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, 559 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); 560 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, 561 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); 562 563 /* SPLL_FUNC_CNTL_3 setup*/ 564 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, 565 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv); 566 567 /* set to use fractional accumulation*/ 568 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, 569 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1); 570 571 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 572 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) { 573 pp_atomctrl_internal_ss_info ss_info; 574 575 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; 576 if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) { 577 /* 578 * ss_info.speed_spectrum_percentage -- in unit of 0.01% 579 * ss_info.speed_spectrum_rate -- in unit of khz 580 */ 581 /* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */ 582 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); 583 584 /* clkv = 2 * D * fbdiv / NS */ 585 uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000); 586 587 cg_spll_spread_spectrum = 588 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS); 589 cg_spll_spread_spectrum = 590 PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1); 591 cg_spll_spread_spectrum_2 = 592 PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV); 593 } 594 } 595 596 sclk->SclkFrequency = engine_clock; 597 sclk->CgSpllFuncCntl3 = spll_func_cntl_3; 598 sclk->CgSpllFuncCntl4 = spll_func_cntl_4; 599 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum; 600 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2; 601 sclk->SclkDid = (uint8_t)dividers.pll_post_divider; 602 603 return 0; 604 } 605 606 static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, 607 uint32_t engine_clock, 608 SMU72_Discrete_GraphicsLevel *graphic_level) 609 { 610 int result; 611 uint32_t mvdd; 612 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 613 struct phm_ppt_v1_information *pptable_info = 614 (struct phm_ppt_v1_information *)(hwmgr->pptable); 615 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL; 616 617 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); 618 619 if (hwmgr->od_enabled) 620 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk; 621 else 622 vdd_dep_table = pptable_info->vdd_dep_on_sclk; 623 624 /* populate graphics levels*/ 625 result = tonga_get_dependency_volt_by_clk(hwmgr, 626 vdd_dep_table, engine_clock, 627 &graphic_level->MinVoltage, &mvdd); 628 PP_ASSERT_WITH_CODE((!result), 629 "can not find VDDC voltage value for VDDC " 630 "engine clock dependency table", return result); 631 632 /* SCLK frequency in units of 10KHz*/ 633 graphic_level->SclkFrequency = engine_clock; 634 /* Indicates maximum activity level for this performance level. 50% for now*/ 635 graphic_level->ActivityLevel = data->current_profile_setting.sclk_activity; 636 637 graphic_level->CcPwrDynRm = 0; 638 graphic_level->CcPwrDynRm1 = 0; 639 /* this level can be used if activity is high enough.*/ 640 graphic_level->EnabledForActivity = 0; 641 /* this level can be used for throttling.*/ 642 graphic_level->EnabledForThrottle = 1; 643 graphic_level->UpHyst = data->current_profile_setting.sclk_up_hyst; 644 graphic_level->DownHyst = data->current_profile_setting.sclk_down_hyst; 645 graphic_level->VoltageDownHyst = 0; 646 graphic_level->PowerThrottle = 0; 647 648 data->display_timing.min_clock_in_sr = 649 hwmgr->display_config->min_core_set_clock_in_sr; 650 651 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 652 PHM_PlatformCaps_SclkDeepSleep)) 653 graphic_level->DeepSleepDivId = 654 smu7_get_sleep_divider_id_from_clock(engine_clock, 655 data->display_timing.min_clock_in_sr); 656 657 /* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/ 658 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 659 660 if (!result) { 661 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/ 662 /* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/ 663 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency); 664 CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel); 665 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3); 666 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4); 667 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum); 668 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2); 669 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm); 670 CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1); 671 } 672 673 return result; 674 } 675 676 static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 677 { 678 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 679 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 680 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 681 struct smu7_dpm_table *dpm_table = &data->dpm_table; 682 struct phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table; 683 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; 684 uint32_t level_array_address = smu_data->smu7_data.dpm_table_start + 685 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel); 686 687 uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) * 688 SMU72_MAX_LEVELS_GRAPHICS; 689 690 SMU72_Discrete_GraphicsLevel *levels = smu_data->smc_state_table.GraphicsLevel; 691 692 uint32_t i, max_entry; 693 uint8_t highest_pcie_level_enabled = 0; 694 uint8_t lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0; 695 uint8_t count = 0; 696 int result = 0; 697 698 memset(levels, 0x00, level_array_size); 699 700 for (i = 0; i < dpm_table->sclk_table.count; i++) { 701 result = tonga_populate_single_graphic_level(hwmgr, 702 dpm_table->sclk_table.dpm_levels[i].value, 703 &(smu_data->smc_state_table.GraphicsLevel[i])); 704 if (result != 0) 705 return result; 706 707 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */ 708 if (i > 1) 709 smu_data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; 710 } 711 712 /* Only enable level 0 for now. */ 713 smu_data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; 714 715 /* set highest level watermark to high */ 716 if (dpm_table->sclk_table.count > 1) 717 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = 718 PPSMC_DISPLAY_WATERMARK_HIGH; 719 720 smu_data->smc_state_table.GraphicsDpmLevelCount = 721 (uint8_t)dpm_table->sclk_table.count; 722 data->dpm_level_enable_mask.sclk_dpm_enable_mask = 723 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); 724 725 if (pcie_table != NULL) { 726 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1), 727 "There must be 1 or more PCIE levels defined in PPTable.", 728 return -EINVAL); 729 max_entry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/ 730 for (i = 0; i < dpm_table->sclk_table.count; i++) { 731 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = 732 (uint8_t) ((i < max_entry) ? i : max_entry); 733 } 734 } else { 735 if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask) 736 pr_err("Pcie Dpm Enablemask is 0 !"); 737 738 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && 739 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & 740 (1<<(highest_pcie_level_enabled+1))) != 0)) { 741 highest_pcie_level_enabled++; 742 } 743 744 while (data->dpm_level_enable_mask.pcie_dpm_enable_mask && 745 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & 746 (1<<lowest_pcie_level_enabled)) == 0)) { 747 lowest_pcie_level_enabled++; 748 } 749 750 while ((count < highest_pcie_level_enabled) && 751 ((data->dpm_level_enable_mask.pcie_dpm_enable_mask & 752 (1<<(lowest_pcie_level_enabled+1+count))) == 0)) { 753 count++; 754 } 755 mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ? 756 (lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled; 757 758 759 /* set pcieDpmLevel to highest_pcie_level_enabled*/ 760 for (i = 2; i < dpm_table->sclk_table.count; i++) 761 smu_data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled; 762 763 /* set pcieDpmLevel to lowest_pcie_level_enabled*/ 764 smu_data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled; 765 766 /* set pcieDpmLevel to mid_pcie_level_enabled*/ 767 smu_data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled; 768 } 769 /* level count will send to smc once at init smc table and never change*/ 770 result = smu7_copy_bytes_to_smc(hwmgr, level_array_address, 771 (uint8_t *)levels, (uint32_t)level_array_size, 772 SMC_RAM_END); 773 774 return result; 775 } 776 777 static int tonga_calculate_mclk_params( 778 struct pp_hwmgr *hwmgr, 779 uint32_t memory_clock, 780 SMU72_Discrete_MemoryLevel *mclk, 781 bool strobe_mode, 782 bool dllStateOn 783 ) 784 { 785 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 786 787 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; 788 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; 789 uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL; 790 uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL; 791 uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL; 792 uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1; 793 uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2; 794 uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1; 795 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2; 796 797 pp_atomctrl_memory_clock_param mpll_param; 798 int result; 799 800 result = atomctrl_get_memory_pll_dividers_si(hwmgr, 801 memory_clock, &mpll_param, strobe_mode); 802 PP_ASSERT_WITH_CODE( 803 !result, 804 "Error retrieving Memory Clock Parameters from VBIOS.", 805 return result); 806 807 /* MPLL_FUNC_CNTL setup*/ 808 mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, 809 mpll_param.bw_ctrl); 810 811 /* MPLL_FUNC_CNTL_1 setup*/ 812 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, 813 MPLL_FUNC_CNTL_1, CLKF, 814 mpll_param.mpll_fb_divider.cl_kf); 815 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, 816 MPLL_FUNC_CNTL_1, CLKFRAC, 817 mpll_param.mpll_fb_divider.clk_frac); 818 mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, 819 MPLL_FUNC_CNTL_1, VCO_MODE, 820 mpll_param.vco_mode); 821 822 /* MPLL_AD_FUNC_CNTL setup*/ 823 mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl, 824 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, 825 mpll_param.mpll_post_divider); 826 827 if (data->is_memory_gddr5) { 828 /* MPLL_DQ_FUNC_CNTL setup*/ 829 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, 830 MPLL_DQ_FUNC_CNTL, YCLK_SEL, 831 mpll_param.yclk_sel); 832 mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl, 833 MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, 834 mpll_param.mpll_post_divider); 835 } 836 837 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 838 PHM_PlatformCaps_MemorySpreadSpectrumSupport)) { 839 /* 840 ************************************ 841 Fref = Reference Frequency 842 NF = Feedback divider ratio 843 NR = Reference divider ratio 844 Fnom = Nominal VCO output frequency = Fref * NF / NR 845 Fs = Spreading Rate 846 D = Percentage down-spread / 2 847 Fint = Reference input frequency to PFD = Fref / NR 848 NS = Spreading rate divider ratio = int(Fint / (2 * Fs)) 849 CLKS = NS - 1 = ISS_STEP_NUM[11:0] 850 NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2) 851 CLKV = 65536 * NV = ISS_STEP_SIZE[25:0] 852 ************************************* 853 */ 854 pp_atomctrl_internal_ss_info ss_info; 855 uint32_t freq_nom; 856 uint32_t tmp; 857 uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr); 858 859 /* for GDDR5 for all modes and DDR3 */ 860 if (1 == mpll_param.qdr) 861 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); 862 else 863 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); 864 865 /* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/ 866 tmp = (freq_nom / reference_clock); 867 tmp = tmp * tmp; 868 869 if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) { 870 /* ss_info.speed_spectrum_percentage -- in unit of 0.01% */ 871 /* ss.Info.speed_spectrum_rate -- in unit of khz */ 872 /* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */ 873 /* = reference_clock * 5 / speed_spectrum_rate */ 874 uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate; 875 876 /* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */ 877 /* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */ 878 uint32_t clkv = 879 (uint32_t)((((131 * ss_info.speed_spectrum_percentage * 880 ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom); 881 882 mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv); 883 mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks); 884 } 885 } 886 887 /* MCLK_PWRMGT_CNTL setup */ 888 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, 889 MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed); 890 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, 891 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn); 892 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, 893 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn); 894 895 /* Save the result data to outpupt memory level structure */ 896 mclk->MclkFrequency = memory_clock; 897 mclk->MpllFuncCntl = mpll_func_cntl; 898 mclk->MpllFuncCntl_1 = mpll_func_cntl_1; 899 mclk->MpllFuncCntl_2 = mpll_func_cntl_2; 900 mclk->MpllAdFuncCntl = mpll_ad_func_cntl; 901 mclk->MpllDqFuncCntl = mpll_dq_func_cntl; 902 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl; 903 mclk->DllCntl = dll_cntl; 904 mclk->MpllSs1 = mpll_ss1; 905 mclk->MpllSs2 = mpll_ss2; 906 907 return 0; 908 } 909 910 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, 911 bool strobe_mode) 912 { 913 uint8_t mc_para_index; 914 915 if (strobe_mode) { 916 if (memory_clock < 12500) 917 mc_para_index = 0x00; 918 else if (memory_clock > 47500) 919 mc_para_index = 0x0f; 920 else 921 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); 922 } else { 923 if (memory_clock < 65000) 924 mc_para_index = 0x00; 925 else if (memory_clock > 135000) 926 mc_para_index = 0x0f; 927 else 928 mc_para_index = (uint8_t)((memory_clock - 60000) / 5000); 929 } 930 931 return mc_para_index; 932 } 933 934 static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) 935 { 936 uint8_t mc_para_index; 937 938 if (memory_clock < 10000) 939 mc_para_index = 0; 940 else if (memory_clock >= 80000) 941 mc_para_index = 0x0f; 942 else 943 mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1); 944 945 return mc_para_index; 946 } 947 948 949 static int tonga_populate_single_memory_level( 950 struct pp_hwmgr *hwmgr, 951 uint32_t memory_clock, 952 SMU72_Discrete_MemoryLevel *memory_level 953 ) 954 { 955 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 956 struct phm_ppt_v1_information *pptable_info = 957 (struct phm_ppt_v1_information *)(hwmgr->pptable); 958 uint32_t mclk_edc_wr_enable_threshold = 40000; 959 uint32_t mclk_stutter_mode_threshold = 30000; 960 uint32_t mclk_edc_enable_threshold = 40000; 961 uint32_t mclk_strobe_mode_threshold = 40000; 962 phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL; 963 int result = 0; 964 bool dll_state_on; 965 uint32_t mvdd = 0; 966 967 if (hwmgr->od_enabled) 968 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk; 969 else 970 vdd_dep_table = pptable_info->vdd_dep_on_mclk; 971 972 if (NULL != vdd_dep_table) { 973 result = tonga_get_dependency_volt_by_clk(hwmgr, 974 vdd_dep_table, 975 memory_clock, 976 &memory_level->MinVoltage, &mvdd); 977 PP_ASSERT_WITH_CODE( 978 !result, 979 "can not find MinVddc voltage value from memory VDDC " 980 "voltage dependency table", 981 return result); 982 } 983 984 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) 985 memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value; 986 else 987 memory_level->MinMvdd = mvdd; 988 989 memory_level->EnabledForThrottle = 1; 990 memory_level->EnabledForActivity = 0; 991 memory_level->UpHyst = data->current_profile_setting.mclk_up_hyst; 992 memory_level->DownHyst = data->current_profile_setting.mclk_down_hyst; 993 memory_level->VoltageDownHyst = 0; 994 995 /* Indicates maximum activity level for this performance level.*/ 996 memory_level->ActivityLevel = data->current_profile_setting.mclk_activity; 997 memory_level->StutterEnable = 0; 998 memory_level->StrobeEnable = 0; 999 memory_level->EdcReadEnable = 0; 1000 memory_level->EdcWriteEnable = 0; 1001 memory_level->RttEnable = 0; 1002 1003 /* default set to low watermark. Highest level will be set to high later.*/ 1004 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 1005 1006 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; 1007 1008 if ((mclk_stutter_mode_threshold != 0) && 1009 (memory_clock <= mclk_stutter_mode_threshold) && 1010 (!data->is_uvd_enabled) 1011 && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1) 1012 && (data->display_timing.num_existing_displays <= 2) 1013 && (data->display_timing.num_existing_displays != 0)) 1014 memory_level->StutterEnable = 1; 1015 1016 /* decide strobe mode*/ 1017 memory_level->StrobeEnable = (mclk_strobe_mode_threshold != 0) && 1018 (memory_clock <= mclk_strobe_mode_threshold); 1019 1020 /* decide EDC mode and memory clock ratio*/ 1021 if (data->is_memory_gddr5) { 1022 memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock, 1023 memory_level->StrobeEnable); 1024 1025 if ((mclk_edc_enable_threshold != 0) && 1026 (memory_clock > mclk_edc_enable_threshold)) { 1027 memory_level->EdcReadEnable = 1; 1028 } 1029 1030 if ((mclk_edc_wr_enable_threshold != 0) && 1031 (memory_clock > mclk_edc_wr_enable_threshold)) { 1032 memory_level->EdcWriteEnable = 1; 1033 } 1034 1035 if (memory_level->StrobeEnable) { 1036 if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >= 1037 ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) { 1038 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; 1039 } else { 1040 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0; 1041 } 1042 1043 } else { 1044 dll_state_on = data->dll_default_on; 1045 } 1046 } else { 1047 memory_level->StrobeRatio = 1048 tonga_get_ddr3_mclk_frequency_ratio(memory_clock); 1049 dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0; 1050 } 1051 1052 result = tonga_calculate_mclk_params(hwmgr, 1053 memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on); 1054 1055 if (!result) { 1056 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd); 1057 /* MCLK frequency in units of 10KHz*/ 1058 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency); 1059 /* Indicates maximum activity level for this performance level.*/ 1060 CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel); 1061 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl); 1062 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1); 1063 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2); 1064 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl); 1065 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl); 1066 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl); 1067 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl); 1068 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1); 1069 CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2); 1070 } 1071 1072 return result; 1073 } 1074 1075 int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr); 1076 int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr) 1077 { 1078 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1079 struct tonga_smumgr *smu_data = 1080 (struct tonga_smumgr *)(hwmgr->smu_backend); 1081 struct smu7_dpm_table *dpm_table = &data->dpm_table; 1082 int result; 1083 1084 /* populate MCLK dpm table to SMU7 */ 1085 uint32_t level_array_address = 1086 smu_data->smu7_data.dpm_table_start + 1087 offsetof(SMU72_Discrete_DpmTable, MemoryLevel); 1088 uint32_t level_array_size = 1089 sizeof(SMU72_Discrete_MemoryLevel) * 1090 SMU72_MAX_LEVELS_MEMORY; 1091 SMU72_Discrete_MemoryLevel *levels = 1092 smu_data->smc_state_table.MemoryLevel; 1093 uint32_t i; 1094 1095 memset(levels, 0x00, level_array_size); 1096 1097 for (i = 0; i < dpm_table->mclk_table.count; i++) { 1098 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), 1099 "can not populate memory level as memory clock is zero", 1100 return -EINVAL); 1101 result = tonga_populate_single_memory_level( 1102 hwmgr, 1103 dpm_table->mclk_table.dpm_levels[i].value, 1104 &(smu_data->smc_state_table.MemoryLevel[i])); 1105 if (result) 1106 return result; 1107 } 1108 1109 /* Only enable level 0 for now.*/ 1110 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; 1111 1112 /* 1113 * in order to prevent MC activity from stutter mode to push DPM up. 1114 * the UVD change complements this by putting the MCLK in a higher state 1115 * by default such that we are not effected by up threshold or and MCLK DPM latency. 1116 */ 1117 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; 1118 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); 1119 1120 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; 1121 data->dpm_level_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); 1122 /* set highest level watermark to high*/ 1123 smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH; 1124 1125 /* level count will send to smc once at init smc table and never change*/ 1126 result = smu7_copy_bytes_to_smc(hwmgr, 1127 level_array_address, (uint8_t *)levels, (uint32_t)level_array_size, 1128 SMC_RAM_END); 1129 1130 return result; 1131 } 1132 1133 static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, 1134 uint32_t mclk, SMIO_Pattern *smio_pattern) 1135 { 1136 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1137 struct phm_ppt_v1_information *table_info = 1138 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1139 uint32_t i = 0; 1140 1141 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) { 1142 /* find mvdd value which clock is more than request */ 1143 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { 1144 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) { 1145 /* Always round to higher voltage. */ 1146 smio_pattern->Voltage = 1147 data->mvdd_voltage_table.entries[i].value; 1148 break; 1149 } 1150 } 1151 1152 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count, 1153 "MVDD Voltage is outside the supported range.", 1154 return -EINVAL); 1155 } else { 1156 return -EINVAL; 1157 } 1158 1159 return 0; 1160 } 1161 1162 1163 static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, 1164 SMU72_Discrete_DpmTable *table) 1165 { 1166 int result = 0; 1167 struct tonga_smumgr *smu_data = 1168 (struct tonga_smumgr *)(hwmgr->smu_backend); 1169 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1170 struct pp_atomctrl_clock_dividers_vi dividers; 1171 1172 SMIO_Pattern voltage_level; 1173 uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL; 1174 uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2; 1175 uint32_t dll_cntl = data->clock_registers.vDLL_CNTL; 1176 uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL; 1177 1178 /* The ACPI state should not do DPM on DC (or ever).*/ 1179 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 1180 1181 table->ACPILevel.MinVoltage = 1182 smu_data->smc_state_table.GraphicsLevel[0].MinVoltage; 1183 1184 /* assign zero for now*/ 1185 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); 1186 1187 /* get the engine clock dividers for this clock value*/ 1188 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, 1189 table->ACPILevel.SclkFrequency, ÷rs); 1190 1191 PP_ASSERT_WITH_CODE(result == 0, 1192 "Error retrieving Engine Clock dividers from VBIOS.", 1193 return result); 1194 1195 /* divider ID for required SCLK*/ 1196 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; 1197 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 1198 table->ACPILevel.DeepSleepDivId = 0; 1199 1200 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, 1201 SPLL_PWRON, 0); 1202 spll_func_cntl = PHM_SET_FIELD(spll_func_cntl, CG_SPLL_FUNC_CNTL, 1203 SPLL_RESET, 1); 1204 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2, 1205 SCLK_MUX_SEL, 4); 1206 1207 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; 1208 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; 1209 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3; 1210 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4; 1211 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM; 1212 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2; 1213 table->ACPILevel.CcPwrDynRm = 0; 1214 table->ACPILevel.CcPwrDynRm1 = 0; 1215 1216 1217 /* For various features to be enabled/disabled while this level is active.*/ 1218 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); 1219 /* SCLK frequency in units of 10KHz*/ 1220 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency); 1221 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl); 1222 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2); 1223 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3); 1224 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4); 1225 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum); 1226 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2); 1227 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); 1228 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1); 1229 1230 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/ 1231 table->MemoryACPILevel.MinVoltage = 1232 smu_data->smc_state_table.MemoryLevel[0].MinVoltage; 1233 1234 /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/ 1235 1236 if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level)) 1237 table->MemoryACPILevel.MinMvdd = 1238 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE); 1239 else 1240 table->MemoryACPILevel.MinMvdd = 0; 1241 1242 /* Force reset on DLL*/ 1243 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, 1244 MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1); 1245 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, 1246 MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1); 1247 1248 /* Disable DLL in ACPIState*/ 1249 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, 1250 MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0); 1251 mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl, 1252 MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0); 1253 1254 /* Enable DLL bypass signal*/ 1255 dll_cntl = PHM_SET_FIELD(dll_cntl, 1256 DLL_CNTL, MRDCK0_BYPASS, 0); 1257 dll_cntl = PHM_SET_FIELD(dll_cntl, 1258 DLL_CNTL, MRDCK1_BYPASS, 0); 1259 1260 table->MemoryACPILevel.DllCntl = 1261 PP_HOST_TO_SMC_UL(dll_cntl); 1262 table->MemoryACPILevel.MclkPwrmgtCntl = 1263 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl); 1264 table->MemoryACPILevel.MpllAdFuncCntl = 1265 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL); 1266 table->MemoryACPILevel.MpllDqFuncCntl = 1267 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL); 1268 table->MemoryACPILevel.MpllFuncCntl = 1269 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL); 1270 table->MemoryACPILevel.MpllFuncCntl_1 = 1271 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1); 1272 table->MemoryACPILevel.MpllFuncCntl_2 = 1273 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2); 1274 table->MemoryACPILevel.MpllSs1 = 1275 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1); 1276 table->MemoryACPILevel.MpllSs2 = 1277 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2); 1278 1279 table->MemoryACPILevel.EnabledForThrottle = 0; 1280 table->MemoryACPILevel.EnabledForActivity = 0; 1281 table->MemoryACPILevel.UpHyst = 0; 1282 table->MemoryACPILevel.DownHyst = 100; 1283 table->MemoryACPILevel.VoltageDownHyst = 0; 1284 /* Indicates maximum activity level for this performance level.*/ 1285 table->MemoryACPILevel.ActivityLevel = 1286 PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity); 1287 1288 table->MemoryACPILevel.StutterEnable = 0; 1289 table->MemoryACPILevel.StrobeEnable = 0; 1290 table->MemoryACPILevel.EdcReadEnable = 0; 1291 table->MemoryACPILevel.EdcWriteEnable = 0; 1292 table->MemoryACPILevel.RttEnable = 0; 1293 1294 return result; 1295 } 1296 1297 static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, 1298 SMU72_Discrete_DpmTable *table) 1299 { 1300 int result = 0; 1301 1302 uint8_t count; 1303 pp_atomctrl_clock_dividers_vi dividers; 1304 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1305 struct phm_ppt_v1_information *pptable_info = 1306 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1307 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 1308 pptable_info->mm_dep_table; 1309 1310 table->UvdLevelCount = (uint8_t) (mm_table->count); 1311 table->UvdBootLevel = 0; 1312 1313 for (count = 0; count < table->UvdLevelCount; count++) { 1314 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; 1315 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; 1316 table->UvdLevel[count].MinVoltage.Vddc = 1317 phm_get_voltage_index(pptable_info->vddc_lookup_table, 1318 mm_table->entries[count].vddc); 1319 table->UvdLevel[count].MinVoltage.VddGfx = 1320 (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ? 1321 phm_get_voltage_index(pptable_info->vddgfx_lookup_table, 1322 mm_table->entries[count].vddgfx) : 0; 1323 table->UvdLevel[count].MinVoltage.Vddci = 1324 phm_get_voltage_id(&data->vddci_voltage_table, 1325 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); 1326 table->UvdLevel[count].MinVoltage.Phases = 1; 1327 1328 /* retrieve divider value for VBIOS */ 1329 result = atomctrl_get_dfs_pll_dividers_vi( 1330 hwmgr, 1331 table->UvdLevel[count].VclkFrequency, 1332 ÷rs); 1333 1334 PP_ASSERT_WITH_CODE((!result), 1335 "can not find divide id for Vclk clock", 1336 return result); 1337 1338 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider; 1339 1340 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1341 table->UvdLevel[count].DclkFrequency, ÷rs); 1342 PP_ASSERT_WITH_CODE((!result), 1343 "can not find divide id for Dclk clock", 1344 return result); 1345 1346 table->UvdLevel[count].DclkDivider = 1347 (uint8_t)dividers.pll_post_divider; 1348 1349 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); 1350 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); 1351 } 1352 1353 return result; 1354 1355 } 1356 1357 static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr, 1358 SMU72_Discrete_DpmTable *table) 1359 { 1360 int result = 0; 1361 1362 uint8_t count; 1363 pp_atomctrl_clock_dividers_vi dividers; 1364 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1365 struct phm_ppt_v1_information *pptable_info = 1366 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1367 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 1368 pptable_info->mm_dep_table; 1369 1370 table->VceLevelCount = (uint8_t) (mm_table->count); 1371 table->VceBootLevel = 0; 1372 1373 for (count = 0; count < table->VceLevelCount; count++) { 1374 table->VceLevel[count].Frequency = 1375 mm_table->entries[count].eclk; 1376 table->VceLevel[count].MinVoltage.Vddc = 1377 phm_get_voltage_index(pptable_info->vddc_lookup_table, 1378 mm_table->entries[count].vddc); 1379 table->VceLevel[count].MinVoltage.VddGfx = 1380 (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ? 1381 phm_get_voltage_index(pptable_info->vddgfx_lookup_table, 1382 mm_table->entries[count].vddgfx) : 0; 1383 table->VceLevel[count].MinVoltage.Vddci = 1384 phm_get_voltage_id(&data->vddci_voltage_table, 1385 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); 1386 table->VceLevel[count].MinVoltage.Phases = 1; 1387 1388 /* retrieve divider value for VBIOS */ 1389 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1390 table->VceLevel[count].Frequency, ÷rs); 1391 PP_ASSERT_WITH_CODE((!result), 1392 "can not find divide id for VCE engine clock", 1393 return result); 1394 1395 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; 1396 1397 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); 1398 } 1399 1400 return result; 1401 } 1402 1403 static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr, 1404 SMU72_Discrete_DpmTable *table) 1405 { 1406 int result = 0; 1407 uint8_t count; 1408 pp_atomctrl_clock_dividers_vi dividers; 1409 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1410 struct phm_ppt_v1_information *pptable_info = 1411 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1412 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 1413 pptable_info->mm_dep_table; 1414 1415 table->AcpLevelCount = (uint8_t) (mm_table->count); 1416 table->AcpBootLevel = 0; 1417 1418 for (count = 0; count < table->AcpLevelCount; count++) { 1419 table->AcpLevel[count].Frequency = 1420 pptable_info->mm_dep_table->entries[count].aclk; 1421 table->AcpLevel[count].MinVoltage.Vddc = 1422 phm_get_voltage_index(pptable_info->vddc_lookup_table, 1423 mm_table->entries[count].vddc); 1424 table->AcpLevel[count].MinVoltage.VddGfx = 1425 (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) ? 1426 phm_get_voltage_index(pptable_info->vddgfx_lookup_table, 1427 mm_table->entries[count].vddgfx) : 0; 1428 table->AcpLevel[count].MinVoltage.Vddci = 1429 phm_get_voltage_id(&data->vddci_voltage_table, 1430 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA); 1431 table->AcpLevel[count].MinVoltage.Phases = 1; 1432 1433 /* retrieve divider value for VBIOS */ 1434 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, 1435 table->AcpLevel[count].Frequency, ÷rs); 1436 PP_ASSERT_WITH_CODE((!result), 1437 "can not find divide id for engine clock", return result); 1438 1439 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider; 1440 1441 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency); 1442 } 1443 1444 return result; 1445 } 1446 1447 static int tonga_populate_memory_timing_parameters( 1448 struct pp_hwmgr *hwmgr, 1449 uint32_t engine_clock, 1450 uint32_t memory_clock, 1451 struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs 1452 ) 1453 { 1454 uint32_t dramTiming; 1455 uint32_t dramTiming2; 1456 uint32_t burstTime; 1457 int result; 1458 1459 result = atomctrl_set_engine_dram_timings_rv770(hwmgr, 1460 engine_clock, memory_clock); 1461 1462 PP_ASSERT_WITH_CODE(result == 0, 1463 "Error calling VBIOS to set DRAM_TIMING.", return result); 1464 1465 dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); 1466 dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); 1467 burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); 1468 1469 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming); 1470 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2); 1471 arb_regs->McArbBurstTime = (uint8_t)burstTime; 1472 1473 return 0; 1474 } 1475 1476 static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) 1477 { 1478 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1479 struct tonga_smumgr *smu_data = 1480 (struct tonga_smumgr *)(hwmgr->smu_backend); 1481 int result = 0; 1482 SMU72_Discrete_MCArbDramTimingTable arb_regs; 1483 uint32_t i, j; 1484 1485 memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable)); 1486 1487 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { 1488 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { 1489 result = tonga_populate_memory_timing_parameters 1490 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, 1491 data->dpm_table.mclk_table.dpm_levels[j].value, 1492 &arb_regs.entries[i][j]); 1493 1494 if (result) 1495 break; 1496 } 1497 } 1498 1499 if (!result) { 1500 result = smu7_copy_bytes_to_smc( 1501 hwmgr, 1502 smu_data->smu7_data.arb_table_start, 1503 (uint8_t *)&arb_regs, 1504 sizeof(SMU72_Discrete_MCArbDramTimingTable), 1505 SMC_RAM_END 1506 ); 1507 } 1508 1509 return result; 1510 } 1511 1512 static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr, 1513 SMU72_Discrete_DpmTable *table) 1514 { 1515 int result = 0; 1516 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1517 struct tonga_smumgr *smu_data = 1518 (struct tonga_smumgr *)(hwmgr->smu_backend); 1519 table->GraphicsBootLevel = 0; 1520 table->MemoryBootLevel = 0; 1521 1522 /* find boot level from dpm table*/ 1523 result = phm_find_boot_level(&(data->dpm_table.sclk_table), 1524 data->vbios_boot_state.sclk_bootup_value, 1525 (uint32_t *)&(smu_data->smc_state_table.GraphicsBootLevel)); 1526 1527 if (result != 0) { 1528 smu_data->smc_state_table.GraphicsBootLevel = 0; 1529 pr_err("[powerplay] VBIOS did not find boot engine " 1530 "clock value in dependency table. " 1531 "Using Graphics DPM level 0 !"); 1532 result = 0; 1533 } 1534 1535 result = phm_find_boot_level(&(data->dpm_table.mclk_table), 1536 data->vbios_boot_state.mclk_bootup_value, 1537 (uint32_t *)&(smu_data->smc_state_table.MemoryBootLevel)); 1538 1539 if (result != 0) { 1540 smu_data->smc_state_table.MemoryBootLevel = 0; 1541 pr_err("[powerplay] VBIOS did not find boot " 1542 "engine clock value in dependency table." 1543 "Using Memory DPM level 0 !"); 1544 result = 0; 1545 } 1546 1547 table->BootVoltage.Vddc = 1548 phm_get_voltage_id(&(data->vddc_voltage_table), 1549 data->vbios_boot_state.vddc_bootup_value); 1550 table->BootVoltage.VddGfx = 1551 phm_get_voltage_id(&(data->vddgfx_voltage_table), 1552 data->vbios_boot_state.vddgfx_bootup_value); 1553 table->BootVoltage.Vddci = 1554 phm_get_voltage_id(&(data->vddci_voltage_table), 1555 data->vbios_boot_state.vddci_bootup_value); 1556 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value; 1557 1558 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd); 1559 1560 return result; 1561 } 1562 1563 static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) 1564 { 1565 uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, 1566 volt_with_cks, value; 1567 uint16_t clock_freq_u16; 1568 struct tonga_smumgr *smu_data = 1569 (struct tonga_smumgr *)(hwmgr->smu_backend); 1570 uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, 1571 volt_offset = 0; 1572 struct phm_ppt_v1_information *table_info = 1573 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1574 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 1575 table_info->vdd_dep_on_sclk; 1576 uint32_t hw_revision, dev_id; 1577 struct amdgpu_device *adev = hwmgr->adev; 1578 1579 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount; 1580 1581 hw_revision = adev->pdev->revision; 1582 dev_id = adev->pdev->device; 1583 1584 /* Read SMU_Eefuse to read and calculate RO and determine 1585 * if the part is SS or FF. if RO >= 1660MHz, part is FF. 1586 */ 1587 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1588 ixSMU_EFUSE_0 + (146 * 4)); 1589 efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1590 ixSMU_EFUSE_0 + (148 * 4)); 1591 efuse &= 0xFF000000; 1592 efuse = efuse >> 24; 1593 efuse2 &= 0xF; 1594 1595 if (efuse2 == 1) 1596 ro = (2300 - 1350) * efuse / 255 + 1350; 1597 else 1598 ro = (2500 - 1000) * efuse / 255 + 1000; 1599 1600 if (ro >= 1660) 1601 type = 0; 1602 else 1603 type = 1; 1604 1605 /* Populate Stretch amount */ 1606 smu_data->smc_state_table.ClockStretcherAmount = stretch_amount; 1607 1608 1609 /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */ 1610 for (i = 0; i < sclk_table->count; i++) { 1611 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |= 1612 sclk_table->entries[i].cks_enable << i; 1613 if (ASICID_IS_TONGA_P(dev_id, hw_revision)) { 1614 volt_without_cks = (uint32_t)((7732 + 60 - ro - 20838 * 1615 (sclk_table->entries[i].clk/100) / 10000) * 1000 / 1616 (8730 - (5301 * (sclk_table->entries[i].clk/100) / 1000))); 1617 volt_with_cks = (uint32_t)((5250 + 51 - ro - 2404 * 1618 (sclk_table->entries[i].clk/100) / 100000) * 1000 / 1619 (6146 - (3193 * (sclk_table->entries[i].clk/100) / 1000))); 1620 } else { 1621 volt_without_cks = (uint32_t)((14041 * 1622 (sclk_table->entries[i].clk/100) / 10000 + 3571 + 75 - ro) * 1000 / 1623 (4026 - (13924 * (sclk_table->entries[i].clk/100) / 10000))); 1624 volt_with_cks = (uint32_t)((13946 * 1625 (sclk_table->entries[i].clk/100) / 10000 + 3320 + 45 - ro) * 1000 / 1626 (3664 - (11454 * (sclk_table->entries[i].clk/100) / 10000))); 1627 } 1628 if (volt_without_cks >= volt_with_cks) 1629 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks + 1630 sclk_table->entries[i].cks_voffset) * 100 / 625) + 1); 1631 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset; 1632 } 1633 1634 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, 1635 STRETCH_ENABLE, 0x0); 1636 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, 1637 masterReset, 0x1); 1638 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, 1639 staticEnable, 0x1); 1640 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE, 1641 masterReset, 0x0); 1642 1643 /* Populate CKS Lookup Table */ 1644 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5) 1645 stretch_amount2 = 0; 1646 else if (stretch_amount == 3 || stretch_amount == 4) 1647 stretch_amount2 = 1; 1648 else { 1649 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1650 PHM_PlatformCaps_ClockStretcher); 1651 PP_ASSERT_WITH_CODE(false, 1652 "Stretch Amount in PPTable not supported", 1653 return -EINVAL); 1654 } 1655 1656 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1657 ixPWR_CKS_CNTL); 1658 value &= 0xFFC2FF87; 1659 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = 1660 tonga_clock_stretcher_lookup_table[stretch_amount2][0]; 1661 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = 1662 tonga_clock_stretcher_lookup_table[stretch_amount2][1]; 1663 clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(smu_data->smc_state_table. 1664 GraphicsLevel[smu_data->smc_state_table.GraphicsDpmLevelCount - 1]. 1665 SclkFrequency) / 100); 1666 if (tonga_clock_stretcher_lookup_table[stretch_amount2][0] < 1667 clock_freq_u16 && 1668 tonga_clock_stretcher_lookup_table[stretch_amount2][1] > 1669 clock_freq_u16) { 1670 /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */ 1671 value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 16; 1672 /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */ 1673 value |= (tonga_clock_stretcher_lookup_table[stretch_amount2][2]) << 18; 1674 /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */ 1675 value |= (tonga_clock_stretch_amount_conversion 1676 [tonga_clock_stretcher_lookup_table[stretch_amount2][3]] 1677 [stretch_amount]) << 3; 1678 } 1679 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable. 1680 CKS_LOOKUPTableEntry[0].minFreq); 1681 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.CKS_LOOKUPTable. 1682 CKS_LOOKUPTableEntry[0].maxFreq); 1683 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = 1684 tonga_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F; 1685 smu_data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= 1686 (tonga_clock_stretcher_lookup_table[stretch_amount2][3]) << 7; 1687 1688 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1689 ixPWR_CKS_CNTL, value); 1690 1691 /* Populate DDT Lookup Table */ 1692 for (i = 0; i < 4; i++) { 1693 /* Assign the minimum and maximum VID stored 1694 * in the last row of Clock Stretcher Voltage Table. 1695 */ 1696 smu_data->smc_state_table.ClockStretcherDataTable. 1697 ClockStretcherDataTableEntry[i].minVID = 1698 (uint8_t) tonga_clock_stretcher_ddt_table[type][i][2]; 1699 smu_data->smc_state_table.ClockStretcherDataTable. 1700 ClockStretcherDataTableEntry[i].maxVID = 1701 (uint8_t) tonga_clock_stretcher_ddt_table[type][i][3]; 1702 /* Loop through each SCLK and check the frequency 1703 * to see if it lies within the frequency for clock stretcher. 1704 */ 1705 for (j = 0; j < smu_data->smc_state_table.GraphicsDpmLevelCount; j++) { 1706 cks_setting = 0; 1707 clock_freq = PP_SMC_TO_HOST_UL( 1708 smu_data->smc_state_table.GraphicsLevel[j].SclkFrequency); 1709 /* Check the allowed frequency against the sclk level[j]. 1710 * Sclk's endianness has already been converted, 1711 * and it's in 10Khz unit, 1712 * as opposed to Data table, which is in Mhz unit. 1713 */ 1714 if (clock_freq >= tonga_clock_stretcher_ddt_table[type][i][0] * 100) { 1715 cks_setting |= 0x2; 1716 if (clock_freq < tonga_clock_stretcher_ddt_table[type][i][1] * 100) 1717 cks_setting |= 0x1; 1718 } 1719 smu_data->smc_state_table.ClockStretcherDataTable. 1720 ClockStretcherDataTableEntry[i].setting |= cks_setting << (j * 2); 1721 } 1722 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table. 1723 ClockStretcherDataTable. 1724 ClockStretcherDataTableEntry[i].setting); 1725 } 1726 1727 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1728 ixPWR_CKS_CNTL); 1729 value &= 0xFFFFFFFE; 1730 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1731 ixPWR_CKS_CNTL, value); 1732 1733 return 0; 1734 } 1735 1736 static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr, 1737 SMU72_Discrete_DpmTable *table) 1738 { 1739 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1740 uint16_t config; 1741 1742 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { 1743 /* Splitted mode */ 1744 config = VR_SVI2_PLANE_1; 1745 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); 1746 1747 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { 1748 config = VR_SVI2_PLANE_2; 1749 table->VRConfig |= config; 1750 } else { 1751 pr_err("VDDC and VDDGFX should " 1752 "be both on SVI2 control in splitted mode !\n"); 1753 } 1754 } else { 1755 /* Merged mode */ 1756 config = VR_MERGED_WITH_VDDC; 1757 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT); 1758 1759 /* Set Vddc Voltage Controller */ 1760 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { 1761 config = VR_SVI2_PLANE_1; 1762 table->VRConfig |= config; 1763 } else { 1764 pr_err("VDDC should be on " 1765 "SVI2 control in merged mode !\n"); 1766 } 1767 } 1768 1769 /* Set Vddci Voltage Controller */ 1770 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { 1771 config = VR_SVI2_PLANE_2; /* only in merged mode */ 1772 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); 1773 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 1774 config = VR_SMIO_PATTERN_1; 1775 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT); 1776 } 1777 1778 /* Set Mvdd Voltage Controller */ 1779 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { 1780 config = VR_SMIO_PATTERN_2; 1781 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT); 1782 } 1783 1784 return 0; 1785 } 1786 1787 static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr) 1788 { 1789 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 1790 uint32_t tmp; 1791 int result; 1792 1793 /* 1794 * This is a read-modify-write on the first byte of the ARB table. 1795 * The first byte in the SMU72_Discrete_MCArbDramTimingTable structure 1796 * is the field 'current'. 1797 * This solution is ugly, but we never write the whole table only 1798 * individual fields in it. 1799 * In reality this field should not be in that structure 1800 * but in a soft register. 1801 */ 1802 result = smu7_read_smc_sram_dword(hwmgr, 1803 smu_data->smu7_data.arb_table_start, &tmp, SMC_RAM_END); 1804 1805 if (result != 0) 1806 return result; 1807 1808 tmp &= 0x00FFFFFF; 1809 tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; 1810 1811 return smu7_write_smc_sram_dword(hwmgr, 1812 smu_data->smu7_data.arb_table_start, tmp, SMC_RAM_END); 1813 } 1814 1815 1816 static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) 1817 { 1818 struct tonga_smumgr *smu_data = 1819 (struct tonga_smumgr *)(hwmgr->smu_backend); 1820 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1821 SMU72_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); 1822 struct phm_ppt_v1_information *table_info = 1823 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1824 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table; 1825 int i, j, k; 1826 const uint16_t *pdef1, *pdef2; 1827 1828 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( 1829 (uint16_t)(cac_dtp_table->usTDP * 256)); 1830 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( 1831 (uint16_t)(cac_dtp_table->usConfigurableTDP * 256)); 1832 1833 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255, 1834 "Target Operating Temp is out of Range !", 1835 ); 1836 1837 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); 1838 dpm_table->GpuTjHyst = 8; 1839 1840 dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base; 1841 1842 dpm_table->BAPM_TEMP_GRADIENT = 1843 PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient); 1844 pdef1 = defaults->bapmti_r; 1845 pdef2 = defaults->bapmti_rc; 1846 1847 for (i = 0; i < SMU72_DTE_ITERATIONS; i++) { 1848 for (j = 0; j < SMU72_DTE_SOURCES; j++) { 1849 for (k = 0; k < SMU72_DTE_SINKS; k++) { 1850 dpm_table->BAPMTI_R[i][j][k] = 1851 PP_HOST_TO_SMC_US(*pdef1); 1852 dpm_table->BAPMTI_RC[i][j][k] = 1853 PP_HOST_TO_SMC_US(*pdef2); 1854 pdef1++; 1855 pdef2++; 1856 } 1857 } 1858 } 1859 1860 return 0; 1861 } 1862 1863 static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr) 1864 { 1865 struct tonga_smumgr *smu_data = 1866 (struct tonga_smumgr *)(hwmgr->smu_backend); 1867 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1868 1869 smu_data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en; 1870 smu_data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC; 1871 smu_data->power_tune_table.SviLoadLineTrimVddC = 3; 1872 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0; 1873 1874 return 0; 1875 } 1876 1877 static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr) 1878 { 1879 uint16_t tdc_limit; 1880 struct tonga_smumgr *smu_data = 1881 (struct tonga_smumgr *)(hwmgr->smu_backend); 1882 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1883 struct phm_ppt_v1_information *table_info = 1884 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1885 1886 /* TDC number of fraction bits are changed from 8 to 7 1887 * for Fiji as requested by SMC team 1888 */ 1889 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 256); 1890 smu_data->power_tune_table.TDC_VDDC_PkgLimit = 1891 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit); 1892 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc = 1893 defaults->tdc_vddc_throttle_release_limit_perc; 1894 smu_data->power_tune_table.TDC_MAWt = defaults->tdc_mawt; 1895 1896 return 0; 1897 } 1898 1899 static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) 1900 { 1901 struct tonga_smumgr *smu_data = 1902 (struct tonga_smumgr *)(hwmgr->smu_backend); 1903 const struct tonga_pt_defaults *defaults = smu_data->power_tune_defaults; 1904 uint32_t temp; 1905 1906 if (smu7_read_smc_sram_dword(hwmgr, 1907 fuse_table_offset + 1908 offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl), 1909 (uint32_t *)&temp, SMC_RAM_END)) 1910 PP_ASSERT_WITH_CODE(false, 1911 "Attempt to read PmFuses.DW6 " 1912 "(SviLoadLineEn) from SMC Failed !", 1913 return -EINVAL); 1914 else 1915 smu_data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl; 1916 1917 return 0; 1918 } 1919 1920 static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr) 1921 { 1922 int i; 1923 struct tonga_smumgr *smu_data = 1924 (struct tonga_smumgr *)(hwmgr->smu_backend); 1925 1926 /* Currently not used. Set all to zero. */ 1927 for (i = 0; i < 16; i++) 1928 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0; 1929 1930 return 0; 1931 } 1932 1933 static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) 1934 { 1935 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 1936 1937 if ((hwmgr->thermal_controller.advanceFanControlParameters. 1938 usFanOutputSensitivity & (1 << 15)) || 1939 (hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0)) 1940 hwmgr->thermal_controller.advanceFanControlParameters. 1941 usFanOutputSensitivity = hwmgr->thermal_controller. 1942 advanceFanControlParameters.usDefaultFanOutputSensitivity; 1943 1944 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = 1945 PP_HOST_TO_SMC_US(hwmgr->thermal_controller. 1946 advanceFanControlParameters.usFanOutputSensitivity); 1947 return 0; 1948 } 1949 1950 static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr) 1951 { 1952 int i; 1953 struct tonga_smumgr *smu_data = 1954 (struct tonga_smumgr *)(hwmgr->smu_backend); 1955 1956 /* Currently not used. Set all to zero. */ 1957 for (i = 0; i < 16; i++) 1958 smu_data->power_tune_table.GnbLPML[i] = 0; 1959 1960 return 0; 1961 } 1962 1963 static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) 1964 { 1965 struct tonga_smumgr *smu_data = 1966 (struct tonga_smumgr *)(hwmgr->smu_backend); 1967 struct phm_ppt_v1_information *table_info = 1968 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1969 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd; 1970 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd; 1971 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table; 1972 1973 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256); 1974 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256); 1975 1976 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd = 1977 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd); 1978 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd = 1979 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd); 1980 1981 return 0; 1982 } 1983 1984 static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr) 1985 { 1986 struct tonga_smumgr *smu_data = 1987 (struct tonga_smumgr *)(hwmgr->smu_backend); 1988 uint32_t pm_fuse_table_offset; 1989 1990 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1991 PHM_PlatformCaps_PowerContainment)) { 1992 if (smu7_read_smc_sram_dword(hwmgr, 1993 SMU72_FIRMWARE_HEADER_LOCATION + 1994 offsetof(SMU72_Firmware_Header, PmFuseTable), 1995 &pm_fuse_table_offset, SMC_RAM_END)) 1996 PP_ASSERT_WITH_CODE(false, 1997 "Attempt to get pm_fuse_table_offset Failed !", 1998 return -EINVAL); 1999 2000 /* DW6 */ 2001 if (tonga_populate_svi_load_line(hwmgr)) 2002 PP_ASSERT_WITH_CODE(false, 2003 "Attempt to populate SviLoadLine Failed !", 2004 return -EINVAL); 2005 /* DW7 */ 2006 if (tonga_populate_tdc_limit(hwmgr)) 2007 PP_ASSERT_WITH_CODE(false, 2008 "Attempt to populate TDCLimit Failed !", 2009 return -EINVAL); 2010 /* DW8 */ 2011 if (tonga_populate_dw8(hwmgr, pm_fuse_table_offset)) 2012 PP_ASSERT_WITH_CODE(false, 2013 "Attempt to populate TdcWaterfallCtl Failed !", 2014 return -EINVAL); 2015 2016 /* DW9-DW12 */ 2017 if (tonga_populate_temperature_scaler(hwmgr) != 0) 2018 PP_ASSERT_WITH_CODE(false, 2019 "Attempt to populate LPMLTemperatureScaler Failed !", 2020 return -EINVAL); 2021 2022 /* DW13-DW14 */ 2023 if (tonga_populate_fuzzy_fan(hwmgr)) 2024 PP_ASSERT_WITH_CODE(false, 2025 "Attempt to populate Fuzzy Fan " 2026 "Control parameters Failed !", 2027 return -EINVAL); 2028 2029 /* DW15-DW18 */ 2030 if (tonga_populate_gnb_lpml(hwmgr)) 2031 PP_ASSERT_WITH_CODE(false, 2032 "Attempt to populate GnbLPML Failed !", 2033 return -EINVAL); 2034 2035 /* DW20 */ 2036 if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr)) 2037 PP_ASSERT_WITH_CODE( 2038 false, 2039 "Attempt to populate BapmVddCBaseLeakage " 2040 "Hi and Lo Sidd Failed !", 2041 return -EINVAL); 2042 2043 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset, 2044 (uint8_t *)&smu_data->power_tune_table, 2045 sizeof(struct SMU72_Discrete_PmFuses), SMC_RAM_END)) 2046 PP_ASSERT_WITH_CODE(false, 2047 "Attempt to download PmFuseTable Failed !", 2048 return -EINVAL); 2049 } 2050 return 0; 2051 } 2052 2053 static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr, 2054 SMU72_Discrete_MCRegisters *mc_reg_table) 2055 { 2056 const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend; 2057 2058 uint32_t i, j; 2059 2060 for (i = 0, j = 0; j < smu_data->mc_reg_table.last; j++) { 2061 if (smu_data->mc_reg_table.validflag & 1<<j) { 2062 PP_ASSERT_WITH_CODE( 2063 i < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE, 2064 "Index of mc_reg_table->address[] array " 2065 "out of boundary", 2066 return -EINVAL); 2067 mc_reg_table->address[i].s0 = 2068 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s0); 2069 mc_reg_table->address[i].s1 = 2070 PP_HOST_TO_SMC_US(smu_data->mc_reg_table.mc_reg_address[j].s1); 2071 i++; 2072 } 2073 } 2074 2075 mc_reg_table->last = (uint8_t)i; 2076 2077 return 0; 2078 } 2079 2080 /*convert register values from driver to SMC format */ 2081 static void tonga_convert_mc_registers( 2082 const struct tonga_mc_reg_entry *entry, 2083 SMU72_Discrete_MCRegisterSet *data, 2084 uint32_t num_entries, uint32_t valid_flag) 2085 { 2086 uint32_t i, j; 2087 2088 for (i = 0, j = 0; j < num_entries; j++) { 2089 if (valid_flag & 1<<j) { 2090 data->value[i] = PP_HOST_TO_SMC_UL(entry->mc_data[j]); 2091 i++; 2092 } 2093 } 2094 } 2095 2096 static int tonga_convert_mc_reg_table_entry_to_smc( 2097 struct pp_hwmgr *hwmgr, 2098 const uint32_t memory_clock, 2099 SMU72_Discrete_MCRegisterSet *mc_reg_table_data 2100 ) 2101 { 2102 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 2103 uint32_t i = 0; 2104 2105 for (i = 0; i < smu_data->mc_reg_table.num_entries; i++) { 2106 if (memory_clock <= 2107 smu_data->mc_reg_table.mc_reg_table_entry[i].mclk_max) { 2108 break; 2109 } 2110 } 2111 2112 if ((i == smu_data->mc_reg_table.num_entries) && (i > 0)) 2113 --i; 2114 2115 tonga_convert_mc_registers(&smu_data->mc_reg_table.mc_reg_table_entry[i], 2116 mc_reg_table_data, smu_data->mc_reg_table.last, 2117 smu_data->mc_reg_table.validflag); 2118 2119 return 0; 2120 } 2121 2122 static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr, 2123 SMU72_Discrete_MCRegisters *mc_regs) 2124 { 2125 int result = 0; 2126 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2127 int res; 2128 uint32_t i; 2129 2130 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { 2131 res = tonga_convert_mc_reg_table_entry_to_smc( 2132 hwmgr, 2133 data->dpm_table.mclk_table.dpm_levels[i].value, 2134 &mc_regs->data[i] 2135 ); 2136 2137 if (0 != res) 2138 result = res; 2139 } 2140 2141 return result; 2142 } 2143 2144 static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr) 2145 { 2146 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 2147 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2148 uint32_t address; 2149 int32_t result; 2150 2151 if (0 == (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) 2152 return 0; 2153 2154 2155 memset(&smu_data->mc_regs, 0, sizeof(SMU72_Discrete_MCRegisters)); 2156 2157 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs)); 2158 2159 if (result != 0) 2160 return result; 2161 2162 2163 address = smu_data->smu7_data.mc_reg_table_start + 2164 (uint32_t)offsetof(SMU72_Discrete_MCRegisters, data[0]); 2165 2166 return smu7_copy_bytes_to_smc( 2167 hwmgr, address, 2168 (uint8_t *)&smu_data->mc_regs.data[0], 2169 sizeof(SMU72_Discrete_MCRegisterSet) * 2170 data->dpm_table.mclk_table.count, 2171 SMC_RAM_END); 2172 } 2173 2174 static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr) 2175 { 2176 int result; 2177 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 2178 2179 memset(&smu_data->mc_regs, 0x00, sizeof(SMU72_Discrete_MCRegisters)); 2180 result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs)); 2181 PP_ASSERT_WITH_CODE(!result, 2182 "Failed to initialize MCRegTable for the MC register addresses !", 2183 return result;); 2184 2185 result = tonga_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs); 2186 PP_ASSERT_WITH_CODE(!result, 2187 "Failed to initialize MCRegTable for driver state !", 2188 return result;); 2189 2190 return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start, 2191 (uint8_t *)&smu_data->mc_regs, sizeof(SMU72_Discrete_MCRegisters), SMC_RAM_END); 2192 } 2193 2194 static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 2195 { 2196 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 2197 struct phm_ppt_v1_information *table_info = 2198 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2199 2200 if (table_info && 2201 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX && 2202 table_info->cac_dtp_table->usPowerTuneDataSetID) 2203 smu_data->power_tune_defaults = 2204 &tonga_power_tune_data_set_array 2205 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1]; 2206 else 2207 smu_data->power_tune_defaults = &tonga_power_tune_data_set_array[0]; 2208 } 2209 2210 static int tonga_init_smc_table(struct pp_hwmgr *hwmgr) 2211 { 2212 int result; 2213 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2214 struct tonga_smumgr *smu_data = 2215 (struct tonga_smumgr *)(hwmgr->smu_backend); 2216 SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table); 2217 struct phm_ppt_v1_information *table_info = 2218 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2219 2220 uint8_t i; 2221 pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; 2222 2223 2224 memset(&(smu_data->smc_state_table), 0x00, sizeof(smu_data->smc_state_table)); 2225 2226 tonga_initialize_power_tune_defaults(hwmgr); 2227 2228 if (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control) 2229 tonga_populate_smc_voltage_tables(hwmgr, table); 2230 2231 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2232 PHM_PlatformCaps_AutomaticDCTransition)) 2233 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 2234 2235 2236 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2237 PHM_PlatformCaps_StepVddc)) 2238 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 2239 2240 if (data->is_memory_gddr5) 2241 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 2242 2243 i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN); 2244 2245 if (i == 1 || i == 0) 2246 table->SystemFlags |= 0x40; 2247 2248 if (data->ulv_supported && table_info->us_ulv_voltage_offset) { 2249 result = tonga_populate_ulv_state(hwmgr, table); 2250 PP_ASSERT_WITH_CODE(!result, 2251 "Failed to initialize ULV state !", 2252 return result;); 2253 2254 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 2255 ixCG_ULV_PARAMETER, 0x40035); 2256 } 2257 2258 result = tonga_populate_smc_link_level(hwmgr, table); 2259 PP_ASSERT_WITH_CODE(!result, 2260 "Failed to initialize Link Level !", return result); 2261 2262 result = tonga_populate_all_graphic_levels(hwmgr); 2263 PP_ASSERT_WITH_CODE(!result, 2264 "Failed to initialize Graphics Level !", return result); 2265 2266 result = tonga_populate_all_memory_levels(hwmgr); 2267 PP_ASSERT_WITH_CODE(!result, 2268 "Failed to initialize Memory Level !", return result); 2269 2270 result = tonga_populate_smc_acpi_level(hwmgr, table); 2271 PP_ASSERT_WITH_CODE(!result, 2272 "Failed to initialize ACPI Level !", return result); 2273 2274 result = tonga_populate_smc_vce_level(hwmgr, table); 2275 PP_ASSERT_WITH_CODE(!result, 2276 "Failed to initialize VCE Level !", return result); 2277 2278 result = tonga_populate_smc_acp_level(hwmgr, table); 2279 PP_ASSERT_WITH_CODE(!result, 2280 "Failed to initialize ACP Level !", return result); 2281 2282 /* Since only the initial state is completely set up at this 2283 * point (the other states are just copies of the boot state) we only 2284 * need to populate the ARB settings for the initial state. 2285 */ 2286 result = tonga_program_memory_timing_parameters(hwmgr); 2287 PP_ASSERT_WITH_CODE(!result, 2288 "Failed to Write ARB settings for the initial state.", 2289 return result;); 2290 2291 result = tonga_populate_smc_uvd_level(hwmgr, table); 2292 PP_ASSERT_WITH_CODE(!result, 2293 "Failed to initialize UVD Level !", return result); 2294 2295 result = tonga_populate_smc_boot_level(hwmgr, table); 2296 PP_ASSERT_WITH_CODE(!result, 2297 "Failed to initialize Boot Level !", return result); 2298 2299 tonga_populate_bapm_parameters_in_dpm_table(hwmgr); 2300 PP_ASSERT_WITH_CODE(!result, 2301 "Failed to populate BAPM Parameters !", return result); 2302 2303 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2304 PHM_PlatformCaps_ClockStretcher)) { 2305 result = tonga_populate_clock_stretcher_data_table(hwmgr); 2306 PP_ASSERT_WITH_CODE(!result, 2307 "Failed to populate Clock Stretcher Data Table !", 2308 return result;); 2309 } 2310 table->GraphicsVoltageChangeEnable = 1; 2311 table->GraphicsThermThrottleEnable = 1; 2312 table->GraphicsInterval = 1; 2313 table->VoltageInterval = 1; 2314 table->ThermalInterval = 1; 2315 table->TemperatureLimitHigh = 2316 table_info->cac_dtp_table->usTargetOperatingTemp * 2317 SMU7_Q88_FORMAT_CONVERSION_UNIT; 2318 table->TemperatureLimitLow = 2319 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) * 2320 SMU7_Q88_FORMAT_CONVERSION_UNIT; 2321 table->MemoryVoltageChangeEnable = 1; 2322 table->MemoryInterval = 1; 2323 table->VoltageResponseTime = 0; 2324 table->PhaseResponseTime = 0; 2325 table->MemoryThermThrottleEnable = 1; 2326 2327 /* 2328 * Cail reads current link status and reports it as cap (we cannot 2329 * change this due to some previous issues we had) 2330 * SMC drops the link status to lowest level after enabling 2331 * DPM by PowerPlay. After pnp or toggling CF, driver gets reloaded again 2332 * but this time Cail reads current link status which was set to low by 2333 * SMC and reports it as cap to powerplay 2334 * To avoid it, we set PCIeBootLinkLevel to highest dpm level 2335 */ 2336 PP_ASSERT_WITH_CODE((1 <= data->dpm_table.pcie_speed_table.count), 2337 "There must be 1 or more PCIE levels defined in PPTable.", 2338 return -EINVAL); 2339 2340 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count); 2341 2342 table->PCIeGenInterval = 1; 2343 2344 result = tonga_populate_vr_config(hwmgr, table); 2345 PP_ASSERT_WITH_CODE(!result, 2346 "Failed to populate VRConfig setting !", return result); 2347 data->vr_config = table->VRConfig; 2348 table->ThermGpio = 17; 2349 table->SclkStepSize = 0x4000; 2350 2351 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, 2352 &gpio_pin_assignment)) { 2353 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; 2354 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2355 PHM_PlatformCaps_RegulatorHot); 2356 } else { 2357 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN; 2358 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2359 PHM_PlatformCaps_RegulatorHot); 2360 } 2361 2362 if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID, 2363 &gpio_pin_assignment)) { 2364 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; 2365 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2366 PHM_PlatformCaps_AutomaticDCTransition); 2367 } else { 2368 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN; 2369 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2370 PHM_PlatformCaps_AutomaticDCTransition); 2371 } 2372 2373 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2374 PHM_PlatformCaps_Falcon_QuickTransition); 2375 2376 if (0) { 2377 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2378 PHM_PlatformCaps_AutomaticDCTransition); 2379 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2380 PHM_PlatformCaps_Falcon_QuickTransition); 2381 } 2382 2383 if (atomctrl_get_pp_assign_pin(hwmgr, 2384 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin_assignment)) { 2385 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2386 PHM_PlatformCaps_ThermalOutGPIO); 2387 2388 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift; 2389 2390 table->ThermOutPolarity = 2391 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) & 2392 (1 << gpio_pin_assignment.uc_gpio_pin_bit_shift))) ? 1 : 0; 2393 2394 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY; 2395 2396 /* if required, combine VRHot/PCC with thermal out GPIO*/ 2397 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2398 PHM_PlatformCaps_RegulatorHot) && 2399 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2400 PHM_PlatformCaps_CombinePCCWithThermalSignal)){ 2401 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT; 2402 } 2403 } else { 2404 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2405 PHM_PlatformCaps_ThermalOutGPIO); 2406 2407 table->ThermOutGpio = 17; 2408 table->ThermOutPolarity = 1; 2409 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE; 2410 } 2411 2412 for (i = 0; i < SMU72_MAX_ENTRIES_SMIO; i++) 2413 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]); 2414 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags); 2415 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig); 2416 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1); 2417 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2); 2418 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize); 2419 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh); 2420 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow); 2421 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime); 2422 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); 2423 2424 /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ 2425 result = smu7_copy_bytes_to_smc( 2426 hwmgr, 2427 smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags), 2428 (uint8_t *)&(table->SystemFlags), 2429 sizeof(SMU72_Discrete_DpmTable) - 3 * sizeof(SMU72_PIDController), 2430 SMC_RAM_END); 2431 2432 PP_ASSERT_WITH_CODE(!result, 2433 "Failed to upload dpm data to SMC memory !", return result;); 2434 2435 result = tonga_init_arb_table_index(hwmgr); 2436 PP_ASSERT_WITH_CODE(!result, 2437 "Failed to upload arb data to SMC memory !", return result); 2438 2439 tonga_populate_pm_fuses(hwmgr); 2440 PP_ASSERT_WITH_CODE((!result), 2441 "Failed to populate initialize pm fuses !", return result); 2442 2443 result = tonga_populate_initial_mc_reg_table(hwmgr); 2444 PP_ASSERT_WITH_CODE((!result), 2445 "Failed to populate initialize MC Reg table !", return result); 2446 2447 return 0; 2448 } 2449 2450 static int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr) 2451 { 2452 struct tonga_smumgr *smu_data = 2453 (struct tonga_smumgr *)(hwmgr->smu_backend); 2454 SMU72_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; 2455 uint32_t duty100; 2456 uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; 2457 uint16_t fdo_min, slope1, slope2; 2458 uint32_t reference_clock; 2459 int res; 2460 uint64_t tmp64; 2461 2462 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2463 PHM_PlatformCaps_MicrocodeFanControl)) 2464 return 0; 2465 2466 if (hwmgr->thermal_controller.fanInfo.bNoFan) { 2467 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2468 PHM_PlatformCaps_MicrocodeFanControl); 2469 return 0; 2470 } 2471 2472 if (0 == smu_data->smu7_data.fan_table_start) { 2473 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2474 PHM_PlatformCaps_MicrocodeFanControl); 2475 return 0; 2476 } 2477 2478 duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 2479 CGS_IND_REG__SMC, 2480 CG_FDO_CTRL1, FMAX_DUTY100); 2481 2482 if (0 == duty100) { 2483 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 2484 PHM_PlatformCaps_MicrocodeFanControl); 2485 return 0; 2486 } 2487 2488 tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100; 2489 do_div(tmp64, 10000); 2490 fdo_min = (uint16_t)tmp64; 2491 2492 t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - 2493 hwmgr->thermal_controller.advanceFanControlParameters.usTMin; 2494 t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - 2495 hwmgr->thermal_controller.advanceFanControlParameters.usTMed; 2496 2497 pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - 2498 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin; 2499 pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - 2500 hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed; 2501 2502 slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 2503 slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 2504 2505 fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100); 2506 fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100); 2507 fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100); 2508 2509 fan_table.Slope1 = cpu_to_be16(slope1); 2510 fan_table.Slope2 = cpu_to_be16(slope2); 2511 2512 fan_table.FdoMin = cpu_to_be16(fdo_min); 2513 2514 fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst); 2515 2516 fan_table.HystUp = cpu_to_be16(1); 2517 2518 fan_table.HystSlope = cpu_to_be16(1); 2519 2520 fan_table.TempRespLim = cpu_to_be16(5); 2521 2522 reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 2523 2524 fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600); 2525 2526 fan_table.FdoMax = cpu_to_be16((uint16_t)duty100); 2527 2528 fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL); 2529 2530 fan_table.FanControl_GL_Flag = 1; 2531 2532 res = smu7_copy_bytes_to_smc(hwmgr, 2533 smu_data->smu7_data.fan_table_start, 2534 (uint8_t *)&fan_table, 2535 (uint32_t)sizeof(fan_table), 2536 SMC_RAM_END); 2537 2538 return 0; 2539 } 2540 2541 2542 static int tonga_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) 2543 { 2544 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2545 2546 if (data->need_update_smu7_dpm_table & 2547 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) 2548 return tonga_program_memory_timing_parameters(hwmgr); 2549 2550 return 0; 2551 } 2552 2553 static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) 2554 { 2555 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2556 struct tonga_smumgr *smu_data = 2557 (struct tonga_smumgr *)(hwmgr->smu_backend); 2558 2559 int result = 0; 2560 uint32_t low_sclk_interrupt_threshold = 0; 2561 2562 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2563 PHM_PlatformCaps_SclkThrottleLowNotification) 2564 && (data->low_sclk_interrupt_threshold != 0)) { 2565 low_sclk_interrupt_threshold = 2566 data->low_sclk_interrupt_threshold; 2567 2568 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); 2569 2570 result = smu7_copy_bytes_to_smc( 2571 hwmgr, 2572 smu_data->smu7_data.dpm_table_start + 2573 offsetof(SMU72_Discrete_DpmTable, 2574 LowSclkInterruptThreshold), 2575 (uint8_t *)&low_sclk_interrupt_threshold, 2576 sizeof(uint32_t), 2577 SMC_RAM_END); 2578 } 2579 2580 result = tonga_update_and_upload_mc_reg_table(hwmgr); 2581 2582 PP_ASSERT_WITH_CODE((!result), 2583 "Failed to upload MC reg table !", 2584 return result); 2585 2586 result = tonga_program_mem_timing_parameters(hwmgr); 2587 PP_ASSERT_WITH_CODE((result == 0), 2588 "Failed to program memory timing parameters !", 2589 ); 2590 2591 return result; 2592 } 2593 2594 static uint32_t tonga_get_offsetof(uint32_t type, uint32_t member) 2595 { 2596 switch (type) { 2597 case SMU_SoftRegisters: 2598 switch (member) { 2599 case HandshakeDisables: 2600 return offsetof(SMU72_SoftRegisters, HandshakeDisables); 2601 case VoltageChangeTimeout: 2602 return offsetof(SMU72_SoftRegisters, VoltageChangeTimeout); 2603 case AverageGraphicsActivity: 2604 return offsetof(SMU72_SoftRegisters, AverageGraphicsActivity); 2605 case PreVBlankGap: 2606 return offsetof(SMU72_SoftRegisters, PreVBlankGap); 2607 case VBlankTimeout: 2608 return offsetof(SMU72_SoftRegisters, VBlankTimeout); 2609 case UcodeLoadStatus: 2610 return offsetof(SMU72_SoftRegisters, UcodeLoadStatus); 2611 case DRAM_LOG_ADDR_H: 2612 return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_H); 2613 case DRAM_LOG_ADDR_L: 2614 return offsetof(SMU72_SoftRegisters, DRAM_LOG_ADDR_L); 2615 case DRAM_LOG_PHY_ADDR_H: 2616 return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_H); 2617 case DRAM_LOG_PHY_ADDR_L: 2618 return offsetof(SMU72_SoftRegisters, DRAM_LOG_PHY_ADDR_L); 2619 case DRAM_LOG_BUFF_SIZE: 2620 return offsetof(SMU72_SoftRegisters, DRAM_LOG_BUFF_SIZE); 2621 } 2622 break; 2623 case SMU_Discrete_DpmTable: 2624 switch (member) { 2625 case UvdBootLevel: 2626 return offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); 2627 case VceBootLevel: 2628 return offsetof(SMU72_Discrete_DpmTable, VceBootLevel); 2629 case LowSclkInterruptThreshold: 2630 return offsetof(SMU72_Discrete_DpmTable, LowSclkInterruptThreshold); 2631 } 2632 break; 2633 } 2634 pr_warn("can't get the offset of type %x member %x\n", type, member); 2635 return 0; 2636 } 2637 2638 static uint32_t tonga_get_mac_definition(uint32_t value) 2639 { 2640 switch (value) { 2641 case SMU_MAX_LEVELS_GRAPHICS: 2642 return SMU72_MAX_LEVELS_GRAPHICS; 2643 case SMU_MAX_LEVELS_MEMORY: 2644 return SMU72_MAX_LEVELS_MEMORY; 2645 case SMU_MAX_LEVELS_LINK: 2646 return SMU72_MAX_LEVELS_LINK; 2647 case SMU_MAX_ENTRIES_SMIO: 2648 return SMU72_MAX_ENTRIES_SMIO; 2649 case SMU_MAX_LEVELS_VDDC: 2650 return SMU72_MAX_LEVELS_VDDC; 2651 case SMU_MAX_LEVELS_VDDGFX: 2652 return SMU72_MAX_LEVELS_VDDGFX; 2653 case SMU_MAX_LEVELS_VDDCI: 2654 return SMU72_MAX_LEVELS_VDDCI; 2655 case SMU_MAX_LEVELS_MVDD: 2656 return SMU72_MAX_LEVELS_MVDD; 2657 } 2658 pr_warn("can't get the mac value %x\n", value); 2659 2660 return 0; 2661 } 2662 2663 static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr) 2664 { 2665 struct tonga_smumgr *smu_data = 2666 (struct tonga_smumgr *)(hwmgr->smu_backend); 2667 uint32_t mm_boot_level_offset, mm_boot_level_value; 2668 struct phm_ppt_v1_information *table_info = 2669 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2670 2671 smu_data->smc_state_table.UvdBootLevel = 0; 2672 if (table_info->mm_dep_table->count > 0) 2673 smu_data->smc_state_table.UvdBootLevel = 2674 (uint8_t) (table_info->mm_dep_table->count - 1); 2675 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + 2676 offsetof(SMU72_Discrete_DpmTable, UvdBootLevel); 2677 mm_boot_level_offset /= 4; 2678 mm_boot_level_offset *= 4; 2679 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, 2680 CGS_IND_REG__SMC, mm_boot_level_offset); 2681 mm_boot_level_value &= 0x00FFFFFF; 2682 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24; 2683 cgs_write_ind_register(hwmgr->device, 2684 CGS_IND_REG__SMC, 2685 mm_boot_level_offset, mm_boot_level_value); 2686 2687 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2688 PHM_PlatformCaps_UVDDPM) || 2689 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2690 PHM_PlatformCaps_StablePState)) 2691 smum_send_msg_to_smc_with_parameter(hwmgr, 2692 PPSMC_MSG_UVDDPM_SetEnabledMask, 2693 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel)); 2694 return 0; 2695 } 2696 2697 static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr) 2698 { 2699 struct tonga_smumgr *smu_data = 2700 (struct tonga_smumgr *)(hwmgr->smu_backend); 2701 uint32_t mm_boot_level_offset, mm_boot_level_value; 2702 struct phm_ppt_v1_information *table_info = 2703 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2704 2705 2706 smu_data->smc_state_table.VceBootLevel = 2707 (uint8_t) (table_info->mm_dep_table->count - 1); 2708 2709 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + 2710 offsetof(SMU72_Discrete_DpmTable, VceBootLevel); 2711 mm_boot_level_offset /= 4; 2712 mm_boot_level_offset *= 4; 2713 mm_boot_level_value = cgs_read_ind_register(hwmgr->device, 2714 CGS_IND_REG__SMC, mm_boot_level_offset); 2715 mm_boot_level_value &= 0xFF00FFFF; 2716 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16; 2717 cgs_write_ind_register(hwmgr->device, 2718 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); 2719 2720 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2721 PHM_PlatformCaps_StablePState)) 2722 smum_send_msg_to_smc_with_parameter(hwmgr, 2723 PPSMC_MSG_VCEDPM_SetEnabledMask, 2724 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel); 2725 return 0; 2726 } 2727 2728 static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type) 2729 { 2730 switch (type) { 2731 case SMU_UVD_TABLE: 2732 tonga_update_uvd_smc_table(hwmgr); 2733 break; 2734 case SMU_VCE_TABLE: 2735 tonga_update_vce_smc_table(hwmgr); 2736 break; 2737 default: 2738 break; 2739 } 2740 return 0; 2741 } 2742 2743 static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr) 2744 { 2745 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2746 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 2747 2748 uint32_t tmp; 2749 int result; 2750 bool error = false; 2751 2752 result = smu7_read_smc_sram_dword(hwmgr, 2753 SMU72_FIRMWARE_HEADER_LOCATION + 2754 offsetof(SMU72_Firmware_Header, DpmTable), 2755 &tmp, SMC_RAM_END); 2756 2757 if (!result) 2758 smu_data->smu7_data.dpm_table_start = tmp; 2759 2760 error |= (result != 0); 2761 2762 result = smu7_read_smc_sram_dword(hwmgr, 2763 SMU72_FIRMWARE_HEADER_LOCATION + 2764 offsetof(SMU72_Firmware_Header, SoftRegisters), 2765 &tmp, SMC_RAM_END); 2766 2767 if (!result) { 2768 data->soft_regs_start = tmp; 2769 smu_data->smu7_data.soft_regs_start = tmp; 2770 } 2771 2772 error |= (result != 0); 2773 2774 2775 result = smu7_read_smc_sram_dword(hwmgr, 2776 SMU72_FIRMWARE_HEADER_LOCATION + 2777 offsetof(SMU72_Firmware_Header, mcRegisterTable), 2778 &tmp, SMC_RAM_END); 2779 2780 if (!result) 2781 smu_data->smu7_data.mc_reg_table_start = tmp; 2782 2783 result = smu7_read_smc_sram_dword(hwmgr, 2784 SMU72_FIRMWARE_HEADER_LOCATION + 2785 offsetof(SMU72_Firmware_Header, FanTable), 2786 &tmp, SMC_RAM_END); 2787 2788 if (!result) 2789 smu_data->smu7_data.fan_table_start = tmp; 2790 2791 error |= (result != 0); 2792 2793 result = smu7_read_smc_sram_dword(hwmgr, 2794 SMU72_FIRMWARE_HEADER_LOCATION + 2795 offsetof(SMU72_Firmware_Header, mcArbDramTimingTable), 2796 &tmp, SMC_RAM_END); 2797 2798 if (!result) 2799 smu_data->smu7_data.arb_table_start = tmp; 2800 2801 error |= (result != 0); 2802 2803 result = smu7_read_smc_sram_dword(hwmgr, 2804 SMU72_FIRMWARE_HEADER_LOCATION + 2805 offsetof(SMU72_Firmware_Header, Version), 2806 &tmp, SMC_RAM_END); 2807 2808 if (!result) 2809 hwmgr->microcode_version_info.SMC = tmp; 2810 2811 error |= (result != 0); 2812 2813 return error ? 1 : 0; 2814 } 2815 2816 /*---------------------------MC----------------------------*/ 2817 2818 static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr) 2819 { 2820 return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16)); 2821 } 2822 2823 static bool tonga_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg) 2824 { 2825 bool result = true; 2826 2827 switch (in_reg) { 2828 case mmMC_SEQ_RAS_TIMING: 2829 *out_reg = mmMC_SEQ_RAS_TIMING_LP; 2830 break; 2831 2832 case mmMC_SEQ_DLL_STBY: 2833 *out_reg = mmMC_SEQ_DLL_STBY_LP; 2834 break; 2835 2836 case mmMC_SEQ_G5PDX_CMD0: 2837 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; 2838 break; 2839 2840 case mmMC_SEQ_G5PDX_CMD1: 2841 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; 2842 break; 2843 2844 case mmMC_SEQ_G5PDX_CTRL: 2845 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; 2846 break; 2847 2848 case mmMC_SEQ_CAS_TIMING: 2849 *out_reg = mmMC_SEQ_CAS_TIMING_LP; 2850 break; 2851 2852 case mmMC_SEQ_MISC_TIMING: 2853 *out_reg = mmMC_SEQ_MISC_TIMING_LP; 2854 break; 2855 2856 case mmMC_SEQ_MISC_TIMING2: 2857 *out_reg = mmMC_SEQ_MISC_TIMING2_LP; 2858 break; 2859 2860 case mmMC_SEQ_PMG_DVS_CMD: 2861 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP; 2862 break; 2863 2864 case mmMC_SEQ_PMG_DVS_CTL: 2865 *out_reg = mmMC_SEQ_PMG_DVS_CTL_LP; 2866 break; 2867 2868 case mmMC_SEQ_RD_CTL_D0: 2869 *out_reg = mmMC_SEQ_RD_CTL_D0_LP; 2870 break; 2871 2872 case mmMC_SEQ_RD_CTL_D1: 2873 *out_reg = mmMC_SEQ_RD_CTL_D1_LP; 2874 break; 2875 2876 case mmMC_SEQ_WR_CTL_D0: 2877 *out_reg = mmMC_SEQ_WR_CTL_D0_LP; 2878 break; 2879 2880 case mmMC_SEQ_WR_CTL_D1: 2881 *out_reg = mmMC_SEQ_WR_CTL_D1_LP; 2882 break; 2883 2884 case mmMC_PMG_CMD_EMRS: 2885 *out_reg = mmMC_SEQ_PMG_CMD_EMRS_LP; 2886 break; 2887 2888 case mmMC_PMG_CMD_MRS: 2889 *out_reg = mmMC_SEQ_PMG_CMD_MRS_LP; 2890 break; 2891 2892 case mmMC_PMG_CMD_MRS1: 2893 *out_reg = mmMC_SEQ_PMG_CMD_MRS1_LP; 2894 break; 2895 2896 case mmMC_SEQ_PMG_TIMING: 2897 *out_reg = mmMC_SEQ_PMG_TIMING_LP; 2898 break; 2899 2900 case mmMC_PMG_CMD_MRS2: 2901 *out_reg = mmMC_SEQ_PMG_CMD_MRS2_LP; 2902 break; 2903 2904 case mmMC_SEQ_WR_CTL_2: 2905 *out_reg = mmMC_SEQ_WR_CTL_2_LP; 2906 break; 2907 2908 default: 2909 result = false; 2910 break; 2911 } 2912 2913 return result; 2914 } 2915 2916 static int tonga_set_s0_mc_reg_index(struct tonga_mc_reg_table *table) 2917 { 2918 uint32_t i; 2919 uint16_t address; 2920 2921 for (i = 0; i < table->last; i++) { 2922 table->mc_reg_address[i].s0 = 2923 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1, 2924 &address) ? 2925 address : 2926 table->mc_reg_address[i].s1; 2927 } 2928 return 0; 2929 } 2930 2931 static int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, 2932 struct tonga_mc_reg_table *ni_table) 2933 { 2934 uint8_t i, j; 2935 2936 PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), 2937 "Invalid VramInfo table.", return -EINVAL); 2938 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES), 2939 "Invalid VramInfo table.", return -EINVAL); 2940 2941 for (i = 0; i < table->last; i++) 2942 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 2943 2944 ni_table->last = table->last; 2945 2946 for (i = 0; i < table->num_entries; i++) { 2947 ni_table->mc_reg_table_entry[i].mclk_max = 2948 table->mc_reg_table_entry[i].mclk_max; 2949 for (j = 0; j < table->last; j++) { 2950 ni_table->mc_reg_table_entry[i].mc_data[j] = 2951 table->mc_reg_table_entry[i].mc_data[j]; 2952 } 2953 } 2954 2955 ni_table->num_entries = table->num_entries; 2956 2957 return 0; 2958 } 2959 2960 static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr, 2961 struct tonga_mc_reg_table *table) 2962 { 2963 uint8_t i, j, k; 2964 uint32_t temp_reg; 2965 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2966 2967 for (i = 0, j = table->last; i < table->last; i++) { 2968 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), 2969 "Invalid VramInfo table.", return -EINVAL); 2970 2971 switch (table->mc_reg_address[i].s1) { 2972 2973 case mmMC_SEQ_MISC1: 2974 temp_reg = cgs_read_register(hwmgr->device, 2975 mmMC_PMG_CMD_EMRS); 2976 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; 2977 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; 2978 for (k = 0; k < table->num_entries; k++) { 2979 table->mc_reg_table_entry[k].mc_data[j] = 2980 ((temp_reg & 0xffff0000)) | 2981 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 2982 } 2983 j++; 2984 2985 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), 2986 "Invalid VramInfo table.", return -EINVAL); 2987 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS); 2988 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; 2989 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; 2990 for (k = 0; k < table->num_entries; k++) { 2991 table->mc_reg_table_entry[k].mc_data[j] = 2992 (temp_reg & 0xffff0000) | 2993 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 2994 2995 if (!data->is_memory_gddr5) 2996 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 2997 } 2998 j++; 2999 3000 if (!data->is_memory_gddr5) { 3001 PP_ASSERT_WITH_CODE((j < SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE), 3002 "Invalid VramInfo table.", return -EINVAL); 3003 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; 3004 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; 3005 for (k = 0; k < table->num_entries; k++) 3006 table->mc_reg_table_entry[k].mc_data[j] = 3007 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 3008 j++; 3009 } 3010 3011 break; 3012 3013 case mmMC_SEQ_RESERVE_M: 3014 temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1); 3015 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; 3016 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; 3017 for (k = 0; k < table->num_entries; k++) { 3018 table->mc_reg_table_entry[k].mc_data[j] = 3019 (temp_reg & 0xffff0000) | 3020 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 3021 } 3022 j++; 3023 break; 3024 3025 default: 3026 break; 3027 } 3028 3029 } 3030 3031 table->last = j; 3032 3033 return 0; 3034 } 3035 3036 static int tonga_set_valid_flag(struct tonga_mc_reg_table *table) 3037 { 3038 uint8_t i, j; 3039 3040 for (i = 0; i < table->last; i++) { 3041 for (j = 1; j < table->num_entries; j++) { 3042 if (table->mc_reg_table_entry[j-1].mc_data[i] != 3043 table->mc_reg_table_entry[j].mc_data[i]) { 3044 table->validflag |= (1<<i); 3045 break; 3046 } 3047 } 3048 } 3049 3050 return 0; 3051 } 3052 3053 static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) 3054 { 3055 int result; 3056 struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend); 3057 pp_atomctrl_mc_reg_table *table; 3058 struct tonga_mc_reg_table *ni_table = &smu_data->mc_reg_table; 3059 uint8_t module_index = tonga_get_memory_modile_index(hwmgr); 3060 3061 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); 3062 3063 if (table == NULL) 3064 return -ENOMEM; 3065 3066 /* Program additional LP registers that are no longer programmed by VBIOS */ 3067 cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, 3068 cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); 3069 cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, 3070 cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING)); 3071 cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, 3072 cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY)); 3073 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, 3074 cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0)); 3075 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, 3076 cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1)); 3077 cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, 3078 cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL)); 3079 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, 3080 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD)); 3081 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, 3082 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL)); 3083 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, 3084 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING)); 3085 cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, 3086 cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2)); 3087 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, 3088 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS)); 3089 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, 3090 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS)); 3091 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, 3092 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1)); 3093 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, 3094 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0)); 3095 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, 3096 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1)); 3097 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, 3098 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0)); 3099 cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, 3100 cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1)); 3101 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, 3102 cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING)); 3103 cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, 3104 cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2)); 3105 cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, 3106 cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2)); 3107 3108 memset(table, 0x00, sizeof(pp_atomctrl_mc_reg_table)); 3109 3110 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table); 3111 3112 if (!result) 3113 result = tonga_copy_vbios_smc_reg_table(table, ni_table); 3114 3115 if (!result) { 3116 tonga_set_s0_mc_reg_index(ni_table); 3117 result = tonga_set_mc_special_registers(hwmgr, ni_table); 3118 } 3119 3120 if (!result) 3121 tonga_set_valid_flag(ni_table); 3122 3123 kfree(table); 3124 3125 return result; 3126 } 3127 3128 static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr) 3129 { 3130 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, 3131 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) 3132 ? true : false; 3133 } 3134 3135 static int tonga_update_dpm_settings(struct pp_hwmgr *hwmgr, 3136 void *profile_setting) 3137 { 3138 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3139 struct tonga_smumgr *smu_data = (struct tonga_smumgr *) 3140 (hwmgr->smu_backend); 3141 struct profile_mode_setting *setting; 3142 struct SMU72_Discrete_GraphicsLevel *levels = 3143 smu_data->smc_state_table.GraphicsLevel; 3144 uint32_t array = smu_data->smu7_data.dpm_table_start + 3145 offsetof(SMU72_Discrete_DpmTable, GraphicsLevel); 3146 3147 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start + 3148 offsetof(SMU72_Discrete_DpmTable, MemoryLevel); 3149 struct SMU72_Discrete_MemoryLevel *mclk_levels = 3150 smu_data->smc_state_table.MemoryLevel; 3151 uint32_t i; 3152 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; 3153 3154 if (profile_setting == NULL) 3155 return -EINVAL; 3156 3157 setting = (struct profile_mode_setting *)profile_setting; 3158 3159 if (setting->bupdate_sclk) { 3160 if (!data->sclk_dpm_key_disabled) 3161 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel); 3162 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) { 3163 if (levels[i].ActivityLevel != 3164 cpu_to_be16(setting->sclk_activity)) { 3165 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity); 3166 3167 clk_activity_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i) 3168 + offsetof(SMU72_Discrete_GraphicsLevel, ActivityLevel); 3169 offset = clk_activity_offset & ~0x3; 3170 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); 3171 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 3172 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); 3173 3174 } 3175 if (levels[i].UpHyst != setting->sclk_up_hyst || 3176 levels[i].DownHyst != setting->sclk_down_hyst) { 3177 levels[i].UpHyst = setting->sclk_up_hyst; 3178 levels[i].DownHyst = setting->sclk_down_hyst; 3179 up_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i) 3180 + offsetof(SMU72_Discrete_GraphicsLevel, UpHyst); 3181 down_hyst_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i) 3182 + offsetof(SMU72_Discrete_GraphicsLevel, DownHyst); 3183 offset = up_hyst_offset & ~0x3; 3184 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); 3185 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t)); 3186 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t)); 3187 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); 3188 } 3189 } 3190 if (!data->sclk_dpm_key_disabled) 3191 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel); 3192 } 3193 3194 if (setting->bupdate_mclk) { 3195 if (!data->mclk_dpm_key_disabled) 3196 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel); 3197 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) { 3198 if (mclk_levels[i].ActivityLevel != 3199 cpu_to_be16(setting->mclk_activity)) { 3200 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity); 3201 3202 clk_activity_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i) 3203 + offsetof(SMU72_Discrete_MemoryLevel, ActivityLevel); 3204 offset = clk_activity_offset & ~0x3; 3205 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); 3206 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t)); 3207 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); 3208 3209 } 3210 if (mclk_levels[i].UpHyst != setting->mclk_up_hyst || 3211 mclk_levels[i].DownHyst != setting->mclk_down_hyst) { 3212 mclk_levels[i].UpHyst = setting->mclk_up_hyst; 3213 mclk_levels[i].DownHyst = setting->mclk_down_hyst; 3214 up_hyst_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i) 3215 + offsetof(SMU72_Discrete_MemoryLevel, UpHyst); 3216 down_hyst_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i) 3217 + offsetof(SMU72_Discrete_MemoryLevel, DownHyst); 3218 offset = up_hyst_offset & ~0x3; 3219 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset)); 3220 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t)); 3221 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t)); 3222 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp)); 3223 } 3224 } 3225 if (!data->mclk_dpm_key_disabled) 3226 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel); 3227 } 3228 return 0; 3229 } 3230 3231 const struct pp_smumgr_func tonga_smu_funcs = { 3232 .smu_init = &tonga_smu_init, 3233 .smu_fini = &smu7_smu_fini, 3234 .start_smu = &tonga_start_smu, 3235 .check_fw_load_finish = &smu7_check_fw_load_finish, 3236 .request_smu_load_fw = &smu7_request_smu_load_fw, 3237 .request_smu_load_specific_fw = NULL, 3238 .send_msg_to_smc = &smu7_send_msg_to_smc, 3239 .send_msg_to_smc_with_parameter = &smu7_send_msg_to_smc_with_parameter, 3240 .download_pptable_settings = NULL, 3241 .upload_pptable_settings = NULL, 3242 .update_smc_table = tonga_update_smc_table, 3243 .get_offsetof = tonga_get_offsetof, 3244 .process_firmware_header = tonga_process_firmware_header, 3245 .init_smc_table = tonga_init_smc_table, 3246 .update_sclk_threshold = tonga_update_sclk_threshold, 3247 .thermal_setup_fan_table = tonga_thermal_setup_fan_table, 3248 .populate_all_graphic_levels = tonga_populate_all_graphic_levels, 3249 .populate_all_memory_levels = tonga_populate_all_memory_levels, 3250 .get_mac_definition = tonga_get_mac_definition, 3251 .initialize_mc_reg_table = tonga_initialize_mc_reg_table, 3252 .is_dpm_running = tonga_is_dpm_running, 3253 .update_dpm_settings = tonga_update_dpm_settings, 3254 }; 3255