1b843c749SSergey Zigachev /*
2b843c749SSergey Zigachev * Copyright 2017 Advanced Micro Devices, Inc.
3b843c749SSergey Zigachev *
4b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10b843c749SSergey Zigachev *
11b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13b843c749SSergey Zigachev *
14b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21b843c749SSergey Zigachev *
22b843c749SSergey Zigachev */
23b843c749SSergey Zigachev #include "pp_debug.h"
24b843c749SSergey Zigachev #include "smumgr.h"
25b843c749SSergey Zigachev #include "smu_ucode_xfer_vi.h"
26b843c749SSergey Zigachev #include "vegam_smumgr.h"
27b843c749SSergey Zigachev #include "smu/smu_7_1_3_d.h"
28b843c749SSergey Zigachev #include "smu/smu_7_1_3_sh_mask.h"
29b843c749SSergey Zigachev #include "gmc/gmc_8_1_d.h"
30b843c749SSergey Zigachev #include "gmc/gmc_8_1_sh_mask.h"
31b843c749SSergey Zigachev #include "oss/oss_3_0_d.h"
32b843c749SSergey Zigachev #include "gca/gfx_8_0_d.h"
33b843c749SSergey Zigachev #include "bif/bif_5_0_d.h"
34b843c749SSergey Zigachev #include "bif/bif_5_0_sh_mask.h"
35b843c749SSergey Zigachev #include "ppatomctrl.h"
36b843c749SSergey Zigachev #include "cgs_common.h"
37b843c749SSergey Zigachev #include "smu7_ppsmc.h"
38b843c749SSergey Zigachev
39b843c749SSergey Zigachev #include "smu7_dyn_defaults.h"
40b843c749SSergey Zigachev
41b843c749SSergey Zigachev #include "smu7_hwmgr.h"
42b843c749SSergey Zigachev #include "hardwaremanager.h"
43b843c749SSergey Zigachev #include "ppatomctrl.h"
44b843c749SSergey Zigachev #include "atombios.h"
45b843c749SSergey Zigachev #include "pppcielanes.h"
46b843c749SSergey Zigachev
47b843c749SSergey Zigachev #include "dce/dce_11_2_d.h"
48b843c749SSergey Zigachev #include "dce/dce_11_2_sh_mask.h"
49b843c749SSergey Zigachev
50b843c749SSergey Zigachev #define PPVEGAM_TARGETACTIVITY_DFLT 50
51b843c749SSergey Zigachev
52b843c749SSergey Zigachev #define VOLTAGE_VID_OFFSET_SCALE1 625
53b843c749SSergey Zigachev #define VOLTAGE_VID_OFFSET_SCALE2 100
54b843c749SSergey Zigachev #define POWERTUNE_DEFAULT_SET_MAX 1
55b843c749SSergey Zigachev #define VDDC_VDDCI_DELTA 200
56b843c749SSergey Zigachev #define MC_CG_ARB_FREQ_F1 0x0b
57b843c749SSergey Zigachev
58b843c749SSergey Zigachev #define STRAP_ASIC_RO_LSB 2168
59b843c749SSergey Zigachev #define STRAP_ASIC_RO_MSB 2175
60b843c749SSergey Zigachev
61b843c749SSergey Zigachev #define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
62b843c749SSergey Zigachev #define PPSMC_MSG_EnableModeSwitchRLCNotification ((uint16_t) 0x305)
63b843c749SSergey Zigachev
64b843c749SSergey Zigachev static const struct vegam_pt_defaults
65b843c749SSergey Zigachev vegam_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
66b843c749SSergey Zigachev /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
67b843c749SSergey Zigachev * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
68b843c749SSergey Zigachev { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
69b843c749SSergey Zigachev { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
70b843c749SSergey Zigachev { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
71b843c749SSergey Zigachev };
72b843c749SSergey Zigachev
73b843c749SSergey Zigachev static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
74b843c749SSergey Zigachev {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
75b843c749SSergey Zigachev {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
76b843c749SSergey Zigachev {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
77b843c749SSergey Zigachev {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
78b843c749SSergey Zigachev {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
79b843c749SSergey Zigachev {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
80b843c749SSergey Zigachev {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
81b843c749SSergey Zigachev {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
82b843c749SSergey Zigachev
vegam_smu_init(struct pp_hwmgr * hwmgr)83b843c749SSergey Zigachev static int vegam_smu_init(struct pp_hwmgr *hwmgr)
84b843c749SSergey Zigachev {
85b843c749SSergey Zigachev struct vegam_smumgr *smu_data;
86b843c749SSergey Zigachev
87b843c749SSergey Zigachev smu_data = kzalloc(sizeof(struct vegam_smumgr), GFP_KERNEL);
88b843c749SSergey Zigachev if (smu_data == NULL)
89b843c749SSergey Zigachev return -ENOMEM;
90b843c749SSergey Zigachev
91b843c749SSergey Zigachev hwmgr->smu_backend = smu_data;
92b843c749SSergey Zigachev
93b843c749SSergey Zigachev if (smu7_init(hwmgr)) {
94b843c749SSergey Zigachev kfree(smu_data);
95b843c749SSergey Zigachev return -EINVAL;
96b843c749SSergey Zigachev }
97b843c749SSergey Zigachev
98b843c749SSergey Zigachev return 0;
99b843c749SSergey Zigachev }
100b843c749SSergey Zigachev
vegam_start_smu_in_protection_mode(struct pp_hwmgr * hwmgr)101b843c749SSergey Zigachev static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
102b843c749SSergey Zigachev {
103b843c749SSergey Zigachev int result = 0;
104b843c749SSergey Zigachev
105b843c749SSergey Zigachev /* Wait for smc boot up */
106b843c749SSergey Zigachev /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
107b843c749SSergey Zigachev
108b843c749SSergey Zigachev /* Assert reset */
109b843c749SSergey Zigachev PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
110b843c749SSergey Zigachev SMC_SYSCON_RESET_CNTL, rst_reg, 1);
111b843c749SSergey Zigachev
112b843c749SSergey Zigachev result = smu7_upload_smu_firmware_image(hwmgr);
113b843c749SSergey Zigachev if (result != 0)
114b843c749SSergey Zigachev return result;
115b843c749SSergey Zigachev
116b843c749SSergey Zigachev /* Clear status */
117b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
118b843c749SSergey Zigachev
119b843c749SSergey Zigachev PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
120b843c749SSergey Zigachev SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
121b843c749SSergey Zigachev
122b843c749SSergey Zigachev /* De-assert reset */
123b843c749SSergey Zigachev PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
124b843c749SSergey Zigachev SMC_SYSCON_RESET_CNTL, rst_reg, 0);
125b843c749SSergey Zigachev
126b843c749SSergey Zigachev
127b843c749SSergey Zigachev PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
128b843c749SSergey Zigachev
129b843c749SSergey Zigachev
130b843c749SSergey Zigachev /* Call Test SMU message with 0x20000 offset to trigger SMU start */
131b843c749SSergey Zigachev smu7_send_msg_to_smc_offset(hwmgr);
132b843c749SSergey Zigachev
133b843c749SSergey Zigachev /* Wait done bit to be set */
134b843c749SSergey Zigachev /* Check pass/failed indicator */
135b843c749SSergey Zigachev
136b843c749SSergey Zigachev PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
137b843c749SSergey Zigachev
138b843c749SSergey Zigachev if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
139b843c749SSergey Zigachev SMU_STATUS, SMU_PASS))
140b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
141b843c749SSergey Zigachev
142b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
143b843c749SSergey Zigachev
144b843c749SSergey Zigachev PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
145b843c749SSergey Zigachev SMC_SYSCON_RESET_CNTL, rst_reg, 1);
146b843c749SSergey Zigachev
147b843c749SSergey Zigachev PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
148b843c749SSergey Zigachev SMC_SYSCON_RESET_CNTL, rst_reg, 0);
149b843c749SSergey Zigachev
150b843c749SSergey Zigachev /* Wait for firmware to initialize */
151b843c749SSergey Zigachev PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
152b843c749SSergey Zigachev
153b843c749SSergey Zigachev return result;
154b843c749SSergey Zigachev }
155b843c749SSergey Zigachev
vegam_start_smu_in_non_protection_mode(struct pp_hwmgr * hwmgr)156b843c749SSergey Zigachev static int vegam_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
157b843c749SSergey Zigachev {
158b843c749SSergey Zigachev int result = 0;
159b843c749SSergey Zigachev
160b843c749SSergey Zigachev /* wait for smc boot up */
161b843c749SSergey Zigachev PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
162b843c749SSergey Zigachev
163b843c749SSergey Zigachev /* Clear firmware interrupt enable flag */
164b843c749SSergey Zigachev /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
165b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
166b843c749SSergey Zigachev ixFIRMWARE_FLAGS, 0);
167b843c749SSergey Zigachev
168b843c749SSergey Zigachev PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
169b843c749SSergey Zigachev SMC_SYSCON_RESET_CNTL,
170b843c749SSergey Zigachev rst_reg, 1);
171b843c749SSergey Zigachev
172b843c749SSergey Zigachev result = smu7_upload_smu_firmware_image(hwmgr);
173b843c749SSergey Zigachev if (result != 0)
174b843c749SSergey Zigachev return result;
175b843c749SSergey Zigachev
176b843c749SSergey Zigachev /* Set smc instruct start point at 0x0 */
177b843c749SSergey Zigachev smu7_program_jump_on_start(hwmgr);
178b843c749SSergey Zigachev
179b843c749SSergey Zigachev PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
180b843c749SSergey Zigachev SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
181b843c749SSergey Zigachev
182b843c749SSergey Zigachev PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
183b843c749SSergey Zigachev SMC_SYSCON_RESET_CNTL, rst_reg, 0);
184b843c749SSergey Zigachev
185b843c749SSergey Zigachev /* Wait for firmware to initialize */
186b843c749SSergey Zigachev
187b843c749SSergey Zigachev PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
188b843c749SSergey Zigachev FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
189b843c749SSergey Zigachev
190b843c749SSergey Zigachev return result;
191b843c749SSergey Zigachev }
192b843c749SSergey Zigachev
vegam_start_smu(struct pp_hwmgr * hwmgr)193b843c749SSergey Zigachev static int vegam_start_smu(struct pp_hwmgr *hwmgr)
194b843c749SSergey Zigachev {
195b843c749SSergey Zigachev int result = 0;
196b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
197b843c749SSergey Zigachev
198b843c749SSergey Zigachev /* Only start SMC if SMC RAM is not running */
199b843c749SSergey Zigachev if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
200b843c749SSergey Zigachev smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
201b843c749SSergey Zigachev CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
202b843c749SSergey Zigachev smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(
203b843c749SSergey Zigachev hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
204b843c749SSergey Zigachev
205b843c749SSergey Zigachev /* Check if SMU is running in protected mode */
206b843c749SSergey Zigachev if (smu_data->protected_mode == 0)
207b843c749SSergey Zigachev result = vegam_start_smu_in_non_protection_mode(hwmgr);
208b843c749SSergey Zigachev else
209b843c749SSergey Zigachev result = vegam_start_smu_in_protection_mode(hwmgr);
210b843c749SSergey Zigachev
211b843c749SSergey Zigachev if (result != 0)
212b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
213b843c749SSergey Zigachev }
214b843c749SSergey Zigachev
215b843c749SSergey Zigachev /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
216b843c749SSergey Zigachev smu7_read_smc_sram_dword(hwmgr,
217b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU75_Firmware_Header, SoftRegisters),
218b843c749SSergey Zigachev &(smu_data->smu7_data.soft_regs_start),
219b843c749SSergey Zigachev 0x40000);
220b843c749SSergey Zigachev
221b843c749SSergey Zigachev result = smu7_request_smu_load_fw(hwmgr);
222b843c749SSergey Zigachev
223b843c749SSergey Zigachev return result;
224b843c749SSergey Zigachev }
225b843c749SSergey Zigachev
vegam_process_firmware_header(struct pp_hwmgr * hwmgr)226b843c749SSergey Zigachev static int vegam_process_firmware_header(struct pp_hwmgr *hwmgr)
227b843c749SSergey Zigachev {
228b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
229b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
230b843c749SSergey Zigachev uint32_t tmp;
231b843c749SSergey Zigachev int result;
232b843c749SSergey Zigachev bool error = false;
233b843c749SSergey Zigachev
234b843c749SSergey Zigachev result = smu7_read_smc_sram_dword(hwmgr,
235b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION +
236b843c749SSergey Zigachev offsetof(SMU75_Firmware_Header, DpmTable),
237b843c749SSergey Zigachev &tmp, SMC_RAM_END);
238b843c749SSergey Zigachev
239b843c749SSergey Zigachev if (0 == result)
240b843c749SSergey Zigachev smu_data->smu7_data.dpm_table_start = tmp;
241b843c749SSergey Zigachev
242b843c749SSergey Zigachev error |= (0 != result);
243b843c749SSergey Zigachev
244b843c749SSergey Zigachev result = smu7_read_smc_sram_dword(hwmgr,
245b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION +
246b843c749SSergey Zigachev offsetof(SMU75_Firmware_Header, SoftRegisters),
247b843c749SSergey Zigachev &tmp, SMC_RAM_END);
248b843c749SSergey Zigachev
249b843c749SSergey Zigachev if (!result) {
250b843c749SSergey Zigachev data->soft_regs_start = tmp;
251b843c749SSergey Zigachev smu_data->smu7_data.soft_regs_start = tmp;
252b843c749SSergey Zigachev }
253b843c749SSergey Zigachev
254b843c749SSergey Zigachev error |= (0 != result);
255b843c749SSergey Zigachev
256b843c749SSergey Zigachev result = smu7_read_smc_sram_dword(hwmgr,
257b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION +
258b843c749SSergey Zigachev offsetof(SMU75_Firmware_Header, mcRegisterTable),
259b843c749SSergey Zigachev &tmp, SMC_RAM_END);
260b843c749SSergey Zigachev
261b843c749SSergey Zigachev if (!result)
262b843c749SSergey Zigachev smu_data->smu7_data.mc_reg_table_start = tmp;
263b843c749SSergey Zigachev
264b843c749SSergey Zigachev result = smu7_read_smc_sram_dword(hwmgr,
265b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION +
266b843c749SSergey Zigachev offsetof(SMU75_Firmware_Header, FanTable),
267b843c749SSergey Zigachev &tmp, SMC_RAM_END);
268b843c749SSergey Zigachev
269b843c749SSergey Zigachev if (!result)
270b843c749SSergey Zigachev smu_data->smu7_data.fan_table_start = tmp;
271b843c749SSergey Zigachev
272b843c749SSergey Zigachev error |= (0 != result);
273b843c749SSergey Zigachev
274b843c749SSergey Zigachev result = smu7_read_smc_sram_dword(hwmgr,
275b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION +
276b843c749SSergey Zigachev offsetof(SMU75_Firmware_Header, mcArbDramTimingTable),
277b843c749SSergey Zigachev &tmp, SMC_RAM_END);
278b843c749SSergey Zigachev
279b843c749SSergey Zigachev if (!result)
280b843c749SSergey Zigachev smu_data->smu7_data.arb_table_start = tmp;
281b843c749SSergey Zigachev
282b843c749SSergey Zigachev error |= (0 != result);
283b843c749SSergey Zigachev
284b843c749SSergey Zigachev result = smu7_read_smc_sram_dword(hwmgr,
285b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION +
286b843c749SSergey Zigachev offsetof(SMU75_Firmware_Header, Version),
287b843c749SSergey Zigachev &tmp, SMC_RAM_END);
288b843c749SSergey Zigachev
289b843c749SSergey Zigachev if (!result)
290b843c749SSergey Zigachev hwmgr->microcode_version_info.SMC = tmp;
291b843c749SSergey Zigachev
292b843c749SSergey Zigachev error |= (0 != result);
293b843c749SSergey Zigachev
294b843c749SSergey Zigachev return error ? -1 : 0;
295b843c749SSergey Zigachev }
296b843c749SSergey Zigachev
vegam_is_dpm_running(struct pp_hwmgr * hwmgr)297b843c749SSergey Zigachev static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr)
298b843c749SSergey Zigachev {
299b843c749SSergey Zigachev return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
300b843c749SSergey Zigachev CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
301b843c749SSergey Zigachev ? true : false;
302b843c749SSergey Zigachev }
303b843c749SSergey Zigachev
vegam_get_mac_definition(uint32_t value)304b843c749SSergey Zigachev static uint32_t vegam_get_mac_definition(uint32_t value)
305b843c749SSergey Zigachev {
306b843c749SSergey Zigachev switch (value) {
307b843c749SSergey Zigachev case SMU_MAX_LEVELS_GRAPHICS:
308b843c749SSergey Zigachev return SMU75_MAX_LEVELS_GRAPHICS;
309b843c749SSergey Zigachev case SMU_MAX_LEVELS_MEMORY:
310b843c749SSergey Zigachev return SMU75_MAX_LEVELS_MEMORY;
311b843c749SSergey Zigachev case SMU_MAX_LEVELS_LINK:
312b843c749SSergey Zigachev return SMU75_MAX_LEVELS_LINK;
313b843c749SSergey Zigachev case SMU_MAX_ENTRIES_SMIO:
314b843c749SSergey Zigachev return SMU75_MAX_ENTRIES_SMIO;
315b843c749SSergey Zigachev case SMU_MAX_LEVELS_VDDC:
316b843c749SSergey Zigachev return SMU75_MAX_LEVELS_VDDC;
317b843c749SSergey Zigachev case SMU_MAX_LEVELS_VDDGFX:
318b843c749SSergey Zigachev return SMU75_MAX_LEVELS_VDDGFX;
319b843c749SSergey Zigachev case SMU_MAX_LEVELS_VDDCI:
320b843c749SSergey Zigachev return SMU75_MAX_LEVELS_VDDCI;
321b843c749SSergey Zigachev case SMU_MAX_LEVELS_MVDD:
322b843c749SSergey Zigachev return SMU75_MAX_LEVELS_MVDD;
323b843c749SSergey Zigachev case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
324b843c749SSergey Zigachev return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
325b843c749SSergey Zigachev SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
326b843c749SSergey Zigachev }
327b843c749SSergey Zigachev
328b843c749SSergey Zigachev pr_warn("can't get the mac of %x\n", value);
329b843c749SSergey Zigachev return 0;
330b843c749SSergey Zigachev }
331b843c749SSergey Zigachev
vegam_update_uvd_smc_table(struct pp_hwmgr * hwmgr)332b843c749SSergey Zigachev static int vegam_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
333b843c749SSergey Zigachev {
334b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
335b843c749SSergey Zigachev uint32_t mm_boot_level_offset, mm_boot_level_value;
336b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
337b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
338b843c749SSergey Zigachev
339b843c749SSergey Zigachev smu_data->smc_state_table.UvdBootLevel = 0;
340b843c749SSergey Zigachev if (table_info->mm_dep_table->count > 0)
341b843c749SSergey Zigachev smu_data->smc_state_table.UvdBootLevel =
342b843c749SSergey Zigachev (uint8_t) (table_info->mm_dep_table->count - 1);
343b843c749SSergey Zigachev mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
344b843c749SSergey Zigachev UvdBootLevel);
345b843c749SSergey Zigachev mm_boot_level_offset /= 4;
346b843c749SSergey Zigachev mm_boot_level_offset *= 4;
347b843c749SSergey Zigachev mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
348b843c749SSergey Zigachev CGS_IND_REG__SMC, mm_boot_level_offset);
349b843c749SSergey Zigachev mm_boot_level_value &= 0x00FFFFFF;
350b843c749SSergey Zigachev mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
351b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device,
352b843c749SSergey Zigachev CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
353b843c749SSergey Zigachev
354b843c749SSergey Zigachev if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
355b843c749SSergey Zigachev PHM_PlatformCaps_UVDDPM) ||
356b843c749SSergey Zigachev phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
357b843c749SSergey Zigachev PHM_PlatformCaps_StablePState))
358b843c749SSergey Zigachev smum_send_msg_to_smc_with_parameter(hwmgr,
359b843c749SSergey Zigachev PPSMC_MSG_UVDDPM_SetEnabledMask,
360b843c749SSergey Zigachev (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
361b843c749SSergey Zigachev return 0;
362b843c749SSergey Zigachev }
363b843c749SSergey Zigachev
vegam_update_vce_smc_table(struct pp_hwmgr * hwmgr)364b843c749SSergey Zigachev static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr)
365b843c749SSergey Zigachev {
366b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
367b843c749SSergey Zigachev uint32_t mm_boot_level_offset, mm_boot_level_value;
368b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
369b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
370b843c749SSergey Zigachev
371b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
372b843c749SSergey Zigachev PHM_PlatformCaps_StablePState))
373b843c749SSergey Zigachev smu_data->smc_state_table.VceBootLevel =
374b843c749SSergey Zigachev (uint8_t) (table_info->mm_dep_table->count - 1);
375b843c749SSergey Zigachev else
376b843c749SSergey Zigachev smu_data->smc_state_table.VceBootLevel = 0;
377b843c749SSergey Zigachev
378b843c749SSergey Zigachev mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
379b843c749SSergey Zigachev offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
380b843c749SSergey Zigachev mm_boot_level_offset /= 4;
381b843c749SSergey Zigachev mm_boot_level_offset *= 4;
382b843c749SSergey Zigachev mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
383b843c749SSergey Zigachev CGS_IND_REG__SMC, mm_boot_level_offset);
384b843c749SSergey Zigachev mm_boot_level_value &= 0xFF00FFFF;
385b843c749SSergey Zigachev mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
386b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device,
387b843c749SSergey Zigachev CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
388b843c749SSergey Zigachev
389b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
390b843c749SSergey Zigachev smum_send_msg_to_smc_with_parameter(hwmgr,
391b843c749SSergey Zigachev PPSMC_MSG_VCEDPM_SetEnabledMask,
392b843c749SSergey Zigachev (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
393b843c749SSergey Zigachev return 0;
394b843c749SSergey Zigachev }
395b843c749SSergey Zigachev
vegam_update_bif_smc_table(struct pp_hwmgr * hwmgr)396b843c749SSergey Zigachev static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr)
397b843c749SSergey Zigachev {
398b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
399b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
400b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
401b843c749SSergey Zigachev struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
402b843c749SSergey Zigachev int max_entry, i;
403b843c749SSergey Zigachev
404b843c749SSergey Zigachev max_entry = (SMU75_MAX_LEVELS_LINK < pcie_table->count) ?
405b843c749SSergey Zigachev SMU75_MAX_LEVELS_LINK :
406b843c749SSergey Zigachev pcie_table->count;
407b843c749SSergey Zigachev /* Setup BIF_SCLK levels */
408b843c749SSergey Zigachev for (i = 0; i < max_entry; i++)
409b843c749SSergey Zigachev smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
410b843c749SSergey Zigachev return 0;
411b843c749SSergey Zigachev }
412b843c749SSergey Zigachev
vegam_update_smc_table(struct pp_hwmgr * hwmgr,uint32_t type)413b843c749SSergey Zigachev static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
414b843c749SSergey Zigachev {
415b843c749SSergey Zigachev switch (type) {
416b843c749SSergey Zigachev case SMU_UVD_TABLE:
417b843c749SSergey Zigachev vegam_update_uvd_smc_table(hwmgr);
418b843c749SSergey Zigachev break;
419b843c749SSergey Zigachev case SMU_VCE_TABLE:
420b843c749SSergey Zigachev vegam_update_vce_smc_table(hwmgr);
421b843c749SSergey Zigachev break;
422b843c749SSergey Zigachev case SMU_BIF_TABLE:
423b843c749SSergey Zigachev vegam_update_bif_smc_table(hwmgr);
424b843c749SSergey Zigachev break;
425b843c749SSergey Zigachev default:
426b843c749SSergey Zigachev break;
427b843c749SSergey Zigachev }
428b843c749SSergey Zigachev return 0;
429b843c749SSergey Zigachev }
430b843c749SSergey Zigachev
vegam_initialize_power_tune_defaults(struct pp_hwmgr * hwmgr)431b843c749SSergey Zigachev static void vegam_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
432b843c749SSergey Zigachev {
433b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
434b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
435b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
436b843c749SSergey Zigachev
437b843c749SSergey Zigachev if (table_info &&
438b843c749SSergey Zigachev table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
439b843c749SSergey Zigachev table_info->cac_dtp_table->usPowerTuneDataSetID)
440b843c749SSergey Zigachev smu_data->power_tune_defaults =
441b843c749SSergey Zigachev &vegam_power_tune_data_set_array
442b843c749SSergey Zigachev [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
443b843c749SSergey Zigachev else
444b843c749SSergey Zigachev smu_data->power_tune_defaults = &vegam_power_tune_data_set_array[0];
445b843c749SSergey Zigachev
446b843c749SSergey Zigachev }
447b843c749SSergey Zigachev
vegam_populate_smc_mvdd_table(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)448b843c749SSergey Zigachev static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
449b843c749SSergey Zigachev SMU75_Discrete_DpmTable *table)
450b843c749SSergey Zigachev {
451b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
452b843c749SSergey Zigachev uint32_t count, level;
453b843c749SSergey Zigachev
454b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
455b843c749SSergey Zigachev count = data->mvdd_voltage_table.count;
456b843c749SSergey Zigachev if (count > SMU_MAX_SMIO_LEVELS)
457b843c749SSergey Zigachev count = SMU_MAX_SMIO_LEVELS;
458b843c749SSergey Zigachev for (level = 0; level < count; level++) {
459b843c749SSergey Zigachev table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
460b843c749SSergey Zigachev data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
461b843c749SSergey Zigachev /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
462b843c749SSergey Zigachev table->SmioTable2.Pattern[level].Smio =
463b843c749SSergey Zigachev (uint8_t) level;
464b843c749SSergey Zigachev table->Smio[level] |=
465b843c749SSergey Zigachev data->mvdd_voltage_table.entries[level].smio_low;
466b843c749SSergey Zigachev }
467b843c749SSergey Zigachev table->SmioMask2 = data->mvdd_voltage_table.mask_low;
468b843c749SSergey Zigachev
469b843c749SSergey Zigachev table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
470b843c749SSergey Zigachev }
471b843c749SSergey Zigachev
472b843c749SSergey Zigachev return 0;
473b843c749SSergey Zigachev }
474b843c749SSergey Zigachev
vegam_populate_smc_vddci_table(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)475b843c749SSergey Zigachev static int vegam_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
476b843c749SSergey Zigachev struct SMU75_Discrete_DpmTable *table)
477b843c749SSergey Zigachev {
478b843c749SSergey Zigachev uint32_t count, level;
479b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
480b843c749SSergey Zigachev
481b843c749SSergey Zigachev count = data->vddci_voltage_table.count;
482b843c749SSergey Zigachev
483b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
484b843c749SSergey Zigachev if (count > SMU_MAX_SMIO_LEVELS)
485b843c749SSergey Zigachev count = SMU_MAX_SMIO_LEVELS;
486b843c749SSergey Zigachev for (level = 0; level < count; ++level) {
487b843c749SSergey Zigachev table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
488b843c749SSergey Zigachev data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
489b843c749SSergey Zigachev table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
490b843c749SSergey Zigachev
491b843c749SSergey Zigachev table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
492b843c749SSergey Zigachev }
493b843c749SSergey Zigachev }
494b843c749SSergey Zigachev
495b843c749SSergey Zigachev table->SmioMask1 = data->vddci_voltage_table.mask_low;
496b843c749SSergey Zigachev
497b843c749SSergey Zigachev return 0;
498b843c749SSergey Zigachev }
499b843c749SSergey Zigachev
vegam_populate_cac_table(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)500b843c749SSergey Zigachev static int vegam_populate_cac_table(struct pp_hwmgr *hwmgr,
501b843c749SSergey Zigachev struct SMU75_Discrete_DpmTable *table)
502b843c749SSergey Zigachev {
503b843c749SSergey Zigachev uint32_t count;
504b843c749SSergey Zigachev uint8_t index;
505b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
506b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
507b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
508b843c749SSergey Zigachev struct phm_ppt_v1_voltage_lookup_table *lookup_table =
509b843c749SSergey Zigachev table_info->vddc_lookup_table;
510b843c749SSergey Zigachev /* tables is already swapped, so in order to use the value from it,
511b843c749SSergey Zigachev * we need to swap it back.
512b843c749SSergey Zigachev * We are populating vddc CAC data to BapmVddc table
513b843c749SSergey Zigachev * in split and merged mode
514b843c749SSergey Zigachev */
515b843c749SSergey Zigachev for (count = 0; count < lookup_table->count; count++) {
516b843c749SSergey Zigachev index = phm_get_voltage_index(lookup_table,
517b843c749SSergey Zigachev data->vddc_voltage_table.entries[count].value);
518b843c749SSergey Zigachev table->BapmVddcVidLoSidd[count] =
519b843c749SSergey Zigachev convert_to_vid(lookup_table->entries[index].us_cac_low);
520b843c749SSergey Zigachev table->BapmVddcVidHiSidd[count] =
521b843c749SSergey Zigachev convert_to_vid(lookup_table->entries[index].us_cac_mid);
522b843c749SSergey Zigachev table->BapmVddcVidHiSidd2[count] =
523b843c749SSergey Zigachev convert_to_vid(lookup_table->entries[index].us_cac_high);
524b843c749SSergey Zigachev }
525b843c749SSergey Zigachev
526b843c749SSergey Zigachev return 0;
527b843c749SSergey Zigachev }
528b843c749SSergey Zigachev
vegam_populate_smc_voltage_tables(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)529b843c749SSergey Zigachev static int vegam_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
530b843c749SSergey Zigachev struct SMU75_Discrete_DpmTable *table)
531b843c749SSergey Zigachev {
532b843c749SSergey Zigachev vegam_populate_smc_vddci_table(hwmgr, table);
533b843c749SSergey Zigachev vegam_populate_smc_mvdd_table(hwmgr, table);
534b843c749SSergey Zigachev vegam_populate_cac_table(hwmgr, table);
535b843c749SSergey Zigachev
536b843c749SSergey Zigachev return 0;
537b843c749SSergey Zigachev }
538b843c749SSergey Zigachev
vegam_populate_ulv_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_Ulv * state)539b843c749SSergey Zigachev static int vegam_populate_ulv_level(struct pp_hwmgr *hwmgr,
540b843c749SSergey Zigachev struct SMU75_Discrete_Ulv *state)
541b843c749SSergey Zigachev {
542b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
543b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
544b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
545b843c749SSergey Zigachev
546b843c749SSergey Zigachev state->CcPwrDynRm = 0;
547b843c749SSergey Zigachev state->CcPwrDynRm1 = 0;
548b843c749SSergey Zigachev
549b843c749SSergey Zigachev state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
550b843c749SSergey Zigachev state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
551b843c749SSergey Zigachev VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
552b843c749SSergey Zigachev
553b843c749SSergey Zigachev state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
554b843c749SSergey Zigachev
555b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
556b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
557b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
558b843c749SSergey Zigachev
559b843c749SSergey Zigachev return 0;
560b843c749SSergey Zigachev }
561b843c749SSergey Zigachev
vegam_populate_ulv_state(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)562b843c749SSergey Zigachev static int vegam_populate_ulv_state(struct pp_hwmgr *hwmgr,
563b843c749SSergey Zigachev struct SMU75_Discrete_DpmTable *table)
564b843c749SSergey Zigachev {
565b843c749SSergey Zigachev return vegam_populate_ulv_level(hwmgr, &table->Ulv);
566b843c749SSergey Zigachev }
567b843c749SSergey Zigachev
vegam_populate_smc_link_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)568b843c749SSergey Zigachev static int vegam_populate_smc_link_level(struct pp_hwmgr *hwmgr,
569b843c749SSergey Zigachev struct SMU75_Discrete_DpmTable *table)
570b843c749SSergey Zigachev {
571b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
572b843c749SSergey Zigachev struct vegam_smumgr *smu_data =
573b843c749SSergey Zigachev (struct vegam_smumgr *)(hwmgr->smu_backend);
574b843c749SSergey Zigachev struct smu7_dpm_table *dpm_table = &data->dpm_table;
575b843c749SSergey Zigachev int i;
576b843c749SSergey Zigachev
577b843c749SSergey Zigachev /* Index (dpm_table->pcie_speed_table.count)
578b843c749SSergey Zigachev * is reserved for PCIE boot level. */
579b843c749SSergey Zigachev for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
580b843c749SSergey Zigachev table->LinkLevel[i].PcieGenSpeed =
581b843c749SSergey Zigachev (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
582b843c749SSergey Zigachev table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
583b843c749SSergey Zigachev dpm_table->pcie_speed_table.dpm_levels[i].param1);
584b843c749SSergey Zigachev table->LinkLevel[i].EnabledForActivity = 1;
585b843c749SSergey Zigachev table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
586b843c749SSergey Zigachev table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
587b843c749SSergey Zigachev table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
588b843c749SSergey Zigachev }
589b843c749SSergey Zigachev
590b843c749SSergey Zigachev smu_data->smc_state_table.LinkLevelCount =
591b843c749SSergey Zigachev (uint8_t)dpm_table->pcie_speed_table.count;
592b843c749SSergey Zigachev
593b843c749SSergey Zigachev /* To Do move to hwmgr */
594b843c749SSergey Zigachev data->dpm_level_enable_mask.pcie_dpm_enable_mask =
595b843c749SSergey Zigachev phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
596b843c749SSergey Zigachev
597b843c749SSergey Zigachev return 0;
598b843c749SSergey Zigachev }
599b843c749SSergey Zigachev
vegam_get_dependency_volt_by_clk(struct pp_hwmgr * hwmgr,struct phm_ppt_v1_clock_voltage_dependency_table * dep_table,uint32_t clock,SMU_VoltageLevel * voltage,uint32_t * mvdd)600b843c749SSergey Zigachev static int vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
601b843c749SSergey Zigachev struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
602b843c749SSergey Zigachev uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
603b843c749SSergey Zigachev {
604b843c749SSergey Zigachev uint32_t i;
605b843c749SSergey Zigachev uint16_t vddci;
606b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
607b843c749SSergey Zigachev
608b843c749SSergey Zigachev *voltage = *mvdd = 0;
609b843c749SSergey Zigachev
610b843c749SSergey Zigachev /* clock - voltage dependency table is empty table */
611b843c749SSergey Zigachev if (dep_table->count == 0)
612b843c749SSergey Zigachev return -EINVAL;
613b843c749SSergey Zigachev
614b843c749SSergey Zigachev for (i = 0; i < dep_table->count; i++) {
615b843c749SSergey Zigachev /* find first sclk bigger than request */
616b843c749SSergey Zigachev if (dep_table->entries[i].clk >= clock) {
617b843c749SSergey Zigachev *voltage |= (dep_table->entries[i].vddc *
618b843c749SSergey Zigachev VOLTAGE_SCALE) << VDDC_SHIFT;
619b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
620b843c749SSergey Zigachev *voltage |= (data->vbios_boot_state.vddci_bootup_value *
621b843c749SSergey Zigachev VOLTAGE_SCALE) << VDDCI_SHIFT;
622b843c749SSergey Zigachev else if (dep_table->entries[i].vddci)
623b843c749SSergey Zigachev *voltage |= (dep_table->entries[i].vddci *
624b843c749SSergey Zigachev VOLTAGE_SCALE) << VDDCI_SHIFT;
625b843c749SSergey Zigachev else {
626b843c749SSergey Zigachev vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
627b843c749SSergey Zigachev (dep_table->entries[i].vddc -
628b843c749SSergey Zigachev (uint16_t)VDDC_VDDCI_DELTA));
629b843c749SSergey Zigachev *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
630b843c749SSergey Zigachev }
631b843c749SSergey Zigachev
632b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
633b843c749SSergey Zigachev *mvdd = data->vbios_boot_state.mvdd_bootup_value *
634b843c749SSergey Zigachev VOLTAGE_SCALE;
635b843c749SSergey Zigachev else if (dep_table->entries[i].mvdd)
636b843c749SSergey Zigachev *mvdd = (uint32_t) dep_table->entries[i].mvdd *
637b843c749SSergey Zigachev VOLTAGE_SCALE;
638b843c749SSergey Zigachev
639b843c749SSergey Zigachev *voltage |= 1 << PHASES_SHIFT;
640b843c749SSergey Zigachev return 0;
641b843c749SSergey Zigachev }
642b843c749SSergey Zigachev }
643b843c749SSergey Zigachev
644b843c749SSergey Zigachev /* sclk is bigger than max sclk in the dependence table */
645b843c749SSergey Zigachev *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
646b843c749SSergey Zigachev
647b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
648b843c749SSergey Zigachev *voltage |= (data->vbios_boot_state.vddci_bootup_value *
649b843c749SSergey Zigachev VOLTAGE_SCALE) << VDDCI_SHIFT;
650b843c749SSergey Zigachev else if (dep_table->entries[i - 1].vddci)
651b843c749SSergey Zigachev *voltage |= (dep_table->entries[i - 1].vddci *
652b843c749SSergey Zigachev VOLTAGE_SCALE) << VDDC_SHIFT;
653b843c749SSergey Zigachev else {
654b843c749SSergey Zigachev vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
655b843c749SSergey Zigachev (dep_table->entries[i - 1].vddc -
656b843c749SSergey Zigachev (uint16_t)VDDC_VDDCI_DELTA));
657b843c749SSergey Zigachev
658b843c749SSergey Zigachev *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
659b843c749SSergey Zigachev }
660b843c749SSergey Zigachev
661b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
662b843c749SSergey Zigachev *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
663b843c749SSergey Zigachev else if (dep_table->entries[i].mvdd)
664b843c749SSergey Zigachev *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
665b843c749SSergey Zigachev
666b843c749SSergey Zigachev return 0;
667b843c749SSergey Zigachev }
668b843c749SSergey Zigachev
vegam_get_sclk_range_table(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)669b843c749SSergey Zigachev static void vegam_get_sclk_range_table(struct pp_hwmgr *hwmgr,
670b843c749SSergey Zigachev SMU75_Discrete_DpmTable *table)
671b843c749SSergey Zigachev {
672b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
673b843c749SSergey Zigachev uint32_t i, ref_clk;
674b843c749SSergey Zigachev
675b843c749SSergey Zigachev struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
676b843c749SSergey Zigachev
677b843c749SSergey Zigachev ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
678b843c749SSergey Zigachev
679b843c749SSergey Zigachev if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
680b843c749SSergey Zigachev for (i = 0; i < NUM_SCLK_RANGE; i++) {
681b843c749SSergey Zigachev table->SclkFcwRangeTable[i].vco_setting =
682b843c749SSergey Zigachev range_table_from_vbios.entry[i].ucVco_setting;
683b843c749SSergey Zigachev table->SclkFcwRangeTable[i].postdiv =
684b843c749SSergey Zigachev range_table_from_vbios.entry[i].ucPostdiv;
685b843c749SSergey Zigachev table->SclkFcwRangeTable[i].fcw_pcc =
686b843c749SSergey Zigachev range_table_from_vbios.entry[i].usFcw_pcc;
687b843c749SSergey Zigachev
688b843c749SSergey Zigachev table->SclkFcwRangeTable[i].fcw_trans_upper =
689b843c749SSergey Zigachev range_table_from_vbios.entry[i].usFcw_trans_upper;
690b843c749SSergey Zigachev table->SclkFcwRangeTable[i].fcw_trans_lower =
691b843c749SSergey Zigachev range_table_from_vbios.entry[i].usRcw_trans_lower;
692b843c749SSergey Zigachev
693b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
694b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
695b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
696b843c749SSergey Zigachev }
697b843c749SSergey Zigachev return;
698b843c749SSergey Zigachev }
699b843c749SSergey Zigachev
700b843c749SSergey Zigachev for (i = 0; i < NUM_SCLK_RANGE; i++) {
701b843c749SSergey Zigachev smu_data->range_table[i].trans_lower_frequency =
702b843c749SSergey Zigachev (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
703b843c749SSergey Zigachev smu_data->range_table[i].trans_upper_frequency =
704b843c749SSergey Zigachev (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
705b843c749SSergey Zigachev
706b843c749SSergey Zigachev table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
707b843c749SSergey Zigachev table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
708b843c749SSergey Zigachev table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
709b843c749SSergey Zigachev
710b843c749SSergey Zigachev table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
711b843c749SSergey Zigachev table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
712b843c749SSergey Zigachev
713b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
714b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
715b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
716b843c749SSergey Zigachev }
717b843c749SSergey Zigachev }
718b843c749SSergey Zigachev
vegam_calculate_sclk_params(struct pp_hwmgr * hwmgr,uint32_t clock,SMU_SclkSetting * sclk_setting)719b843c749SSergey Zigachev static int vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr,
720b843c749SSergey Zigachev uint32_t clock, SMU_SclkSetting *sclk_setting)
721b843c749SSergey Zigachev {
722b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
723b843c749SSergey Zigachev const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
724b843c749SSergey Zigachev struct pp_atomctrl_clock_dividers_ai dividers;
725b843c749SSergey Zigachev uint32_t ref_clock;
726b843c749SSergey Zigachev uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
727b843c749SSergey Zigachev uint8_t i;
728b843c749SSergey Zigachev int result;
729b843c749SSergey Zigachev uint64_t temp;
730b843c749SSergey Zigachev
731b843c749SSergey Zigachev sclk_setting->SclkFrequency = clock;
732b843c749SSergey Zigachev /* get the engine clock dividers for this clock value */
733b843c749SSergey Zigachev result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
734b843c749SSergey Zigachev if (result == 0) {
735b843c749SSergey Zigachev sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
736b843c749SSergey Zigachev sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
737b843c749SSergey Zigachev sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
738b843c749SSergey Zigachev sclk_setting->PllRange = dividers.ucSclkPllRange;
739b843c749SSergey Zigachev sclk_setting->Sclk_slew_rate = 0x400;
740b843c749SSergey Zigachev sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
741b843c749SSergey Zigachev sclk_setting->Pcc_down_slew_rate = 0xffff;
742b843c749SSergey Zigachev sclk_setting->SSc_En = dividers.ucSscEnable;
743b843c749SSergey Zigachev sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
744b843c749SSergey Zigachev sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
745b843c749SSergey Zigachev sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
746b843c749SSergey Zigachev return result;
747b843c749SSergey Zigachev }
748b843c749SSergey Zigachev
749b843c749SSergey Zigachev ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
750b843c749SSergey Zigachev
751b843c749SSergey Zigachev for (i = 0; i < NUM_SCLK_RANGE; i++) {
752b843c749SSergey Zigachev if (clock > smu_data->range_table[i].trans_lower_frequency
753b843c749SSergey Zigachev && clock <= smu_data->range_table[i].trans_upper_frequency) {
754b843c749SSergey Zigachev sclk_setting->PllRange = i;
755b843c749SSergey Zigachev break;
756b843c749SSergey Zigachev }
757b843c749SSergey Zigachev }
758b843c749SSergey Zigachev
759b843c749SSergey Zigachev sclk_setting->Fcw_int = (uint16_t)
760b843c749SSergey Zigachev ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
761b843c749SSergey Zigachev ref_clock);
762b843c749SSergey Zigachev temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
763b843c749SSergey Zigachev temp <<= 0x10;
764b843c749SSergey Zigachev do_div(temp, ref_clock);
765b843c749SSergey Zigachev sclk_setting->Fcw_frac = temp & 0xffff;
766b843c749SSergey Zigachev
767b843c749SSergey Zigachev pcc_target_percent = 10; /* Hardcode 10% for now. */
768b843c749SSergey Zigachev pcc_target_freq = clock - (clock * pcc_target_percent / 100);
769b843c749SSergey Zigachev sclk_setting->Pcc_fcw_int = (uint16_t)
770b843c749SSergey Zigachev ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
771b843c749SSergey Zigachev ref_clock);
772b843c749SSergey Zigachev
773b843c749SSergey Zigachev ss_target_percent = 2; /* Hardcode 2% for now. */
774b843c749SSergey Zigachev sclk_setting->SSc_En = 0;
775b843c749SSergey Zigachev if (ss_target_percent) {
776b843c749SSergey Zigachev sclk_setting->SSc_En = 1;
777b843c749SSergey Zigachev ss_target_freq = clock - (clock * ss_target_percent / 100);
778b843c749SSergey Zigachev sclk_setting->Fcw1_int = (uint16_t)
779b843c749SSergey Zigachev ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
780b843c749SSergey Zigachev ref_clock);
781b843c749SSergey Zigachev temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
782b843c749SSergey Zigachev temp <<= 0x10;
783b843c749SSergey Zigachev do_div(temp, ref_clock);
784b843c749SSergey Zigachev sclk_setting->Fcw1_frac = temp & 0xffff;
785b843c749SSergey Zigachev }
786b843c749SSergey Zigachev
787b843c749SSergey Zigachev return 0;
788b843c749SSergey Zigachev }
789b843c749SSergey Zigachev
vegam_get_sleep_divider_id_from_clock(uint32_t clock,uint32_t clock_insr)790b843c749SSergey Zigachev static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,
791b843c749SSergey Zigachev uint32_t clock_insr)
792b843c749SSergey Zigachev {
793b843c749SSergey Zigachev uint8_t i;
794b843c749SSergey Zigachev uint32_t temp;
795b843c749SSergey Zigachev uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
796b843c749SSergey Zigachev
797b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((clock >= min),
798b843c749SSergey Zigachev "Engine clock can't satisfy stutter requirement!",
799b843c749SSergey Zigachev return 0);
800b843c749SSergey Zigachev for (i = 31; ; i--) {
801b843c749SSergey Zigachev temp = clock / (i + 1);
802b843c749SSergey Zigachev
803b843c749SSergey Zigachev if (temp >= min || i == 0)
804b843c749SSergey Zigachev break;
805b843c749SSergey Zigachev }
806b843c749SSergey Zigachev return i;
807b843c749SSergey Zigachev }
808b843c749SSergey Zigachev
vegam_populate_single_graphic_level(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU75_Discrete_GraphicsLevel * level)809b843c749SSergey Zigachev static int vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
810b843c749SSergey Zigachev uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level)
811b843c749SSergey Zigachev {
812b843c749SSergey Zigachev int result;
813b843c749SSergey Zigachev /* PP_Clocks minClocks; */
814b843c749SSergey Zigachev uint32_t mvdd;
815b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
816b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
817b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
818b843c749SSergey Zigachev SMU_SclkSetting curr_sclk_setting = { 0 };
819b843c749SSergey Zigachev
820b843c749SSergey Zigachev result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
821b843c749SSergey Zigachev
822b843c749SSergey Zigachev /* populate graphics levels */
823b843c749SSergey Zigachev result = vegam_get_dependency_volt_by_clk(hwmgr,
824b843c749SSergey Zigachev table_info->vdd_dep_on_sclk, clock,
825b843c749SSergey Zigachev &level->MinVoltage, &mvdd);
826b843c749SSergey Zigachev
827b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result),
828b843c749SSergey Zigachev "can not find VDDC voltage value for "
829b843c749SSergey Zigachev "VDDC engine clock dependency table",
830b843c749SSergey Zigachev return result);
831b843c749SSergey Zigachev level->ActivityLevel = (uint16_t)(SclkDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
832b843c749SSergey Zigachev
833b843c749SSergey Zigachev level->CcPwrDynRm = 0;
834b843c749SSergey Zigachev level->CcPwrDynRm1 = 0;
835b843c749SSergey Zigachev level->EnabledForActivity = 0;
836b843c749SSergey Zigachev level->EnabledForThrottle = 1;
837b843c749SSergey Zigachev level->VoltageDownHyst = 0;
838b843c749SSergey Zigachev level->PowerThrottle = 0;
839b843c749SSergey Zigachev data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
840b843c749SSergey Zigachev
841b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
842b843c749SSergey Zigachev level->DeepSleepDivId = vegam_get_sleep_divider_id_from_clock(clock,
843b843c749SSergey Zigachev hwmgr->display_config->min_core_set_clock_in_sr);
844b843c749SSergey Zigachev
845b843c749SSergey Zigachev level->SclkSetting = curr_sclk_setting;
846b843c749SSergey Zigachev
847b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
848b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
849b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
850b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
851b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
852b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
853b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
854b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
855b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
856b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
857b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
858b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
859b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
860b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
861b843c749SSergey Zigachev return 0;
862b843c749SSergey Zigachev }
863b843c749SSergey Zigachev
vegam_populate_all_graphic_levels(struct pp_hwmgr * hwmgr)864b843c749SSergey Zigachev static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
865b843c749SSergey Zigachev {
866b843c749SSergey Zigachev struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
867b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
868b843c749SSergey Zigachev struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
869b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
870b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
871b843c749SSergey Zigachev struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
872b843c749SSergey Zigachev uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
873b843c749SSergey Zigachev int result = 0;
874b843c749SSergey Zigachev uint32_t array = smu_data->smu7_data.dpm_table_start +
875b843c749SSergey Zigachev offsetof(SMU75_Discrete_DpmTable, GraphicsLevel);
876b843c749SSergey Zigachev uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) *
877b843c749SSergey Zigachev SMU75_MAX_LEVELS_GRAPHICS;
878b843c749SSergey Zigachev struct SMU75_Discrete_GraphicsLevel *levels =
879b843c749SSergey Zigachev smu_data->smc_state_table.GraphicsLevel;
880b843c749SSergey Zigachev uint32_t i, max_entry;
881b843c749SSergey Zigachev uint8_t hightest_pcie_level_enabled = 0,
882b843c749SSergey Zigachev lowest_pcie_level_enabled = 0,
883b843c749SSergey Zigachev mid_pcie_level_enabled = 0,
884b843c749SSergey Zigachev count = 0;
885b843c749SSergey Zigachev
886b843c749SSergey Zigachev vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
887b843c749SSergey Zigachev
888b843c749SSergey Zigachev for (i = 0; i < dpm_table->sclk_table.count; i++) {
889b843c749SSergey Zigachev
890b843c749SSergey Zigachev result = vegam_populate_single_graphic_level(hwmgr,
891b843c749SSergey Zigachev dpm_table->sclk_table.dpm_levels[i].value,
892b843c749SSergey Zigachev &(smu_data->smc_state_table.GraphicsLevel[i]));
893b843c749SSergey Zigachev if (result)
894b843c749SSergey Zigachev return result;
895b843c749SSergey Zigachev
896b843c749SSergey Zigachev levels[i].UpHyst = (uint8_t)
897b843c749SSergey Zigachev (SclkDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
898b843c749SSergey Zigachev levels[i].DownHyst = (uint8_t)
899b843c749SSergey Zigachev (SclkDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
900b843c749SSergey Zigachev /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
901b843c749SSergey Zigachev if (i > 1)
902b843c749SSergey Zigachev levels[i].DeepSleepDivId = 0;
903b843c749SSergey Zigachev }
904b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
905b843c749SSergey Zigachev PHM_PlatformCaps_SPLLShutdownSupport))
906b843c749SSergey Zigachev smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
907b843c749SSergey Zigachev
908b843c749SSergey Zigachev smu_data->smc_state_table.GraphicsDpmLevelCount =
909b843c749SSergey Zigachev (uint8_t)dpm_table->sclk_table.count;
910b843c749SSergey Zigachev hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
911b843c749SSergey Zigachev phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
912b843c749SSergey Zigachev
913b843c749SSergey Zigachev for (i = 0; i < dpm_table->sclk_table.count; i++)
914b843c749SSergey Zigachev levels[i].EnabledForActivity =
915b843c749SSergey Zigachev (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
916b843c749SSergey Zigachev
917b843c749SSergey Zigachev if (pcie_table != NULL) {
918b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
919b843c749SSergey Zigachev "There must be 1 or more PCIE levels defined in PPTable.",
920b843c749SSergey Zigachev return -EINVAL);
921b843c749SSergey Zigachev max_entry = pcie_entry_cnt - 1;
922b843c749SSergey Zigachev for (i = 0; i < dpm_table->sclk_table.count; i++)
923b843c749SSergey Zigachev levels[i].pcieDpmLevel =
924b843c749SSergey Zigachev (uint8_t) ((i < max_entry) ? i : max_entry);
925b843c749SSergey Zigachev } else {
926b843c749SSergey Zigachev while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
927b843c749SSergey Zigachev ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
928b843c749SSergey Zigachev (1 << (hightest_pcie_level_enabled + 1))) != 0))
929b843c749SSergey Zigachev hightest_pcie_level_enabled++;
930b843c749SSergey Zigachev
931b843c749SSergey Zigachev while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
932b843c749SSergey Zigachev ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
933b843c749SSergey Zigachev (1 << lowest_pcie_level_enabled)) == 0))
934b843c749SSergey Zigachev lowest_pcie_level_enabled++;
935b843c749SSergey Zigachev
936b843c749SSergey Zigachev while ((count < hightest_pcie_level_enabled) &&
937b843c749SSergey Zigachev ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
938b843c749SSergey Zigachev (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
939b843c749SSergey Zigachev count++;
940b843c749SSergey Zigachev
941b843c749SSergey Zigachev mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
942b843c749SSergey Zigachev hightest_pcie_level_enabled ?
943b843c749SSergey Zigachev (lowest_pcie_level_enabled + 1 + count) :
944b843c749SSergey Zigachev hightest_pcie_level_enabled;
945b843c749SSergey Zigachev
946b843c749SSergey Zigachev /* set pcieDpmLevel to hightest_pcie_level_enabled */
947b843c749SSergey Zigachev for (i = 2; i < dpm_table->sclk_table.count; i++)
948b843c749SSergey Zigachev levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
949b843c749SSergey Zigachev
950b843c749SSergey Zigachev /* set pcieDpmLevel to lowest_pcie_level_enabled */
951b843c749SSergey Zigachev levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
952b843c749SSergey Zigachev
953b843c749SSergey Zigachev /* set pcieDpmLevel to mid_pcie_level_enabled */
954b843c749SSergey Zigachev levels[1].pcieDpmLevel = mid_pcie_level_enabled;
955b843c749SSergey Zigachev }
956b843c749SSergey Zigachev /* level count will send to smc once at init smc table and never change */
957b843c749SSergey Zigachev result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
958b843c749SSergey Zigachev (uint32_t)array_size, SMC_RAM_END);
959b843c749SSergey Zigachev
960b843c749SSergey Zigachev return result;
961b843c749SSergey Zigachev }
962b843c749SSergey Zigachev
vegam_calculate_mclk_params(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU75_Discrete_MemoryLevel * mem_level)963b843c749SSergey Zigachev static int vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr,
964b843c749SSergey Zigachev uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
965b843c749SSergey Zigachev {
966b843c749SSergey Zigachev struct pp_atomctrl_memory_clock_param_ai mpll_param;
967b843c749SSergey Zigachev
968b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
969b843c749SSergey Zigachev clock, &mpll_param),
970b843c749SSergey Zigachev "Failed to retrieve memory pll parameter.",
971b843c749SSergey Zigachev return -EINVAL);
972b843c749SSergey Zigachev
973b843c749SSergey Zigachev mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;
974b843c749SSergey Zigachev mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int;
975b843c749SSergey Zigachev mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac;
976b843c749SSergey Zigachev mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;
977b843c749SSergey Zigachev
978b843c749SSergey Zigachev return 0;
979b843c749SSergey Zigachev }
980b843c749SSergey Zigachev
vegam_populate_single_memory_level(struct pp_hwmgr * hwmgr,uint32_t clock,struct SMU75_Discrete_MemoryLevel * mem_level)981b843c749SSergey Zigachev static int vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr,
982b843c749SSergey Zigachev uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
983b843c749SSergey Zigachev {
984b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
985b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
986b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
987b843c749SSergey Zigachev int result = 0;
988b843c749SSergey Zigachev uint32_t mclk_stutter_mode_threshold = 60000;
989b843c749SSergey Zigachev
990b843c749SSergey Zigachev
991b843c749SSergey Zigachev if (table_info->vdd_dep_on_mclk) {
992b843c749SSergey Zigachev result = vegam_get_dependency_volt_by_clk(hwmgr,
993b843c749SSergey Zigachev table_info->vdd_dep_on_mclk, clock,
994b843c749SSergey Zigachev &mem_level->MinVoltage, &mem_level->MinMvdd);
995b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
996b843c749SSergey Zigachev "can not find MinVddc voltage value from memory "
997b843c749SSergey Zigachev "VDDC voltage dependency table", return result);
998b843c749SSergey Zigachev }
999b843c749SSergey Zigachev
1000b843c749SSergey Zigachev result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);
1001b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1002b843c749SSergey Zigachev "Failed to calculate mclk params.",
1003b843c749SSergey Zigachev return -EINVAL);
1004b843c749SSergey Zigachev
1005b843c749SSergey Zigachev mem_level->EnabledForThrottle = 1;
1006b843c749SSergey Zigachev mem_level->EnabledForActivity = 0;
1007b843c749SSergey Zigachev mem_level->VoltageDownHyst = 0;
1008b843c749SSergey Zigachev mem_level->ActivityLevel = (uint16_t)
1009b843c749SSergey Zigachev (MemoryDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
1010b843c749SSergey Zigachev mem_level->StutterEnable = false;
1011b843c749SSergey Zigachev mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1012b843c749SSergey Zigachev
1013b843c749SSergey Zigachev data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1014b843c749SSergey Zigachev
1015b843c749SSergey Zigachev if (mclk_stutter_mode_threshold &&
1016b843c749SSergey Zigachev (clock <= mclk_stutter_mode_threshold) &&
1017b843c749SSergey Zigachev (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1018b843c749SSergey Zigachev STUTTER_ENABLE) & 0x1))
1019b843c749SSergey Zigachev mem_level->StutterEnable = true;
1020b843c749SSergey Zigachev
1021b843c749SSergey Zigachev if (!result) {
1022b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1023b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1024b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_int);
1025b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_frac);
1026b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1027b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1028b843c749SSergey Zigachev }
1029b843c749SSergey Zigachev
1030b843c749SSergey Zigachev return result;
1031b843c749SSergey Zigachev }
1032b843c749SSergey Zigachev
vegam_populate_all_memory_levels(struct pp_hwmgr * hwmgr)1033b843c749SSergey Zigachev static int vegam_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1034b843c749SSergey Zigachev {
1035b843c749SSergey Zigachev struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1036b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1037b843c749SSergey Zigachev struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1038b843c749SSergey Zigachev int result;
1039b843c749SSergey Zigachev /* populate MCLK dpm table to SMU7 */
1040b843c749SSergey Zigachev uint32_t array = smu_data->smu7_data.dpm_table_start +
1041b843c749SSergey Zigachev offsetof(SMU75_Discrete_DpmTable, MemoryLevel);
1042b843c749SSergey Zigachev uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) *
1043b843c749SSergey Zigachev SMU75_MAX_LEVELS_MEMORY;
1044b843c749SSergey Zigachev struct SMU75_Discrete_MemoryLevel *levels =
1045b843c749SSergey Zigachev smu_data->smc_state_table.MemoryLevel;
1046b843c749SSergey Zigachev uint32_t i;
1047b843c749SSergey Zigachev
1048b843c749SSergey Zigachev for (i = 0; i < dpm_table->mclk_table.count; i++) {
1049b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1050b843c749SSergey Zigachev "can not populate memory level as memory clock is zero",
1051b843c749SSergey Zigachev return -EINVAL);
1052b843c749SSergey Zigachev result = vegam_populate_single_memory_level(hwmgr,
1053b843c749SSergey Zigachev dpm_table->mclk_table.dpm_levels[i].value,
1054b843c749SSergey Zigachev &levels[i]);
1055b843c749SSergey Zigachev
1056b843c749SSergey Zigachev if (result)
1057b843c749SSergey Zigachev return result;
1058b843c749SSergey Zigachev
1059b843c749SSergey Zigachev levels[i].UpHyst = (uint8_t)
1060b843c749SSergey Zigachev (MemoryDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
1061b843c749SSergey Zigachev levels[i].DownHyst = (uint8_t)
1062b843c749SSergey Zigachev (MemoryDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
1063b843c749SSergey Zigachev }
1064b843c749SSergey Zigachev
1065b843c749SSergey Zigachev smu_data->smc_state_table.MemoryDpmLevelCount =
1066b843c749SSergey Zigachev (uint8_t)dpm_table->mclk_table.count;
1067b843c749SSergey Zigachev hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1068b843c749SSergey Zigachev phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1069b843c749SSergey Zigachev
1070b843c749SSergey Zigachev for (i = 0; i < dpm_table->mclk_table.count; i++)
1071b843c749SSergey Zigachev levels[i].EnabledForActivity =
1072b843c749SSergey Zigachev (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1;
1073b843c749SSergey Zigachev
1074b843c749SSergey Zigachev levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
1075b843c749SSergey Zigachev PPSMC_DISPLAY_WATERMARK_HIGH;
1076b843c749SSergey Zigachev
1077b843c749SSergey Zigachev /* level count will send to smc once at init smc table and never change */
1078b843c749SSergey Zigachev result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1079b843c749SSergey Zigachev (uint32_t)array_size, SMC_RAM_END);
1080b843c749SSergey Zigachev
1081b843c749SSergey Zigachev return result;
1082b843c749SSergey Zigachev }
1083b843c749SSergey Zigachev
vegam_populate_mvdd_value(struct pp_hwmgr * hwmgr,uint32_t mclk,SMIO_Pattern * smio_pat)1084b843c749SSergey Zigachev static int vegam_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1085b843c749SSergey Zigachev uint32_t mclk, SMIO_Pattern *smio_pat)
1086b843c749SSergey Zigachev {
1087b843c749SSergey Zigachev const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1088b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1089b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1090b843c749SSergey Zigachev uint32_t i = 0;
1091b843c749SSergey Zigachev
1092b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1093b843c749SSergey Zigachev /* find mvdd value which clock is more than request */
1094b843c749SSergey Zigachev for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1095b843c749SSergey Zigachev if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1096b843c749SSergey Zigachev smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1097b843c749SSergey Zigachev break;
1098b843c749SSergey Zigachev }
1099b843c749SSergey Zigachev }
1100b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1101b843c749SSergey Zigachev "MVDD Voltage is outside the supported range.",
1102b843c749SSergey Zigachev return -EINVAL);
1103b843c749SSergey Zigachev } else
1104b843c749SSergey Zigachev return -EINVAL;
1105b843c749SSergey Zigachev
1106b843c749SSergey Zigachev return 0;
1107b843c749SSergey Zigachev }
1108b843c749SSergey Zigachev
vegam_populate_smc_acpi_level(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)1109b843c749SSergey Zigachev static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1110b843c749SSergey Zigachev SMU75_Discrete_DpmTable *table)
1111b843c749SSergey Zigachev {
1112b843c749SSergey Zigachev int result = 0;
1113b843c749SSergey Zigachev uint32_t sclk_frequency;
1114b843c749SSergey Zigachev const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1115b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1116b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1117b843c749SSergey Zigachev SMIO_Pattern vol_level;
1118b843c749SSergey Zigachev uint32_t mvdd;
1119b843c749SSergey Zigachev uint16_t us_mvdd;
1120b843c749SSergey Zigachev
1121b843c749SSergey Zigachev table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1122b843c749SSergey Zigachev
1123b843c749SSergey Zigachev /* Get MinVoltage and Frequency from DPM0,
1124b843c749SSergey Zigachev * already converted to SMC_UL */
1125b843c749SSergey Zigachev sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1126b843c749SSergey Zigachev result = vegam_get_dependency_volt_by_clk(hwmgr,
1127b843c749SSergey Zigachev table_info->vdd_dep_on_sclk,
1128b843c749SSergey Zigachev sclk_frequency,
1129b843c749SSergey Zigachev &table->ACPILevel.MinVoltage, &mvdd);
1130b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1131b843c749SSergey Zigachev "Cannot find ACPI VDDC voltage value "
1132b843c749SSergey Zigachev "in Clock Dependency Table",
1133b843c749SSergey Zigachev );
1134b843c749SSergey Zigachev
1135b843c749SSergey Zigachev result = vegam_calculate_sclk_params(hwmgr, sclk_frequency,
1136b843c749SSergey Zigachev &(table->ACPILevel.SclkSetting));
1137b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1138b843c749SSergey Zigachev "Error retrieving Engine Clock dividers from VBIOS.",
1139b843c749SSergey Zigachev return result);
1140b843c749SSergey Zigachev
1141b843c749SSergey Zigachev table->ACPILevel.DeepSleepDivId = 0;
1142b843c749SSergey Zigachev table->ACPILevel.CcPwrDynRm = 0;
1143b843c749SSergey Zigachev table->ACPILevel.CcPwrDynRm1 = 0;
1144b843c749SSergey Zigachev
1145b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1146b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1147b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1148b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1149b843c749SSergey Zigachev
1150b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1151b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1152b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1153b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1154b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1155b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1156b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1157b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1158b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1159b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1160b843c749SSergey Zigachev
1161b843c749SSergey Zigachev
1162b843c749SSergey Zigachev /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1163b843c749SSergey Zigachev table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1164b843c749SSergey Zigachev result = vegam_get_dependency_volt_by_clk(hwmgr,
1165b843c749SSergey Zigachev table_info->vdd_dep_on_mclk,
1166b843c749SSergey Zigachev table->MemoryACPILevel.MclkFrequency,
1167b843c749SSergey Zigachev &table->MemoryACPILevel.MinVoltage, &mvdd);
1168b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result),
1169b843c749SSergey Zigachev "Cannot find ACPI VDDCI voltage value "
1170b843c749SSergey Zigachev "in Clock Dependency Table",
1171b843c749SSergey Zigachev );
1172b843c749SSergey Zigachev
1173b843c749SSergey Zigachev us_mvdd = 0;
1174b843c749SSergey Zigachev if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1175b843c749SSergey Zigachev (data->mclk_dpm_key_disabled))
1176b843c749SSergey Zigachev us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1177b843c749SSergey Zigachev else {
1178b843c749SSergey Zigachev if (!vegam_populate_mvdd_value(hwmgr,
1179b843c749SSergey Zigachev data->dpm_table.mclk_table.dpm_levels[0].value,
1180b843c749SSergey Zigachev &vol_level))
1181b843c749SSergey Zigachev us_mvdd = vol_level.Voltage;
1182b843c749SSergey Zigachev }
1183b843c749SSergey Zigachev
1184b843c749SSergey Zigachev if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
1185b843c749SSergey Zigachev table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1186b843c749SSergey Zigachev else
1187b843c749SSergey Zigachev table->MemoryACPILevel.MinMvdd = 0;
1188b843c749SSergey Zigachev
1189b843c749SSergey Zigachev table->MemoryACPILevel.StutterEnable = false;
1190b843c749SSergey Zigachev
1191b843c749SSergey Zigachev table->MemoryACPILevel.EnabledForThrottle = 0;
1192b843c749SSergey Zigachev table->MemoryACPILevel.EnabledForActivity = 0;
1193b843c749SSergey Zigachev table->MemoryACPILevel.UpHyst = 0;
1194b843c749SSergey Zigachev table->MemoryACPILevel.DownHyst = 100;
1195b843c749SSergey Zigachev table->MemoryACPILevel.VoltageDownHyst = 0;
1196b843c749SSergey Zigachev table->MemoryACPILevel.ActivityLevel =
1197b843c749SSergey Zigachev PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1198b843c749SSergey Zigachev
1199b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1200b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1201b843c749SSergey Zigachev
1202b843c749SSergey Zigachev return result;
1203b843c749SSergey Zigachev }
1204b843c749SSergey Zigachev
vegam_populate_smc_vce_level(struct pp_hwmgr * hwmgr,SMU75_Discrete_DpmTable * table)1205b843c749SSergey Zigachev static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1206b843c749SSergey Zigachev SMU75_Discrete_DpmTable *table)
1207b843c749SSergey Zigachev {
1208b843c749SSergey Zigachev int result = -EINVAL;
1209b843c749SSergey Zigachev uint8_t count;
1210b843c749SSergey Zigachev struct pp_atomctrl_clock_dividers_vi dividers;
1211b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1212b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1213b843c749SSergey Zigachev struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1214b843c749SSergey Zigachev table_info->mm_dep_table;
1215b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1216b843c749SSergey Zigachev uint32_t vddci;
1217b843c749SSergey Zigachev
1218b843c749SSergey Zigachev table->VceLevelCount = (uint8_t)(mm_table->count);
1219b843c749SSergey Zigachev table->VceBootLevel = 0;
1220b843c749SSergey Zigachev
1221b843c749SSergey Zigachev for (count = 0; count < table->VceLevelCount; count++) {
1222b843c749SSergey Zigachev table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1223b843c749SSergey Zigachev table->VceLevel[count].MinVoltage = 0;
1224b843c749SSergey Zigachev table->VceLevel[count].MinVoltage |=
1225b843c749SSergey Zigachev (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1226b843c749SSergey Zigachev
1227b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1228b843c749SSergey Zigachev vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1229b843c749SSergey Zigachev mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1230b843c749SSergey Zigachev else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1231b843c749SSergey Zigachev vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1232b843c749SSergey Zigachev else
1233b843c749SSergey Zigachev vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1234b843c749SSergey Zigachev
1235b843c749SSergey Zigachev
1236b843c749SSergey Zigachev table->VceLevel[count].MinVoltage |=
1237b843c749SSergey Zigachev (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1238b843c749SSergey Zigachev table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1239b843c749SSergey Zigachev
1240b843c749SSergey Zigachev /*retrieve divider value for VBIOS */
1241b843c749SSergey Zigachev result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1242b843c749SSergey Zigachev table->VceLevel[count].Frequency, ÷rs);
1243b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result),
1244b843c749SSergey Zigachev "can not find divide id for VCE engine clock",
1245b843c749SSergey Zigachev return result);
1246b843c749SSergey Zigachev
1247b843c749SSergey Zigachev table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1248b843c749SSergey Zigachev
1249b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1250b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1251b843c749SSergey Zigachev }
1252b843c749SSergey Zigachev return result;
1253b843c749SSergey Zigachev }
1254b843c749SSergey Zigachev
vegam_populate_memory_timing_parameters(struct pp_hwmgr * hwmgr,int32_t eng_clock,int32_t mem_clock,SMU75_Discrete_MCArbDramTimingTableEntry * arb_regs)1255b843c749SSergey Zigachev static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1256b843c749SSergey Zigachev int32_t eng_clock, int32_t mem_clock,
1257b843c749SSergey Zigachev SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs)
1258b843c749SSergey Zigachev {
1259b843c749SSergey Zigachev uint32_t dram_timing;
1260b843c749SSergey Zigachev uint32_t dram_timing2;
1261b843c749SSergey Zigachev uint32_t burst_time;
1262b843c749SSergey Zigachev uint32_t rfsh_rate;
1263b843c749SSergey Zigachev uint32_t misc3;
1264b843c749SSergey Zigachev
1265b843c749SSergey Zigachev int result;
1266b843c749SSergey Zigachev
1267b843c749SSergey Zigachev result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1268b843c749SSergey Zigachev eng_clock, mem_clock);
1269b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(result == 0,
1270b843c749SSergey Zigachev "Error calling VBIOS to set DRAM_TIMING.",
1271b843c749SSergey Zigachev return result);
1272b843c749SSergey Zigachev
1273b843c749SSergey Zigachev dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1274b843c749SSergey Zigachev dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1275b843c749SSergey Zigachev burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
1276b843c749SSergey Zigachev rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE);
1277b843c749SSergey Zigachev misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3);
1278b843c749SSergey Zigachev
1279b843c749SSergey Zigachev arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1280b843c749SSergey Zigachev arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1281b843c749SSergey Zigachev arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time);
1282b843c749SSergey Zigachev arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate);
1283b843c749SSergey Zigachev arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3);
1284b843c749SSergey Zigachev
1285b843c749SSergey Zigachev return 0;
1286b843c749SSergey Zigachev }
1287b843c749SSergey Zigachev
vegam_program_memory_timing_parameters(struct pp_hwmgr * hwmgr)1288b843c749SSergey Zigachev static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1289b843c749SSergey Zigachev {
1290b843c749SSergey Zigachev struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1291b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1292b843c749SSergey Zigachev struct SMU75_Discrete_MCArbDramTimingTable arb_regs;
1293b843c749SSergey Zigachev uint32_t i, j;
1294b843c749SSergey Zigachev int result = 0;
1295b843c749SSergey Zigachev
1296b843c749SSergey Zigachev memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
1297b843c749SSergey Zigachev
1298b843c749SSergey Zigachev for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1299b843c749SSergey Zigachev for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1300b843c749SSergey Zigachev result = vegam_populate_memory_timing_parameters(hwmgr,
1301b843c749SSergey Zigachev hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1302b843c749SSergey Zigachev hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1303b843c749SSergey Zigachev &arb_regs.entries[i][j]);
1304b843c749SSergey Zigachev if (result)
1305b843c749SSergey Zigachev return result;
1306b843c749SSergey Zigachev }
1307b843c749SSergey Zigachev }
1308b843c749SSergey Zigachev
1309b843c749SSergey Zigachev result = smu7_copy_bytes_to_smc(
1310b843c749SSergey Zigachev hwmgr,
1311b843c749SSergey Zigachev smu_data->smu7_data.arb_table_start,
1312b843c749SSergey Zigachev (uint8_t *)&arb_regs,
1313b843c749SSergey Zigachev sizeof(SMU75_Discrete_MCArbDramTimingTable),
1314b843c749SSergey Zigachev SMC_RAM_END);
1315b843c749SSergey Zigachev return result;
1316b843c749SSergey Zigachev }
1317b843c749SSergey Zigachev
vegam_populate_smc_uvd_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)1318b843c749SSergey Zigachev static int vegam_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1319b843c749SSergey Zigachev struct SMU75_Discrete_DpmTable *table)
1320b843c749SSergey Zigachev {
1321b843c749SSergey Zigachev int result = -EINVAL;
1322b843c749SSergey Zigachev uint8_t count;
1323b843c749SSergey Zigachev struct pp_atomctrl_clock_dividers_vi dividers;
1324b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1325b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1326b843c749SSergey Zigachev struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1327b843c749SSergey Zigachev table_info->mm_dep_table;
1328b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1329b843c749SSergey Zigachev uint32_t vddci;
1330b843c749SSergey Zigachev
1331b843c749SSergey Zigachev table->UvdLevelCount = (uint8_t)(mm_table->count);
1332b843c749SSergey Zigachev table->UvdBootLevel = 0;
1333b843c749SSergey Zigachev
1334b843c749SSergey Zigachev for (count = 0; count < table->UvdLevelCount; count++) {
1335b843c749SSergey Zigachev table->UvdLevel[count].MinVoltage = 0;
1336b843c749SSergey Zigachev table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1337b843c749SSergey Zigachev table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1338b843c749SSergey Zigachev table->UvdLevel[count].MinVoltage |=
1339b843c749SSergey Zigachev (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1340b843c749SSergey Zigachev
1341b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1342b843c749SSergey Zigachev vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1343b843c749SSergey Zigachev mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1344b843c749SSergey Zigachev else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1345b843c749SSergey Zigachev vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1346b843c749SSergey Zigachev else
1347b843c749SSergey Zigachev vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1348b843c749SSergey Zigachev
1349b843c749SSergey Zigachev table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1350b843c749SSergey Zigachev table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1351b843c749SSergey Zigachev
1352b843c749SSergey Zigachev /* retrieve divider value for VBIOS */
1353b843c749SSergey Zigachev result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1354b843c749SSergey Zigachev table->UvdLevel[count].VclkFrequency, ÷rs);
1355b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result),
1356b843c749SSergey Zigachev "can not find divide id for Vclk clock", return result);
1357b843c749SSergey Zigachev
1358b843c749SSergey Zigachev table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1359b843c749SSergey Zigachev
1360b843c749SSergey Zigachev result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1361b843c749SSergey Zigachev table->UvdLevel[count].DclkFrequency, ÷rs);
1362b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((0 == result),
1363b843c749SSergey Zigachev "can not find divide id for Dclk clock", return result);
1364b843c749SSergey Zigachev
1365b843c749SSergey Zigachev table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1366b843c749SSergey Zigachev
1367b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1368b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1369b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1370b843c749SSergey Zigachev }
1371b843c749SSergey Zigachev
1372b843c749SSergey Zigachev return result;
1373b843c749SSergey Zigachev }
1374b843c749SSergey Zigachev
vegam_populate_smc_boot_level(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)1375b843c749SSergey Zigachev static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1376b843c749SSergey Zigachev struct SMU75_Discrete_DpmTable *table)
1377b843c749SSergey Zigachev {
1378b843c749SSergey Zigachev int result = 0;
1379b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1380b843c749SSergey Zigachev
1381b843c749SSergey Zigachev table->GraphicsBootLevel = 0;
1382b843c749SSergey Zigachev table->MemoryBootLevel = 0;
1383b843c749SSergey Zigachev
1384b843c749SSergey Zigachev /* find boot level from dpm table */
1385b843c749SSergey Zigachev result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1386b843c749SSergey Zigachev data->vbios_boot_state.sclk_bootup_value,
1387b843c749SSergey Zigachev (uint32_t *)&(table->GraphicsBootLevel));
1388b843c749SSergey Zigachev
1389b843c749SSergey Zigachev result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1390b843c749SSergey Zigachev data->vbios_boot_state.mclk_bootup_value,
1391b843c749SSergey Zigachev (uint32_t *)&(table->MemoryBootLevel));
1392b843c749SSergey Zigachev
1393b843c749SSergey Zigachev table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1394b843c749SSergey Zigachev VOLTAGE_SCALE;
1395b843c749SSergey Zigachev table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1396b843c749SSergey Zigachev VOLTAGE_SCALE;
1397b843c749SSergey Zigachev table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1398b843c749SSergey Zigachev VOLTAGE_SCALE;
1399b843c749SSergey Zigachev
1400b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1401b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1402b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1403b843c749SSergey Zigachev
1404b843c749SSergey Zigachev return 0;
1405b843c749SSergey Zigachev }
1406b843c749SSergey Zigachev
vegam_populate_smc_initial_state(struct pp_hwmgr * hwmgr)1407b843c749SSergey Zigachev static int vegam_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1408b843c749SSergey Zigachev {
1409b843c749SSergey Zigachev struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1410b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1411b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1412b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1413b843c749SSergey Zigachev uint8_t count, level;
1414b843c749SSergey Zigachev
1415b843c749SSergey Zigachev count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1416b843c749SSergey Zigachev
1417b843c749SSergey Zigachev for (level = 0; level < count; level++) {
1418b843c749SSergey Zigachev if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1419b843c749SSergey Zigachev hw_data->vbios_boot_state.sclk_bootup_value) {
1420b843c749SSergey Zigachev smu_data->smc_state_table.GraphicsBootLevel = level;
1421b843c749SSergey Zigachev break;
1422b843c749SSergey Zigachev }
1423b843c749SSergey Zigachev }
1424b843c749SSergey Zigachev
1425b843c749SSergey Zigachev count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1426b843c749SSergey Zigachev for (level = 0; level < count; level++) {
1427b843c749SSergey Zigachev if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1428b843c749SSergey Zigachev hw_data->vbios_boot_state.mclk_bootup_value) {
1429b843c749SSergey Zigachev smu_data->smc_state_table.MemoryBootLevel = level;
1430b843c749SSergey Zigachev break;
1431b843c749SSergey Zigachev }
1432b843c749SSergey Zigachev }
1433b843c749SSergey Zigachev
1434b843c749SSergey Zigachev return 0;
1435b843c749SSergey Zigachev }
1436b843c749SSergey Zigachev
scale_fan_gain_settings(uint16_t raw_setting)1437b843c749SSergey Zigachev static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
1438b843c749SSergey Zigachev {
1439b843c749SSergey Zigachev uint32_t tmp;
1440b843c749SSergey Zigachev tmp = raw_setting * 4096 / 100;
1441b843c749SSergey Zigachev return (uint16_t)tmp;
1442b843c749SSergey Zigachev }
1443b843c749SSergey Zigachev
vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr * hwmgr)1444b843c749SSergey Zigachev static int vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1445b843c749SSergey Zigachev {
1446b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1447b843c749SSergey Zigachev
1448b843c749SSergey Zigachev const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1449b843c749SSergey Zigachev SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1450b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1451b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1452b843c749SSergey Zigachev struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
1453b843c749SSergey Zigachev struct pp_advance_fan_control_parameters *fan_table =
1454b843c749SSergey Zigachev &hwmgr->thermal_controller.advanceFanControlParameters;
1455b843c749SSergey Zigachev int i, j, k;
1456b843c749SSergey Zigachev const uint16_t *pdef1;
1457b843c749SSergey Zigachev const uint16_t *pdef2;
1458b843c749SSergey Zigachev
1459b843c749SSergey Zigachev table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1460b843c749SSergey Zigachev table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1461b843c749SSergey Zigachev
1462b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
1463b843c749SSergey Zigachev "Target Operating Temp is out of Range!",
1464b843c749SSergey Zigachev );
1465b843c749SSergey Zigachev
1466b843c749SSergey Zigachev table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
1467b843c749SSergey Zigachev cac_dtp_table->usTargetOperatingTemp * 256);
1468b843c749SSergey Zigachev table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
1469b843c749SSergey Zigachev cac_dtp_table->usTemperatureLimitHotspot * 256);
1470b843c749SSergey Zigachev table->FanGainEdge = PP_HOST_TO_SMC_US(
1471b843c749SSergey Zigachev scale_fan_gain_settings(fan_table->usFanGainEdge));
1472b843c749SSergey Zigachev table->FanGainHotspot = PP_HOST_TO_SMC_US(
1473b843c749SSergey Zigachev scale_fan_gain_settings(fan_table->usFanGainHotspot));
1474b843c749SSergey Zigachev
1475b843c749SSergey Zigachev pdef1 = defaults->BAPMTI_R;
1476b843c749SSergey Zigachev pdef2 = defaults->BAPMTI_RC;
1477b843c749SSergey Zigachev
1478b843c749SSergey Zigachev for (i = 0; i < SMU75_DTE_ITERATIONS; i++) {
1479b843c749SSergey Zigachev for (j = 0; j < SMU75_DTE_SOURCES; j++) {
1480b843c749SSergey Zigachev for (k = 0; k < SMU75_DTE_SINKS; k++) {
1481b843c749SSergey Zigachev table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
1482b843c749SSergey Zigachev table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
1483b843c749SSergey Zigachev pdef1++;
1484b843c749SSergey Zigachev pdef2++;
1485b843c749SSergey Zigachev }
1486b843c749SSergey Zigachev }
1487b843c749SSergey Zigachev }
1488b843c749SSergey Zigachev
1489b843c749SSergey Zigachev return 0;
1490b843c749SSergey Zigachev }
1491b843c749SSergey Zigachev
vegam_populate_clock_stretcher_data_table(struct pp_hwmgr * hwmgr)1492b843c749SSergey Zigachev static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1493b843c749SSergey Zigachev {
1494b843c749SSergey Zigachev uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1495b843c749SSergey Zigachev struct vegam_smumgr *smu_data =
1496b843c749SSergey Zigachev (struct vegam_smumgr *)(hwmgr->smu_backend);
1497b843c749SSergey Zigachev
1498b843c749SSergey Zigachev uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1499b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1500b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1501b843c749SSergey Zigachev struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1502b843c749SSergey Zigachev table_info->vdd_dep_on_sclk;
1503b843c749SSergey Zigachev uint32_t mask = (1 << ((STRAP_ASIC_RO_MSB - STRAP_ASIC_RO_LSB) + 1)) - 1;
1504b843c749SSergey Zigachev
1505b843c749SSergey Zigachev stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1506b843c749SSergey Zigachev
1507b843c749SSergey Zigachev atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB,
1508b843c749SSergey Zigachev mask, &efuse);
1509b843c749SSergey Zigachev
1510b843c749SSergey Zigachev min = 1200;
1511b843c749SSergey Zigachev max = 2500;
1512b843c749SSergey Zigachev
1513b843c749SSergey Zigachev ro = efuse * (max - min) / 255 + min;
1514b843c749SSergey Zigachev
1515b843c749SSergey Zigachev /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1516b843c749SSergey Zigachev for (i = 0; i < sclk_table->count; i++) {
1517b843c749SSergey Zigachev smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1518b843c749SSergey Zigachev sclk_table->entries[i].cks_enable << i;
1519b843c749SSergey Zigachev volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) *
1520b843c749SSergey Zigachev 136418 - (ro - 70) * 1000000) /
1521b843c749SSergey Zigachev (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1522b843c749SSergey Zigachev volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 *
1523b843c749SSergey Zigachev 3232 - (ro - 65) * 1000000) /
1524b843c749SSergey Zigachev (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1525b843c749SSergey Zigachev
1526b843c749SSergey Zigachev if (volt_without_cks >= volt_with_cks)
1527b843c749SSergey Zigachev volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1528b843c749SSergey Zigachev sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1529b843c749SSergey Zigachev
1530b843c749SSergey Zigachev smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1531b843c749SSergey Zigachev }
1532b843c749SSergey Zigachev
1533b843c749SSergey Zigachev smu_data->smc_state_table.LdoRefSel =
1534b843c749SSergey Zigachev (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ?
1535b843c749SSergey Zigachev table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
1536b843c749SSergey Zigachev /* Populate CKS Lookup Table */
1537b843c749SSergey Zigachev if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1538b843c749SSergey Zigachev stretch_amount2 = 0;
1539b843c749SSergey Zigachev else if (stretch_amount == 3 || stretch_amount == 4)
1540b843c749SSergey Zigachev stretch_amount2 = 1;
1541b843c749SSergey Zigachev else {
1542b843c749SSergey Zigachev phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1543b843c749SSergey Zigachev PHM_PlatformCaps_ClockStretcher);
1544b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1545b843c749SSergey Zigachev "Stretch Amount in PPTable not supported\n",
1546b843c749SSergey Zigachev return -EINVAL);
1547b843c749SSergey Zigachev }
1548b843c749SSergey Zigachev
1549b843c749SSergey Zigachev value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1550b843c749SSergey Zigachev value &= 0xFFFFFFFE;
1551b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1552b843c749SSergey Zigachev
1553b843c749SSergey Zigachev return 0;
1554b843c749SSergey Zigachev }
1555b843c749SSergey Zigachev
vegam_is_hw_avfs_present(struct pp_hwmgr * hwmgr)1556b843c749SSergey Zigachev static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
1557b843c749SSergey Zigachev {
1558b843c749SSergey Zigachev uint32_t efuse;
1559b843c749SSergey Zigachev
1560b843c749SSergey Zigachev efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1561b843c749SSergey Zigachev ixSMU_EFUSE_0 + (49 * 4));
1562b843c749SSergey Zigachev efuse &= 0x00000001;
1563b843c749SSergey Zigachev
1564b843c749SSergey Zigachev if (efuse)
1565b843c749SSergey Zigachev return true;
1566b843c749SSergey Zigachev
1567b843c749SSergey Zigachev return false;
1568b843c749SSergey Zigachev }
1569b843c749SSergey Zigachev
vegam_populate_avfs_parameters(struct pp_hwmgr * hwmgr)1570b843c749SSergey Zigachev static int vegam_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1571b843c749SSergey Zigachev {
1572b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1573b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1574b843c749SSergey Zigachev
1575b843c749SSergey Zigachev SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1576b843c749SSergey Zigachev int result = 0;
1577b843c749SSergey Zigachev struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1578b843c749SSergey Zigachev AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1579b843c749SSergey Zigachev AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1580b843c749SSergey Zigachev uint32_t tmp, i;
1581b843c749SSergey Zigachev
1582b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1583b843c749SSergey Zigachev (struct phm_ppt_v1_information *)hwmgr->pptable;
1584b843c749SSergey Zigachev struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1585b843c749SSergey Zigachev table_info->vdd_dep_on_sclk;
1586b843c749SSergey Zigachev
1587b843c749SSergey Zigachev if (!hwmgr->avfs_supported)
1588b843c749SSergey Zigachev return 0;
1589b843c749SSergey Zigachev
1590b843c749SSergey Zigachev result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1591b843c749SSergey Zigachev
1592b843c749SSergey Zigachev if (0 == result) {
1593b843c749SSergey Zigachev table->BTCGB_VDROOP_TABLE[0].a0 =
1594b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1595b843c749SSergey Zigachev table->BTCGB_VDROOP_TABLE[0].a1 =
1596b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1597b843c749SSergey Zigachev table->BTCGB_VDROOP_TABLE[0].a2 =
1598b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1599b843c749SSergey Zigachev table->BTCGB_VDROOP_TABLE[1].a0 =
1600b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1601b843c749SSergey Zigachev table->BTCGB_VDROOP_TABLE[1].a1 =
1602b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1603b843c749SSergey Zigachev table->BTCGB_VDROOP_TABLE[1].a2 =
1604b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1605b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[0].m1 =
1606b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1607b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[0].m2 =
1608b843c749SSergey Zigachev PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1609b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[0].b =
1610b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1611b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[0].m1_shift = 24;
1612b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[0].m2_shift = 12;
1613b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[1].m1 =
1614b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1615b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[1].m2 =
1616b843c749SSergey Zigachev PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1617b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[1].b =
1618b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1619b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[1].m1_shift = 24;
1620b843c749SSergey Zigachev table->AVFSGB_FUSE_TABLE[1].m2_shift = 12;
1621b843c749SSergey Zigachev table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1622b843c749SSergey Zigachev AVFS_meanNsigma.Aconstant[0] =
1623b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1624b843c749SSergey Zigachev AVFS_meanNsigma.Aconstant[1] =
1625b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1626b843c749SSergey Zigachev AVFS_meanNsigma.Aconstant[2] =
1627b843c749SSergey Zigachev PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1628b843c749SSergey Zigachev AVFS_meanNsigma.DC_tol_sigma =
1629b843c749SSergey Zigachev PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1630b843c749SSergey Zigachev AVFS_meanNsigma.Platform_mean =
1631b843c749SSergey Zigachev PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1632b843c749SSergey Zigachev AVFS_meanNsigma.PSM_Age_CompFactor =
1633b843c749SSergey Zigachev PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1634b843c749SSergey Zigachev AVFS_meanNsigma.Platform_sigma =
1635b843c749SSergey Zigachev PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1636b843c749SSergey Zigachev
1637b843c749SSergey Zigachev for (i = 0; i < sclk_table->count; i++) {
1638b843c749SSergey Zigachev AVFS_meanNsigma.Static_Voltage_Offset[i] =
1639b843c749SSergey Zigachev (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1640b843c749SSergey Zigachev AVFS_SclkOffset.Sclk_Offset[i] =
1641b843c749SSergey Zigachev PP_HOST_TO_SMC_US((uint16_t)
1642b843c749SSergey Zigachev (sclk_table->entries[i].sclk_offset) / 100);
1643b843c749SSergey Zigachev }
1644b843c749SSergey Zigachev
1645b843c749SSergey Zigachev result = smu7_read_smc_sram_dword(hwmgr,
1646b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION +
1647b843c749SSergey Zigachev offsetof(SMU75_Firmware_Header, AvfsMeanNSigma),
1648b843c749SSergey Zigachev &tmp, SMC_RAM_END);
1649b843c749SSergey Zigachev smu7_copy_bytes_to_smc(hwmgr,
1650b843c749SSergey Zigachev tmp,
1651b843c749SSergey Zigachev (uint8_t *)&AVFS_meanNsigma,
1652b843c749SSergey Zigachev sizeof(AVFS_meanNsigma_t),
1653b843c749SSergey Zigachev SMC_RAM_END);
1654b843c749SSergey Zigachev
1655b843c749SSergey Zigachev result = smu7_read_smc_sram_dword(hwmgr,
1656b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION +
1657b843c749SSergey Zigachev offsetof(SMU75_Firmware_Header, AvfsSclkOffsetTable),
1658b843c749SSergey Zigachev &tmp, SMC_RAM_END);
1659b843c749SSergey Zigachev smu7_copy_bytes_to_smc(hwmgr,
1660b843c749SSergey Zigachev tmp,
1661b843c749SSergey Zigachev (uint8_t *)&AVFS_SclkOffset,
1662b843c749SSergey Zigachev sizeof(AVFS_Sclk_Offset_t),
1663b843c749SSergey Zigachev SMC_RAM_END);
1664b843c749SSergey Zigachev
1665b843c749SSergey Zigachev data->avfs_vdroop_override_setting =
1666b843c749SSergey Zigachev (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1667b843c749SSergey Zigachev (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1668b843c749SSergey Zigachev (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1669b843c749SSergey Zigachev (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1670b843c749SSergey Zigachev data->apply_avfs_cks_off_voltage =
1671b843c749SSergey Zigachev (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1672b843c749SSergey Zigachev }
1673b843c749SSergey Zigachev return result;
1674b843c749SSergey Zigachev }
1675b843c749SSergey Zigachev
vegam_populate_vr_config(struct pp_hwmgr * hwmgr,struct SMU75_Discrete_DpmTable * table)1676b843c749SSergey Zigachev static int vegam_populate_vr_config(struct pp_hwmgr *hwmgr,
1677b843c749SSergey Zigachev struct SMU75_Discrete_DpmTable *table)
1678b843c749SSergey Zigachev {
1679b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1680b843c749SSergey Zigachev struct vegam_smumgr *smu_data =
1681b843c749SSergey Zigachev (struct vegam_smumgr *)(hwmgr->smu_backend);
1682b843c749SSergey Zigachev uint16_t config;
1683b843c749SSergey Zigachev
1684b843c749SSergey Zigachev config = VR_MERGED_WITH_VDDC;
1685b843c749SSergey Zigachev table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1686b843c749SSergey Zigachev
1687b843c749SSergey Zigachev /* Set Vddc Voltage Controller */
1688b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1689b843c749SSergey Zigachev config = VR_SVI2_PLANE_1;
1690b843c749SSergey Zigachev table->VRConfig |= config;
1691b843c749SSergey Zigachev } else {
1692b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1693b843c749SSergey Zigachev "VDDC should be on SVI2 control in merged mode!",
1694b843c749SSergey Zigachev );
1695b843c749SSergey Zigachev }
1696b843c749SSergey Zigachev /* Set Vddci Voltage Controller */
1697b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1698b843c749SSergey Zigachev config = VR_SVI2_PLANE_2; /* only in merged mode */
1699b843c749SSergey Zigachev table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1700b843c749SSergey Zigachev } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1701b843c749SSergey Zigachev config = VR_SMIO_PATTERN_1;
1702b843c749SSergey Zigachev table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1703b843c749SSergey Zigachev } else {
1704b843c749SSergey Zigachev config = VR_STATIC_VOLTAGE;
1705b843c749SSergey Zigachev table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1706b843c749SSergey Zigachev }
1707b843c749SSergey Zigachev /* Set Mvdd Voltage Controller */
1708b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1709b843c749SSergey Zigachev if (config != VR_SVI2_PLANE_2) {
1710b843c749SSergey Zigachev config = VR_SVI2_PLANE_2;
1711b843c749SSergey Zigachev table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1712b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device,
1713b843c749SSergey Zigachev CGS_IND_REG__SMC,
1714b843c749SSergey Zigachev smu_data->smu7_data.soft_regs_start +
1715b843c749SSergey Zigachev offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1716b843c749SSergey Zigachev 0x1);
1717b843c749SSergey Zigachev } else {
1718b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1719b843c749SSergey Zigachev "SVI2 Plane 2 is already taken, set MVDD as Static",);
1720b843c749SSergey Zigachev config = VR_STATIC_VOLTAGE;
1721b843c749SSergey Zigachev table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1722b843c749SSergey Zigachev }
1723b843c749SSergey Zigachev } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1724b843c749SSergey Zigachev config = VR_SMIO_PATTERN_2;
1725b843c749SSergey Zigachev table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1726b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device,
1727b843c749SSergey Zigachev CGS_IND_REG__SMC,
1728b843c749SSergey Zigachev smu_data->smu7_data.soft_regs_start +
1729b843c749SSergey Zigachev offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1730b843c749SSergey Zigachev 0x1);
1731b843c749SSergey Zigachev } else {
1732b843c749SSergey Zigachev config = VR_STATIC_VOLTAGE;
1733b843c749SSergey Zigachev table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1734b843c749SSergey Zigachev }
1735b843c749SSergey Zigachev
1736b843c749SSergey Zigachev return 0;
1737b843c749SSergey Zigachev }
1738b843c749SSergey Zigachev
vegam_populate_svi_load_line(struct pp_hwmgr * hwmgr)1739b843c749SSergey Zigachev static int vegam_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1740b843c749SSergey Zigachev {
1741b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1742b843c749SSergey Zigachev const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1743b843c749SSergey Zigachev
1744b843c749SSergey Zigachev smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
1745b843c749SSergey Zigachev smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
1746b843c749SSergey Zigachev smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
1747b843c749SSergey Zigachev smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
1748b843c749SSergey Zigachev
1749b843c749SSergey Zigachev return 0;
1750b843c749SSergey Zigachev }
1751b843c749SSergey Zigachev
vegam_populate_tdc_limit(struct pp_hwmgr * hwmgr)1752b843c749SSergey Zigachev static int vegam_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1753b843c749SSergey Zigachev {
1754b843c749SSergey Zigachev uint16_t tdc_limit;
1755b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1756b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1757b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1758b843c749SSergey Zigachev const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1759b843c749SSergey Zigachev
1760b843c749SSergey Zigachev tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
1761b843c749SSergey Zigachev smu_data->power_tune_table.TDC_VDDC_PkgLimit =
1762b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
1763b843c749SSergey Zigachev smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
1764b843c749SSergey Zigachev defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
1765b843c749SSergey Zigachev smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
1766b843c749SSergey Zigachev
1767b843c749SSergey Zigachev return 0;
1768b843c749SSergey Zigachev }
1769b843c749SSergey Zigachev
vegam_populate_dw8(struct pp_hwmgr * hwmgr,uint32_t fuse_table_offset)1770b843c749SSergey Zigachev static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1771b843c749SSergey Zigachev {
1772b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1773b843c749SSergey Zigachev const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1774b843c749SSergey Zigachev uint32_t temp;
1775b843c749SSergey Zigachev
1776b843c749SSergey Zigachev if (smu7_read_smc_sram_dword(hwmgr,
1777b843c749SSergey Zigachev fuse_table_offset +
1778b843c749SSergey Zigachev offsetof(SMU75_Discrete_PmFuses, TdcWaterfallCtl),
1779b843c749SSergey Zigachev (uint32_t *)&temp, SMC_RAM_END))
1780b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1781b843c749SSergey Zigachev "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
1782b843c749SSergey Zigachev return -EINVAL);
1783b843c749SSergey Zigachev else {
1784b843c749SSergey Zigachev smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
1785b843c749SSergey Zigachev smu_data->power_tune_table.LPMLTemperatureMin =
1786b843c749SSergey Zigachev (uint8_t)((temp >> 16) & 0xff);
1787b843c749SSergey Zigachev smu_data->power_tune_table.LPMLTemperatureMax =
1788b843c749SSergey Zigachev (uint8_t)((temp >> 8) & 0xff);
1789b843c749SSergey Zigachev smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
1790b843c749SSergey Zigachev }
1791b843c749SSergey Zigachev return 0;
1792b843c749SSergey Zigachev }
1793b843c749SSergey Zigachev
vegam_populate_temperature_scaler(struct pp_hwmgr * hwmgr)1794b843c749SSergey Zigachev static int vegam_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1795b843c749SSergey Zigachev {
1796b843c749SSergey Zigachev int i;
1797b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1798b843c749SSergey Zigachev
1799b843c749SSergey Zigachev /* Currently not used. Set all to zero. */
1800b843c749SSergey Zigachev for (i = 0; i < 16; i++)
1801b843c749SSergey Zigachev smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
1802b843c749SSergey Zigachev
1803b843c749SSergey Zigachev return 0;
1804b843c749SSergey Zigachev }
1805b843c749SSergey Zigachev
vegam_populate_fuzzy_fan(struct pp_hwmgr * hwmgr)1806b843c749SSergey Zigachev static int vegam_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1807b843c749SSergey Zigachev {
1808b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1809b843c749SSergey Zigachev
1810b843c749SSergey Zigachev /* TO DO move to hwmgr */
1811b843c749SSergey Zigachev if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
1812b843c749SSergey Zigachev || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
1813b843c749SSergey Zigachev hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
1814b843c749SSergey Zigachev hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
1815b843c749SSergey Zigachev
1816b843c749SSergey Zigachev smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
1817b843c749SSergey Zigachev hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
1818b843c749SSergey Zigachev return 0;
1819b843c749SSergey Zigachev }
1820b843c749SSergey Zigachev
vegam_populate_gnb_lpml(struct pp_hwmgr * hwmgr)1821b843c749SSergey Zigachev static int vegam_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1822b843c749SSergey Zigachev {
1823b843c749SSergey Zigachev int i;
1824b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1825b843c749SSergey Zigachev
1826b843c749SSergey Zigachev /* Currently not used. Set all to zero. */
1827b843c749SSergey Zigachev for (i = 0; i < 16; i++)
1828b843c749SSergey Zigachev smu_data->power_tune_table.GnbLPML[i] = 0;
1829b843c749SSergey Zigachev
1830b843c749SSergey Zigachev return 0;
1831b843c749SSergey Zigachev }
1832b843c749SSergey Zigachev
vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr * hwmgr)1833b843c749SSergey Zigachev static int vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1834b843c749SSergey Zigachev {
1835b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1836b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1837b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1838b843c749SSergey Zigachev uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
1839b843c749SSergey Zigachev uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
1840b843c749SSergey Zigachev struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
1841b843c749SSergey Zigachev
1842b843c749SSergey Zigachev hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
1843b843c749SSergey Zigachev lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
1844b843c749SSergey Zigachev
1845b843c749SSergey Zigachev smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
1846b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
1847b843c749SSergey Zigachev smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
1848b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
1849b843c749SSergey Zigachev
1850b843c749SSergey Zigachev return 0;
1851b843c749SSergey Zigachev }
1852b843c749SSergey Zigachev
vegam_populate_pm_fuses(struct pp_hwmgr * hwmgr)1853b843c749SSergey Zigachev static int vegam_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1854b843c749SSergey Zigachev {
1855b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1856b843c749SSergey Zigachev uint32_t pm_fuse_table_offset;
1857b843c749SSergey Zigachev
1858b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1859b843c749SSergey Zigachev PHM_PlatformCaps_PowerContainment)) {
1860b843c749SSergey Zigachev if (smu7_read_smc_sram_dword(hwmgr,
1861b843c749SSergey Zigachev SMU7_FIRMWARE_HEADER_LOCATION +
1862b843c749SSergey Zigachev offsetof(SMU75_Firmware_Header, PmFuseTable),
1863b843c749SSergey Zigachev &pm_fuse_table_offset, SMC_RAM_END))
1864b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1865b843c749SSergey Zigachev "Attempt to get pm_fuse_table_offset Failed!",
1866b843c749SSergey Zigachev return -EINVAL);
1867b843c749SSergey Zigachev
1868b843c749SSergey Zigachev if (vegam_populate_svi_load_line(hwmgr))
1869b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1870b843c749SSergey Zigachev "Attempt to populate SviLoadLine Failed!",
1871b843c749SSergey Zigachev return -EINVAL);
1872b843c749SSergey Zigachev
1873b843c749SSergey Zigachev if (vegam_populate_tdc_limit(hwmgr))
1874b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1875b843c749SSergey Zigachev "Attempt to populate TDCLimit Failed!", return -EINVAL);
1876b843c749SSergey Zigachev
1877b843c749SSergey Zigachev if (vegam_populate_dw8(hwmgr, pm_fuse_table_offset))
1878b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1879b843c749SSergey Zigachev "Attempt to populate TdcWaterfallCtl, "
1880b843c749SSergey Zigachev "LPMLTemperature Min and Max Failed!",
1881b843c749SSergey Zigachev return -EINVAL);
1882b843c749SSergey Zigachev
1883b843c749SSergey Zigachev if (0 != vegam_populate_temperature_scaler(hwmgr))
1884b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1885b843c749SSergey Zigachev "Attempt to populate LPMLTemperatureScaler Failed!",
1886b843c749SSergey Zigachev return -EINVAL);
1887b843c749SSergey Zigachev
1888b843c749SSergey Zigachev if (vegam_populate_fuzzy_fan(hwmgr))
1889b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1890b843c749SSergey Zigachev "Attempt to populate Fuzzy Fan Control parameters Failed!",
1891b843c749SSergey Zigachev return -EINVAL);
1892b843c749SSergey Zigachev
1893b843c749SSergey Zigachev if (vegam_populate_gnb_lpml(hwmgr))
1894b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1895b843c749SSergey Zigachev "Attempt to populate GnbLPML Failed!",
1896b843c749SSergey Zigachev return -EINVAL);
1897b843c749SSergey Zigachev
1898b843c749SSergey Zigachev if (vegam_populate_bapm_vddc_base_leakage_sidd(hwmgr))
1899b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1900b843c749SSergey Zigachev "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
1901b843c749SSergey Zigachev "Sidd Failed!", return -EINVAL);
1902b843c749SSergey Zigachev
1903b843c749SSergey Zigachev if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
1904b843c749SSergey Zigachev (uint8_t *)&smu_data->power_tune_table,
1905b843c749SSergey Zigachev (sizeof(struct SMU75_Discrete_PmFuses) - PMFUSES_AVFSSIZE),
1906b843c749SSergey Zigachev SMC_RAM_END))
1907b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(false,
1908b843c749SSergey Zigachev "Attempt to download PmFuseTable Failed!",
1909b843c749SSergey Zigachev return -EINVAL);
1910b843c749SSergey Zigachev }
1911b843c749SSergey Zigachev return 0;
1912b843c749SSergey Zigachev }
1913b843c749SSergey Zigachev
vegam_enable_reconfig_cus(struct pp_hwmgr * hwmgr)1914b843c749SSergey Zigachev static int vegam_enable_reconfig_cus(struct pp_hwmgr *hwmgr)
1915b843c749SSergey Zigachev {
1916b843c749SSergey Zigachev struct amdgpu_device *adev = hwmgr->adev;
1917b843c749SSergey Zigachev
1918b843c749SSergey Zigachev smum_send_msg_to_smc_with_parameter(hwmgr,
1919b843c749SSergey Zigachev PPSMC_MSG_EnableModeSwitchRLCNotification,
1920b843c749SSergey Zigachev adev->gfx.cu_info.number);
1921b843c749SSergey Zigachev
1922b843c749SSergey Zigachev return 0;
1923b843c749SSergey Zigachev }
1924b843c749SSergey Zigachev
vegam_init_smc_table(struct pp_hwmgr * hwmgr)1925b843c749SSergey Zigachev static int vegam_init_smc_table(struct pp_hwmgr *hwmgr)
1926b843c749SSergey Zigachev {
1927b843c749SSergey Zigachev int result;
1928b843c749SSergey Zigachev struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1929b843c749SSergey Zigachev struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1930b843c749SSergey Zigachev
1931b843c749SSergey Zigachev struct phm_ppt_v1_information *table_info =
1932b843c749SSergey Zigachev (struct phm_ppt_v1_information *)(hwmgr->pptable);
1933b843c749SSergey Zigachev struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1934b843c749SSergey Zigachev uint8_t i;
1935b843c749SSergey Zigachev struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1936b843c749SSergey Zigachev struct phm_ppt_v1_gpio_table *gpio_table =
1937b843c749SSergey Zigachev (struct phm_ppt_v1_gpio_table *)table_info->gpio_table;
1938b843c749SSergey Zigachev pp_atomctrl_clock_dividers_vi dividers;
1939b843c749SSergey Zigachev
1940b843c749SSergey Zigachev phm_cap_set(hwmgr->platform_descriptor.platformCaps,
1941b843c749SSergey Zigachev PHM_PlatformCaps_AutomaticDCTransition);
1942b843c749SSergey Zigachev
1943b843c749SSergey Zigachev vegam_initialize_power_tune_defaults(hwmgr);
1944b843c749SSergey Zigachev
1945b843c749SSergey Zigachev if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1946b843c749SSergey Zigachev vegam_populate_smc_voltage_tables(hwmgr, table);
1947b843c749SSergey Zigachev
1948b843c749SSergey Zigachev table->SystemFlags = 0;
1949b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1950b843c749SSergey Zigachev PHM_PlatformCaps_AutomaticDCTransition))
1951b843c749SSergey Zigachev table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1952b843c749SSergey Zigachev
1953b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1954b843c749SSergey Zigachev PHM_PlatformCaps_StepVddc))
1955b843c749SSergey Zigachev table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1956b843c749SSergey Zigachev
1957b843c749SSergey Zigachev if (hw_data->is_memory_gddr5)
1958b843c749SSergey Zigachev table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1959b843c749SSergey Zigachev
1960b843c749SSergey Zigachev if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1961b843c749SSergey Zigachev result = vegam_populate_ulv_state(hwmgr, table);
1962b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1963b843c749SSergey Zigachev "Failed to initialize ULV state!", return result);
1964b843c749SSergey Zigachev cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1965b843c749SSergey Zigachev ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1966b843c749SSergey Zigachev }
1967b843c749SSergey Zigachev
1968b843c749SSergey Zigachev result = vegam_populate_smc_link_level(hwmgr, table);
1969b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1970b843c749SSergey Zigachev "Failed to initialize Link Level!", return result);
1971b843c749SSergey Zigachev
1972b843c749SSergey Zigachev result = vegam_populate_all_graphic_levels(hwmgr);
1973b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1974b843c749SSergey Zigachev "Failed to initialize Graphics Level!", return result);
1975b843c749SSergey Zigachev
1976b843c749SSergey Zigachev result = vegam_populate_all_memory_levels(hwmgr);
1977b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1978b843c749SSergey Zigachev "Failed to initialize Memory Level!", return result);
1979b843c749SSergey Zigachev
1980b843c749SSergey Zigachev result = vegam_populate_smc_acpi_level(hwmgr, table);
1981b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1982b843c749SSergey Zigachev "Failed to initialize ACPI Level!", return result);
1983b843c749SSergey Zigachev
1984b843c749SSergey Zigachev result = vegam_populate_smc_vce_level(hwmgr, table);
1985b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1986b843c749SSergey Zigachev "Failed to initialize VCE Level!", return result);
1987b843c749SSergey Zigachev
1988b843c749SSergey Zigachev /* Since only the initial state is completely set up at this point
1989b843c749SSergey Zigachev * (the other states are just copies of the boot state) we only
1990b843c749SSergey Zigachev * need to populate the ARB settings for the initial state.
1991b843c749SSergey Zigachev */
1992b843c749SSergey Zigachev result = vegam_program_memory_timing_parameters(hwmgr);
1993b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1994b843c749SSergey Zigachev "Failed to Write ARB settings for the initial state.", return result);
1995b843c749SSergey Zigachev
1996b843c749SSergey Zigachev result = vegam_populate_smc_uvd_level(hwmgr, table);
1997b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
1998b843c749SSergey Zigachev "Failed to initialize UVD Level!", return result);
1999b843c749SSergey Zigachev
2000b843c749SSergey Zigachev result = vegam_populate_smc_boot_level(hwmgr, table);
2001b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2002b843c749SSergey Zigachev "Failed to initialize Boot Level!", return result);
2003b843c749SSergey Zigachev
2004b843c749SSergey Zigachev result = vegam_populate_smc_initial_state(hwmgr);
2005b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2006b843c749SSergey Zigachev "Failed to initialize Boot State!", return result);
2007b843c749SSergey Zigachev
2008b843c749SSergey Zigachev result = vegam_populate_bapm_parameters_in_dpm_table(hwmgr);
2009b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2010b843c749SSergey Zigachev "Failed to populate BAPM Parameters!", return result);
2011b843c749SSergey Zigachev
2012b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2013b843c749SSergey Zigachev PHM_PlatformCaps_ClockStretcher)) {
2014b843c749SSergey Zigachev result = vegam_populate_clock_stretcher_data_table(hwmgr);
2015b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2016b843c749SSergey Zigachev "Failed to populate Clock Stretcher Data Table!",
2017b843c749SSergey Zigachev return result);
2018b843c749SSergey Zigachev }
2019b843c749SSergey Zigachev
2020b843c749SSergey Zigachev result = vegam_populate_avfs_parameters(hwmgr);
2021b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2022b843c749SSergey Zigachev "Failed to populate AVFS Parameters!", return result;);
2023b843c749SSergey Zigachev
2024b843c749SSergey Zigachev table->CurrSclkPllRange = 0xff;
2025b843c749SSergey Zigachev table->GraphicsVoltageChangeEnable = 1;
2026b843c749SSergey Zigachev table->GraphicsThermThrottleEnable = 1;
2027b843c749SSergey Zigachev table->GraphicsInterval = 1;
2028b843c749SSergey Zigachev table->VoltageInterval = 1;
2029b843c749SSergey Zigachev table->ThermalInterval = 1;
2030b843c749SSergey Zigachev table->TemperatureLimitHigh =
2031b843c749SSergey Zigachev table_info->cac_dtp_table->usTargetOperatingTemp *
2032b843c749SSergey Zigachev SMU7_Q88_FORMAT_CONVERSION_UNIT;
2033b843c749SSergey Zigachev table->TemperatureLimitLow =
2034b843c749SSergey Zigachev (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2035b843c749SSergey Zigachev SMU7_Q88_FORMAT_CONVERSION_UNIT;
2036b843c749SSergey Zigachev table->MemoryVoltageChangeEnable = 1;
2037b843c749SSergey Zigachev table->MemoryInterval = 1;
2038b843c749SSergey Zigachev table->VoltageResponseTime = 0;
2039b843c749SSergey Zigachev table->PhaseResponseTime = 0;
2040b843c749SSergey Zigachev table->MemoryThermThrottleEnable = 1;
2041b843c749SSergey Zigachev
2042b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
2043b843c749SSergey Zigachev "There must be 1 or more PCIE levels defined in PPTable.",
2044b843c749SSergey Zigachev return -EINVAL);
2045b843c749SSergey Zigachev table->PCIeBootLinkLevel =
2046b843c749SSergey Zigachev hw_data->dpm_table.pcie_speed_table.count;
2047b843c749SSergey Zigachev table->PCIeGenInterval = 1;
2048b843c749SSergey Zigachev table->VRConfig = 0;
2049b843c749SSergey Zigachev
2050b843c749SSergey Zigachev result = vegam_populate_vr_config(hwmgr, table);
2051b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2052b843c749SSergey Zigachev "Failed to populate VRConfig setting!", return result);
2053b843c749SSergey Zigachev
2054b843c749SSergey Zigachev table->ThermGpio = 17;
2055b843c749SSergey Zigachev table->SclkStepSize = 0x4000;
2056b843c749SSergey Zigachev
2057b843c749SSergey Zigachev if (atomctrl_get_pp_assign_pin(hwmgr,
2058b843c749SSergey Zigachev VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2059b843c749SSergey Zigachev table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2060b843c749SSergey Zigachev if (gpio_table)
2061b843c749SSergey Zigachev table->VRHotLevel =
2062b843c749SSergey Zigachev table_info->gpio_table->vrhot_triggered_sclk_dpm_index;
2063b843c749SSergey Zigachev } else {
2064b843c749SSergey Zigachev table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2065b843c749SSergey Zigachev phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2066b843c749SSergey Zigachev PHM_PlatformCaps_RegulatorHot);
2067b843c749SSergey Zigachev }
2068b843c749SSergey Zigachev
2069b843c749SSergey Zigachev if (atomctrl_get_pp_assign_pin(hwmgr,
2070b843c749SSergey Zigachev PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin)) {
2071b843c749SSergey Zigachev table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2072b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2073b843c749SSergey Zigachev PHM_PlatformCaps_AutomaticDCTransition) &&
2074b843c749SSergey Zigachev !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme))
2075b843c749SSergey Zigachev phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2076b843c749SSergey Zigachev PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
2077b843c749SSergey Zigachev } else {
2078b843c749SSergey Zigachev table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2079b843c749SSergey Zigachev phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2080b843c749SSergey Zigachev PHM_PlatformCaps_AutomaticDCTransition);
2081b843c749SSergey Zigachev }
2082b843c749SSergey Zigachev
2083b843c749SSergey Zigachev /* Thermal Output GPIO */
2084b843c749SSergey Zigachev if (atomctrl_get_pp_assign_pin(hwmgr,
2085b843c749SSergey Zigachev THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin)) {
2086b843c749SSergey Zigachev table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2087b843c749SSergey Zigachev
2088b843c749SSergey Zigachev /* For porlarity read GPIOPAD_A with assigned Gpio pin
2089b843c749SSergey Zigachev * since VBIOS will program this register to set 'inactive state',
2090b843c749SSergey Zigachev * driver can then determine 'active state' from this and
2091b843c749SSergey Zigachev * program SMU with correct polarity
2092b843c749SSergey Zigachev */
2093b843c749SSergey Zigachev table->ThermOutPolarity =
2094b843c749SSergey Zigachev (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2095b843c749SSergey Zigachev (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2096b843c749SSergey Zigachev table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2097b843c749SSergey Zigachev
2098b843c749SSergey Zigachev /* if required, combine VRHot/PCC with thermal out GPIO */
2099b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2100b843c749SSergey Zigachev PHM_PlatformCaps_RegulatorHot) &&
2101b843c749SSergey Zigachev phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2102b843c749SSergey Zigachev PHM_PlatformCaps_CombinePCCWithThermalSignal))
2103b843c749SSergey Zigachev table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2104b843c749SSergey Zigachev } else {
2105b843c749SSergey Zigachev table->ThermOutGpio = 17;
2106b843c749SSergey Zigachev table->ThermOutPolarity = 1;
2107b843c749SSergey Zigachev table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2108b843c749SSergey Zigachev }
2109b843c749SSergey Zigachev
2110b843c749SSergey Zigachev /* Populate BIF_SCLK levels into SMC DPM table */
2111b843c749SSergey Zigachev for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2112b843c749SSergey Zigachev result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2113b843c749SSergey Zigachev smu_data->bif_sclk_table[i], ÷rs);
2114b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2115b843c749SSergey Zigachev "Can not find DFS divide id for Sclk",
2116b843c749SSergey Zigachev return result);
2117b843c749SSergey Zigachev
2118b843c749SSergey Zigachev if (i == 0)
2119b843c749SSergey Zigachev table->Ulv.BifSclkDfs =
2120b843c749SSergey Zigachev PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2121b843c749SSergey Zigachev else
2122b843c749SSergey Zigachev table->LinkLevel[i - 1].BifSclkDfs =
2123b843c749SSergey Zigachev PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2124b843c749SSergey Zigachev }
2125b843c749SSergey Zigachev
2126b843c749SSergey Zigachev for (i = 0; i < SMU75_MAX_ENTRIES_SMIO; i++)
2127b843c749SSergey Zigachev table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2128b843c749SSergey Zigachev
2129b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2130b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2131b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2132b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2133b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2134b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2135b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2136b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2137b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2138b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2139b843c749SSergey Zigachev
2140b843c749SSergey Zigachev /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2141b843c749SSergey Zigachev result = smu7_copy_bytes_to_smc(hwmgr,
2142b843c749SSergey Zigachev smu_data->smu7_data.dpm_table_start +
2143b843c749SSergey Zigachev offsetof(SMU75_Discrete_DpmTable, SystemFlags),
2144b843c749SSergey Zigachev (uint8_t *)&(table->SystemFlags),
2145b843c749SSergey Zigachev sizeof(SMU75_Discrete_DpmTable) - 3 * sizeof(SMU75_PIDController),
2146b843c749SSergey Zigachev SMC_RAM_END);
2147b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2148b843c749SSergey Zigachev "Failed to upload dpm data to SMC memory!", return result);
2149b843c749SSergey Zigachev
2150b843c749SSergey Zigachev result = vegam_populate_pm_fuses(hwmgr);
2151b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2152b843c749SSergey Zigachev "Failed to populate PM fuses to SMC memory!", return result);
2153b843c749SSergey Zigachev
2154b843c749SSergey Zigachev result = vegam_enable_reconfig_cus(hwmgr);
2155b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(!result,
2156b843c749SSergey Zigachev "Failed to enable reconfigurable CUs!", return result);
2157b843c749SSergey Zigachev
2158b843c749SSergey Zigachev return 0;
2159b843c749SSergey Zigachev }
2160b843c749SSergey Zigachev
vegam_get_offsetof(uint32_t type,uint32_t member)2161b843c749SSergey Zigachev static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member)
2162b843c749SSergey Zigachev {
2163b843c749SSergey Zigachev switch (type) {
2164b843c749SSergey Zigachev case SMU_SoftRegisters:
2165b843c749SSergey Zigachev switch (member) {
2166b843c749SSergey Zigachev case HandshakeDisables:
2167b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, HandshakeDisables);
2168b843c749SSergey Zigachev case VoltageChangeTimeout:
2169b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, VoltageChangeTimeout);
2170b843c749SSergey Zigachev case AverageGraphicsActivity:
2171b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, AverageGraphicsActivity);
2172b843c749SSergey Zigachev case PreVBlankGap:
2173b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, PreVBlankGap);
2174b843c749SSergey Zigachev case VBlankTimeout:
2175b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, VBlankTimeout);
2176b843c749SSergey Zigachev case UcodeLoadStatus:
2177b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, UcodeLoadStatus);
2178b843c749SSergey Zigachev case DRAM_LOG_ADDR_H:
2179b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_H);
2180b843c749SSergey Zigachev case DRAM_LOG_ADDR_L:
2181b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_L);
2182b843c749SSergey Zigachev case DRAM_LOG_PHY_ADDR_H:
2183b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2184b843c749SSergey Zigachev case DRAM_LOG_PHY_ADDR_L:
2185b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2186b843c749SSergey Zigachev case DRAM_LOG_BUFF_SIZE:
2187b843c749SSergey Zigachev return offsetof(SMU75_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2188b843c749SSergey Zigachev }
2189b843c749SSergey Zigachev break;
2190b843c749SSergey Zigachev case SMU_Discrete_DpmTable:
2191b843c749SSergey Zigachev switch (member) {
2192b843c749SSergey Zigachev case UvdBootLevel:
2193b843c749SSergey Zigachev return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);
2194b843c749SSergey Zigachev case VceBootLevel:
2195b843c749SSergey Zigachev return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
2196b843c749SSergey Zigachev case LowSclkInterruptThreshold:
2197b843c749SSergey Zigachev return offsetof(SMU75_Discrete_DpmTable, LowSclkInterruptThreshold);
2198b843c749SSergey Zigachev }
2199b843c749SSergey Zigachev break;
2200b843c749SSergey Zigachev }
2201b843c749SSergey Zigachev pr_warn("can't get the offset of type %x member %x\n", type, member);
2202b843c749SSergey Zigachev return 0;
2203b843c749SSergey Zigachev }
2204b843c749SSergey Zigachev
vegam_program_mem_timing_parameters(struct pp_hwmgr * hwmgr)2205b843c749SSergey Zigachev static int vegam_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2206b843c749SSergey Zigachev {
2207b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2208b843c749SSergey Zigachev
2209b843c749SSergey Zigachev if (data->need_update_smu7_dpm_table &
2210b843c749SSergey Zigachev (DPMTABLE_OD_UPDATE_SCLK +
2211b843c749SSergey Zigachev DPMTABLE_UPDATE_SCLK +
2212b843c749SSergey Zigachev DPMTABLE_UPDATE_MCLK))
2213b843c749SSergey Zigachev return vegam_program_memory_timing_parameters(hwmgr);
2214b843c749SSergey Zigachev
2215b843c749SSergey Zigachev return 0;
2216b843c749SSergey Zigachev }
2217b843c749SSergey Zigachev
vegam_update_sclk_threshold(struct pp_hwmgr * hwmgr)2218b843c749SSergey Zigachev static int vegam_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2219b843c749SSergey Zigachev {
2220b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2221b843c749SSergey Zigachev struct vegam_smumgr *smu_data =
2222b843c749SSergey Zigachev (struct vegam_smumgr *)(hwmgr->smu_backend);
2223b843c749SSergey Zigachev int result = 0;
2224b843c749SSergey Zigachev uint32_t low_sclk_interrupt_threshold = 0;
2225b843c749SSergey Zigachev
2226b843c749SSergey Zigachev if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2227b843c749SSergey Zigachev PHM_PlatformCaps_SclkThrottleLowNotification)
2228b843c749SSergey Zigachev && (data->low_sclk_interrupt_threshold != 0)) {
2229b843c749SSergey Zigachev low_sclk_interrupt_threshold =
2230b843c749SSergey Zigachev data->low_sclk_interrupt_threshold;
2231b843c749SSergey Zigachev
2232b843c749SSergey Zigachev CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2233b843c749SSergey Zigachev
2234b843c749SSergey Zigachev result = smu7_copy_bytes_to_smc(
2235b843c749SSergey Zigachev hwmgr,
2236b843c749SSergey Zigachev smu_data->smu7_data.dpm_table_start +
2237b843c749SSergey Zigachev offsetof(SMU75_Discrete_DpmTable,
2238b843c749SSergey Zigachev LowSclkInterruptThreshold),
2239b843c749SSergey Zigachev (uint8_t *)&low_sclk_interrupt_threshold,
2240b843c749SSergey Zigachev sizeof(uint32_t),
2241b843c749SSergey Zigachev SMC_RAM_END);
2242b843c749SSergey Zigachev }
2243b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((result == 0),
2244b843c749SSergey Zigachev "Failed to update SCLK threshold!", return result);
2245b843c749SSergey Zigachev
2246b843c749SSergey Zigachev result = vegam_program_mem_timing_parameters(hwmgr);
2247b843c749SSergey Zigachev PP_ASSERT_WITH_CODE((result == 0),
2248b843c749SSergey Zigachev "Failed to program memory timing parameters!",
2249b843c749SSergey Zigachev );
2250b843c749SSergey Zigachev
2251b843c749SSergey Zigachev return result;
2252b843c749SSergey Zigachev }
2253b843c749SSergey Zigachev
2254*78973132SSergey Zigachev int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
vegam_thermal_avfs_enable(struct pp_hwmgr * hwmgr)2255b843c749SSergey Zigachev int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2256b843c749SSergey Zigachev {
2257b843c749SSergey Zigachev struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2258b843c749SSergey Zigachev int ret;
2259b843c749SSergey Zigachev
2260b843c749SSergey Zigachev if (!hwmgr->avfs_supported)
2261b843c749SSergey Zigachev return 0;
2262b843c749SSergey Zigachev
2263b843c749SSergey Zigachev ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
2264b843c749SSergey Zigachev if (!ret) {
2265b843c749SSergey Zigachev if (data->apply_avfs_cks_off_voltage)
2266b843c749SSergey Zigachev ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
2267b843c749SSergey Zigachev }
2268b843c749SSergey Zigachev
2269b843c749SSergey Zigachev return ret;
2270b843c749SSergey Zigachev }
2271b843c749SSergey Zigachev
vegam_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)2272b843c749SSergey Zigachev static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2273b843c749SSergey Zigachev {
2274b843c749SSergey Zigachev PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,
2275b843c749SSergey Zigachev "VBIOS fan info is not correct!",
2276b843c749SSergey Zigachev );
2277b843c749SSergey Zigachev phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2278b843c749SSergey Zigachev PHM_PlatformCaps_MicrocodeFanControl);
2279b843c749SSergey Zigachev return 0;
2280b843c749SSergey Zigachev }
2281b843c749SSergey Zigachev
2282b843c749SSergey Zigachev const struct pp_smumgr_func vegam_smu_funcs = {
2283b843c749SSergey Zigachev .smu_init = vegam_smu_init,
2284b843c749SSergey Zigachev .smu_fini = smu7_smu_fini,
2285b843c749SSergey Zigachev .start_smu = vegam_start_smu,
2286b843c749SSergey Zigachev .check_fw_load_finish = smu7_check_fw_load_finish,
2287b843c749SSergey Zigachev .request_smu_load_fw = smu7_reload_firmware,
2288b843c749SSergey Zigachev .request_smu_load_specific_fw = NULL,
2289b843c749SSergey Zigachev .send_msg_to_smc = smu7_send_msg_to_smc,
2290b843c749SSergey Zigachev .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2291b843c749SSergey Zigachev .process_firmware_header = vegam_process_firmware_header,
2292b843c749SSergey Zigachev .is_dpm_running = vegam_is_dpm_running,
2293b843c749SSergey Zigachev .get_mac_definition = vegam_get_mac_definition,
2294b843c749SSergey Zigachev .update_smc_table = vegam_update_smc_table,
2295b843c749SSergey Zigachev .init_smc_table = vegam_init_smc_table,
2296b843c749SSergey Zigachev .get_offsetof = vegam_get_offsetof,
2297b843c749SSergey Zigachev .populate_all_graphic_levels = vegam_populate_all_graphic_levels,
2298b843c749SSergey Zigachev .populate_all_memory_levels = vegam_populate_all_memory_levels,
2299b843c749SSergey Zigachev .update_sclk_threshold = vegam_update_sclk_threshold,
2300b843c749SSergey Zigachev .is_hw_avfs_present = vegam_is_hw_avfs_present,
2301b843c749SSergey Zigachev .thermal_avfs_enable = vegam_thermal_avfs_enable,
2302b843c749SSergey Zigachev .thermal_setup_fan_table = vegam_thermal_setup_fan_table,
2303b843c749SSergey Zigachev };
2304