1 /************************************************************************** 2 * 3 * Copyright (c) 2006-2007 Tungsten Graphics, Inc., Cedar Park, TX., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 /* 28 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com> 29 */ 30 31 #include <linux/export.h> 32 #include <linux/highmem.h> 33 34 #include <drm/drm_cache.h> 35 36 #if defined(CONFIG_X86) 37 #include <asm/smp.h> 38 39 /* 40 * clflushopt is an unordered instruction which needs fencing with mfence or 41 * sfence to avoid ordering issues. For drm_clflush_page this fencing happens 42 * in the caller. 43 */ 44 static void 45 drm_clflush_page(struct page *page) 46 { 47 uint8_t *page_virtual; 48 unsigned int i; 49 const int size = boot_cpu_data.x86_clflush_size; 50 51 if (unlikely(page == NULL)) 52 return; 53 54 page_virtual = kmap_atomic(page); 55 for (i = 0; i < PAGE_SIZE; i += size) 56 clflushopt(page_virtual + i); 57 kunmap_atomic(page_virtual); 58 } 59 60 static void drm_cache_flush_clflush(struct page *pages[], 61 unsigned long num_pages) 62 { 63 unsigned long i; 64 65 mb(); 66 for (i = 0; i < num_pages; i++) 67 drm_clflush_page(*pages++); 68 mb(); 69 } 70 #endif 71 72 void 73 drm_clflush_pages(struct page *pages[], unsigned long num_pages) 74 { 75 76 #if defined(CONFIG_X86) 77 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 78 drm_cache_flush_clflush(pages, num_pages); 79 return; 80 } 81 82 cpu_wbinvd_on_all_cpus(); 83 84 #elif defined(__powerpc__) 85 unsigned long i; 86 for (i = 0; i < num_pages; i++) { 87 struct page *page = pages[i]; 88 void *page_virtual; 89 90 if (unlikely(page == NULL)) 91 continue; 92 93 page_virtual = kmap_atomic(page); 94 flush_dcache_range((unsigned long)page_virtual, 95 (unsigned long)page_virtual + PAGE_SIZE); 96 kunmap_atomic(page_virtual); 97 } 98 #else 99 pr_err("Architecture has no drm_cache.c support\n"); 100 WARN_ON_ONCE(1); 101 #endif 102 } 103 EXPORT_SYMBOL(drm_clflush_pages); 104 105 void 106 drm_clflush_sg(struct sg_table *st) 107 { 108 #if defined(CONFIG_X86) 109 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 110 struct sg_page_iter sg_iter; 111 112 mb(); 113 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) 114 drm_clflush_page(sg_page_iter_page(&sg_iter)); 115 mb(); 116 117 return; 118 } 119 120 cpu_wbinvd_on_all_cpus(); 121 #else 122 printk(KERN_ERR "Architecture has no drm_cache.c support\n"); 123 WARN_ON_ONCE(1); 124 #endif 125 } 126 EXPORT_SYMBOL(drm_clflush_sg); 127 128 void 129 drm_clflush_virt_range(void *addr, unsigned long length) 130 { 131 #if defined(CONFIG_X86) 132 if (static_cpu_has(X86_FEATURE_CLFLUSH)) { 133 const int size = boot_cpu_data.x86_clflush_size; 134 void *end = addr + length; 135 addr = (void *)(((unsigned long)addr) & -size); 136 mb(); 137 for (; addr < end; addr += size) 138 clflushopt(addr); 139 clflushopt(end - 1); /* force serialisation */ 140 mb(); 141 return; 142 } 143 144 cpu_wbinvd_on_all_cpus(); 145 #else 146 printk(KERN_ERR "Architecture has no drm_cache.c support\n"); 147 WARN_ON_ONCE(1); 148 #endif 149 } 150 EXPORT_SYMBOL(drm_clflush_virt_range); 151