xref: /dragonfly/sys/dev/drm/drm_dp_helper.c (revision cd1c6085)
1 /*
2  * Copyright © 2009 Keith Packard
3  *
4  * Permission to use, copy, modify, distribute, and sell this software and its
5  * documentation for any purpose is hereby granted without fee, provided that
6  * the above copyright notice appear in all copies and that both that copyright
7  * notice and this permission notice appear in supporting documentation, and
8  * that the name of the copyright holders not be used in advertising or
9  * publicity pertaining to distribution of the software without specific,
10  * written prior permission.  The copyright holders make no representations
11  * about the suitability of this software for any purpose.  It is provided "as
12  * is" without express or implied warranty.
13  *
14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20  * OF THIS SOFTWARE.
21  */
22 
23 #include <linux/export.h>
24 #include <drm/drmP.h>
25 #include <drm/drm_dp_helper.h>
26 
27 
28 /* Helpers for DP link training */
29 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
30 {
31 	return link_status[r - DP_LANE0_1_STATUS];
32 }
33 
34 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
35 			     int lane)
36 {
37 	int i = DP_LANE0_1_STATUS + (lane >> 1);
38 	int s = (lane & 1) * 4;
39 	u8 l = dp_link_status(link_status, i);
40 	return (l >> s) & 0xf;
41 }
42 
43 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
44 			  int lane_count)
45 {
46 	u8 lane_align;
47 	u8 lane_status;
48 	int lane;
49 
50 	lane_align = dp_link_status(link_status,
51 				    DP_LANE_ALIGN_STATUS_UPDATED);
52 	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
53 		return false;
54 	for (lane = 0; lane < lane_count; lane++) {
55 		lane_status = dp_get_lane_status(link_status, lane);
56 		if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
57 			return false;
58 	}
59 	return true;
60 }
61 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
62 
63 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
64 			      int lane_count)
65 {
66 	int lane;
67 	u8 lane_status;
68 
69 	for (lane = 0; lane < lane_count; lane++) {
70 		lane_status = dp_get_lane_status(link_status, lane);
71 		if ((lane_status & DP_LANE_CR_DONE) == 0)
72 			return false;
73 	}
74 	return true;
75 }
76 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
77 
78 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
79 				     int lane)
80 {
81 	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
82 	int s = ((lane & 1) ?
83 		 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
84 		 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
85 	u8 l = dp_link_status(link_status, i);
86 
87 	return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
88 }
89 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
90 
91 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
92 					  int lane)
93 {
94 	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
95 	int s = ((lane & 1) ?
96 		 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
97 		 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
98 	u8 l = dp_link_status(link_status, i);
99 
100 	return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
101 }
102 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
103 
104 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
105 	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
106 		udelay(100);
107 	else
108 		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
109 }
110 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
111 
112 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
113 	if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
114 		udelay(400);
115 	else
116 		mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
117 }
118 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
119 
120 u8 drm_dp_link_rate_to_bw_code(int link_rate)
121 {
122 	switch (link_rate) {
123 	case 162000:
124 	default:
125 		return DP_LINK_BW_1_62;
126 	case 270000:
127 		return DP_LINK_BW_2_7;
128 	case 540000:
129 		return DP_LINK_BW_5_4;
130 	}
131 }
132 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
133 
134 int drm_dp_bw_code_to_link_rate(u8 link_bw)
135 {
136 	switch (link_bw) {
137 	case DP_LINK_BW_1_62:
138 	default:
139 		return 162000;
140 	case DP_LINK_BW_2_7:
141 		return 270000;
142 	case DP_LINK_BW_5_4:
143 		return 540000;
144 	}
145 }
146 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
147