1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/module.h> 34 #include <drm/drmP.h> 35 #include <drm/drm_edid.h> 36 #include <linux/string.h> 37 38 #include <bus/iicbus/iic.h> 39 #include <bus/iicbus/iiconf.h> 40 #include "iicbus_if.h" 41 42 #define version_greater(edid, maj, min) \ 43 (((edid)->version > (maj)) || \ 44 ((edid)->version == (maj) && (edid)->revision > (min))) 45 46 #define EDID_EST_TIMINGS 16 47 #define EDID_STD_TIMINGS 8 48 #define EDID_DETAILED_TIMINGS 4 49 50 /* 51 * EDID blocks out in the wild have a variety of bugs, try to collect 52 * them here (note that userspace may work around broken monitors first, 53 * but fixes should make their way here so that the kernel "just works" 54 * on as many displays as possible). 55 */ 56 57 /* First detailed mode wrong, use largest 60Hz mode */ 58 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 59 /* Reported 135MHz pixel clock is too high, needs adjustment */ 60 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 61 /* Prefer the largest mode at 75 Hz */ 62 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 63 /* Detail timing is in cm not mm */ 64 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 65 /* Detailed timing descriptors have bogus size values, so just take the 66 * maximum size and use that. 67 */ 68 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 69 /* Monitor forgot to set the first detailed is preferred bit. */ 70 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 71 /* use +hsync +vsync for detailed mode */ 72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 73 /* Force reduced-blanking timings for detailed modes */ 74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 75 /* Force 8bpc */ 76 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 77 /* Force 12bpc */ 78 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 79 80 struct detailed_mode_closure { 81 struct drm_connector *connector; 82 struct edid *edid; 83 bool preferred; 84 u32 quirks; 85 int modes; 86 }; 87 88 #define LEVEL_DMT 0 89 #define LEVEL_GTF 1 90 #define LEVEL_GTF2 2 91 #define LEVEL_CVT 3 92 93 static struct edid_quirk { 94 char vendor[4]; 95 int product_id; 96 u32 quirks; 97 } edid_quirk_list[] = { 98 /* Acer AL1706 */ 99 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 100 /* Acer F51 */ 101 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 102 /* Unknown Acer */ 103 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 104 105 /* Belinea 10 15 55 */ 106 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 107 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 108 109 /* Envision Peripherals, Inc. EN-7100e */ 110 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 111 /* Envision EN2028 */ 112 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 113 114 /* Funai Electronics PM36B */ 115 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 116 EDID_QUIRK_DETAILED_IN_CM }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 }; 146 147 /* 148 * Autogenerated from the DMT spec. 149 * This table is copied from xfree86/modes/xf86EdidModes.c. 150 */ 151 static const struct drm_display_mode drm_dmt_modes[] = { 152 /* 640x350@85Hz */ 153 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 154 736, 832, 0, 350, 382, 385, 445, 0, 155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 156 /* 640x400@85Hz */ 157 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 158 736, 832, 0, 400, 401, 404, 445, 0, 159 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 160 /* 720x400@85Hz */ 161 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 162 828, 936, 0, 400, 401, 404, 446, 0, 163 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 164 /* 640x480@60Hz */ 165 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 166 752, 800, 0, 480, 489, 492, 525, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 168 /* 640x480@72Hz */ 169 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 170 704, 832, 0, 480, 489, 492, 520, 0, 171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 172 /* 640x480@75Hz */ 173 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 174 720, 840, 0, 480, 481, 484, 500, 0, 175 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 176 /* 640x480@85Hz */ 177 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 178 752, 832, 0, 480, 481, 484, 509, 0, 179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 180 /* 800x600@56Hz */ 181 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 182 896, 1024, 0, 600, 601, 603, 625, 0, 183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 184 /* 800x600@60Hz */ 185 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 186 968, 1056, 0, 600, 601, 605, 628, 0, 187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 188 /* 800x600@72Hz */ 189 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 190 976, 1040, 0, 600, 637, 643, 666, 0, 191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 192 /* 800x600@75Hz */ 193 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 194 896, 1056, 0, 600, 601, 604, 625, 0, 195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 196 /* 800x600@85Hz */ 197 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 198 896, 1048, 0, 600, 601, 604, 631, 0, 199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 200 /* 800x600@120Hz RB */ 201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 202 880, 960, 0, 600, 603, 607, 636, 0, 203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 204 /* 848x480@60Hz */ 205 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 206 976, 1088, 0, 480, 486, 494, 517, 0, 207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 208 /* 1024x768@43Hz, interlace */ 209 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 210 1208, 1264, 0, 768, 768, 772, 817, 0, 211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 212 DRM_MODE_FLAG_INTERLACE) }, 213 /* 1024x768@60Hz */ 214 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 215 1184, 1344, 0, 768, 771, 777, 806, 0, 216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 217 /* 1024x768@70Hz */ 218 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 219 1184, 1328, 0, 768, 771, 777, 806, 0, 220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 221 /* 1024x768@75Hz */ 222 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 223 1136, 1312, 0, 768, 769, 772, 800, 0, 224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 225 /* 1024x768@85Hz */ 226 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 227 1168, 1376, 0, 768, 769, 772, 808, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 229 /* 1024x768@120Hz RB */ 230 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 231 1104, 1184, 0, 768, 771, 775, 813, 0, 232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 233 /* 1152x864@75Hz */ 234 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 235 1344, 1600, 0, 864, 865, 868, 900, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 1280x768@60Hz RB */ 238 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 239 1360, 1440, 0, 768, 771, 778, 790, 0, 240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 1280x768@60Hz */ 242 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 243 1472, 1664, 0, 768, 771, 778, 798, 0, 244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 245 /* 1280x768@75Hz */ 246 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 247 1488, 1696, 0, 768, 771, 778, 805, 0, 248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 249 /* 1280x768@85Hz */ 250 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 251 1496, 1712, 0, 768, 771, 778, 809, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 1280x768@120Hz RB */ 254 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 255 1360, 1440, 0, 768, 771, 778, 813, 0, 256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 257 /* 1280x800@60Hz RB */ 258 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 259 1360, 1440, 0, 800, 803, 809, 823, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 1280x800@60Hz */ 262 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 263 1480, 1680, 0, 800, 803, 809, 831, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 1280x800@75Hz */ 266 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 267 1488, 1696, 0, 800, 803, 809, 838, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 1280x800@85Hz */ 270 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 271 1496, 1712, 0, 800, 803, 809, 843, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 1280x800@120Hz RB */ 274 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 275 1360, 1440, 0, 800, 803, 809, 847, 0, 276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 277 /* 1280x960@60Hz */ 278 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 279 1488, 1800, 0, 960, 961, 964, 1000, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 1280x960@85Hz */ 282 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 283 1504, 1728, 0, 960, 961, 964, 1011, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 1280x960@120Hz RB */ 286 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 287 1360, 1440, 0, 960, 963, 967, 1017, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 289 /* 1280x1024@60Hz */ 290 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 291 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 293 /* 1280x1024@75Hz */ 294 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 295 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 1280x1024@85Hz */ 298 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 299 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 1280x1024@120Hz RB */ 302 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 303 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 305 /* 1360x768@60Hz */ 306 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 307 1536, 1792, 0, 768, 771, 777, 795, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 309 /* 1360x768@120Hz RB */ 310 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 311 1440, 1520, 0, 768, 771, 776, 813, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 313 /* 1400x1050@60Hz RB */ 314 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 315 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 1400x1050@60Hz */ 318 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 319 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 1400x1050@75Hz */ 322 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 323 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 1400x1050@85Hz */ 326 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 327 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 1400x1050@120Hz RB */ 330 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 331 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 333 /* 1440x900@60Hz RB */ 334 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 335 1520, 1600, 0, 900, 903, 909, 926, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 1440x900@60Hz */ 338 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 339 1672, 1904, 0, 900, 903, 909, 934, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 1440x900@75Hz */ 342 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 343 1688, 1936, 0, 900, 903, 909, 942, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 1440x900@85Hz */ 346 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 347 1696, 1952, 0, 900, 903, 909, 948, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 1440x900@120Hz RB */ 350 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 351 1520, 1600, 0, 900, 903, 909, 953, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 1600x1200@60Hz */ 354 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 355 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 1600x1200@65Hz */ 358 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 359 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 1600x1200@70Hz */ 362 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 363 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 365 /* 1600x1200@75Hz */ 366 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 367 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 1600x1200@85Hz */ 370 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 371 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 1600x1200@120Hz RB */ 374 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 375 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 377 /* 1680x1050@60Hz RB */ 378 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 379 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 381 /* 1680x1050@60Hz */ 382 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 383 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 384 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 1680x1050@75Hz */ 386 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 387 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 1680x1050@85Hz */ 390 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 391 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 392 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 1680x1050@120Hz RB */ 394 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 395 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 397 /* 1792x1344@60Hz */ 398 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 399 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 400 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 1792x1344@75Hz */ 402 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 403 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 1792x1344@120Hz RB */ 406 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 407 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 409 /* 1856x1392@60Hz */ 410 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 411 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 1856x1392@75Hz */ 414 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 415 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 1856x1392@120Hz RB */ 418 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 419 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 1920x1200@60Hz RB */ 422 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 423 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 425 /* 1920x1200@60Hz */ 426 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 427 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 1920x1200@75Hz */ 430 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 431 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 1920x1200@85Hz */ 434 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 435 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 437 /* 1920x1200@120Hz RB */ 438 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 439 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 441 /* 1920x1440@60Hz */ 442 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 443 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 1920x1440@75Hz */ 446 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 447 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 1920x1440@120Hz RB */ 450 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 451 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 453 /* 2560x1600@60Hz RB */ 454 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 455 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 457 /* 2560x1600@60Hz */ 458 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 459 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 2560x1600@75HZ */ 462 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 463 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 2560x1600@85HZ */ 466 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 467 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 2560x1600@120Hz RB */ 470 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 471 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 473 }; 474 475 /* 476 * These more or less come from the DMT spec. The 720x400 modes are 477 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 478 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 479 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 480 * mode. 481 * 482 * The DMT modes have been fact-checked; the rest are mild guesses. 483 */ 484 static const struct drm_display_mode edid_est_modes[] = { 485 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 486 968, 1056, 0, 600, 601, 605, 628, 0, 487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 488 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 489 896, 1024, 0, 600, 601, 603, 625, 0, 490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 491 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 492 720, 840, 0, 480, 481, 484, 500, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 494 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 495 704, 832, 0, 480, 489, 491, 520, 0, 496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 497 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 498 768, 864, 0, 480, 483, 486, 525, 0, 499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 500 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 501 752, 800, 0, 480, 490, 492, 525, 0, 502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 503 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 504 846, 900, 0, 400, 421, 423, 449, 0, 505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 506 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 507 846, 900, 0, 400, 412, 414, 449, 0, 508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 509 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 510 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 512 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 513 1136, 1312, 0, 768, 769, 772, 800, 0, 514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 515 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 516 1184, 1328, 0, 768, 771, 777, 806, 0, 517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 518 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 519 1184, 1344, 0, 768, 771, 777, 806, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 521 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 522 1208, 1264, 0, 768, 768, 776, 817, 0, 523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 524 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 525 928, 1152, 0, 624, 625, 628, 667, 0, 526 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 527 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 528 896, 1056, 0, 600, 601, 604, 625, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 530 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 531 976, 1040, 0, 600, 637, 643, 666, 0, 532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 533 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 534 1344, 1600, 0, 864, 865, 868, 900, 0, 535 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 536 }; 537 538 struct minimode { 539 short w; 540 short h; 541 short r; 542 short rb; 543 }; 544 545 static const struct minimode est3_modes[] = { 546 /* byte 6 */ 547 { 640, 350, 85, 0 }, 548 { 640, 400, 85, 0 }, 549 { 720, 400, 85, 0 }, 550 { 640, 480, 85, 0 }, 551 { 848, 480, 60, 0 }, 552 { 800, 600, 85, 0 }, 553 { 1024, 768, 85, 0 }, 554 { 1152, 864, 75, 0 }, 555 /* byte 7 */ 556 { 1280, 768, 60, 1 }, 557 { 1280, 768, 60, 0 }, 558 { 1280, 768, 75, 0 }, 559 { 1280, 768, 85, 0 }, 560 { 1280, 960, 60, 0 }, 561 { 1280, 960, 85, 0 }, 562 { 1280, 1024, 60, 0 }, 563 { 1280, 1024, 85, 0 }, 564 /* byte 8 */ 565 { 1360, 768, 60, 0 }, 566 { 1440, 900, 60, 1 }, 567 { 1440, 900, 60, 0 }, 568 { 1440, 900, 75, 0 }, 569 { 1440, 900, 85, 0 }, 570 { 1400, 1050, 60, 1 }, 571 { 1400, 1050, 60, 0 }, 572 { 1400, 1050, 75, 0 }, 573 /* byte 9 */ 574 { 1400, 1050, 85, 0 }, 575 { 1680, 1050, 60, 1 }, 576 { 1680, 1050, 60, 0 }, 577 { 1680, 1050, 75, 0 }, 578 { 1680, 1050, 85, 0 }, 579 { 1600, 1200, 60, 0 }, 580 { 1600, 1200, 65, 0 }, 581 { 1600, 1200, 70, 0 }, 582 /* byte 10 */ 583 { 1600, 1200, 75, 0 }, 584 { 1600, 1200, 85, 0 }, 585 { 1792, 1344, 60, 0 }, 586 { 1792, 1344, 75, 0 }, 587 { 1856, 1392, 60, 0 }, 588 { 1856, 1392, 75, 0 }, 589 { 1920, 1200, 60, 1 }, 590 { 1920, 1200, 60, 0 }, 591 /* byte 11 */ 592 { 1920, 1200, 75, 0 }, 593 { 1920, 1200, 85, 0 }, 594 { 1920, 1440, 60, 0 }, 595 { 1920, 1440, 75, 0 }, 596 }; 597 598 static const struct minimode extra_modes[] = { 599 { 1024, 576, 60, 0 }, 600 { 1366, 768, 60, 0 }, 601 { 1600, 900, 60, 0 }, 602 { 1680, 945, 60, 0 }, 603 { 1920, 1080, 60, 0 }, 604 { 2048, 1152, 60, 0 }, 605 { 2048, 1536, 60, 0 }, 606 }; 607 608 /* 609 * Probably taken from CEA-861 spec. 610 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 611 */ 612 static const struct drm_display_mode edid_cea_modes[] = { 613 /* 1 - 640x480@60Hz */ 614 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 615 752, 800, 0, 480, 490, 492, 525, 0, 616 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 617 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 618 /* 2 - 720x480@60Hz */ 619 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 620 798, 858, 0, 480, 489, 495, 525, 0, 621 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 622 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 623 /* 3 - 720x480@60Hz */ 624 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 625 798, 858, 0, 480, 489, 495, 525, 0, 626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 627 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 628 /* 4 - 1280x720@60Hz */ 629 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 630 1430, 1650, 0, 720, 725, 730, 750, 0, 631 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 632 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 633 /* 5 - 1920x1080i@60Hz */ 634 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 635 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 637 DRM_MODE_FLAG_INTERLACE), 638 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 639 /* 6 - 720(1440)x480i@60Hz */ 640 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 641 801, 858, 0, 480, 488, 494, 525, 0, 642 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 643 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 644 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 645 /* 7 - 720(1440)x480i@60Hz */ 646 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 647 801, 858, 0, 480, 488, 494, 525, 0, 648 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 649 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 650 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 651 /* 8 - 720(1440)x240@60Hz */ 652 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 653 801, 858, 0, 240, 244, 247, 262, 0, 654 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 655 DRM_MODE_FLAG_DBLCLK), 656 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 657 /* 9 - 720(1440)x240@60Hz */ 658 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 659 801, 858, 0, 240, 244, 247, 262, 0, 660 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 661 DRM_MODE_FLAG_DBLCLK), 662 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 663 /* 10 - 2880x480i@60Hz */ 664 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 665 3204, 3432, 0, 480, 488, 494, 525, 0, 666 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 667 DRM_MODE_FLAG_INTERLACE), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 669 /* 11 - 2880x480i@60Hz */ 670 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 671 3204, 3432, 0, 480, 488, 494, 525, 0, 672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 673 DRM_MODE_FLAG_INTERLACE), 674 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 675 /* 12 - 2880x240@60Hz */ 676 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 677 3204, 3432, 0, 240, 244, 247, 262, 0, 678 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 679 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 680 /* 13 - 2880x240@60Hz */ 681 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 682 3204, 3432, 0, 240, 244, 247, 262, 0, 683 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 684 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 685 /* 14 - 1440x480@60Hz */ 686 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 687 1596, 1716, 0, 480, 489, 495, 525, 0, 688 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 689 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 690 /* 15 - 1440x480@60Hz */ 691 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 692 1596, 1716, 0, 480, 489, 495, 525, 0, 693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 694 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 695 /* 16 - 1920x1080@60Hz */ 696 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 697 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 698 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 699 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 700 /* 17 - 720x576@50Hz */ 701 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 702 796, 864, 0, 576, 581, 586, 625, 0, 703 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 704 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 705 /* 18 - 720x576@50Hz */ 706 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 707 796, 864, 0, 576, 581, 586, 625, 0, 708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 709 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 710 /* 19 - 1280x720@50Hz */ 711 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 712 1760, 1980, 0, 720, 725, 730, 750, 0, 713 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 714 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 715 /* 20 - 1920x1080i@50Hz */ 716 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 717 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 718 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 719 DRM_MODE_FLAG_INTERLACE), 720 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 721 /* 21 - 720(1440)x576i@50Hz */ 722 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 723 795, 864, 0, 576, 580, 586, 625, 0, 724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 725 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 726 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 727 /* 22 - 720(1440)x576i@50Hz */ 728 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 729 795, 864, 0, 576, 580, 586, 625, 0, 730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 731 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 732 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 733 /* 23 - 720(1440)x288@50Hz */ 734 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 735 795, 864, 0, 288, 290, 293, 312, 0, 736 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 737 DRM_MODE_FLAG_DBLCLK), 738 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 739 /* 24 - 720(1440)x288@50Hz */ 740 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 741 795, 864, 0, 288, 290, 293, 312, 0, 742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 743 DRM_MODE_FLAG_DBLCLK), 744 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 745 /* 25 - 2880x576i@50Hz */ 746 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 747 3180, 3456, 0, 576, 580, 586, 625, 0, 748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 749 DRM_MODE_FLAG_INTERLACE), 750 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 751 /* 26 - 2880x576i@50Hz */ 752 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 753 3180, 3456, 0, 576, 580, 586, 625, 0, 754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 755 DRM_MODE_FLAG_INTERLACE), 756 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 27 - 2880x288@50Hz */ 758 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 759 3180, 3456, 0, 288, 290, 293, 312, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 761 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 762 /* 28 - 2880x288@50Hz */ 763 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 764 3180, 3456, 0, 288, 290, 293, 312, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 766 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 767 /* 29 - 1440x576@50Hz */ 768 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 769 1592, 1728, 0, 576, 581, 586, 625, 0, 770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 771 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 772 /* 30 - 1440x576@50Hz */ 773 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 774 1592, 1728, 0, 576, 581, 586, 625, 0, 775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 776 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 777 /* 31 - 1920x1080@50Hz */ 778 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 779 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 780 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 781 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 782 /* 32 - 1920x1080@24Hz */ 783 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 784 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 785 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 786 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 787 /* 33 - 1920x1080@25Hz */ 788 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 789 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 790 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 791 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 792 /* 34 - 1920x1080@30Hz */ 793 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 794 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 795 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 796 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 797 /* 35 - 2880x480@60Hz */ 798 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 799 3192, 3432, 0, 480, 489, 495, 525, 0, 800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 801 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 802 /* 36 - 2880x480@60Hz */ 803 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 804 3192, 3432, 0, 480, 489, 495, 525, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 806 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 807 /* 37 - 2880x576@50Hz */ 808 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 809 3184, 3456, 0, 576, 581, 586, 625, 0, 810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 811 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 812 /* 38 - 2880x576@50Hz */ 813 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 814 3184, 3456, 0, 576, 581, 586, 625, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 817 /* 39 - 1920x1080i@50Hz */ 818 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 819 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 821 DRM_MODE_FLAG_INTERLACE), 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 40 - 1920x1080i@100Hz */ 824 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 825 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 827 DRM_MODE_FLAG_INTERLACE), 828 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 41 - 1280x720@100Hz */ 830 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 831 1760, 1980, 0, 720, 725, 730, 750, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 833 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 42 - 720x576@100Hz */ 835 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 836 796, 864, 0, 576, 581, 586, 625, 0, 837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 838 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 839 /* 43 - 720x576@100Hz */ 840 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 841 796, 864, 0, 576, 581, 586, 625, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 843 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 844 /* 44 - 720(1440)x576i@100Hz */ 845 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 846 795, 864, 0, 576, 580, 586, 625, 0, 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 848 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 849 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 850 /* 45 - 720(1440)x576i@100Hz */ 851 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 852 795, 864, 0, 576, 580, 586, 625, 0, 853 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 854 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 855 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 856 /* 46 - 1920x1080i@120Hz */ 857 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 858 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 859 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 860 DRM_MODE_FLAG_INTERLACE), 861 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 862 /* 47 - 1280x720@120Hz */ 863 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 864 1430, 1650, 0, 720, 725, 730, 750, 0, 865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 866 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 867 /* 48 - 720x480@120Hz */ 868 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 869 798, 858, 0, 480, 489, 495, 525, 0, 870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 871 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 872 /* 49 - 720x480@120Hz */ 873 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 874 798, 858, 0, 480, 489, 495, 525, 0, 875 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 876 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 877 /* 50 - 720(1440)x480i@120Hz */ 878 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 879 801, 858, 0, 480, 488, 494, 525, 0, 880 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 881 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 882 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 883 /* 51 - 720(1440)x480i@120Hz */ 884 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 885 801, 858, 0, 480, 488, 494, 525, 0, 886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 887 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 888 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 889 /* 52 - 720x576@200Hz */ 890 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 891 796, 864, 0, 576, 581, 586, 625, 0, 892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 893 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 894 /* 53 - 720x576@200Hz */ 895 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 896 796, 864, 0, 576, 581, 586, 625, 0, 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 898 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 54 - 720(1440)x576i@200Hz */ 900 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 901 795, 864, 0, 576, 580, 586, 625, 0, 902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 903 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 904 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 905 /* 55 - 720(1440)x576i@200Hz */ 906 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 907 795, 864, 0, 576, 580, 586, 625, 0, 908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 909 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 910 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 911 /* 56 - 720x480@240Hz */ 912 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 913 798, 858, 0, 480, 489, 495, 525, 0, 914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 915 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 916 /* 57 - 720x480@240Hz */ 917 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 918 798, 858, 0, 480, 489, 495, 525, 0, 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 920 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 58 - 720(1440)x480i@240 */ 922 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 923 801, 858, 0, 480, 488, 494, 525, 0, 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 925 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 926 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 927 /* 59 - 720(1440)x480i@240 */ 928 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 929 801, 858, 0, 480, 488, 494, 525, 0, 930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 931 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 932 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 933 /* 60 - 1280x720@24Hz */ 934 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 935 3080, 3300, 0, 720, 725, 730, 750, 0, 936 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 937 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 938 /* 61 - 1280x720@25Hz */ 939 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 940 3740, 3960, 0, 720, 725, 730, 750, 0, 941 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 942 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 943 /* 62 - 1280x720@30Hz */ 944 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 945 3080, 3300, 0, 720, 725, 730, 750, 0, 946 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 947 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 63 - 1920x1080@120Hz */ 949 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 950 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 951 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 952 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 953 /* 64 - 1920x1080@100Hz */ 954 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 955 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 956 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 957 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 958 }; 959 960 /* 961 * HDMI 1.4 4k modes. 962 */ 963 static const struct drm_display_mode edid_4k_modes[] = { 964 /* 1 - 3840x2160@30Hz */ 965 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 966 3840, 4016, 4104, 4400, 0, 967 2160, 2168, 2178, 2250, 0, 968 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 969 .vrefresh = 30, }, 970 /* 2 - 3840x2160@25Hz */ 971 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 972 3840, 4896, 4984, 5280, 0, 973 2160, 2168, 2178, 2250, 0, 974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 975 .vrefresh = 25, }, 976 /* 3 - 3840x2160@24Hz */ 977 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 978 3840, 5116, 5204, 5500, 0, 979 2160, 2168, 2178, 2250, 0, 980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 981 .vrefresh = 24, }, 982 /* 4 - 4096x2160@24Hz (SMPTE) */ 983 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 984 4096, 5116, 5204, 5500, 0, 985 2160, 2168, 2178, 2250, 0, 986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 987 .vrefresh = 24, }, 988 }; 989 990 /*** DDC fetch and block validation ***/ 991 992 static const u8 edid_header[] = { 993 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 994 }; 995 996 /** 997 * drm_edid_header_is_valid - sanity check the header of the base EDID block 998 * @raw_edid: pointer to raw base EDID block 999 * 1000 * Sanity check the header of the base EDID block. 1001 * 1002 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1003 */ 1004 int drm_edid_header_is_valid(const u8 *raw_edid) 1005 { 1006 int i, score = 0; 1007 1008 for (i = 0; i < sizeof(edid_header); i++) 1009 if (raw_edid[i] == edid_header[i]) 1010 score++; 1011 1012 return score; 1013 } 1014 EXPORT_SYMBOL(drm_edid_header_is_valid); 1015 1016 static int edid_fixup __read_mostly = 6; 1017 module_param_named(edid_fixup, edid_fixup, int, 0400); 1018 MODULE_PARM_DESC(edid_fixup, 1019 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1020 1021 static int drm_edid_block_checksum(const u8 *raw_edid) 1022 { 1023 int i; 1024 u8 csum = 0; 1025 for (i = 0; i < EDID_LENGTH; i++) 1026 csum += raw_edid[i]; 1027 1028 return csum; 1029 } 1030 1031 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1032 { 1033 if (memchr_inv(in_edid, 0, length)) 1034 return false; 1035 1036 return true; 1037 } 1038 1039 /** 1040 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1041 * @raw_edid: pointer to raw EDID block 1042 * @block: type of block to validate (0 for base, extension otherwise) 1043 * @print_bad_edid: if true, dump bad EDID blocks to the console 1044 * 1045 * Validate a base or extension EDID block and optionally dump bad blocks to 1046 * the console. 1047 * 1048 * Return: True if the block is valid, false otherwise. 1049 */ 1050 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) 1051 { 1052 int i; 1053 u8 csum; 1054 struct edid *edid = (struct edid *)raw_edid; 1055 1056 if (WARN_ON(!raw_edid)) 1057 return false; 1058 1059 if (edid_fixup > 8 || edid_fixup < 0) 1060 edid_fixup = 6; 1061 1062 if (block == 0) { 1063 int score = drm_edid_header_is_valid(raw_edid); 1064 if (score == 8) ; 1065 else if (score >= edid_fixup) { 1066 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1067 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1068 } else { 1069 goto bad; 1070 } 1071 } 1072 1073 csum = drm_edid_block_checksum(raw_edid); 1074 if (csum) { 1075 if (print_bad_edid) { 1076 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1077 } 1078 1079 /* allow CEA to slide through, switches mangle this */ 1080 if (raw_edid[0] != 0x02) 1081 goto bad; 1082 } 1083 1084 /* per-block-type checks */ 1085 switch (raw_edid[0]) { 1086 case 0: /* base */ 1087 if (edid->version != 1) { 1088 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1089 goto bad; 1090 } 1091 1092 if (edid->revision > 4) 1093 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1094 break; 1095 1096 default: 1097 break; 1098 } 1099 1100 return true; 1101 1102 bad: 1103 if (print_bad_edid) { 1104 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1105 printk(KERN_ERR "EDID block is all zeroes\n"); 1106 } else { 1107 printk(KERN_ERR "Raw EDID:\n"); 1108 for (i = 0; i < EDID_LENGTH; ) { 1109 kprintf("%02x", raw_edid[i]); 1110 i++; 1111 if (i % 16 == 0 || i == EDID_LENGTH) 1112 kprintf("\n"); 1113 else if (i % 8 == 0) 1114 kprintf(" "); 1115 else 1116 kprintf(" "); 1117 } 1118 } 1119 } 1120 return false; 1121 } 1122 EXPORT_SYMBOL(drm_edid_block_valid); 1123 1124 /** 1125 * drm_edid_is_valid - sanity check EDID data 1126 * @edid: EDID data 1127 * 1128 * Sanity-check an entire EDID record (including extensions) 1129 * 1130 * Return: True if the EDID data is valid, false otherwise. 1131 */ 1132 bool drm_edid_is_valid(struct edid *edid) 1133 { 1134 int i; 1135 u8 *raw = (u8 *)edid; 1136 1137 if (!edid) 1138 return false; 1139 1140 for (i = 0; i <= edid->extensions; i++) 1141 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true)) 1142 return false; 1143 1144 return true; 1145 } 1146 EXPORT_SYMBOL(drm_edid_is_valid); 1147 1148 #define DDC_SEGMENT_ADDR 0x30 1149 /** 1150 * drm_do_probe_ddc_edid() - get EDID information via I2C 1151 * @data: I2C device adapter 1152 * @buf: EDID data buffer to be filled 1153 * @block: 128 byte EDID block to start fetching from 1154 * @len: EDID data buffer length to fetch 1155 * 1156 * Try to fetch EDID information by calling I2C driver functions. 1157 * 1158 * Return: 0 on success or -1 on failure. 1159 */ 1160 static int 1161 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1162 { 1163 struct i2c_adapter *adapter = data; 1164 unsigned char start = block * EDID_LENGTH; 1165 unsigned char segment = block >> 1; 1166 unsigned char xfers = segment ? 3 : 2; 1167 int ret, retries = 5; 1168 1169 /* 1170 * The core I2C driver will automatically retry the transfer if the 1171 * adapter reports EAGAIN. However, we find that bit-banging transfers 1172 * are susceptible to errors under a heavily loaded machine and 1173 * generate spurious NAKs and timeouts. Retrying the transfer 1174 * of the individual block a few times seems to overcome this. 1175 */ 1176 do { 1177 struct i2c_msg msgs[] = { 1178 { 1179 .slave = DDC_SEGMENT_ADDR << 1, 1180 .flags = 0, 1181 .len = 1, 1182 .buf = &segment, 1183 }, { 1184 .slave = DDC_ADDR << 1, 1185 .flags = 0, 1186 .len = 1, 1187 .buf = &start, 1188 }, { 1189 .slave = DDC_ADDR << 1, 1190 .flags = I2C_M_RD, 1191 .len = len, 1192 .buf = buf, 1193 } 1194 }; 1195 1196 /* 1197 * Avoid sending the segment addr to not upset non-compliant 1198 * DDC monitors. 1199 */ 1200 ret = iicbus_transfer(adapter, &msgs[3 - xfers], xfers); 1201 1202 if (ret != 0) 1203 DRM_DEBUG_KMS("iicbus_transfer countdown %d error %d\n", 1204 retries, ret); 1205 } while (ret != 0 && --retries); 1206 1207 return (ret == 0 ? 0 : -1); 1208 } 1209 1210 /** 1211 * drm_do_get_edid - get EDID data using a custom EDID block read function 1212 * @connector: connector we're probing 1213 * @get_edid_block: EDID block read function 1214 * @data: private data passed to the block read function 1215 * 1216 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1217 * exposes a different interface to read EDID blocks this function can be used 1218 * to get EDID data using a custom block read function. 1219 * 1220 * As in the general case the DDC bus is accessible by the kernel at the I2C 1221 * level, drivers must make all reasonable efforts to expose it as an I2C 1222 * adapter and use drm_get_edid() instead of abusing this function. 1223 * 1224 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1225 */ 1226 struct edid *drm_do_get_edid(struct drm_connector *connector, 1227 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1228 size_t len), 1229 void *data) 1230 { 1231 int i, j = 0, valid_extensions = 0; 1232 u8 *block, *new; 1233 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1234 1235 if ((block = kmalloc(EDID_LENGTH, M_DRM, M_WAITOK)) == NULL) 1236 return NULL; 1237 1238 /* base block fetch */ 1239 for (i = 0; i < 4; i++) { 1240 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1241 goto out; 1242 if (drm_edid_block_valid(block, 0, print_bad_edid)) 1243 break; 1244 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1245 connector->null_edid_counter++; 1246 goto carp; 1247 } 1248 } 1249 if (i == 4) 1250 goto carp; 1251 1252 /* if there's no extensions, we're done */ 1253 if (block[0x7e] == 0) 1254 return (struct edid *)block; 1255 1256 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1257 if (!new) 1258 goto out; 1259 block = new; 1260 1261 for (j = 1; j <= block[0x7e]; j++) { 1262 for (i = 0; i < 4; i++) { 1263 if (get_edid_block(data, 1264 block + (valid_extensions + 1) * EDID_LENGTH, 1265 j, EDID_LENGTH)) 1266 goto out; 1267 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) { 1268 valid_extensions++; 1269 break; 1270 } 1271 } 1272 1273 if (i == 4 && print_bad_edid) { 1274 dev_warn(connector->dev->dev, 1275 "%s: Ignoring invalid EDID block %d.\n", 1276 connector->name, j); 1277 1278 connector->bad_edid_counter++; 1279 } 1280 } 1281 1282 if (valid_extensions != block[0x7e]) { 1283 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1284 block[0x7e] = valid_extensions; 1285 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1286 if (!new) 1287 goto out; 1288 block = new; 1289 } 1290 1291 return (struct edid *)block; 1292 1293 carp: 1294 if (print_bad_edid) { 1295 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1296 connector->name, j); 1297 } 1298 connector->bad_edid_counter++; 1299 1300 out: 1301 kfree(block); 1302 return NULL; 1303 } 1304 1305 /** 1306 * drm_probe_ddc() - probe DDC presence 1307 * @adapter: I2C adapter to probe 1308 * 1309 * Return: True on success, false on failure. 1310 */ 1311 bool 1312 drm_probe_ddc(struct device *adapter) 1313 { 1314 unsigned char out; 1315 1316 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1317 } 1318 EXPORT_SYMBOL(drm_probe_ddc); 1319 1320 /** 1321 * drm_get_edid - get EDID data, if available 1322 * @connector: connector we're probing 1323 * @adapter: I2C adapter to use for DDC 1324 * 1325 * Poke the given I2C channel to grab EDID data if possible. If found, 1326 * attach it to the connector. 1327 * 1328 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1329 */ 1330 struct edid *drm_get_edid(struct drm_connector *connector, 1331 struct device *adapter) 1332 { 1333 if (!drm_probe_ddc(adapter)) 1334 return NULL; 1335 1336 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1337 } 1338 EXPORT_SYMBOL(drm_get_edid); 1339 1340 /** 1341 * drm_edid_duplicate - duplicate an EDID and the extensions 1342 * @edid: EDID to duplicate 1343 * 1344 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1345 */ 1346 struct edid *drm_edid_duplicate(const struct edid *edid) 1347 { 1348 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1349 } 1350 EXPORT_SYMBOL(drm_edid_duplicate); 1351 1352 /*** EDID parsing ***/ 1353 1354 /** 1355 * edid_vendor - match a string against EDID's obfuscated vendor field 1356 * @edid: EDID to match 1357 * @vendor: vendor string 1358 * 1359 * Returns true if @vendor is in @edid, false otherwise 1360 */ 1361 static bool edid_vendor(struct edid *edid, char *vendor) 1362 { 1363 char edid_vendor[3]; 1364 1365 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1366 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1367 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1368 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1369 1370 return !strncmp(edid_vendor, vendor, 3); 1371 } 1372 1373 /** 1374 * edid_get_quirks - return quirk flags for a given EDID 1375 * @edid: EDID to process 1376 * 1377 * This tells subsequent routines what fixes they need to apply. 1378 */ 1379 static u32 edid_get_quirks(struct edid *edid) 1380 { 1381 struct edid_quirk *quirk; 1382 int i; 1383 1384 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1385 quirk = &edid_quirk_list[i]; 1386 1387 if (edid_vendor(edid, quirk->vendor) && 1388 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1389 return quirk->quirks; 1390 } 1391 1392 return 0; 1393 } 1394 1395 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1396 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1397 1398 /** 1399 * edid_fixup_preferred - set preferred modes based on quirk list 1400 * @connector: has mode list to fix up 1401 * @quirks: quirks list 1402 * 1403 * Walk the mode list for @connector, clearing the preferred status 1404 * on existing modes and setting it anew for the right mode ala @quirks. 1405 */ 1406 static void edid_fixup_preferred(struct drm_connector *connector, 1407 u32 quirks) 1408 { 1409 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1410 int target_refresh = 0; 1411 int cur_vrefresh, preferred_vrefresh; 1412 1413 if (list_empty(&connector->probed_modes)) 1414 return; 1415 1416 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1417 target_refresh = 60; 1418 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1419 target_refresh = 75; 1420 1421 preferred_mode = list_first_entry(&connector->probed_modes, 1422 struct drm_display_mode, head); 1423 1424 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1425 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1426 1427 if (cur_mode == preferred_mode) 1428 continue; 1429 1430 /* Largest mode is preferred */ 1431 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1432 preferred_mode = cur_mode; 1433 1434 cur_vrefresh = cur_mode->vrefresh ? 1435 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1436 preferred_vrefresh = preferred_mode->vrefresh ? 1437 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1438 /* At a given size, try to get closest to target refresh */ 1439 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1440 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1441 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1442 preferred_mode = cur_mode; 1443 } 1444 } 1445 1446 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1447 } 1448 1449 static bool 1450 mode_is_rb(const struct drm_display_mode *mode) 1451 { 1452 return (mode->htotal - mode->hdisplay == 160) && 1453 (mode->hsync_end - mode->hdisplay == 80) && 1454 (mode->hsync_end - mode->hsync_start == 32) && 1455 (mode->vsync_start - mode->vdisplay == 3); 1456 } 1457 1458 /* 1459 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1460 * @dev: Device to duplicate against 1461 * @hsize: Mode width 1462 * @vsize: Mode height 1463 * @fresh: Mode refresh rate 1464 * @rb: Mode reduced-blanking-ness 1465 * 1466 * Walk the DMT mode list looking for a match for the given parameters. 1467 * 1468 * Return: A newly allocated copy of the mode, or NULL if not found. 1469 */ 1470 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1471 int hsize, int vsize, int fresh, 1472 bool rb) 1473 { 1474 int i; 1475 1476 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1477 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1478 if (hsize != ptr->hdisplay) 1479 continue; 1480 if (vsize != ptr->vdisplay) 1481 continue; 1482 if (fresh != drm_mode_vrefresh(ptr)) 1483 continue; 1484 if (rb != mode_is_rb(ptr)) 1485 continue; 1486 1487 return drm_mode_duplicate(dev, ptr); 1488 } 1489 1490 return NULL; 1491 } 1492 EXPORT_SYMBOL(drm_mode_find_dmt); 1493 1494 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1495 1496 static void 1497 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1498 { 1499 int i, n = 0; 1500 u8 d = ext[0x02]; 1501 u8 *det_base = ext + d; 1502 1503 n = (127 - d) / 18; 1504 for (i = 0; i < n; i++) 1505 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1506 } 1507 1508 static void 1509 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1510 { 1511 unsigned int i, n = min((int)ext[0x02], 6); 1512 u8 *det_base = ext + 5; 1513 1514 if (ext[0x01] != 1) 1515 return; /* unknown version */ 1516 1517 for (i = 0; i < n; i++) 1518 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1519 } 1520 1521 static void 1522 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1523 { 1524 int i; 1525 struct edid *edid = (struct edid *)raw_edid; 1526 1527 if (edid == NULL) 1528 return; 1529 1530 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1531 cb(&(edid->detailed_timings[i]), closure); 1532 1533 for (i = 1; i <= raw_edid[0x7e]; i++) { 1534 u8 *ext = raw_edid + (i * EDID_LENGTH); 1535 switch (*ext) { 1536 case CEA_EXT: 1537 cea_for_each_detailed_block(ext, cb, closure); 1538 break; 1539 case VTB_EXT: 1540 vtb_for_each_detailed_block(ext, cb, closure); 1541 break; 1542 default: 1543 break; 1544 } 1545 } 1546 } 1547 1548 static void 1549 is_rb(struct detailed_timing *t, void *data) 1550 { 1551 u8 *r = (u8 *)t; 1552 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1553 if (r[15] & 0x10) 1554 *(bool *)data = true; 1555 } 1556 1557 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1558 static bool 1559 drm_monitor_supports_rb(struct edid *edid) 1560 { 1561 if (edid->revision >= 4) { 1562 bool ret = false; 1563 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1564 return ret; 1565 } 1566 1567 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1568 } 1569 1570 static void 1571 find_gtf2(struct detailed_timing *t, void *data) 1572 { 1573 u8 *r = (u8 *)t; 1574 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1575 *(u8 **)data = r; 1576 } 1577 1578 /* Secondary GTF curve kicks in above some break frequency */ 1579 static int 1580 drm_gtf2_hbreak(struct edid *edid) 1581 { 1582 u8 *r = NULL; 1583 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1584 return r ? (r[12] * 2) : 0; 1585 } 1586 1587 static int 1588 drm_gtf2_2c(struct edid *edid) 1589 { 1590 u8 *r = NULL; 1591 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1592 return r ? r[13] : 0; 1593 } 1594 1595 static int 1596 drm_gtf2_m(struct edid *edid) 1597 { 1598 u8 *r = NULL; 1599 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1600 return r ? (r[15] << 8) + r[14] : 0; 1601 } 1602 1603 static int 1604 drm_gtf2_k(struct edid *edid) 1605 { 1606 u8 *r = NULL; 1607 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1608 return r ? r[16] : 0; 1609 } 1610 1611 static int 1612 drm_gtf2_2j(struct edid *edid) 1613 { 1614 u8 *r = NULL; 1615 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1616 return r ? r[17] : 0; 1617 } 1618 1619 /** 1620 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1621 * @edid: EDID block to scan 1622 */ 1623 static int standard_timing_level(struct edid *edid) 1624 { 1625 if (edid->revision >= 2) { 1626 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1627 return LEVEL_CVT; 1628 if (drm_gtf2_hbreak(edid)) 1629 return LEVEL_GTF2; 1630 return LEVEL_GTF; 1631 } 1632 return LEVEL_DMT; 1633 } 1634 1635 /* 1636 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1637 * monitors fill with ascii space (0x20) instead. 1638 */ 1639 static int 1640 bad_std_timing(u8 a, u8 b) 1641 { 1642 return (a == 0x00 && b == 0x00) || 1643 (a == 0x01 && b == 0x01) || 1644 (a == 0x20 && b == 0x20); 1645 } 1646 1647 /** 1648 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1649 * @connector: connector of for the EDID block 1650 * @edid: EDID block to scan 1651 * @t: standard timing params 1652 * 1653 * Take the standard timing params (in this case width, aspect, and refresh) 1654 * and convert them into a real mode using CVT/GTF/DMT. 1655 */ 1656 static struct drm_display_mode * 1657 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1658 struct std_timing *t) 1659 { 1660 struct drm_device *dev = connector->dev; 1661 struct drm_display_mode *m, *mode = NULL; 1662 int hsize, vsize; 1663 int vrefresh_rate; 1664 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1665 >> EDID_TIMING_ASPECT_SHIFT; 1666 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1667 >> EDID_TIMING_VFREQ_SHIFT; 1668 int timing_level = standard_timing_level(edid); 1669 1670 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1671 return NULL; 1672 1673 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1674 hsize = t->hsize * 8 + 248; 1675 /* vrefresh_rate = vfreq + 60 */ 1676 vrefresh_rate = vfreq + 60; 1677 /* the vdisplay is calculated based on the aspect ratio */ 1678 if (aspect_ratio == 0) { 1679 if (edid->revision < 3) 1680 vsize = hsize; 1681 else 1682 vsize = (hsize * 10) / 16; 1683 } else if (aspect_ratio == 1) 1684 vsize = (hsize * 3) / 4; 1685 else if (aspect_ratio == 2) 1686 vsize = (hsize * 4) / 5; 1687 else 1688 vsize = (hsize * 9) / 16; 1689 1690 /* HDTV hack, part 1 */ 1691 if (vrefresh_rate == 60 && 1692 ((hsize == 1360 && vsize == 765) || 1693 (hsize == 1368 && vsize == 769))) { 1694 hsize = 1366; 1695 vsize = 768; 1696 } 1697 1698 /* 1699 * If this connector already has a mode for this size and refresh 1700 * rate (because it came from detailed or CVT info), use that 1701 * instead. This way we don't have to guess at interlace or 1702 * reduced blanking. 1703 */ 1704 list_for_each_entry(m, &connector->probed_modes, head) 1705 if (m->hdisplay == hsize && m->vdisplay == vsize && 1706 drm_mode_vrefresh(m) == vrefresh_rate) 1707 return NULL; 1708 1709 /* HDTV hack, part 2 */ 1710 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1711 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1712 false); 1713 mode->hdisplay = 1366; 1714 mode->hsync_start = mode->hsync_start - 1; 1715 mode->hsync_end = mode->hsync_end - 1; 1716 return mode; 1717 } 1718 1719 /* check whether it can be found in default mode table */ 1720 if (drm_monitor_supports_rb(edid)) { 1721 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1722 true); 1723 if (mode) 1724 return mode; 1725 } 1726 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1727 if (mode) 1728 return mode; 1729 1730 /* okay, generate it */ 1731 switch (timing_level) { 1732 case LEVEL_DMT: 1733 break; 1734 case LEVEL_GTF: 1735 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1736 break; 1737 case LEVEL_GTF2: 1738 /* 1739 * This is potentially wrong if there's ever a monitor with 1740 * more than one ranges section, each claiming a different 1741 * secondary GTF curve. Please don't do that. 1742 */ 1743 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1744 if (!mode) 1745 return NULL; 1746 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1747 drm_mode_destroy(dev, mode); 1748 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1749 vrefresh_rate, 0, 0, 1750 drm_gtf2_m(edid), 1751 drm_gtf2_2c(edid), 1752 drm_gtf2_k(edid), 1753 drm_gtf2_2j(edid)); 1754 } 1755 break; 1756 case LEVEL_CVT: 1757 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1758 false); 1759 break; 1760 } 1761 return mode; 1762 } 1763 1764 /* 1765 * EDID is delightfully ambiguous about how interlaced modes are to be 1766 * encoded. Our internal representation is of frame height, but some 1767 * HDTV detailed timings are encoded as field height. 1768 * 1769 * The format list here is from CEA, in frame size. Technically we 1770 * should be checking refresh rate too. Whatever. 1771 */ 1772 static void 1773 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1774 struct detailed_pixel_timing *pt) 1775 { 1776 int i; 1777 static const struct { 1778 int w, h; 1779 } cea_interlaced[] = { 1780 { 1920, 1080 }, 1781 { 720, 480 }, 1782 { 1440, 480 }, 1783 { 2880, 480 }, 1784 { 720, 576 }, 1785 { 1440, 576 }, 1786 { 2880, 576 }, 1787 }; 1788 1789 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1790 return; 1791 1792 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1793 if ((mode->hdisplay == cea_interlaced[i].w) && 1794 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1795 mode->vdisplay *= 2; 1796 mode->vsync_start *= 2; 1797 mode->vsync_end *= 2; 1798 mode->vtotal *= 2; 1799 mode->vtotal |= 1; 1800 } 1801 } 1802 1803 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1804 } 1805 1806 /** 1807 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1808 * @dev: DRM device (needed to create new mode) 1809 * @edid: EDID block 1810 * @timing: EDID detailed timing info 1811 * @quirks: quirks to apply 1812 * 1813 * An EDID detailed timing block contains enough info for us to create and 1814 * return a new struct drm_display_mode. 1815 */ 1816 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1817 struct edid *edid, 1818 struct detailed_timing *timing, 1819 u32 quirks) 1820 { 1821 struct drm_display_mode *mode; 1822 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1823 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1824 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1825 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1826 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1827 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1828 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1829 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1830 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1831 1832 /* ignore tiny modes */ 1833 if (hactive < 64 || vactive < 64) 1834 return NULL; 1835 1836 if (pt->misc & DRM_EDID_PT_STEREO) { 1837 DRM_DEBUG_KMS("stereo mode not supported\n"); 1838 return NULL; 1839 } 1840 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1841 DRM_DEBUG_KMS("composite sync not supported\n"); 1842 } 1843 1844 /* it is incorrect if hsync/vsync width is zero */ 1845 if (!hsync_pulse_width || !vsync_pulse_width) { 1846 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1847 "Wrong Hsync/Vsync pulse width\n"); 1848 return NULL; 1849 } 1850 1851 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1852 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1853 if (!mode) 1854 return NULL; 1855 1856 goto set_size; 1857 } 1858 1859 mode = drm_mode_create(dev); 1860 if (!mode) 1861 return NULL; 1862 1863 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1864 timing->pixel_clock = cpu_to_le16(1088); 1865 1866 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1867 1868 mode->hdisplay = hactive; 1869 mode->hsync_start = mode->hdisplay + hsync_offset; 1870 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1871 mode->htotal = mode->hdisplay + hblank; 1872 1873 mode->vdisplay = vactive; 1874 mode->vsync_start = mode->vdisplay + vsync_offset; 1875 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1876 mode->vtotal = mode->vdisplay + vblank; 1877 1878 /* Some EDIDs have bogus h/vtotal values */ 1879 if (mode->hsync_end > mode->htotal) 1880 mode->htotal = mode->hsync_end + 1; 1881 if (mode->vsync_end > mode->vtotal) 1882 mode->vtotal = mode->vsync_end + 1; 1883 1884 drm_mode_do_interlace_quirk(mode, pt); 1885 1886 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1887 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1888 } 1889 1890 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1891 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1892 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1893 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1894 1895 set_size: 1896 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1897 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1898 1899 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1900 mode->width_mm *= 10; 1901 mode->height_mm *= 10; 1902 } 1903 1904 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1905 mode->width_mm = edid->width_cm * 10; 1906 mode->height_mm = edid->height_cm * 10; 1907 } 1908 1909 mode->type = DRM_MODE_TYPE_DRIVER; 1910 mode->vrefresh = drm_mode_vrefresh(mode); 1911 drm_mode_set_name(mode); 1912 1913 return mode; 1914 } 1915 1916 static bool 1917 mode_in_hsync_range(const struct drm_display_mode *mode, 1918 struct edid *edid, u8 *t) 1919 { 1920 int hsync, hmin, hmax; 1921 1922 hmin = t[7]; 1923 if (edid->revision >= 4) 1924 hmin += ((t[4] & 0x04) ? 255 : 0); 1925 hmax = t[8]; 1926 if (edid->revision >= 4) 1927 hmax += ((t[4] & 0x08) ? 255 : 0); 1928 hsync = drm_mode_hsync(mode); 1929 1930 return (hsync <= hmax && hsync >= hmin); 1931 } 1932 1933 static bool 1934 mode_in_vsync_range(const struct drm_display_mode *mode, 1935 struct edid *edid, u8 *t) 1936 { 1937 int vsync, vmin, vmax; 1938 1939 vmin = t[5]; 1940 if (edid->revision >= 4) 1941 vmin += ((t[4] & 0x01) ? 255 : 0); 1942 vmax = t[6]; 1943 if (edid->revision >= 4) 1944 vmax += ((t[4] & 0x02) ? 255 : 0); 1945 vsync = drm_mode_vrefresh(mode); 1946 1947 return (vsync <= vmax && vsync >= vmin); 1948 } 1949 1950 static u32 1951 range_pixel_clock(struct edid *edid, u8 *t) 1952 { 1953 /* unspecified */ 1954 if (t[9] == 0 || t[9] == 255) 1955 return 0; 1956 1957 /* 1.4 with CVT support gives us real precision, yay */ 1958 if (edid->revision >= 4 && t[10] == 0x04) 1959 return (t[9] * 10000) - ((t[12] >> 2) * 250); 1960 1961 /* 1.3 is pathetic, so fuzz up a bit */ 1962 return t[9] * 10000 + 5001; 1963 } 1964 1965 static bool 1966 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 1967 struct detailed_timing *timing) 1968 { 1969 u32 max_clock; 1970 u8 *t = (u8 *)timing; 1971 1972 if (!mode_in_hsync_range(mode, edid, t)) 1973 return false; 1974 1975 if (!mode_in_vsync_range(mode, edid, t)) 1976 return false; 1977 1978 if ((max_clock = range_pixel_clock(edid, t))) 1979 if (mode->clock > max_clock) 1980 return false; 1981 1982 /* 1.4 max horizontal check */ 1983 if (edid->revision >= 4 && t[10] == 0x04) 1984 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 1985 return false; 1986 1987 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 1988 return false; 1989 1990 return true; 1991 } 1992 1993 static bool valid_inferred_mode(const struct drm_connector *connector, 1994 const struct drm_display_mode *mode) 1995 { 1996 struct drm_display_mode *m; 1997 bool ok = false; 1998 1999 list_for_each_entry(m, &connector->probed_modes, head) { 2000 if (mode->hdisplay == m->hdisplay && 2001 mode->vdisplay == m->vdisplay && 2002 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2003 return false; /* duplicated */ 2004 if (mode->hdisplay <= m->hdisplay && 2005 mode->vdisplay <= m->vdisplay) 2006 ok = true; 2007 } 2008 return ok; 2009 } 2010 2011 static int 2012 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2013 struct detailed_timing *timing) 2014 { 2015 int i, modes = 0; 2016 struct drm_display_mode *newmode; 2017 struct drm_device *dev = connector->dev; 2018 2019 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2020 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2021 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2022 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2023 if (newmode) { 2024 drm_mode_probed_add(connector, newmode); 2025 modes++; 2026 } 2027 } 2028 } 2029 2030 return modes; 2031 } 2032 2033 /* fix up 1366x768 mode from 1368x768; 2034 * GFT/CVT can't express 1366 width which isn't dividable by 8 2035 */ 2036 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2037 { 2038 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2039 mode->hdisplay = 1366; 2040 mode->hsync_start--; 2041 mode->hsync_end--; 2042 drm_mode_set_name(mode); 2043 } 2044 } 2045 2046 static int 2047 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2048 struct detailed_timing *timing) 2049 { 2050 int i, modes = 0; 2051 struct drm_display_mode *newmode; 2052 struct drm_device *dev = connector->dev; 2053 2054 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2055 const struct minimode *m = &extra_modes[i]; 2056 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2057 if (!newmode) 2058 return modes; 2059 2060 fixup_mode_1366x768(newmode); 2061 if (!mode_in_range(newmode, edid, timing) || 2062 !valid_inferred_mode(connector, newmode)) { 2063 drm_mode_destroy(dev, newmode); 2064 continue; 2065 } 2066 2067 drm_mode_probed_add(connector, newmode); 2068 modes++; 2069 } 2070 2071 return modes; 2072 } 2073 2074 static int 2075 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2076 struct detailed_timing *timing) 2077 { 2078 int i, modes = 0; 2079 struct drm_display_mode *newmode; 2080 struct drm_device *dev = connector->dev; 2081 bool rb = drm_monitor_supports_rb(edid); 2082 2083 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2084 const struct minimode *m = &extra_modes[i]; 2085 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2086 if (!newmode) 2087 return modes; 2088 2089 fixup_mode_1366x768(newmode); 2090 if (!mode_in_range(newmode, edid, timing) || 2091 !valid_inferred_mode(connector, newmode)) { 2092 drm_mode_destroy(dev, newmode); 2093 continue; 2094 } 2095 2096 drm_mode_probed_add(connector, newmode); 2097 modes++; 2098 } 2099 2100 return modes; 2101 } 2102 2103 static void 2104 do_inferred_modes(struct detailed_timing *timing, void *c) 2105 { 2106 struct detailed_mode_closure *closure = c; 2107 struct detailed_non_pixel *data = &timing->data.other_data; 2108 struct detailed_data_monitor_range *range = &data->data.range; 2109 2110 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2111 return; 2112 2113 closure->modes += drm_dmt_modes_for_range(closure->connector, 2114 closure->edid, 2115 timing); 2116 2117 if (!version_greater(closure->edid, 1, 1)) 2118 return; /* GTF not defined yet */ 2119 2120 switch (range->flags) { 2121 case 0x02: /* secondary gtf, XXX could do more */ 2122 case 0x00: /* default gtf */ 2123 closure->modes += drm_gtf_modes_for_range(closure->connector, 2124 closure->edid, 2125 timing); 2126 break; 2127 case 0x04: /* cvt, only in 1.4+ */ 2128 if (!version_greater(closure->edid, 1, 3)) 2129 break; 2130 2131 closure->modes += drm_cvt_modes_for_range(closure->connector, 2132 closure->edid, 2133 timing); 2134 break; 2135 case 0x01: /* just the ranges, no formula */ 2136 default: 2137 break; 2138 } 2139 } 2140 2141 static int 2142 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2143 { 2144 struct detailed_mode_closure closure = { 2145 .connector = connector, 2146 .edid = edid, 2147 }; 2148 2149 if (version_greater(edid, 1, 0)) 2150 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2151 &closure); 2152 2153 return closure.modes; 2154 } 2155 2156 static int 2157 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2158 { 2159 int i, j, m, modes = 0; 2160 struct drm_display_mode *mode; 2161 u8 *est = ((u8 *)timing) + 5; 2162 2163 for (i = 0; i < 6; i++) { 2164 for (j = 7; j >= 0; j--) { 2165 m = (i * 8) + (7 - j); 2166 if (m >= ARRAY_SIZE(est3_modes)) 2167 break; 2168 if (est[i] & (1 << j)) { 2169 mode = drm_mode_find_dmt(connector->dev, 2170 est3_modes[m].w, 2171 est3_modes[m].h, 2172 est3_modes[m].r, 2173 est3_modes[m].rb); 2174 if (mode) { 2175 drm_mode_probed_add(connector, mode); 2176 modes++; 2177 } 2178 } 2179 } 2180 } 2181 2182 return modes; 2183 } 2184 2185 static void 2186 do_established_modes(struct detailed_timing *timing, void *c) 2187 { 2188 struct detailed_mode_closure *closure = c; 2189 struct detailed_non_pixel *data = &timing->data.other_data; 2190 2191 if (data->type == EDID_DETAIL_EST_TIMINGS) 2192 closure->modes += drm_est3_modes(closure->connector, timing); 2193 } 2194 2195 /** 2196 * add_established_modes - get est. modes from EDID and add them 2197 * @connector: connector to add mode(s) to 2198 * @edid: EDID block to scan 2199 * 2200 * Each EDID block contains a bitmap of the supported "established modes" list 2201 * (defined above). Tease them out and add them to the global modes list. 2202 */ 2203 static int 2204 add_established_modes(struct drm_connector *connector, struct edid *edid) 2205 { 2206 struct drm_device *dev = connector->dev; 2207 unsigned long est_bits = edid->established_timings.t1 | 2208 (edid->established_timings.t2 << 8) | 2209 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2210 int i, modes = 0; 2211 struct detailed_mode_closure closure = { 2212 .connector = connector, 2213 .edid = edid, 2214 }; 2215 2216 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2217 if (est_bits & (1<<i)) { 2218 struct drm_display_mode *newmode; 2219 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2220 if (newmode) { 2221 drm_mode_probed_add(connector, newmode); 2222 modes++; 2223 } 2224 } 2225 } 2226 2227 if (version_greater(edid, 1, 0)) 2228 drm_for_each_detailed_block((u8 *)edid, 2229 do_established_modes, &closure); 2230 2231 return modes + closure.modes; 2232 } 2233 2234 static void 2235 do_standard_modes(struct detailed_timing *timing, void *c) 2236 { 2237 struct detailed_mode_closure *closure = c; 2238 struct detailed_non_pixel *data = &timing->data.other_data; 2239 struct drm_connector *connector = closure->connector; 2240 struct edid *edid = closure->edid; 2241 2242 if (data->type == EDID_DETAIL_STD_MODES) { 2243 int i; 2244 for (i = 0; i < 6; i++) { 2245 struct std_timing *std; 2246 struct drm_display_mode *newmode; 2247 2248 std = &data->data.timings[i]; 2249 newmode = drm_mode_std(connector, edid, std); 2250 if (newmode) { 2251 drm_mode_probed_add(connector, newmode); 2252 closure->modes++; 2253 } 2254 } 2255 } 2256 } 2257 2258 /** 2259 * add_standard_modes - get std. modes from EDID and add them 2260 * @connector: connector to add mode(s) to 2261 * @edid: EDID block to scan 2262 * 2263 * Standard modes can be calculated using the appropriate standard (DMT, 2264 * GTF or CVT. Grab them from @edid and add them to the list. 2265 */ 2266 static int 2267 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2268 { 2269 int i, modes = 0; 2270 struct detailed_mode_closure closure = { 2271 .connector = connector, 2272 .edid = edid, 2273 }; 2274 2275 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2276 struct drm_display_mode *newmode; 2277 2278 newmode = drm_mode_std(connector, edid, 2279 &edid->standard_timings[i]); 2280 if (newmode) { 2281 drm_mode_probed_add(connector, newmode); 2282 modes++; 2283 } 2284 } 2285 2286 if (version_greater(edid, 1, 0)) 2287 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2288 &closure); 2289 2290 /* XXX should also look for standard codes in VTB blocks */ 2291 2292 return modes + closure.modes; 2293 } 2294 2295 static int drm_cvt_modes(struct drm_connector *connector, 2296 struct detailed_timing *timing) 2297 { 2298 int i, j, modes = 0; 2299 struct drm_display_mode *newmode; 2300 struct drm_device *dev = connector->dev; 2301 struct cvt_timing *cvt; 2302 const int rates[] = { 60, 85, 75, 60, 50 }; 2303 const u8 empty[3] = { 0, 0, 0 }; 2304 2305 for (i = 0; i < 4; i++) { 2306 int width = 0, height; 2307 cvt = &(timing->data.other_data.data.cvt[i]); 2308 2309 if (!memcmp(cvt->code, empty, 3)) 2310 continue; 2311 2312 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2313 switch (cvt->code[1] & 0x0c) { 2314 case 0x00: 2315 width = height * 4 / 3; 2316 break; 2317 case 0x04: 2318 width = height * 16 / 9; 2319 break; 2320 case 0x08: 2321 width = height * 16 / 10; 2322 break; 2323 case 0x0c: 2324 width = height * 15 / 9; 2325 break; 2326 } 2327 2328 for (j = 1; j < 5; j++) { 2329 if (cvt->code[2] & (1 << j)) { 2330 newmode = drm_cvt_mode(dev, width, height, 2331 rates[j], j == 0, 2332 false, false); 2333 if (newmode) { 2334 drm_mode_probed_add(connector, newmode); 2335 modes++; 2336 } 2337 } 2338 } 2339 } 2340 2341 return modes; 2342 } 2343 2344 static void 2345 do_cvt_mode(struct detailed_timing *timing, void *c) 2346 { 2347 struct detailed_mode_closure *closure = c; 2348 struct detailed_non_pixel *data = &timing->data.other_data; 2349 2350 if (data->type == EDID_DETAIL_CVT_3BYTE) 2351 closure->modes += drm_cvt_modes(closure->connector, timing); 2352 } 2353 2354 static int 2355 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2356 { 2357 struct detailed_mode_closure closure = { 2358 .connector = connector, 2359 .edid = edid, 2360 }; 2361 2362 if (version_greater(edid, 1, 2)) 2363 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2364 2365 /* XXX should also look for CVT codes in VTB blocks */ 2366 2367 return closure.modes; 2368 } 2369 2370 static void 2371 do_detailed_mode(struct detailed_timing *timing, void *c) 2372 { 2373 struct detailed_mode_closure *closure = c; 2374 struct drm_display_mode *newmode; 2375 2376 if (timing->pixel_clock) { 2377 newmode = drm_mode_detailed(closure->connector->dev, 2378 closure->edid, timing, 2379 closure->quirks); 2380 if (!newmode) 2381 return; 2382 2383 if (closure->preferred) 2384 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2385 2386 drm_mode_probed_add(closure->connector, newmode); 2387 closure->modes++; 2388 closure->preferred = 0; 2389 } 2390 } 2391 2392 /* 2393 * add_detailed_modes - Add modes from detailed timings 2394 * @connector: attached connector 2395 * @edid: EDID block to scan 2396 * @quirks: quirks to apply 2397 */ 2398 static int 2399 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2400 u32 quirks) 2401 { 2402 struct detailed_mode_closure closure = { 2403 .connector = connector, 2404 .edid = edid, 2405 .preferred = 1, 2406 .quirks = quirks, 2407 }; 2408 2409 if (closure.preferred && !version_greater(edid, 1, 3)) 2410 closure.preferred = 2411 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2412 2413 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2414 2415 return closure.modes; 2416 } 2417 2418 #define AUDIO_BLOCK 0x01 2419 #define VIDEO_BLOCK 0x02 2420 #define VENDOR_BLOCK 0x03 2421 #define SPEAKER_BLOCK 0x04 2422 #define VIDEO_CAPABILITY_BLOCK 0x07 2423 #define EDID_BASIC_AUDIO (1 << 6) 2424 #define EDID_CEA_YCRCB444 (1 << 5) 2425 #define EDID_CEA_YCRCB422 (1 << 4) 2426 #define EDID_CEA_VCDB_QS (1 << 6) 2427 2428 /* 2429 * Search EDID for CEA extension block. 2430 */ 2431 static u8 *drm_find_cea_extension(struct edid *edid) 2432 { 2433 u8 *edid_ext = NULL; 2434 int i; 2435 2436 /* No EDID or EDID extensions */ 2437 if (edid == NULL || edid->extensions == 0) 2438 return NULL; 2439 2440 /* Find CEA extension */ 2441 for (i = 0; i < edid->extensions; i++) { 2442 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2443 if (edid_ext[0] == CEA_EXT) 2444 break; 2445 } 2446 2447 if (i == edid->extensions) 2448 return NULL; 2449 2450 return edid_ext; 2451 } 2452 2453 /* 2454 * Calculate the alternate clock for the CEA mode 2455 * (60Hz vs. 59.94Hz etc.) 2456 */ 2457 static unsigned int 2458 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2459 { 2460 unsigned int clock = cea_mode->clock; 2461 2462 if (cea_mode->vrefresh % 6 != 0) 2463 return clock; 2464 2465 /* 2466 * edid_cea_modes contains the 59.94Hz 2467 * variant for 240 and 480 line modes, 2468 * and the 60Hz variant otherwise. 2469 */ 2470 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2471 clock = clock * 1001 / 1000; 2472 else 2473 clock = DIV_ROUND_UP(clock * 1000, 1001); 2474 2475 return clock; 2476 } 2477 2478 /** 2479 * drm_match_cea_mode - look for a CEA mode matching given mode 2480 * @to_match: display mode 2481 * 2482 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2483 * mode. 2484 */ 2485 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2486 { 2487 u8 mode; 2488 2489 if (!to_match->clock) 2490 return 0; 2491 2492 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2493 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2494 unsigned int clock1, clock2; 2495 2496 /* Check both 60Hz and 59.94Hz */ 2497 clock1 = cea_mode->clock; 2498 clock2 = cea_mode_alternate_clock(cea_mode); 2499 2500 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2501 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2502 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2503 return mode + 1; 2504 } 2505 return 0; 2506 } 2507 EXPORT_SYMBOL(drm_match_cea_mode); 2508 2509 /** 2510 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2511 * the input VIC from the CEA mode list 2512 * @video_code: ID given to each of the CEA modes 2513 * 2514 * Returns picture aspect ratio 2515 */ 2516 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2517 { 2518 /* return picture aspect ratio for video_code - 1 to access the 2519 * right array element 2520 */ 2521 return edid_cea_modes[video_code-1].picture_aspect_ratio; 2522 } 2523 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2524 2525 /* 2526 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2527 * specific block). 2528 * 2529 * It's almost like cea_mode_alternate_clock(), we just need to add an 2530 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2531 * one. 2532 */ 2533 static unsigned int 2534 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2535 { 2536 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2537 return hdmi_mode->clock; 2538 2539 return cea_mode_alternate_clock(hdmi_mode); 2540 } 2541 2542 /* 2543 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2544 * @to_match: display mode 2545 * 2546 * An HDMI mode is one defined in the HDMI vendor specific block. 2547 * 2548 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2549 */ 2550 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2551 { 2552 u8 mode; 2553 2554 if (!to_match->clock) 2555 return 0; 2556 2557 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2558 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2559 unsigned int clock1, clock2; 2560 2561 /* Make sure to also match alternate clocks */ 2562 clock1 = hdmi_mode->clock; 2563 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2564 2565 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2566 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2567 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2568 return mode + 1; 2569 } 2570 return 0; 2571 } 2572 2573 static int 2574 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2575 { 2576 struct drm_device *dev = connector->dev; 2577 struct drm_display_mode *mode, *tmp; 2578 LINUX_LIST_HEAD(list); 2579 int modes = 0; 2580 2581 /* Don't add CEA modes if the CEA extension block is missing */ 2582 if (!drm_find_cea_extension(edid)) 2583 return 0; 2584 2585 /* 2586 * Go through all probed modes and create a new mode 2587 * with the alternate clock for certain CEA modes. 2588 */ 2589 list_for_each_entry(mode, &connector->probed_modes, head) { 2590 const struct drm_display_mode *cea_mode = NULL; 2591 struct drm_display_mode *newmode; 2592 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2593 unsigned int clock1, clock2; 2594 2595 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2596 cea_mode = &edid_cea_modes[mode_idx]; 2597 clock2 = cea_mode_alternate_clock(cea_mode); 2598 } else { 2599 mode_idx = drm_match_hdmi_mode(mode) - 1; 2600 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2601 cea_mode = &edid_4k_modes[mode_idx]; 2602 clock2 = hdmi_mode_alternate_clock(cea_mode); 2603 } 2604 } 2605 2606 if (!cea_mode) 2607 continue; 2608 2609 clock1 = cea_mode->clock; 2610 2611 if (clock1 == clock2) 2612 continue; 2613 2614 if (mode->clock != clock1 && mode->clock != clock2) 2615 continue; 2616 2617 newmode = drm_mode_duplicate(dev, cea_mode); 2618 if (!newmode) 2619 continue; 2620 2621 /* Carry over the stereo flags */ 2622 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2623 2624 /* 2625 * The current mode could be either variant. Make 2626 * sure to pick the "other" clock for the new mode. 2627 */ 2628 if (mode->clock != clock1) 2629 newmode->clock = clock1; 2630 else 2631 newmode->clock = clock2; 2632 2633 list_add_tail(&newmode->head, &list); 2634 } 2635 2636 list_for_each_entry_safe(mode, tmp, &list, head) { 2637 list_del(&mode->head); 2638 drm_mode_probed_add(connector, mode); 2639 modes++; 2640 } 2641 2642 return modes; 2643 } 2644 2645 static struct drm_display_mode * 2646 drm_display_mode_from_vic_index(struct drm_connector *connector, 2647 const u8 *video_db, u8 video_len, 2648 u8 video_index) 2649 { 2650 struct drm_device *dev = connector->dev; 2651 struct drm_display_mode *newmode; 2652 u8 cea_mode; 2653 2654 if (video_db == NULL || video_index >= video_len) 2655 return NULL; 2656 2657 /* CEA modes are numbered 1..127 */ 2658 cea_mode = (video_db[video_index] & 127) - 1; 2659 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2660 return NULL; 2661 2662 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2663 if (!newmode) 2664 return NULL; 2665 2666 newmode->vrefresh = 0; 2667 2668 return newmode; 2669 } 2670 2671 static int 2672 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2673 { 2674 int i, modes = 0; 2675 2676 for (i = 0; i < len; i++) { 2677 struct drm_display_mode *mode; 2678 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2679 if (mode) { 2680 drm_mode_probed_add(connector, mode); 2681 modes++; 2682 } 2683 } 2684 2685 return modes; 2686 } 2687 2688 struct stereo_mandatory_mode { 2689 int width, height, vrefresh; 2690 unsigned int flags; 2691 }; 2692 2693 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2694 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2695 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2696 { 1920, 1080, 50, 2697 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2698 { 1920, 1080, 60, 2699 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2700 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2701 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2702 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2703 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2704 }; 2705 2706 static bool 2707 stereo_match_mandatory(const struct drm_display_mode *mode, 2708 const struct stereo_mandatory_mode *stereo_mode) 2709 { 2710 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2711 2712 return mode->hdisplay == stereo_mode->width && 2713 mode->vdisplay == stereo_mode->height && 2714 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2715 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2716 } 2717 2718 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2719 { 2720 struct drm_device *dev = connector->dev; 2721 struct drm_display_mode *mode; 2722 struct list_head stereo_modes; 2723 int modes = 0, i; 2724 2725 INIT_LIST_HEAD(&stereo_modes); 2726 2727 list_for_each_entry(mode, &connector->probed_modes, head) { 2728 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2729 const struct stereo_mandatory_mode *mandatory; 2730 struct drm_display_mode *new_mode; 2731 2732 if (!stereo_match_mandatory(mode, 2733 &stereo_mandatory_modes[i])) 2734 continue; 2735 2736 mandatory = &stereo_mandatory_modes[i]; 2737 new_mode = drm_mode_duplicate(dev, mode); 2738 if (!new_mode) 2739 continue; 2740 2741 new_mode->flags |= mandatory->flags; 2742 list_add_tail(&new_mode->head, &stereo_modes); 2743 modes++; 2744 } 2745 } 2746 2747 list_splice_tail(&stereo_modes, &connector->probed_modes); 2748 2749 return modes; 2750 } 2751 2752 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2753 { 2754 struct drm_device *dev = connector->dev; 2755 struct drm_display_mode *newmode; 2756 2757 vic--; /* VICs start at 1 */ 2758 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2759 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2760 return 0; 2761 } 2762 2763 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2764 if (!newmode) 2765 return 0; 2766 2767 drm_mode_probed_add(connector, newmode); 2768 2769 return 1; 2770 } 2771 2772 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2773 const u8 *video_db, u8 video_len, u8 video_index) 2774 { 2775 struct drm_display_mode *newmode; 2776 int modes = 0; 2777 2778 if (structure & (1 << 0)) { 2779 newmode = drm_display_mode_from_vic_index(connector, video_db, 2780 video_len, 2781 video_index); 2782 if (newmode) { 2783 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2784 drm_mode_probed_add(connector, newmode); 2785 modes++; 2786 } 2787 } 2788 if (structure & (1 << 6)) { 2789 newmode = drm_display_mode_from_vic_index(connector, video_db, 2790 video_len, 2791 video_index); 2792 if (newmode) { 2793 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2794 drm_mode_probed_add(connector, newmode); 2795 modes++; 2796 } 2797 } 2798 if (structure & (1 << 8)) { 2799 newmode = drm_display_mode_from_vic_index(connector, video_db, 2800 video_len, 2801 video_index); 2802 if (newmode) { 2803 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2804 drm_mode_probed_add(connector, newmode); 2805 modes++; 2806 } 2807 } 2808 2809 return modes; 2810 } 2811 2812 /* 2813 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2814 * @connector: connector corresponding to the HDMI sink 2815 * @db: start of the CEA vendor specific block 2816 * @len: length of the CEA block payload, ie. one can access up to db[len] 2817 * 2818 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2819 * also adds the stereo 3d modes when applicable. 2820 */ 2821 static int 2822 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2823 const u8 *video_db, u8 video_len) 2824 { 2825 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2826 u8 vic_len, hdmi_3d_len = 0; 2827 u16 mask; 2828 u16 structure_all; 2829 2830 if (len < 8) 2831 goto out; 2832 2833 /* no HDMI_Video_Present */ 2834 if (!(db[8] & (1 << 5))) 2835 goto out; 2836 2837 /* Latency_Fields_Present */ 2838 if (db[8] & (1 << 7)) 2839 offset += 2; 2840 2841 /* I_Latency_Fields_Present */ 2842 if (db[8] & (1 << 6)) 2843 offset += 2; 2844 2845 /* the declared length is not long enough for the 2 first bytes 2846 * of additional video format capabilities */ 2847 if (len < (8 + offset + 2)) 2848 goto out; 2849 2850 /* 3D_Present */ 2851 offset++; 2852 if (db[8 + offset] & (1 << 7)) { 2853 modes += add_hdmi_mandatory_stereo_modes(connector); 2854 2855 /* 3D_Multi_present */ 2856 multi_present = (db[8 + offset] & 0x60) >> 5; 2857 } 2858 2859 offset++; 2860 vic_len = db[8 + offset] >> 5; 2861 hdmi_3d_len = db[8 + offset] & 0x1f; 2862 2863 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2864 u8 vic; 2865 2866 vic = db[9 + offset + i]; 2867 modes += add_hdmi_mode(connector, vic); 2868 } 2869 offset += 1 + vic_len; 2870 2871 if (multi_present == 1) 2872 multi_len = 2; 2873 else if (multi_present == 2) 2874 multi_len = 4; 2875 else 2876 multi_len = 0; 2877 2878 if (len < (8 + offset + hdmi_3d_len - 1)) 2879 goto out; 2880 2881 if (hdmi_3d_len < multi_len) 2882 goto out; 2883 2884 if (multi_present == 1 || multi_present == 2) { 2885 /* 3D_Structure_ALL */ 2886 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2887 2888 /* check if 3D_MASK is present */ 2889 if (multi_present == 2) 2890 mask = (db[10 + offset] << 8) | db[11 + offset]; 2891 else 2892 mask = 0xffff; 2893 2894 for (i = 0; i < 16; i++) { 2895 if (mask & (1 << i)) 2896 modes += add_3d_struct_modes(connector, 2897 structure_all, 2898 video_db, 2899 video_len, i); 2900 } 2901 } 2902 2903 offset += multi_len; 2904 2905 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2906 int vic_index; 2907 struct drm_display_mode *newmode = NULL; 2908 unsigned int newflag = 0; 2909 bool detail_present; 2910 2911 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2912 2913 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2914 break; 2915 2916 /* 2D_VIC_order_X */ 2917 vic_index = db[8 + offset + i] >> 4; 2918 2919 /* 3D_Structure_X */ 2920 switch (db[8 + offset + i] & 0x0f) { 2921 case 0: 2922 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2923 break; 2924 case 6: 2925 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2926 break; 2927 case 8: 2928 /* 3D_Detail_X */ 2929 if ((db[9 + offset + i] >> 4) == 1) 2930 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2931 break; 2932 } 2933 2934 if (newflag != 0) { 2935 newmode = drm_display_mode_from_vic_index(connector, 2936 video_db, 2937 video_len, 2938 vic_index); 2939 2940 if (newmode) { 2941 newmode->flags |= newflag; 2942 drm_mode_probed_add(connector, newmode); 2943 modes++; 2944 } 2945 } 2946 2947 if (detail_present) 2948 i++; 2949 } 2950 2951 out: 2952 return modes; 2953 } 2954 2955 static int 2956 cea_db_payload_len(const u8 *db) 2957 { 2958 return db[0] & 0x1f; 2959 } 2960 2961 static int 2962 cea_db_tag(const u8 *db) 2963 { 2964 return db[0] >> 5; 2965 } 2966 2967 static int 2968 cea_revision(const u8 *cea) 2969 { 2970 return cea[1]; 2971 } 2972 2973 static int 2974 cea_db_offsets(const u8 *cea, int *start, int *end) 2975 { 2976 /* Data block offset in CEA extension block */ 2977 *start = 4; 2978 *end = cea[2]; 2979 if (*end == 0) 2980 *end = 127; 2981 if (*end < 4 || *end > 127) 2982 return -ERANGE; 2983 return 0; 2984 } 2985 2986 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2987 { 2988 int hdmi_id; 2989 2990 if (cea_db_tag(db) != VENDOR_BLOCK) 2991 return false; 2992 2993 if (cea_db_payload_len(db) < 5) 2994 return false; 2995 2996 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2997 2998 return hdmi_id == HDMI_IEEE_OUI; 2999 } 3000 3001 #define for_each_cea_db(cea, i, start, end) \ 3002 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3003 3004 static int 3005 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3006 { 3007 const u8 *cea = drm_find_cea_extension(edid); 3008 const u8 *db, *hdmi = NULL, *video = NULL; 3009 u8 dbl, hdmi_len, video_len = 0; 3010 int modes = 0; 3011 3012 if (cea && cea_revision(cea) >= 3) { 3013 int i, start, end; 3014 3015 if (cea_db_offsets(cea, &start, &end)) 3016 return 0; 3017 3018 for_each_cea_db(cea, i, start, end) { 3019 db = &cea[i]; 3020 dbl = cea_db_payload_len(db); 3021 3022 if (cea_db_tag(db) == VIDEO_BLOCK) { 3023 video = db + 1; 3024 video_len = dbl; 3025 modes += do_cea_modes(connector, video, dbl); 3026 } 3027 else if (cea_db_is_hdmi_vsdb(db)) { 3028 hdmi = db; 3029 hdmi_len = dbl; 3030 } 3031 } 3032 } 3033 3034 /* 3035 * We parse the HDMI VSDB after having added the cea modes as we will 3036 * be patching their flags when the sink supports stereo 3D. 3037 */ 3038 if (hdmi) 3039 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3040 video_len); 3041 3042 return modes; 3043 } 3044 3045 static void 3046 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3047 { 3048 u8 len = cea_db_payload_len(db); 3049 3050 if (len >= 6) { 3051 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3052 connector->dvi_dual = db[6] & 1; 3053 } 3054 if (len >= 7) 3055 connector->max_tmds_clock = db[7] * 5; 3056 if (len >= 8) { 3057 connector->latency_present[0] = db[8] >> 7; 3058 connector->latency_present[1] = (db[8] >> 6) & 1; 3059 } 3060 if (len >= 9) 3061 connector->video_latency[0] = db[9]; 3062 if (len >= 10) 3063 connector->audio_latency[0] = db[10]; 3064 if (len >= 11) 3065 connector->video_latency[1] = db[11]; 3066 if (len >= 12) 3067 connector->audio_latency[1] = db[12]; 3068 3069 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3070 "max TMDS clock %d, " 3071 "latency present %d %d, " 3072 "video latency %d %d, " 3073 "audio latency %d %d\n", 3074 connector->dvi_dual, 3075 connector->max_tmds_clock, 3076 (int) connector->latency_present[0], 3077 (int) connector->latency_present[1], 3078 connector->video_latency[0], 3079 connector->video_latency[1], 3080 connector->audio_latency[0], 3081 connector->audio_latency[1]); 3082 } 3083 3084 static void 3085 monitor_name(struct detailed_timing *t, void *data) 3086 { 3087 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3088 *(u8 **)data = t->data.other_data.data.str.str; 3089 } 3090 3091 /** 3092 * drm_edid_to_eld - build ELD from EDID 3093 * @connector: connector corresponding to the HDMI/DP sink 3094 * @edid: EDID to parse 3095 * 3096 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3097 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3098 * fill in. 3099 */ 3100 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3101 { 3102 uint8_t *eld = connector->eld; 3103 u8 *cea; 3104 u8 *name; 3105 u8 *db; 3106 int sad_count = 0; 3107 int mnl; 3108 int dbl; 3109 3110 memset(eld, 0, sizeof(connector->eld)); 3111 3112 cea = drm_find_cea_extension(edid); 3113 if (!cea) { 3114 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3115 return; 3116 } 3117 3118 name = NULL; 3119 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3120 for (mnl = 0; name && mnl < 13; mnl++) { 3121 if (name[mnl] == 0x0a) 3122 break; 3123 eld[20 + mnl] = name[mnl]; 3124 } 3125 eld[4] = (cea[1] << 5) | mnl; 3126 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3127 3128 eld[0] = 2 << 3; /* ELD version: 2 */ 3129 3130 eld[16] = edid->mfg_id[0]; 3131 eld[17] = edid->mfg_id[1]; 3132 eld[18] = edid->prod_code[0]; 3133 eld[19] = edid->prod_code[1]; 3134 3135 if (cea_revision(cea) >= 3) { 3136 int i, start, end; 3137 3138 if (cea_db_offsets(cea, &start, &end)) { 3139 start = 0; 3140 end = 0; 3141 } 3142 3143 for_each_cea_db(cea, i, start, end) { 3144 db = &cea[i]; 3145 dbl = cea_db_payload_len(db); 3146 3147 switch (cea_db_tag(db)) { 3148 case AUDIO_BLOCK: 3149 /* Audio Data Block, contains SADs */ 3150 sad_count = dbl / 3; 3151 if (dbl >= 1) 3152 memcpy(eld + 20 + mnl, &db[1], dbl); 3153 break; 3154 case SPEAKER_BLOCK: 3155 /* Speaker Allocation Data Block */ 3156 if (dbl >= 1) 3157 eld[7] = db[1]; 3158 break; 3159 case VENDOR_BLOCK: 3160 /* HDMI Vendor-Specific Data Block */ 3161 if (cea_db_is_hdmi_vsdb(db)) 3162 parse_hdmi_vsdb(connector, db); 3163 break; 3164 default: 3165 break; 3166 } 3167 } 3168 } 3169 eld[5] |= sad_count << 4; 3170 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; 3171 3172 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); 3173 } 3174 EXPORT_SYMBOL(drm_edid_to_eld); 3175 3176 /** 3177 * drm_edid_to_sad - extracts SADs from EDID 3178 * @edid: EDID to parse 3179 * @sads: pointer that will be set to the extracted SADs 3180 * 3181 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3182 * 3183 * Note: The returned pointer needs to be freed using kfree(). 3184 * 3185 * Return: The number of found SADs or negative number on error. 3186 */ 3187 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3188 { 3189 int count = 0; 3190 int i, start, end, dbl; 3191 u8 *cea; 3192 3193 cea = drm_find_cea_extension(edid); 3194 if (!cea) { 3195 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3196 return -ENOENT; 3197 } 3198 3199 if (cea_revision(cea) < 3) { 3200 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3201 return -EOPNOTSUPP; 3202 } 3203 3204 if (cea_db_offsets(cea, &start, &end)) { 3205 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3206 return -EPROTO; 3207 } 3208 3209 for_each_cea_db(cea, i, start, end) { 3210 u8 *db = &cea[i]; 3211 3212 if (cea_db_tag(db) == AUDIO_BLOCK) { 3213 int j; 3214 dbl = cea_db_payload_len(db); 3215 3216 count = dbl / 3; /* SAD is 3B */ 3217 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3218 if (!*sads) 3219 return -ENOMEM; 3220 for (j = 0; j < count; j++) { 3221 u8 *sad = &db[1 + j * 3]; 3222 3223 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3224 (*sads)[j].channels = sad[0] & 0x7; 3225 (*sads)[j].freq = sad[1] & 0x7F; 3226 (*sads)[j].byte2 = sad[2]; 3227 } 3228 break; 3229 } 3230 } 3231 3232 return count; 3233 } 3234 EXPORT_SYMBOL(drm_edid_to_sad); 3235 3236 /** 3237 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3238 * @edid: EDID to parse 3239 * @sadb: pointer to the speaker block 3240 * 3241 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3242 * 3243 * Note: The returned pointer needs to be freed using kfree(). 3244 * 3245 * Return: The number of found Speaker Allocation Blocks or negative number on 3246 * error. 3247 */ 3248 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3249 { 3250 int count = 0; 3251 int i, start, end, dbl; 3252 const u8 *cea; 3253 3254 cea = drm_find_cea_extension(edid); 3255 if (!cea) { 3256 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3257 return -ENOENT; 3258 } 3259 3260 if (cea_revision(cea) < 3) { 3261 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3262 return -ENOTSUPP; 3263 } 3264 3265 if (cea_db_offsets(cea, &start, &end)) { 3266 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3267 return -EPROTO; 3268 } 3269 3270 for_each_cea_db(cea, i, start, end) { 3271 const u8 *db = &cea[i]; 3272 3273 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3274 dbl = cea_db_payload_len(db); 3275 3276 /* Speaker Allocation Data Block */ 3277 if (dbl == 3) { 3278 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3279 if (!*sadb) 3280 return -ENOMEM; 3281 count = dbl; 3282 break; 3283 } 3284 } 3285 } 3286 3287 return count; 3288 } 3289 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3290 3291 /** 3292 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3293 * @connector: connector associated with the HDMI/DP sink 3294 * @mode: the display mode 3295 * 3296 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3297 * the sink doesn't support audio or video. 3298 */ 3299 int drm_av_sync_delay(struct drm_connector *connector, 3300 struct drm_display_mode *mode) 3301 { 3302 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3303 int a, v; 3304 3305 if (!connector->latency_present[0]) 3306 return 0; 3307 if (!connector->latency_present[1]) 3308 i = 0; 3309 3310 a = connector->audio_latency[i]; 3311 v = connector->video_latency[i]; 3312 3313 /* 3314 * HDMI/DP sink doesn't support audio or video? 3315 */ 3316 if (a == 255 || v == 255) 3317 return 0; 3318 3319 /* 3320 * Convert raw EDID values to millisecond. 3321 * Treat unknown latency as 0ms. 3322 */ 3323 if (a) 3324 a = min(2 * (a - 1), 500); 3325 if (v) 3326 v = min(2 * (v - 1), 500); 3327 3328 return max(v - a, 0); 3329 } 3330 EXPORT_SYMBOL(drm_av_sync_delay); 3331 3332 /** 3333 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3334 * @encoder: the encoder just changed display mode 3335 * @mode: the adjusted display mode 3336 * 3337 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3338 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3339 * 3340 * Return: The connector associated with the first HDMI/DP sink that has ELD 3341 * attached to it. 3342 */ 3343 struct drm_connector *drm_select_eld(struct drm_encoder *encoder, 3344 struct drm_display_mode *mode) 3345 { 3346 struct drm_connector *connector; 3347 struct drm_device *dev = encoder->dev; 3348 3349 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3350 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3351 3352 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 3353 if (connector->encoder == encoder && connector->eld[0]) 3354 return connector; 3355 3356 return NULL; 3357 } 3358 EXPORT_SYMBOL(drm_select_eld); 3359 3360 /** 3361 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3362 * @edid: monitor EDID information 3363 * 3364 * Parse the CEA extension according to CEA-861-B. 3365 * 3366 * Return: True if the monitor is HDMI, false if not or unknown. 3367 */ 3368 bool drm_detect_hdmi_monitor(struct edid *edid) 3369 { 3370 u8 *edid_ext; 3371 int i; 3372 int start_offset, end_offset; 3373 3374 edid_ext = drm_find_cea_extension(edid); 3375 if (!edid_ext) 3376 return false; 3377 3378 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3379 return false; 3380 3381 /* 3382 * Because HDMI identifier is in Vendor Specific Block, 3383 * search it from all data blocks of CEA extension. 3384 */ 3385 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3386 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3387 return true; 3388 } 3389 3390 return false; 3391 } 3392 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3393 3394 /** 3395 * drm_detect_monitor_audio - check monitor audio capability 3396 * @edid: EDID block to scan 3397 * 3398 * Monitor should have CEA extension block. 3399 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3400 * audio' only. If there is any audio extension block and supported 3401 * audio format, assume at least 'basic audio' support, even if 'basic 3402 * audio' is not defined in EDID. 3403 * 3404 * Return: True if the monitor supports audio, false otherwise. 3405 */ 3406 bool drm_detect_monitor_audio(struct edid *edid) 3407 { 3408 u8 *edid_ext; 3409 int i, j; 3410 bool has_audio = false; 3411 int start_offset, end_offset; 3412 3413 edid_ext = drm_find_cea_extension(edid); 3414 if (!edid_ext) 3415 goto end; 3416 3417 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3418 3419 if (has_audio) { 3420 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3421 goto end; 3422 } 3423 3424 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3425 goto end; 3426 3427 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3428 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3429 has_audio = true; 3430 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3431 DRM_DEBUG_KMS("CEA audio format %d\n", 3432 (edid_ext[i + j] >> 3) & 0xf); 3433 goto end; 3434 } 3435 } 3436 end: 3437 return has_audio; 3438 } 3439 EXPORT_SYMBOL(drm_detect_monitor_audio); 3440 3441 /** 3442 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3443 * @edid: EDID block to scan 3444 * 3445 * Check whether the monitor reports the RGB quantization range selection 3446 * as supported. The AVI infoframe can then be used to inform the monitor 3447 * which quantization range (full or limited) is used. 3448 * 3449 * Return: True if the RGB quantization range is selectable, false otherwise. 3450 */ 3451 bool drm_rgb_quant_range_selectable(struct edid *edid) 3452 { 3453 u8 *edid_ext; 3454 int i, start, end; 3455 3456 edid_ext = drm_find_cea_extension(edid); 3457 if (!edid_ext) 3458 return false; 3459 3460 if (cea_db_offsets(edid_ext, &start, &end)) 3461 return false; 3462 3463 for_each_cea_db(edid_ext, i, start, end) { 3464 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3465 cea_db_payload_len(&edid_ext[i]) == 2) { 3466 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3467 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3468 } 3469 } 3470 3471 return false; 3472 } 3473 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3474 3475 /** 3476 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3477 * hdmi deep color modes and update drm_display_info if so. 3478 * @edid: monitor EDID information 3479 * @info: Updated with maximum supported deep color bpc and color format 3480 * if deep color supported. 3481 * @connector: DRM connector, used only for debug output 3482 * 3483 * Parse the CEA extension according to CEA-861-B. 3484 * Return true if HDMI deep color supported, false if not or unknown. 3485 */ 3486 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3487 struct drm_display_info *info, 3488 struct drm_connector *connector) 3489 { 3490 u8 *edid_ext, *hdmi; 3491 int i; 3492 int start_offset, end_offset; 3493 unsigned int dc_bpc = 0; 3494 3495 edid_ext = drm_find_cea_extension(edid); 3496 if (!edid_ext) 3497 return false; 3498 3499 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3500 return false; 3501 3502 /* 3503 * Because HDMI identifier is in Vendor Specific Block, 3504 * search it from all data blocks of CEA extension. 3505 */ 3506 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3507 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3508 /* HDMI supports at least 8 bpc */ 3509 info->bpc = 8; 3510 3511 hdmi = &edid_ext[i]; 3512 if (cea_db_payload_len(hdmi) < 6) 3513 return false; 3514 3515 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3516 dc_bpc = 10; 3517 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3518 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3519 connector->name); 3520 } 3521 3522 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3523 dc_bpc = 12; 3524 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3525 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3526 connector->name); 3527 } 3528 3529 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3530 dc_bpc = 16; 3531 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3532 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3533 connector->name); 3534 } 3535 3536 if (dc_bpc > 0) { 3537 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3538 connector->name, dc_bpc); 3539 info->bpc = dc_bpc; 3540 3541 /* 3542 * Deep color support mandates RGB444 support for all video 3543 * modes and forbids YCRCB422 support for all video modes per 3544 * HDMI 1.3 spec. 3545 */ 3546 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3547 3548 /* YCRCB444 is optional according to spec. */ 3549 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3550 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3551 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3552 connector->name); 3553 } 3554 3555 /* 3556 * Spec says that if any deep color mode is supported at all, 3557 * then deep color 36 bit must be supported. 3558 */ 3559 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3560 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3561 connector->name); 3562 } 3563 3564 return true; 3565 } 3566 else { 3567 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3568 connector->name); 3569 } 3570 } 3571 } 3572 3573 return false; 3574 } 3575 3576 /** 3577 * drm_add_display_info - pull display info out if present 3578 * @edid: EDID data 3579 * @info: display info (attached to connector) 3580 * @connector: connector whose edid is used to build display info 3581 * 3582 * Grab any available display info and stuff it into the drm_display_info 3583 * structure that's part of the connector. Useful for tracking bpp and 3584 * color spaces. 3585 */ 3586 static void drm_add_display_info(struct edid *edid, 3587 struct drm_display_info *info, 3588 struct drm_connector *connector) 3589 { 3590 u8 *edid_ext; 3591 3592 info->width_mm = edid->width_cm * 10; 3593 info->height_mm = edid->height_cm * 10; 3594 3595 /* driver figures it out in this case */ 3596 info->bpc = 0; 3597 info->color_formats = 0; 3598 3599 if (edid->revision < 3) 3600 return; 3601 3602 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3603 return; 3604 3605 /* Get data from CEA blocks if present */ 3606 edid_ext = drm_find_cea_extension(edid); 3607 if (edid_ext) { 3608 info->cea_rev = edid_ext[1]; 3609 3610 /* The existence of a CEA block should imply RGB support */ 3611 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3612 if (edid_ext[3] & EDID_CEA_YCRCB444) 3613 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3614 if (edid_ext[3] & EDID_CEA_YCRCB422) 3615 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3616 } 3617 3618 /* HDMI deep color modes supported? Assign to info, if so */ 3619 drm_assign_hdmi_deep_color_info(edid, info, connector); 3620 3621 /* Only defined for 1.4 with digital displays */ 3622 if (edid->revision < 4) 3623 return; 3624 3625 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3626 case DRM_EDID_DIGITAL_DEPTH_6: 3627 info->bpc = 6; 3628 break; 3629 case DRM_EDID_DIGITAL_DEPTH_8: 3630 info->bpc = 8; 3631 break; 3632 case DRM_EDID_DIGITAL_DEPTH_10: 3633 info->bpc = 10; 3634 break; 3635 case DRM_EDID_DIGITAL_DEPTH_12: 3636 info->bpc = 12; 3637 break; 3638 case DRM_EDID_DIGITAL_DEPTH_14: 3639 info->bpc = 14; 3640 break; 3641 case DRM_EDID_DIGITAL_DEPTH_16: 3642 info->bpc = 16; 3643 break; 3644 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3645 default: 3646 info->bpc = 0; 3647 break; 3648 } 3649 3650 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3651 connector->name, info->bpc); 3652 3653 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3654 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3655 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3656 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3657 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3658 } 3659 3660 /** 3661 * drm_add_edid_modes - add modes from EDID data, if available 3662 * @connector: connector we're probing 3663 * @edid: EDID data 3664 * 3665 * Add the specified modes to the connector's mode list. 3666 * 3667 * Return: The number of modes added or 0 if we couldn't find any. 3668 */ 3669 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3670 { 3671 int num_modes = 0; 3672 u32 quirks; 3673 3674 if (edid == NULL) { 3675 return 0; 3676 } 3677 if (!drm_edid_is_valid(edid)) { 3678 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3679 connector->name); 3680 return 0; 3681 } 3682 3683 quirks = edid_get_quirks(edid); 3684 3685 /* 3686 * EDID spec says modes should be preferred in this order: 3687 * - preferred detailed mode 3688 * - other detailed modes from base block 3689 * - detailed modes from extension blocks 3690 * - CVT 3-byte code modes 3691 * - standard timing codes 3692 * - established timing codes 3693 * - modes inferred from GTF or CVT range information 3694 * 3695 * We get this pretty much right. 3696 * 3697 * XXX order for additional mode types in extension blocks? 3698 */ 3699 num_modes += add_detailed_modes(connector, edid, quirks); 3700 num_modes += add_cvt_modes(connector, edid); 3701 num_modes += add_standard_modes(connector, edid); 3702 num_modes += add_established_modes(connector, edid); 3703 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3704 num_modes += add_inferred_modes(connector, edid); 3705 num_modes += add_cea_modes(connector, edid); 3706 num_modes += add_alternate_cea_modes(connector, edid); 3707 3708 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3709 edid_fixup_preferred(connector, quirks); 3710 3711 drm_add_display_info(edid, &connector->display_info, connector); 3712 3713 if (quirks & EDID_QUIRK_FORCE_8BPC) 3714 connector->display_info.bpc = 8; 3715 3716 if (quirks & EDID_QUIRK_FORCE_12BPC) 3717 connector->display_info.bpc = 12; 3718 3719 return num_modes; 3720 } 3721 EXPORT_SYMBOL(drm_add_edid_modes); 3722 3723 /** 3724 * drm_add_modes_noedid - add modes for the connectors without EDID 3725 * @connector: connector we're probing 3726 * @hdisplay: the horizontal display limit 3727 * @vdisplay: the vertical display limit 3728 * 3729 * Add the specified modes to the connector's mode list. Only when the 3730 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3731 * 3732 * Return: The number of modes added or 0 if we couldn't find any. 3733 */ 3734 int drm_add_modes_noedid(struct drm_connector *connector, 3735 int hdisplay, int vdisplay) 3736 { 3737 int i, count, num_modes = 0; 3738 struct drm_display_mode *mode; 3739 struct drm_device *dev = connector->dev; 3740 3741 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); 3742 if (hdisplay < 0) 3743 hdisplay = 0; 3744 if (vdisplay < 0) 3745 vdisplay = 0; 3746 3747 for (i = 0; i < count; i++) { 3748 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3749 if (hdisplay && vdisplay) { 3750 /* 3751 * Only when two are valid, they will be used to check 3752 * whether the mode should be added to the mode list of 3753 * the connector. 3754 */ 3755 if (ptr->hdisplay > hdisplay || 3756 ptr->vdisplay > vdisplay) 3757 continue; 3758 } 3759 if (drm_mode_vrefresh(ptr) > 61) 3760 continue; 3761 mode = drm_mode_duplicate(dev, ptr); 3762 if (mode) { 3763 drm_mode_probed_add(connector, mode); 3764 num_modes++; 3765 } 3766 } 3767 return num_modes; 3768 } 3769 EXPORT_SYMBOL(drm_add_modes_noedid); 3770 3771 /** 3772 * drm_set_preferred_mode - Sets the preferred mode of a connector 3773 * @connector: connector whose mode list should be processed 3774 * @hpref: horizontal resolution of preferred mode 3775 * @vpref: vertical resolution of preferred mode 3776 * 3777 * Marks a mode as preferred if it matches the resolution specified by @hpref 3778 * and @vpref. 3779 */ 3780 void drm_set_preferred_mode(struct drm_connector *connector, 3781 int hpref, int vpref) 3782 { 3783 struct drm_display_mode *mode; 3784 3785 list_for_each_entry(mode, &connector->probed_modes, head) { 3786 if (mode->hdisplay == hpref && 3787 mode->vdisplay == vpref) 3788 mode->type |= DRM_MODE_TYPE_PREFERRED; 3789 } 3790 } 3791 EXPORT_SYMBOL(drm_set_preferred_mode); 3792 3793 /** 3794 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3795 * data from a DRM display mode 3796 * @frame: HDMI AVI infoframe 3797 * @mode: DRM display mode 3798 * 3799 * Return: 0 on success or a negative error code on failure. 3800 */ 3801 int 3802 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3803 const struct drm_display_mode *mode) 3804 { 3805 int err; 3806 3807 if (!frame || !mode) 3808 return -EINVAL; 3809 3810 err = hdmi_avi_infoframe_init(frame); 3811 if (err < 0) 3812 return err; 3813 3814 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3815 frame->pixel_repeat = 1; 3816 3817 frame->video_code = drm_match_cea_mode(mode); 3818 3819 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3820 3821 /* 3822 * Populate picture aspect ratio from either 3823 * user input (if specified) or from the CEA mode list. 3824 */ 3825 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 3826 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 3827 frame->picture_aspect = mode->picture_aspect_ratio; 3828 else if (frame->video_code > 0) 3829 frame->picture_aspect = drm_get_cea_aspect_ratio( 3830 frame->video_code); 3831 3832 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3833 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 3834 3835 return 0; 3836 } 3837 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3838 3839 static enum hdmi_3d_structure 3840 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 3841 { 3842 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 3843 3844 switch (layout) { 3845 case DRM_MODE_FLAG_3D_FRAME_PACKING: 3846 return HDMI_3D_STRUCTURE_FRAME_PACKING; 3847 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 3848 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 3849 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 3850 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 3851 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 3852 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 3853 case DRM_MODE_FLAG_3D_L_DEPTH: 3854 return HDMI_3D_STRUCTURE_L_DEPTH; 3855 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 3856 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 3857 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 3858 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 3859 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 3860 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 3861 default: 3862 return HDMI_3D_STRUCTURE_INVALID; 3863 } 3864 } 3865 3866 /** 3867 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 3868 * data from a DRM display mode 3869 * @frame: HDMI vendor infoframe 3870 * @mode: DRM display mode 3871 * 3872 * Note that there's is a need to send HDMI vendor infoframes only when using a 3873 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 3874 * function will return -EINVAL, error that can be safely ignored. 3875 * 3876 * Return: 0 on success or a negative error code on failure. 3877 */ 3878 int 3879 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 3880 const struct drm_display_mode *mode) 3881 { 3882 int err; 3883 u32 s3d_flags; 3884 u8 vic; 3885 3886 if (!frame || !mode) 3887 return -EINVAL; 3888 3889 vic = drm_match_hdmi_mode(mode); 3890 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 3891 3892 if (!vic && !s3d_flags) 3893 return -EINVAL; 3894 3895 if (vic && s3d_flags) 3896 return -EINVAL; 3897 3898 err = hdmi_vendor_infoframe_init(frame); 3899 if (err < 0) 3900 return err; 3901 3902 if (vic) 3903 frame->vic = vic; 3904 else 3905 frame->s3d_struct = s3d_structure_from_display_mode(mode); 3906 3907 return 0; 3908 } 3909 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 3910