1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #ifdef __DragonFly__ 32 #include "opt_drm.h" 33 #endif 34 35 #include <linux/kernel.h> 36 #include <linux/slab.h> 37 #include <linux/hdmi.h> 38 #include <linux/i2c.h> 39 #include <linux/module.h> 40 #include <linux/vga_switcheroo.h> 41 #include <drm/drmP.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_displayid.h> 44 45 #define version_greater(edid, maj, min) \ 46 (((edid)->version > (maj)) || \ 47 ((edid)->version == (maj) && (edid)->revision > (min))) 48 49 #define EDID_EST_TIMINGS 16 50 #define EDID_STD_TIMINGS 8 51 #define EDID_DETAILED_TIMINGS 4 52 53 /* 54 * EDID blocks out in the wild have a variety of bugs, try to collect 55 * them here (note that userspace may work around broken monitors first, 56 * but fixes should make their way here so that the kernel "just works" 57 * on as many displays as possible). 58 */ 59 60 /* First detailed mode wrong, use largest 60Hz mode */ 61 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 62 /* Reported 135MHz pixel clock is too high, needs adjustment */ 63 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 64 /* Prefer the largest mode at 75 Hz */ 65 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 66 /* Detail timing is in cm not mm */ 67 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 68 /* Detailed timing descriptors have bogus size values, so just take the 69 * maximum size and use that. 70 */ 71 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 72 /* Monitor forgot to set the first detailed is preferred bit. */ 73 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 /* Force 12bpc */ 81 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 82 /* Force 6bpc */ 83 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 84 85 struct detailed_mode_closure { 86 struct drm_connector *connector; 87 struct edid *edid; 88 bool preferred; 89 u32 quirks; 90 int modes; 91 }; 92 93 #define LEVEL_DMT 0 94 #define LEVEL_GTF 1 95 #define LEVEL_GTF2 2 96 #define LEVEL_CVT 3 97 98 static struct edid_quirk { 99 char vendor[4]; 100 int product_id; 101 u32 quirks; 102 } edid_quirk_list[] = { 103 /* Acer AL1706 */ 104 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 105 /* Acer F51 */ 106 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 107 /* Unknown Acer */ 108 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 109 110 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 111 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 112 113 /* Belinea 10 15 55 */ 114 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 115 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 116 117 /* Envision Peripherals, Inc. EN-7100e */ 118 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 119 /* Envision EN2028 */ 120 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 121 122 /* Funai Electronics PM36B */ 123 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 124 EDID_QUIRK_DETAILED_IN_CM }, 125 126 /* LG Philips LCD LP154W01-A5 */ 127 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 128 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 129 130 /* Philips 107p5 CRT */ 131 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 132 133 /* Proview AY765C */ 134 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 135 136 /* Samsung SyncMaster 205BW. Note: irony */ 137 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 138 /* Samsung SyncMaster 22[5-6]BW */ 139 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 140 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 141 142 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 143 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 144 145 /* ViewSonic VA2026w */ 146 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 147 148 /* Medion MD 30217 PG */ 149 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 150 151 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 152 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 153 }; 154 155 /* 156 * Autogenerated from the DMT spec. 157 * This table is copied from xfree86/modes/xf86EdidModes.c. 158 */ 159 static const struct drm_display_mode drm_dmt_modes[] = { 160 /* 0x01 - 640x350@85Hz */ 161 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 162 736, 832, 0, 350, 382, 385, 445, 0, 163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 164 /* 0x02 - 640x400@85Hz */ 165 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 166 736, 832, 0, 400, 401, 404, 445, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 168 /* 0x03 - 720x400@85Hz */ 169 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 170 828, 936, 0, 400, 401, 404, 446, 0, 171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 172 /* 0x04 - 640x480@60Hz */ 173 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 174 752, 800, 0, 480, 490, 492, 525, 0, 175 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 176 /* 0x05 - 640x480@72Hz */ 177 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 178 704, 832, 0, 480, 489, 492, 520, 0, 179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 180 /* 0x06 - 640x480@75Hz */ 181 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 182 720, 840, 0, 480, 481, 484, 500, 0, 183 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 184 /* 0x07 - 640x480@85Hz */ 185 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 186 752, 832, 0, 480, 481, 484, 509, 0, 187 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 188 /* 0x08 - 800x600@56Hz */ 189 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 190 896, 1024, 0, 600, 601, 603, 625, 0, 191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 192 /* 0x09 - 800x600@60Hz */ 193 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 194 968, 1056, 0, 600, 601, 605, 628, 0, 195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 196 /* 0x0a - 800x600@72Hz */ 197 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 198 976, 1040, 0, 600, 637, 643, 666, 0, 199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 200 /* 0x0b - 800x600@75Hz */ 201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 202 896, 1056, 0, 600, 601, 604, 625, 0, 203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 204 /* 0x0c - 800x600@85Hz */ 205 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 206 896, 1048, 0, 600, 601, 604, 631, 0, 207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 208 /* 0x0d - 800x600@120Hz RB */ 209 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 210 880, 960, 0, 600, 603, 607, 636, 0, 211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 212 /* 0x0e - 848x480@60Hz */ 213 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 214 976, 1088, 0, 480, 486, 494, 517, 0, 215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 216 /* 0x0f - 1024x768@43Hz, interlace */ 217 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 218 1208, 1264, 0, 768, 768, 776, 817, 0, 219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 220 DRM_MODE_FLAG_INTERLACE) }, 221 /* 0x10 - 1024x768@60Hz */ 222 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 223 1184, 1344, 0, 768, 771, 777, 806, 0, 224 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 225 /* 0x11 - 1024x768@70Hz */ 226 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 227 1184, 1328, 0, 768, 771, 777, 806, 0, 228 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 0x12 - 1024x768@75Hz */ 230 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 231 1136, 1312, 0, 768, 769, 772, 800, 0, 232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x13 - 1024x768@85Hz */ 234 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 235 1168, 1376, 0, 768, 769, 772, 808, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x14 - 1024x768@120Hz RB */ 238 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 239 1104, 1184, 0, 768, 771, 775, 813, 0, 240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 241 /* 0x15 - 1152x864@75Hz */ 242 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 243 1344, 1600, 0, 864, 865, 868, 900, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 245 /* 0x55 - 1280x720@60Hz */ 246 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 247 1430, 1650, 0, 720, 725, 730, 750, 0, 248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x16 - 1280x768@60Hz RB */ 250 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 251 1360, 1440, 0, 768, 771, 778, 790, 0, 252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 253 /* 0x17 - 1280x768@60Hz */ 254 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 255 1472, 1664, 0, 768, 771, 778, 798, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x18 - 1280x768@75Hz */ 258 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 259 1488, 1696, 0, 768, 771, 778, 805, 0, 260 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 261 /* 0x19 - 1280x768@85Hz */ 262 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 263 1496, 1712, 0, 768, 771, 778, 809, 0, 264 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 265 /* 0x1a - 1280x768@120Hz RB */ 266 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 267 1360, 1440, 0, 768, 771, 778, 813, 0, 268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 269 /* 0x1b - 1280x800@60Hz RB */ 270 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 271 1360, 1440, 0, 800, 803, 809, 823, 0, 272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 273 /* 0x1c - 1280x800@60Hz */ 274 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 275 1480, 1680, 0, 800, 803, 809, 831, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x1d - 1280x800@75Hz */ 278 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 279 1488, 1696, 0, 800, 803, 809, 838, 0, 280 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 281 /* 0x1e - 1280x800@85Hz */ 282 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 283 1496, 1712, 0, 800, 803, 809, 843, 0, 284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 0x1f - 1280x800@120Hz RB */ 286 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 287 1360, 1440, 0, 800, 803, 809, 847, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 289 /* 0x20 - 1280x960@60Hz */ 290 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 291 1488, 1800, 0, 960, 961, 964, 1000, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 293 /* 0x21 - 1280x960@85Hz */ 294 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 295 1504, 1728, 0, 960, 961, 964, 1011, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x22 - 1280x960@120Hz RB */ 298 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 299 1360, 1440, 0, 960, 963, 967, 1017, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 301 /* 0x23 - 1280x1024@60Hz */ 302 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 303 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 0x24 - 1280x1024@75Hz */ 306 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 307 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 309 /* 0x25 - 1280x1024@85Hz */ 310 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 311 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x26 - 1280x1024@120Hz RB */ 314 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 315 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 0x27 - 1360x768@60Hz */ 318 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 319 1536, 1792, 0, 768, 771, 777, 795, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x28 - 1360x768@120Hz RB */ 322 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 323 1440, 1520, 0, 768, 771, 776, 813, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 325 /* 0x51 - 1366x768@60Hz */ 326 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 327 1579, 1792, 0, 768, 771, 774, 798, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x56 - 1366x768@60Hz */ 330 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 331 1436, 1500, 0, 768, 769, 772, 800, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x29 - 1400x1050@60Hz RB */ 334 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 335 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x2a - 1400x1050@60Hz */ 338 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 339 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x2b - 1400x1050@75Hz */ 342 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 343 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 344 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x2c - 1400x1050@85Hz */ 346 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 347 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x2d - 1400x1050@120Hz RB */ 350 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 351 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 353 /* 0x2e - 1440x900@60Hz RB */ 354 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 355 1520, 1600, 0, 900, 903, 909, 926, 0, 356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 357 /* 0x2f - 1440x900@60Hz */ 358 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 359 1672, 1904, 0, 900, 903, 909, 934, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x30 - 1440x900@75Hz */ 362 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 363 1688, 1936, 0, 900, 903, 909, 942, 0, 364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 365 /* 0x31 - 1440x900@85Hz */ 366 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 367 1696, 1952, 0, 900, 903, 909, 948, 0, 368 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x32 - 1440x900@120Hz RB */ 370 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 371 1520, 1600, 0, 900, 903, 909, 953, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 373 /* 0x53 - 1600x900@60Hz */ 374 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 375 1704, 1800, 0, 900, 901, 904, 1000, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x33 - 1600x1200@60Hz */ 378 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 379 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x34 - 1600x1200@65Hz */ 382 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 383 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x35 - 1600x1200@70Hz */ 386 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 387 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x36 - 1600x1200@75Hz */ 390 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 391 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x37 - 1600x1200@85Hz */ 394 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 395 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 397 /* 0x38 - 1600x1200@120Hz RB */ 398 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 399 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 401 /* 0x39 - 1680x1050@60Hz RB */ 402 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 403 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 405 /* 0x3a - 1680x1050@60Hz */ 406 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 407 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x3b - 1680x1050@75Hz */ 410 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 411 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x3c - 1680x1050@85Hz */ 414 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 415 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x3d - 1680x1050@120Hz RB */ 418 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 419 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x3e - 1792x1344@60Hz */ 422 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 423 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 424 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x3f - 1792x1344@75Hz */ 426 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 427 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x40 - 1792x1344@120Hz RB */ 430 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 431 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 433 /* 0x41 - 1856x1392@60Hz */ 434 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 435 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 437 /* 0x42 - 1856x1392@75Hz */ 438 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 439 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 0x43 - 1856x1392@120Hz RB */ 442 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 443 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 445 /* 0x52 - 1920x1080@60Hz */ 446 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 447 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 449 /* 0x44 - 1920x1200@60Hz RB */ 450 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 451 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 453 /* 0x45 - 1920x1200@60Hz */ 454 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 455 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x46 - 1920x1200@75Hz */ 458 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 459 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x47 - 1920x1200@85Hz */ 462 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 463 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x48 - 1920x1200@120Hz RB */ 466 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 467 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 469 /* 0x49 - 1920x1440@60Hz */ 470 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 471 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x4a - 1920x1440@75Hz */ 474 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 475 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x4b - 1920x1440@120Hz RB */ 478 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 479 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 481 /* 0x54 - 2048x1152@60Hz */ 482 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 483 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 485 /* 0x4c - 2560x1600@60Hz RB */ 486 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 487 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 489 /* 0x4d - 2560x1600@60Hz */ 490 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 491 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x4e - 2560x1600@75Hz */ 494 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 495 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 497 /* 0x4f - 2560x1600@85Hz */ 498 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 499 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 501 /* 0x50 - 2560x1600@120Hz RB */ 502 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 503 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 505 /* 0x57 - 4096x2160@60Hz RB */ 506 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 507 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 509 /* 0x58 - 4096x2160@59.94Hz RB */ 510 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 511 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 513 }; 514 515 /* 516 * These more or less come from the DMT spec. The 720x400 modes are 517 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 518 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 519 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 520 * mode. 521 * 522 * The DMT modes have been fact-checked; the rest are mild guesses. 523 */ 524 static const struct drm_display_mode edid_est_modes[] = { 525 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 526 968, 1056, 0, 600, 601, 605, 628, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 528 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 529 896, 1024, 0, 600, 601, 603, 625, 0, 530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 531 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 532 720, 840, 0, 480, 481, 484, 500, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 534 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 535 704, 832, 0, 480, 489, 492, 520, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 537 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 538 768, 864, 0, 480, 483, 486, 525, 0, 539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 540 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 541 752, 800, 0, 480, 490, 492, 525, 0, 542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 543 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 544 846, 900, 0, 400, 421, 423, 449, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 546 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 547 846, 900, 0, 400, 412, 414, 449, 0, 548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 549 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 550 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 552 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 553 1136, 1312, 0, 768, 769, 772, 800, 0, 554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 555 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 556 1184, 1328, 0, 768, 771, 777, 806, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 558 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 559 1184, 1344, 0, 768, 771, 777, 806, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 561 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 562 1208, 1264, 0, 768, 768, 776, 817, 0, 563 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 564 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 565 928, 1152, 0, 624, 625, 628, 667, 0, 566 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 567 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 568 896, 1056, 0, 600, 601, 604, 625, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 570 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 571 976, 1040, 0, 600, 637, 643, 666, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 573 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 574 1344, 1600, 0, 864, 865, 868, 900, 0, 575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 576 }; 577 578 struct minimode { 579 short w; 580 short h; 581 short r; 582 short rb; 583 }; 584 585 static const struct minimode est3_modes[] = { 586 /* byte 6 */ 587 { 640, 350, 85, 0 }, 588 { 640, 400, 85, 0 }, 589 { 720, 400, 85, 0 }, 590 { 640, 480, 85, 0 }, 591 { 848, 480, 60, 0 }, 592 { 800, 600, 85, 0 }, 593 { 1024, 768, 85, 0 }, 594 { 1152, 864, 75, 0 }, 595 /* byte 7 */ 596 { 1280, 768, 60, 1 }, 597 { 1280, 768, 60, 0 }, 598 { 1280, 768, 75, 0 }, 599 { 1280, 768, 85, 0 }, 600 { 1280, 960, 60, 0 }, 601 { 1280, 960, 85, 0 }, 602 { 1280, 1024, 60, 0 }, 603 { 1280, 1024, 85, 0 }, 604 /* byte 8 */ 605 { 1360, 768, 60, 0 }, 606 { 1440, 900, 60, 1 }, 607 { 1440, 900, 60, 0 }, 608 { 1440, 900, 75, 0 }, 609 { 1440, 900, 85, 0 }, 610 { 1400, 1050, 60, 1 }, 611 { 1400, 1050, 60, 0 }, 612 { 1400, 1050, 75, 0 }, 613 /* byte 9 */ 614 { 1400, 1050, 85, 0 }, 615 { 1680, 1050, 60, 1 }, 616 { 1680, 1050, 60, 0 }, 617 { 1680, 1050, 75, 0 }, 618 { 1680, 1050, 85, 0 }, 619 { 1600, 1200, 60, 0 }, 620 { 1600, 1200, 65, 0 }, 621 { 1600, 1200, 70, 0 }, 622 /* byte 10 */ 623 { 1600, 1200, 75, 0 }, 624 { 1600, 1200, 85, 0 }, 625 { 1792, 1344, 60, 0 }, 626 { 1792, 1344, 75, 0 }, 627 { 1856, 1392, 60, 0 }, 628 { 1856, 1392, 75, 0 }, 629 { 1920, 1200, 60, 1 }, 630 { 1920, 1200, 60, 0 }, 631 /* byte 11 */ 632 { 1920, 1200, 75, 0 }, 633 { 1920, 1200, 85, 0 }, 634 { 1920, 1440, 60, 0 }, 635 { 1920, 1440, 75, 0 }, 636 }; 637 638 static const struct minimode extra_modes[] = { 639 { 1024, 576, 60, 0 }, 640 { 1366, 768, 60, 0 }, 641 { 1600, 900, 60, 0 }, 642 { 1680, 945, 60, 0 }, 643 { 1920, 1080, 60, 0 }, 644 { 2048, 1152, 60, 0 }, 645 { 2048, 1536, 60, 0 }, 646 }; 647 648 /* 649 * Probably taken from CEA-861 spec. 650 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 651 * 652 * Index using the VIC. 653 */ 654 static const struct drm_display_mode edid_cea_modes[] = { 655 /* 0 - dummy, VICs start at 1 */ 656 { }, 657 /* 1 - 640x480@60Hz */ 658 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 659 752, 800, 0, 480, 490, 492, 525, 0, 660 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 661 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 662 /* 2 - 720x480@60Hz */ 663 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 664 798, 858, 0, 480, 489, 495, 525, 0, 665 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 666 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 667 /* 3 - 720x480@60Hz */ 668 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 669 798, 858, 0, 480, 489, 495, 525, 0, 670 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 671 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 672 /* 4 - 1280x720@60Hz */ 673 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 674 1430, 1650, 0, 720, 725, 730, 750, 0, 675 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 677 /* 5 - 1920x1080i@60Hz */ 678 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 679 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 680 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 681 DRM_MODE_FLAG_INTERLACE), 682 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 683 /* 6 - 720(1440)x480i@60Hz */ 684 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 685 801, 858, 0, 480, 488, 494, 525, 0, 686 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 687 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 688 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 689 /* 7 - 720(1440)x480i@60Hz */ 690 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 691 801, 858, 0, 480, 488, 494, 525, 0, 692 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 693 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 694 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 695 /* 8 - 720(1440)x240@60Hz */ 696 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 697 801, 858, 0, 240, 244, 247, 262, 0, 698 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 699 DRM_MODE_FLAG_DBLCLK), 700 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 701 /* 9 - 720(1440)x240@60Hz */ 702 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 703 801, 858, 0, 240, 244, 247, 262, 0, 704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 705 DRM_MODE_FLAG_DBLCLK), 706 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 707 /* 10 - 2880x480i@60Hz */ 708 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 709 3204, 3432, 0, 480, 488, 494, 525, 0, 710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 711 DRM_MODE_FLAG_INTERLACE), 712 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 713 /* 11 - 2880x480i@60Hz */ 714 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 715 3204, 3432, 0, 480, 488, 494, 525, 0, 716 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 717 DRM_MODE_FLAG_INTERLACE), 718 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 719 /* 12 - 2880x240@60Hz */ 720 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 721 3204, 3432, 0, 240, 244, 247, 262, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 723 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 724 /* 13 - 2880x240@60Hz */ 725 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 726 3204, 3432, 0, 240, 244, 247, 262, 0, 727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 729 /* 14 - 1440x480@60Hz */ 730 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 731 1596, 1716, 0, 480, 489, 495, 525, 0, 732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 734 /* 15 - 1440x480@60Hz */ 735 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 736 1596, 1716, 0, 480, 489, 495, 525, 0, 737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 739 /* 16 - 1920x1080@60Hz */ 740 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 741 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 744 /* 17 - 720x576@50Hz */ 745 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 746 796, 864, 0, 576, 581, 586, 625, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 748 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 749 /* 18 - 720x576@50Hz */ 750 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 751 796, 864, 0, 576, 581, 586, 625, 0, 752 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 753 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 754 /* 19 - 1280x720@50Hz */ 755 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 756 1760, 1980, 0, 720, 725, 730, 750, 0, 757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 758 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 759 /* 20 - 1920x1080i@50Hz */ 760 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 761 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 762 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 763 DRM_MODE_FLAG_INTERLACE), 764 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 765 /* 21 - 720(1440)x576i@50Hz */ 766 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 767 795, 864, 0, 576, 580, 586, 625, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 769 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 770 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 771 /* 22 - 720(1440)x576i@50Hz */ 772 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 773 795, 864, 0, 576, 580, 586, 625, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 775 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 776 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 777 /* 23 - 720(1440)x288@50Hz */ 778 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 779 795, 864, 0, 288, 290, 293, 312, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 781 DRM_MODE_FLAG_DBLCLK), 782 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 783 /* 24 - 720(1440)x288@50Hz */ 784 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 785 795, 864, 0, 288, 290, 293, 312, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 787 DRM_MODE_FLAG_DBLCLK), 788 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 789 /* 25 - 2880x576i@50Hz */ 790 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 791 3180, 3456, 0, 576, 580, 586, 625, 0, 792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 793 DRM_MODE_FLAG_INTERLACE), 794 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 795 /* 26 - 2880x576i@50Hz */ 796 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 797 3180, 3456, 0, 576, 580, 586, 625, 0, 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 799 DRM_MODE_FLAG_INTERLACE), 800 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 801 /* 27 - 2880x288@50Hz */ 802 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 803 3180, 3456, 0, 288, 290, 293, 312, 0, 804 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 805 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 806 /* 28 - 2880x288@50Hz */ 807 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 808 3180, 3456, 0, 288, 290, 293, 312, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 811 /* 29 - 1440x576@50Hz */ 812 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 813 1592, 1728, 0, 576, 581, 586, 625, 0, 814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 816 /* 30 - 1440x576@50Hz */ 817 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 818 1592, 1728, 0, 576, 581, 586, 625, 0, 819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 31 - 1920x1080@50Hz */ 822 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 823 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 826 /* 32 - 1920x1080@24Hz */ 827 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 828 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 830 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 831 /* 33 - 1920x1080@25Hz */ 832 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 833 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 835 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 836 /* 34 - 1920x1080@30Hz */ 837 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 838 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 840 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 841 /* 35 - 2880x480@60Hz */ 842 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 843 3192, 3432, 0, 480, 489, 495, 525, 0, 844 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 845 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 846 /* 36 - 2880x480@60Hz */ 847 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 848 3192, 3432, 0, 480, 489, 495, 525, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 850 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 37 - 2880x576@50Hz */ 852 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 853 3184, 3456, 0, 576, 581, 586, 625, 0, 854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 855 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 856 /* 38 - 2880x576@50Hz */ 857 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 858 3184, 3456, 0, 576, 581, 586, 625, 0, 859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 860 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 861 /* 39 - 1920x1080i@50Hz */ 862 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 863 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 865 DRM_MODE_FLAG_INTERLACE), 866 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 867 /* 40 - 1920x1080i@100Hz */ 868 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 869 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 871 DRM_MODE_FLAG_INTERLACE), 872 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 873 /* 41 - 1280x720@100Hz */ 874 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 875 1760, 1980, 0, 720, 725, 730, 750, 0, 876 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 877 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 878 /* 42 - 720x576@100Hz */ 879 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 880 796, 864, 0, 576, 581, 586, 625, 0, 881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 882 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 883 /* 43 - 720x576@100Hz */ 884 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 885 796, 864, 0, 576, 581, 586, 625, 0, 886 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 887 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 44 - 720(1440)x576i@100Hz */ 889 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 890 795, 864, 0, 576, 580, 586, 625, 0, 891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 892 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 893 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 894 /* 45 - 720(1440)x576i@100Hz */ 895 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 896 795, 864, 0, 576, 580, 586, 625, 0, 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 898 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 899 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 900 /* 46 - 1920x1080i@120Hz */ 901 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 902 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 904 DRM_MODE_FLAG_INTERLACE), 905 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 906 /* 47 - 1280x720@120Hz */ 907 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 908 1430, 1650, 0, 720, 725, 730, 750, 0, 909 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 910 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 911 /* 48 - 720x480@120Hz */ 912 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 913 798, 858, 0, 480, 489, 495, 525, 0, 914 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 915 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 916 /* 49 - 720x480@120Hz */ 917 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 918 798, 858, 0, 480, 489, 495, 525, 0, 919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 920 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 50 - 720(1440)x480i@120Hz */ 922 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 923 801, 858, 0, 480, 488, 494, 525, 0, 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 925 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 926 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 927 /* 51 - 720(1440)x480i@120Hz */ 928 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 929 801, 858, 0, 480, 488, 494, 525, 0, 930 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 931 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 932 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 933 /* 52 - 720x576@200Hz */ 934 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 935 796, 864, 0, 576, 581, 586, 625, 0, 936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 937 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 938 /* 53 - 720x576@200Hz */ 939 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 940 796, 864, 0, 576, 581, 586, 625, 0, 941 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 942 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 943 /* 54 - 720(1440)x576i@200Hz */ 944 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 945 795, 864, 0, 576, 580, 586, 625, 0, 946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 947 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 948 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 949 /* 55 - 720(1440)x576i@200Hz */ 950 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 951 795, 864, 0, 576, 580, 586, 625, 0, 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 954 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 955 /* 56 - 720x480@240Hz */ 956 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 957 798, 858, 0, 480, 489, 495, 525, 0, 958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 959 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 960 /* 57 - 720x480@240Hz */ 961 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 962 798, 858, 0, 480, 489, 495, 525, 0, 963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 964 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 965 /* 58 - 720(1440)x480i@240 */ 966 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 967 801, 858, 0, 480, 488, 494, 525, 0, 968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 969 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 970 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 971 /* 59 - 720(1440)x480i@240 */ 972 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 973 801, 858, 0, 480, 488, 494, 525, 0, 974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 975 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 976 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 977 /* 60 - 1280x720@24Hz */ 978 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 979 3080, 3300, 0, 720, 725, 730, 750, 0, 980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 981 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 982 /* 61 - 1280x720@25Hz */ 983 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 984 3740, 3960, 0, 720, 725, 730, 750, 0, 985 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 986 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 987 /* 62 - 1280x720@30Hz */ 988 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 989 3080, 3300, 0, 720, 725, 730, 750, 0, 990 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 991 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 992 /* 63 - 1920x1080@120Hz */ 993 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 994 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 995 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 996 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 997 /* 64 - 1920x1080@100Hz */ 998 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 999 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1001 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1002 }; 1003 1004 /* 1005 * HDMI 1.4 4k modes. Index using the VIC. 1006 */ 1007 static const struct drm_display_mode edid_4k_modes[] = { 1008 /* 0 - dummy, VICs start at 1 */ 1009 { }, 1010 /* 1 - 3840x2160@30Hz */ 1011 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1012 3840, 4016, 4104, 4400, 0, 1013 2160, 2168, 2178, 2250, 0, 1014 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1015 .vrefresh = 30, }, 1016 /* 2 - 3840x2160@25Hz */ 1017 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1018 3840, 4896, 4984, 5280, 0, 1019 2160, 2168, 2178, 2250, 0, 1020 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1021 .vrefresh = 25, }, 1022 /* 3 - 3840x2160@24Hz */ 1023 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1024 3840, 5116, 5204, 5500, 0, 1025 2160, 2168, 2178, 2250, 0, 1026 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1027 .vrefresh = 24, }, 1028 /* 4 - 4096x2160@24Hz (SMPTE) */ 1029 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1030 4096, 5116, 5204, 5500, 0, 1031 2160, 2168, 2178, 2250, 0, 1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1033 .vrefresh = 24, }, 1034 }; 1035 1036 /*** DDC fetch and block validation ***/ 1037 1038 static const u8 edid_header[] = { 1039 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1040 }; 1041 1042 /** 1043 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1044 * @raw_edid: pointer to raw base EDID block 1045 * 1046 * Sanity check the header of the base EDID block. 1047 * 1048 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1049 */ 1050 int drm_edid_header_is_valid(const u8 *raw_edid) 1051 { 1052 int i, score = 0; 1053 1054 for (i = 0; i < sizeof(edid_header); i++) 1055 if (raw_edid[i] == edid_header[i]) 1056 score++; 1057 1058 return score; 1059 } 1060 EXPORT_SYMBOL(drm_edid_header_is_valid); 1061 1062 static int edid_fixup __read_mostly = 6; 1063 module_param_named(edid_fixup, edid_fixup, int, 0400); 1064 MODULE_PARM_DESC(edid_fixup, 1065 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1066 1067 static void drm_get_displayid(struct drm_connector *connector, 1068 struct edid *edid); 1069 1070 static int drm_edid_block_checksum(const u8 *raw_edid) 1071 { 1072 int i; 1073 u8 csum = 0; 1074 for (i = 0; i < EDID_LENGTH; i++) 1075 csum += raw_edid[i]; 1076 1077 return csum; 1078 } 1079 1080 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1081 { 1082 if (memchr_inv(in_edid, 0, length)) 1083 return false; 1084 1085 return true; 1086 } 1087 1088 /** 1089 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1090 * @raw_edid: pointer to raw EDID block 1091 * @block: type of block to validate (0 for base, extension otherwise) 1092 * @print_bad_edid: if true, dump bad EDID blocks to the console 1093 * @edid_corrupt: if true, the header or checksum is invalid 1094 * 1095 * Validate a base or extension EDID block and optionally dump bad blocks to 1096 * the console. 1097 * 1098 * Return: True if the block is valid, false otherwise. 1099 */ 1100 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1101 bool *edid_corrupt) 1102 { 1103 u8 csum; 1104 struct edid *edid = (struct edid *)raw_edid; 1105 1106 if (WARN_ON(!raw_edid)) 1107 return false; 1108 1109 if (edid_fixup > 8 || edid_fixup < 0) 1110 edid_fixup = 6; 1111 1112 if (block == 0) { 1113 int score = drm_edid_header_is_valid(raw_edid); 1114 if (score == 8) { 1115 if (edid_corrupt) 1116 *edid_corrupt = false; 1117 } else if (score >= edid_fixup) { 1118 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1119 * The corrupt flag needs to be set here otherwise, the 1120 * fix-up code here will correct the problem, the 1121 * checksum is correct and the test fails 1122 */ 1123 if (edid_corrupt) 1124 *edid_corrupt = true; 1125 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1126 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1127 } else { 1128 if (edid_corrupt) 1129 *edid_corrupt = true; 1130 goto bad; 1131 } 1132 } 1133 1134 csum = drm_edid_block_checksum(raw_edid); 1135 if (csum) { 1136 if (print_bad_edid) { 1137 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1138 } 1139 1140 if (edid_corrupt) 1141 *edid_corrupt = true; 1142 1143 /* allow CEA to slide through, switches mangle this */ 1144 if (raw_edid[0] != 0x02) 1145 goto bad; 1146 } 1147 1148 /* per-block-type checks */ 1149 switch (raw_edid[0]) { 1150 case 0: /* base */ 1151 if (edid->version != 1) { 1152 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1153 goto bad; 1154 } 1155 1156 if (edid->revision > 4) 1157 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1158 break; 1159 1160 default: 1161 break; 1162 } 1163 1164 return true; 1165 1166 bad: 1167 if (print_bad_edid) { 1168 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1169 printk(KERN_ERR "EDID block is all zeroes\n"); 1170 } else { 1171 printk(KERN_ERR "Raw EDID:\n"); 1172 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1173 raw_edid, EDID_LENGTH, false); 1174 } 1175 } 1176 return false; 1177 } 1178 EXPORT_SYMBOL(drm_edid_block_valid); 1179 1180 /** 1181 * drm_edid_is_valid - sanity check EDID data 1182 * @edid: EDID data 1183 * 1184 * Sanity-check an entire EDID record (including extensions) 1185 * 1186 * Return: True if the EDID data is valid, false otherwise. 1187 */ 1188 bool drm_edid_is_valid(struct edid *edid) 1189 { 1190 int i; 1191 u8 *raw = (u8 *)edid; 1192 1193 if (!edid) 1194 return false; 1195 1196 for (i = 0; i <= edid->extensions; i++) 1197 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1198 return false; 1199 1200 return true; 1201 } 1202 EXPORT_SYMBOL(drm_edid_is_valid); 1203 1204 #define DDC_SEGMENT_ADDR 0x30 1205 /** 1206 * drm_do_probe_ddc_edid() - get EDID information via I2C 1207 * @data: I2C device adapter 1208 * @buf: EDID data buffer to be filled 1209 * @block: 128 byte EDID block to start fetching from 1210 * @len: EDID data buffer length to fetch 1211 * 1212 * Try to fetch EDID information by calling I2C driver functions. 1213 * 1214 * Return: 0 on success or -1 on failure. 1215 */ 1216 static int 1217 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1218 { 1219 struct i2c_adapter *adapter = data; 1220 unsigned char start = block * EDID_LENGTH; 1221 unsigned char segment = block >> 1; 1222 unsigned char xfers = segment ? 3 : 2; 1223 int ret, retries = 5; 1224 1225 /* 1226 * The core I2C driver will automatically retry the transfer if the 1227 * adapter reports EAGAIN. However, we find that bit-banging transfers 1228 * are susceptible to errors under a heavily loaded machine and 1229 * generate spurious NAKs and timeouts. Retrying the transfer 1230 * of the individual block a few times seems to overcome this. 1231 */ 1232 do { 1233 struct i2c_msg msgs[] = { 1234 { 1235 .addr = DDC_SEGMENT_ADDR, 1236 .flags = 0, 1237 .len = 1, 1238 .buf = &segment, 1239 }, { 1240 .addr = DDC_ADDR, 1241 .flags = 0, 1242 .len = 1, 1243 .buf = &start, 1244 }, { 1245 .addr = DDC_ADDR, 1246 .flags = I2C_M_RD, 1247 .len = len, 1248 .buf = buf, 1249 } 1250 }; 1251 1252 /* 1253 * Avoid sending the segment addr to not upset non-compliant 1254 * DDC monitors. 1255 */ 1256 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1257 1258 if (ret == -ENXIO) { 1259 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1260 adapter->name); 1261 break; 1262 } 1263 } while (ret != xfers && --retries); 1264 1265 return ret == xfers ? 0 : -1; 1266 } 1267 1268 /** 1269 * drm_do_get_edid - get EDID data using a custom EDID block read function 1270 * @connector: connector we're probing 1271 * @get_edid_block: EDID block read function 1272 * @data: private data passed to the block read function 1273 * 1274 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1275 * exposes a different interface to read EDID blocks this function can be used 1276 * to get EDID data using a custom block read function. 1277 * 1278 * As in the general case the DDC bus is accessible by the kernel at the I2C 1279 * level, drivers must make all reasonable efforts to expose it as an I2C 1280 * adapter and use drm_get_edid() instead of abusing this function. 1281 * 1282 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1283 */ 1284 struct edid *drm_do_get_edid(struct drm_connector *connector, 1285 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1286 size_t len), 1287 void *data) 1288 { 1289 int i, j = 0, valid_extensions = 0; 1290 u8 *block, *new; 1291 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1292 1293 if ((block = kmalloc(EDID_LENGTH, M_DRM, GFP_KERNEL)) == NULL) 1294 return NULL; 1295 1296 /* base block fetch */ 1297 for (i = 0; i < 4; i++) { 1298 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1299 goto out; 1300 if (drm_edid_block_valid(block, 0, print_bad_edid, 1301 &connector->edid_corrupt)) 1302 break; 1303 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1304 connector->null_edid_counter++; 1305 goto carp; 1306 } 1307 } 1308 if (i == 4) 1309 goto carp; 1310 1311 /* if there's no extensions, we're done */ 1312 if (block[0x7e] == 0) 1313 return (struct edid *)block; 1314 1315 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, 1316 GFP_KERNEL); 1317 if (!new) 1318 goto out; 1319 block = new; 1320 1321 for (j = 1; j <= block[0x7e]; j++) { 1322 for (i = 0; i < 4; i++) { 1323 if (get_edid_block(data, 1324 block + (valid_extensions + 1) * EDID_LENGTH, 1325 j, EDID_LENGTH)) 1326 goto out; 1327 if (drm_edid_block_valid(block + (valid_extensions + 1) 1328 * EDID_LENGTH, j, 1329 print_bad_edid, 1330 NULL)) { 1331 valid_extensions++; 1332 break; 1333 } 1334 } 1335 1336 if (i == 4 && print_bad_edid) { 1337 dev_warn(connector->dev->dev, 1338 "%s: Ignoring invalid EDID block %d.\n", 1339 connector->name, j); 1340 1341 connector->bad_edid_counter++; 1342 } 1343 } 1344 1345 if (valid_extensions != block[0x7e]) { 1346 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1347 block[0x7e] = valid_extensions; 1348 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, 1349 M_DRM, GFP_KERNEL); 1350 if (!new) 1351 goto out; 1352 block = new; 1353 } 1354 1355 return (struct edid *)block; 1356 1357 carp: 1358 if (print_bad_edid) { 1359 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1360 connector->name, j); 1361 } 1362 connector->bad_edid_counter++; 1363 1364 out: 1365 kfree(block); 1366 return NULL; 1367 } 1368 1369 /** 1370 * drm_probe_ddc() - probe DDC presence 1371 * @adapter: I2C adapter to probe 1372 * 1373 * Return: True on success, false on failure. 1374 */ 1375 bool 1376 drm_probe_ddc(struct i2c_adapter *adapter) 1377 { 1378 unsigned char out; 1379 1380 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1381 } 1382 EXPORT_SYMBOL(drm_probe_ddc); 1383 1384 /** 1385 * drm_get_edid - get EDID data, if available 1386 * @connector: connector we're probing 1387 * @adapter: I2C adapter to use for DDC 1388 * 1389 * Poke the given I2C channel to grab EDID data if possible. If found, 1390 * attach it to the connector. 1391 * 1392 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1393 */ 1394 struct edid *drm_get_edid(struct drm_connector *connector, 1395 struct i2c_adapter *adapter) 1396 { 1397 struct edid *edid; 1398 1399 if (!drm_probe_ddc(adapter)) 1400 return NULL; 1401 1402 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1403 if (edid) 1404 drm_get_displayid(connector, edid); 1405 return edid; 1406 } 1407 EXPORT_SYMBOL(drm_get_edid); 1408 1409 /** 1410 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1411 * @connector: connector we're probing 1412 * @adapter: I2C adapter to use for DDC 1413 * 1414 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1415 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1416 * switch DDC to the GPU which is retrieving EDID. 1417 * 1418 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1419 */ 1420 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1421 struct i2c_adapter *adapter) 1422 { 1423 struct pci_dev *pdev = connector->dev->pdev; 1424 struct edid *edid; 1425 1426 vga_switcheroo_lock_ddc(pdev); 1427 edid = drm_get_edid(connector, adapter); 1428 vga_switcheroo_unlock_ddc(pdev); 1429 1430 return edid; 1431 } 1432 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1433 1434 /** 1435 * drm_edid_duplicate - duplicate an EDID and the extensions 1436 * @edid: EDID to duplicate 1437 * 1438 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1439 */ 1440 struct edid *drm_edid_duplicate(const struct edid *edid) 1441 { 1442 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1443 } 1444 EXPORT_SYMBOL(drm_edid_duplicate); 1445 1446 /*** EDID parsing ***/ 1447 1448 /** 1449 * edid_vendor - match a string against EDID's obfuscated vendor field 1450 * @edid: EDID to match 1451 * @vendor: vendor string 1452 * 1453 * Returns true if @vendor is in @edid, false otherwise 1454 */ 1455 static bool edid_vendor(struct edid *edid, char *vendor) 1456 { 1457 char edid_vendor[3]; 1458 1459 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1460 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1461 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1462 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1463 1464 return !strncmp(edid_vendor, vendor, 3); 1465 } 1466 1467 /** 1468 * edid_get_quirks - return quirk flags for a given EDID 1469 * @edid: EDID to process 1470 * 1471 * This tells subsequent routines what fixes they need to apply. 1472 */ 1473 static u32 edid_get_quirks(struct edid *edid) 1474 { 1475 struct edid_quirk *quirk; 1476 int i; 1477 1478 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1479 quirk = &edid_quirk_list[i]; 1480 1481 if (edid_vendor(edid, quirk->vendor) && 1482 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1483 return quirk->quirks; 1484 } 1485 1486 return 0; 1487 } 1488 1489 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1490 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1491 1492 /** 1493 * edid_fixup_preferred - set preferred modes based on quirk list 1494 * @connector: has mode list to fix up 1495 * @quirks: quirks list 1496 * 1497 * Walk the mode list for @connector, clearing the preferred status 1498 * on existing modes and setting it anew for the right mode ala @quirks. 1499 */ 1500 static void edid_fixup_preferred(struct drm_connector *connector, 1501 u32 quirks) 1502 { 1503 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1504 int target_refresh = 0; 1505 int cur_vrefresh, preferred_vrefresh; 1506 1507 if (list_empty(&connector->probed_modes)) 1508 return; 1509 1510 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1511 target_refresh = 60; 1512 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1513 target_refresh = 75; 1514 1515 preferred_mode = list_first_entry(&connector->probed_modes, 1516 struct drm_display_mode, head); 1517 1518 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1519 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1520 1521 if (cur_mode == preferred_mode) 1522 continue; 1523 1524 /* Largest mode is preferred */ 1525 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1526 preferred_mode = cur_mode; 1527 1528 cur_vrefresh = cur_mode->vrefresh ? 1529 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1530 preferred_vrefresh = preferred_mode->vrefresh ? 1531 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1532 /* At a given size, try to get closest to target refresh */ 1533 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1534 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1535 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1536 preferred_mode = cur_mode; 1537 } 1538 } 1539 1540 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1541 } 1542 1543 static bool 1544 mode_is_rb(const struct drm_display_mode *mode) 1545 { 1546 return (mode->htotal - mode->hdisplay == 160) && 1547 (mode->hsync_end - mode->hdisplay == 80) && 1548 (mode->hsync_end - mode->hsync_start == 32) && 1549 (mode->vsync_start - mode->vdisplay == 3); 1550 } 1551 1552 /* 1553 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1554 * @dev: Device to duplicate against 1555 * @hsize: Mode width 1556 * @vsize: Mode height 1557 * @fresh: Mode refresh rate 1558 * @rb: Mode reduced-blanking-ness 1559 * 1560 * Walk the DMT mode list looking for a match for the given parameters. 1561 * 1562 * Return: A newly allocated copy of the mode, or NULL if not found. 1563 */ 1564 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1565 int hsize, int vsize, int fresh, 1566 bool rb) 1567 { 1568 int i; 1569 1570 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1571 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1572 if (hsize != ptr->hdisplay) 1573 continue; 1574 if (vsize != ptr->vdisplay) 1575 continue; 1576 if (fresh != drm_mode_vrefresh(ptr)) 1577 continue; 1578 if (rb != mode_is_rb(ptr)) 1579 continue; 1580 1581 return drm_mode_duplicate(dev, ptr); 1582 } 1583 1584 return NULL; 1585 } 1586 EXPORT_SYMBOL(drm_mode_find_dmt); 1587 1588 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1589 1590 static void 1591 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1592 { 1593 int i, n = 0; 1594 u8 d = ext[0x02]; 1595 u8 *det_base = ext + d; 1596 1597 n = (127 - d) / 18; 1598 for (i = 0; i < n; i++) 1599 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1600 } 1601 1602 static void 1603 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1604 { 1605 unsigned int i, n = min((int)ext[0x02], 6); 1606 u8 *det_base = ext + 5; 1607 1608 if (ext[0x01] != 1) 1609 return; /* unknown version */ 1610 1611 for (i = 0; i < n; i++) 1612 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1613 } 1614 1615 static void 1616 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1617 { 1618 int i; 1619 struct edid *edid = (struct edid *)raw_edid; 1620 1621 if (edid == NULL) 1622 return; 1623 1624 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1625 cb(&(edid->detailed_timings[i]), closure); 1626 1627 for (i = 1; i <= raw_edid[0x7e]; i++) { 1628 u8 *ext = raw_edid + (i * EDID_LENGTH); 1629 switch (*ext) { 1630 case CEA_EXT: 1631 cea_for_each_detailed_block(ext, cb, closure); 1632 break; 1633 case VTB_EXT: 1634 vtb_for_each_detailed_block(ext, cb, closure); 1635 break; 1636 default: 1637 break; 1638 } 1639 } 1640 } 1641 1642 static void 1643 is_rb(struct detailed_timing *t, void *data) 1644 { 1645 u8 *r = (u8 *)t; 1646 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1647 if (r[15] & 0x10) 1648 *(bool *)data = true; 1649 } 1650 1651 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1652 static bool 1653 drm_monitor_supports_rb(struct edid *edid) 1654 { 1655 if (edid->revision >= 4) { 1656 bool ret = false; 1657 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1658 return ret; 1659 } 1660 1661 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1662 } 1663 1664 static void 1665 find_gtf2(struct detailed_timing *t, void *data) 1666 { 1667 u8 *r = (u8 *)t; 1668 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1669 *(u8 **)data = r; 1670 } 1671 1672 /* Secondary GTF curve kicks in above some break frequency */ 1673 static int 1674 drm_gtf2_hbreak(struct edid *edid) 1675 { 1676 u8 *r = NULL; 1677 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1678 return r ? (r[12] * 2) : 0; 1679 } 1680 1681 static int 1682 drm_gtf2_2c(struct edid *edid) 1683 { 1684 u8 *r = NULL; 1685 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1686 return r ? r[13] : 0; 1687 } 1688 1689 static int 1690 drm_gtf2_m(struct edid *edid) 1691 { 1692 u8 *r = NULL; 1693 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1694 return r ? (r[15] << 8) + r[14] : 0; 1695 } 1696 1697 static int 1698 drm_gtf2_k(struct edid *edid) 1699 { 1700 u8 *r = NULL; 1701 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1702 return r ? r[16] : 0; 1703 } 1704 1705 static int 1706 drm_gtf2_2j(struct edid *edid) 1707 { 1708 u8 *r = NULL; 1709 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1710 return r ? r[17] : 0; 1711 } 1712 1713 /** 1714 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1715 * @edid: EDID block to scan 1716 */ 1717 static int standard_timing_level(struct edid *edid) 1718 { 1719 if (edid->revision >= 2) { 1720 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1721 return LEVEL_CVT; 1722 if (drm_gtf2_hbreak(edid)) 1723 return LEVEL_GTF2; 1724 return LEVEL_GTF; 1725 } 1726 return LEVEL_DMT; 1727 } 1728 1729 /* 1730 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1731 * monitors fill with ascii space (0x20) instead. 1732 */ 1733 static int 1734 bad_std_timing(u8 a, u8 b) 1735 { 1736 return (a == 0x00 && b == 0x00) || 1737 (a == 0x01 && b == 0x01) || 1738 (a == 0x20 && b == 0x20); 1739 } 1740 1741 /** 1742 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1743 * @connector: connector of for the EDID block 1744 * @edid: EDID block to scan 1745 * @t: standard timing params 1746 * 1747 * Take the standard timing params (in this case width, aspect, and refresh) 1748 * and convert them into a real mode using CVT/GTF/DMT. 1749 */ 1750 static struct drm_display_mode * 1751 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1752 struct std_timing *t) 1753 { 1754 struct drm_device *dev = connector->dev; 1755 struct drm_display_mode *m, *mode = NULL; 1756 int hsize, vsize; 1757 int vrefresh_rate; 1758 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1759 >> EDID_TIMING_ASPECT_SHIFT; 1760 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1761 >> EDID_TIMING_VFREQ_SHIFT; 1762 int timing_level = standard_timing_level(edid); 1763 1764 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1765 return NULL; 1766 1767 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1768 hsize = t->hsize * 8 + 248; 1769 /* vrefresh_rate = vfreq + 60 */ 1770 vrefresh_rate = vfreq + 60; 1771 /* the vdisplay is calculated based on the aspect ratio */ 1772 if (aspect_ratio == 0) { 1773 if (edid->revision < 3) 1774 vsize = hsize; 1775 else 1776 vsize = (hsize * 10) / 16; 1777 } else if (aspect_ratio == 1) 1778 vsize = (hsize * 3) / 4; 1779 else if (aspect_ratio == 2) 1780 vsize = (hsize * 4) / 5; 1781 else 1782 vsize = (hsize * 9) / 16; 1783 1784 /* HDTV hack, part 1 */ 1785 if (vrefresh_rate == 60 && 1786 ((hsize == 1360 && vsize == 765) || 1787 (hsize == 1368 && vsize == 769))) { 1788 hsize = 1366; 1789 vsize = 768; 1790 } 1791 1792 /* 1793 * If this connector already has a mode for this size and refresh 1794 * rate (because it came from detailed or CVT info), use that 1795 * instead. This way we don't have to guess at interlace or 1796 * reduced blanking. 1797 */ 1798 list_for_each_entry(m, &connector->probed_modes, head) 1799 if (m->hdisplay == hsize && m->vdisplay == vsize && 1800 drm_mode_vrefresh(m) == vrefresh_rate) 1801 return NULL; 1802 1803 /* HDTV hack, part 2 */ 1804 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1805 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1806 false); 1807 mode->hdisplay = 1366; 1808 mode->hsync_start = mode->hsync_start - 1; 1809 mode->hsync_end = mode->hsync_end - 1; 1810 return mode; 1811 } 1812 1813 /* check whether it can be found in default mode table */ 1814 if (drm_monitor_supports_rb(edid)) { 1815 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1816 true); 1817 if (mode) 1818 return mode; 1819 } 1820 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1821 if (mode) 1822 return mode; 1823 1824 /* okay, generate it */ 1825 switch (timing_level) { 1826 case LEVEL_DMT: 1827 break; 1828 case LEVEL_GTF: 1829 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1830 break; 1831 case LEVEL_GTF2: 1832 /* 1833 * This is potentially wrong if there's ever a monitor with 1834 * more than one ranges section, each claiming a different 1835 * secondary GTF curve. Please don't do that. 1836 */ 1837 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1838 if (!mode) 1839 return NULL; 1840 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1841 drm_mode_destroy(dev, mode); 1842 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1843 vrefresh_rate, 0, 0, 1844 drm_gtf2_m(edid), 1845 drm_gtf2_2c(edid), 1846 drm_gtf2_k(edid), 1847 drm_gtf2_2j(edid)); 1848 } 1849 break; 1850 case LEVEL_CVT: 1851 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1852 false); 1853 break; 1854 } 1855 return mode; 1856 } 1857 1858 /* 1859 * EDID is delightfully ambiguous about how interlaced modes are to be 1860 * encoded. Our internal representation is of frame height, but some 1861 * HDTV detailed timings are encoded as field height. 1862 * 1863 * The format list here is from CEA, in frame size. Technically we 1864 * should be checking refresh rate too. Whatever. 1865 */ 1866 static void 1867 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1868 struct detailed_pixel_timing *pt) 1869 { 1870 int i; 1871 static const struct { 1872 int w, h; 1873 } cea_interlaced[] = { 1874 { 1920, 1080 }, 1875 { 720, 480 }, 1876 { 1440, 480 }, 1877 { 2880, 480 }, 1878 { 720, 576 }, 1879 { 1440, 576 }, 1880 { 2880, 576 }, 1881 }; 1882 1883 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1884 return; 1885 1886 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1887 if ((mode->hdisplay == cea_interlaced[i].w) && 1888 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1889 mode->vdisplay *= 2; 1890 mode->vsync_start *= 2; 1891 mode->vsync_end *= 2; 1892 mode->vtotal *= 2; 1893 mode->vtotal |= 1; 1894 } 1895 } 1896 1897 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1898 } 1899 1900 /** 1901 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1902 * @dev: DRM device (needed to create new mode) 1903 * @edid: EDID block 1904 * @timing: EDID detailed timing info 1905 * @quirks: quirks to apply 1906 * 1907 * An EDID detailed timing block contains enough info for us to create and 1908 * return a new struct drm_display_mode. 1909 */ 1910 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1911 struct edid *edid, 1912 struct detailed_timing *timing, 1913 u32 quirks) 1914 { 1915 struct drm_display_mode *mode; 1916 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1917 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1918 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1919 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1920 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1921 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1922 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1923 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1924 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1925 1926 /* ignore tiny modes */ 1927 if (hactive < 64 || vactive < 64) 1928 return NULL; 1929 1930 if (pt->misc & DRM_EDID_PT_STEREO) { 1931 DRM_DEBUG_KMS("stereo mode not supported\n"); 1932 return NULL; 1933 } 1934 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1935 DRM_DEBUG_KMS("composite sync not supported\n"); 1936 } 1937 1938 /* it is incorrect if hsync/vsync width is zero */ 1939 if (!hsync_pulse_width || !vsync_pulse_width) { 1940 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1941 "Wrong Hsync/Vsync pulse width\n"); 1942 return NULL; 1943 } 1944 1945 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1946 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1947 if (!mode) 1948 return NULL; 1949 1950 goto set_size; 1951 } 1952 1953 mode = drm_mode_create(dev); 1954 if (!mode) 1955 return NULL; 1956 1957 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1958 timing->pixel_clock = cpu_to_le16(1088); 1959 1960 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1961 1962 mode->hdisplay = hactive; 1963 mode->hsync_start = mode->hdisplay + hsync_offset; 1964 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1965 mode->htotal = mode->hdisplay + hblank; 1966 1967 mode->vdisplay = vactive; 1968 mode->vsync_start = mode->vdisplay + vsync_offset; 1969 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1970 mode->vtotal = mode->vdisplay + vblank; 1971 1972 /* Some EDIDs have bogus h/vtotal values */ 1973 if (mode->hsync_end > mode->htotal) 1974 mode->htotal = mode->hsync_end + 1; 1975 if (mode->vsync_end > mode->vtotal) 1976 mode->vtotal = mode->vsync_end + 1; 1977 1978 drm_mode_do_interlace_quirk(mode, pt); 1979 1980 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1981 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1982 } 1983 1984 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1985 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1986 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1987 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1988 1989 set_size: 1990 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1991 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1992 1993 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1994 mode->width_mm *= 10; 1995 mode->height_mm *= 10; 1996 } 1997 1998 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1999 mode->width_mm = edid->width_cm * 10; 2000 mode->height_mm = edid->height_cm * 10; 2001 } 2002 2003 mode->type = DRM_MODE_TYPE_DRIVER; 2004 mode->vrefresh = drm_mode_vrefresh(mode); 2005 drm_mode_set_name(mode); 2006 2007 return mode; 2008 } 2009 2010 static bool 2011 mode_in_hsync_range(const struct drm_display_mode *mode, 2012 struct edid *edid, u8 *t) 2013 { 2014 int hsync, hmin, hmax; 2015 2016 hmin = t[7]; 2017 if (edid->revision >= 4) 2018 hmin += ((t[4] & 0x04) ? 255 : 0); 2019 hmax = t[8]; 2020 if (edid->revision >= 4) 2021 hmax += ((t[4] & 0x08) ? 255 : 0); 2022 hsync = drm_mode_hsync(mode); 2023 2024 return (hsync <= hmax && hsync >= hmin); 2025 } 2026 2027 static bool 2028 mode_in_vsync_range(const struct drm_display_mode *mode, 2029 struct edid *edid, u8 *t) 2030 { 2031 int vsync, vmin, vmax; 2032 2033 vmin = t[5]; 2034 if (edid->revision >= 4) 2035 vmin += ((t[4] & 0x01) ? 255 : 0); 2036 vmax = t[6]; 2037 if (edid->revision >= 4) 2038 vmax += ((t[4] & 0x02) ? 255 : 0); 2039 vsync = drm_mode_vrefresh(mode); 2040 2041 return (vsync <= vmax && vsync >= vmin); 2042 } 2043 2044 static u32 2045 range_pixel_clock(struct edid *edid, u8 *t) 2046 { 2047 /* unspecified */ 2048 if (t[9] == 0 || t[9] == 255) 2049 return 0; 2050 2051 /* 1.4 with CVT support gives us real precision, yay */ 2052 if (edid->revision >= 4 && t[10] == 0x04) 2053 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2054 2055 /* 1.3 is pathetic, so fuzz up a bit */ 2056 return t[9] * 10000 + 5001; 2057 } 2058 2059 static bool 2060 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2061 struct detailed_timing *timing) 2062 { 2063 u32 max_clock; 2064 u8 *t = (u8 *)timing; 2065 2066 if (!mode_in_hsync_range(mode, edid, t)) 2067 return false; 2068 2069 if (!mode_in_vsync_range(mode, edid, t)) 2070 return false; 2071 2072 if ((max_clock = range_pixel_clock(edid, t))) 2073 if (mode->clock > max_clock) 2074 return false; 2075 2076 /* 1.4 max horizontal check */ 2077 if (edid->revision >= 4 && t[10] == 0x04) 2078 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2079 return false; 2080 2081 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2082 return false; 2083 2084 return true; 2085 } 2086 2087 static bool valid_inferred_mode(const struct drm_connector *connector, 2088 const struct drm_display_mode *mode) 2089 { 2090 const struct drm_display_mode *m; 2091 bool ok = false; 2092 2093 list_for_each_entry(m, &connector->probed_modes, head) { 2094 if (mode->hdisplay == m->hdisplay && 2095 mode->vdisplay == m->vdisplay && 2096 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2097 return false; /* duplicated */ 2098 if (mode->hdisplay <= m->hdisplay && 2099 mode->vdisplay <= m->vdisplay) 2100 ok = true; 2101 } 2102 return ok; 2103 } 2104 2105 static int 2106 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2107 struct detailed_timing *timing) 2108 { 2109 int i, modes = 0; 2110 struct drm_display_mode *newmode; 2111 struct drm_device *dev = connector->dev; 2112 2113 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2114 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2115 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2116 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2117 if (newmode) { 2118 drm_mode_probed_add(connector, newmode); 2119 modes++; 2120 } 2121 } 2122 } 2123 2124 return modes; 2125 } 2126 2127 /* fix up 1366x768 mode from 1368x768; 2128 * GFT/CVT can't express 1366 width which isn't dividable by 8 2129 */ 2130 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2131 { 2132 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2133 mode->hdisplay = 1366; 2134 mode->hsync_start--; 2135 mode->hsync_end--; 2136 drm_mode_set_name(mode); 2137 } 2138 } 2139 2140 static int 2141 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2142 struct detailed_timing *timing) 2143 { 2144 int i, modes = 0; 2145 struct drm_display_mode *newmode; 2146 struct drm_device *dev = connector->dev; 2147 2148 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2149 const struct minimode *m = &extra_modes[i]; 2150 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2151 if (!newmode) 2152 return modes; 2153 2154 fixup_mode_1366x768(newmode); 2155 if (!mode_in_range(newmode, edid, timing) || 2156 !valid_inferred_mode(connector, newmode)) { 2157 drm_mode_destroy(dev, newmode); 2158 continue; 2159 } 2160 2161 drm_mode_probed_add(connector, newmode); 2162 modes++; 2163 } 2164 2165 return modes; 2166 } 2167 2168 static int 2169 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2170 struct detailed_timing *timing) 2171 { 2172 int i, modes = 0; 2173 struct drm_display_mode *newmode; 2174 struct drm_device *dev = connector->dev; 2175 bool rb = drm_monitor_supports_rb(edid); 2176 2177 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2178 const struct minimode *m = &extra_modes[i]; 2179 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2180 if (!newmode) 2181 return modes; 2182 2183 fixup_mode_1366x768(newmode); 2184 if (!mode_in_range(newmode, edid, timing) || 2185 !valid_inferred_mode(connector, newmode)) { 2186 drm_mode_destroy(dev, newmode); 2187 continue; 2188 } 2189 2190 drm_mode_probed_add(connector, newmode); 2191 modes++; 2192 } 2193 2194 return modes; 2195 } 2196 2197 static void 2198 do_inferred_modes(struct detailed_timing *timing, void *c) 2199 { 2200 struct detailed_mode_closure *closure = c; 2201 struct detailed_non_pixel *data = &timing->data.other_data; 2202 struct detailed_data_monitor_range *range = &data->data.range; 2203 2204 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2205 return; 2206 2207 closure->modes += drm_dmt_modes_for_range(closure->connector, 2208 closure->edid, 2209 timing); 2210 2211 if (!version_greater(closure->edid, 1, 1)) 2212 return; /* GTF not defined yet */ 2213 2214 switch (range->flags) { 2215 case 0x02: /* secondary gtf, XXX could do more */ 2216 case 0x00: /* default gtf */ 2217 closure->modes += drm_gtf_modes_for_range(closure->connector, 2218 closure->edid, 2219 timing); 2220 break; 2221 case 0x04: /* cvt, only in 1.4+ */ 2222 if (!version_greater(closure->edid, 1, 3)) 2223 break; 2224 2225 closure->modes += drm_cvt_modes_for_range(closure->connector, 2226 closure->edid, 2227 timing); 2228 break; 2229 case 0x01: /* just the ranges, no formula */ 2230 default: 2231 break; 2232 } 2233 } 2234 2235 static int 2236 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2237 { 2238 struct detailed_mode_closure closure = { 2239 .connector = connector, 2240 .edid = edid, 2241 }; 2242 2243 if (version_greater(edid, 1, 0)) 2244 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2245 &closure); 2246 2247 return closure.modes; 2248 } 2249 2250 static int 2251 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2252 { 2253 int i, j, m, modes = 0; 2254 struct drm_display_mode *mode; 2255 u8 *est = ((u8 *)timing) + 6; 2256 2257 for (i = 0; i < 6; i++) { 2258 for (j = 7; j >= 0; j--) { 2259 m = (i * 8) + (7 - j); 2260 if (m >= ARRAY_SIZE(est3_modes)) 2261 break; 2262 if (est[i] & (1 << j)) { 2263 mode = drm_mode_find_dmt(connector->dev, 2264 est3_modes[m].w, 2265 est3_modes[m].h, 2266 est3_modes[m].r, 2267 est3_modes[m].rb); 2268 if (mode) { 2269 drm_mode_probed_add(connector, mode); 2270 modes++; 2271 } 2272 } 2273 } 2274 } 2275 2276 return modes; 2277 } 2278 2279 static void 2280 do_established_modes(struct detailed_timing *timing, void *c) 2281 { 2282 struct detailed_mode_closure *closure = c; 2283 struct detailed_non_pixel *data = &timing->data.other_data; 2284 2285 if (data->type == EDID_DETAIL_EST_TIMINGS) 2286 closure->modes += drm_est3_modes(closure->connector, timing); 2287 } 2288 2289 /** 2290 * add_established_modes - get est. modes from EDID and add them 2291 * @connector: connector to add mode(s) to 2292 * @edid: EDID block to scan 2293 * 2294 * Each EDID block contains a bitmap of the supported "established modes" list 2295 * (defined above). Tease them out and add them to the global modes list. 2296 */ 2297 static int 2298 add_established_modes(struct drm_connector *connector, struct edid *edid) 2299 { 2300 struct drm_device *dev = connector->dev; 2301 unsigned long est_bits = edid->established_timings.t1 | 2302 (edid->established_timings.t2 << 8) | 2303 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2304 int i, modes = 0; 2305 struct detailed_mode_closure closure = { 2306 .connector = connector, 2307 .edid = edid, 2308 }; 2309 2310 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2311 if (est_bits & (1<<i)) { 2312 struct drm_display_mode *newmode; 2313 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2314 if (newmode) { 2315 drm_mode_probed_add(connector, newmode); 2316 modes++; 2317 } 2318 } 2319 } 2320 2321 if (version_greater(edid, 1, 0)) 2322 drm_for_each_detailed_block((u8 *)edid, 2323 do_established_modes, &closure); 2324 2325 return modes + closure.modes; 2326 } 2327 2328 static void 2329 do_standard_modes(struct detailed_timing *timing, void *c) 2330 { 2331 struct detailed_mode_closure *closure = c; 2332 struct detailed_non_pixel *data = &timing->data.other_data; 2333 struct drm_connector *connector = closure->connector; 2334 struct edid *edid = closure->edid; 2335 2336 if (data->type == EDID_DETAIL_STD_MODES) { 2337 int i; 2338 for (i = 0; i < 6; i++) { 2339 struct std_timing *std; 2340 struct drm_display_mode *newmode; 2341 2342 std = &data->data.timings[i]; 2343 newmode = drm_mode_std(connector, edid, std); 2344 if (newmode) { 2345 drm_mode_probed_add(connector, newmode); 2346 closure->modes++; 2347 } 2348 } 2349 } 2350 } 2351 2352 /** 2353 * add_standard_modes - get std. modes from EDID and add them 2354 * @connector: connector to add mode(s) to 2355 * @edid: EDID block to scan 2356 * 2357 * Standard modes can be calculated using the appropriate standard (DMT, 2358 * GTF or CVT. Grab them from @edid and add them to the list. 2359 */ 2360 static int 2361 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2362 { 2363 int i, modes = 0; 2364 struct detailed_mode_closure closure = { 2365 .connector = connector, 2366 .edid = edid, 2367 }; 2368 2369 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2370 struct drm_display_mode *newmode; 2371 2372 newmode = drm_mode_std(connector, edid, 2373 &edid->standard_timings[i]); 2374 if (newmode) { 2375 drm_mode_probed_add(connector, newmode); 2376 modes++; 2377 } 2378 } 2379 2380 if (version_greater(edid, 1, 0)) 2381 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2382 &closure); 2383 2384 /* XXX should also look for standard codes in VTB blocks */ 2385 2386 return modes + closure.modes; 2387 } 2388 2389 static int drm_cvt_modes(struct drm_connector *connector, 2390 struct detailed_timing *timing) 2391 { 2392 int i, j, modes = 0; 2393 struct drm_display_mode *newmode; 2394 struct drm_device *dev = connector->dev; 2395 struct cvt_timing *cvt; 2396 const int rates[] = { 60, 85, 75, 60, 50 }; 2397 const u8 empty[3] = { 0, 0, 0 }; 2398 2399 for (i = 0; i < 4; i++) { 2400 int width = 0, height; 2401 cvt = &(timing->data.other_data.data.cvt[i]); 2402 2403 if (!memcmp(cvt->code, empty, 3)) 2404 continue; 2405 2406 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2407 switch (cvt->code[1] & 0x0c) { 2408 case 0x00: 2409 width = height * 4 / 3; 2410 break; 2411 case 0x04: 2412 width = height * 16 / 9; 2413 break; 2414 case 0x08: 2415 width = height * 16 / 10; 2416 break; 2417 case 0x0c: 2418 width = height * 15 / 9; 2419 break; 2420 } 2421 2422 for (j = 1; j < 5; j++) { 2423 if (cvt->code[2] & (1 << j)) { 2424 newmode = drm_cvt_mode(dev, width, height, 2425 rates[j], j == 0, 2426 false, false); 2427 if (newmode) { 2428 drm_mode_probed_add(connector, newmode); 2429 modes++; 2430 } 2431 } 2432 } 2433 } 2434 2435 return modes; 2436 } 2437 2438 static void 2439 do_cvt_mode(struct detailed_timing *timing, void *c) 2440 { 2441 struct detailed_mode_closure *closure = c; 2442 struct detailed_non_pixel *data = &timing->data.other_data; 2443 2444 if (data->type == EDID_DETAIL_CVT_3BYTE) 2445 closure->modes += drm_cvt_modes(closure->connector, timing); 2446 } 2447 2448 static int 2449 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2450 { 2451 struct detailed_mode_closure closure = { 2452 .connector = connector, 2453 .edid = edid, 2454 }; 2455 2456 if (version_greater(edid, 1, 2)) 2457 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2458 2459 /* XXX should also look for CVT codes in VTB blocks */ 2460 2461 return closure.modes; 2462 } 2463 2464 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2465 2466 static void 2467 do_detailed_mode(struct detailed_timing *timing, void *c) 2468 { 2469 struct detailed_mode_closure *closure = c; 2470 struct drm_display_mode *newmode; 2471 2472 if (timing->pixel_clock) { 2473 newmode = drm_mode_detailed(closure->connector->dev, 2474 closure->edid, timing, 2475 closure->quirks); 2476 if (!newmode) 2477 return; 2478 2479 if (closure->preferred) 2480 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2481 2482 /* 2483 * Detailed modes are limited to 10kHz pixel clock resolution, 2484 * so fix up anything that looks like CEA/HDMI mode, but the clock 2485 * is just slightly off. 2486 */ 2487 fixup_detailed_cea_mode_clock(newmode); 2488 2489 drm_mode_probed_add(closure->connector, newmode); 2490 closure->modes++; 2491 closure->preferred = 0; 2492 } 2493 } 2494 2495 /* 2496 * add_detailed_modes - Add modes from detailed timings 2497 * @connector: attached connector 2498 * @edid: EDID block to scan 2499 * @quirks: quirks to apply 2500 */ 2501 static int 2502 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2503 u32 quirks) 2504 { 2505 struct detailed_mode_closure closure = { 2506 .connector = connector, 2507 .edid = edid, 2508 .preferred = 1, 2509 .quirks = quirks, 2510 }; 2511 2512 if (closure.preferred && !version_greater(edid, 1, 3)) 2513 closure.preferred = 2514 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2515 2516 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2517 2518 return closure.modes; 2519 } 2520 2521 #define AUDIO_BLOCK 0x01 2522 #define VIDEO_BLOCK 0x02 2523 #define VENDOR_BLOCK 0x03 2524 #define SPEAKER_BLOCK 0x04 2525 #define VIDEO_CAPABILITY_BLOCK 0x07 2526 #define EDID_BASIC_AUDIO (1 << 6) 2527 #define EDID_CEA_YCRCB444 (1 << 5) 2528 #define EDID_CEA_YCRCB422 (1 << 4) 2529 #define EDID_CEA_VCDB_QS (1 << 6) 2530 2531 /* 2532 * Search EDID for CEA extension block. 2533 */ 2534 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2535 { 2536 u8 *edid_ext = NULL; 2537 int i; 2538 2539 /* No EDID or EDID extensions */ 2540 if (edid == NULL || edid->extensions == 0) 2541 return NULL; 2542 2543 /* Find CEA extension */ 2544 for (i = 0; i < edid->extensions; i++) { 2545 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2546 if (edid_ext[0] == ext_id) 2547 break; 2548 } 2549 2550 if (i == edid->extensions) 2551 return NULL; 2552 2553 return edid_ext; 2554 } 2555 2556 static u8 *drm_find_cea_extension(struct edid *edid) 2557 { 2558 return drm_find_edid_extension(edid, CEA_EXT); 2559 } 2560 2561 static u8 *drm_find_displayid_extension(struct edid *edid) 2562 { 2563 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2564 } 2565 2566 /* 2567 * Calculate the alternate clock for the CEA mode 2568 * (60Hz vs. 59.94Hz etc.) 2569 */ 2570 static unsigned int 2571 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2572 { 2573 unsigned int clock = cea_mode->clock; 2574 2575 if (cea_mode->vrefresh % 6 != 0) 2576 return clock; 2577 2578 /* 2579 * edid_cea_modes contains the 59.94Hz 2580 * variant for 240 and 480 line modes, 2581 * and the 60Hz variant otherwise. 2582 */ 2583 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2584 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2585 else 2586 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2587 2588 return clock; 2589 } 2590 2591 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2592 unsigned int clock_tolerance) 2593 { 2594 u8 vic; 2595 2596 if (!to_match->clock) 2597 return 0; 2598 2599 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2600 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2601 unsigned int clock1, clock2; 2602 2603 /* Check both 60Hz and 59.94Hz */ 2604 clock1 = cea_mode->clock; 2605 clock2 = cea_mode_alternate_clock(cea_mode); 2606 2607 if (abs(to_match->clock - clock1) > clock_tolerance && 2608 abs(to_match->clock - clock2) > clock_tolerance) 2609 continue; 2610 2611 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 2612 return vic; 2613 } 2614 2615 return 0; 2616 } 2617 2618 /** 2619 * drm_match_cea_mode - look for a CEA mode matching given mode 2620 * @to_match: display mode 2621 * 2622 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2623 * mode. 2624 */ 2625 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2626 { 2627 u8 vic; 2628 2629 if (!to_match->clock) 2630 return 0; 2631 2632 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2633 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2634 unsigned int clock1, clock2; 2635 2636 /* Check both 60Hz and 59.94Hz */ 2637 clock1 = cea_mode->clock; 2638 clock2 = cea_mode_alternate_clock(cea_mode); 2639 2640 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2641 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2642 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2643 return vic; 2644 } 2645 return 0; 2646 } 2647 EXPORT_SYMBOL(drm_match_cea_mode); 2648 2649 static bool drm_valid_cea_vic(u8 vic) 2650 { 2651 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2652 } 2653 2654 /** 2655 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2656 * the input VIC from the CEA mode list 2657 * @video_code: ID given to each of the CEA modes 2658 * 2659 * Returns picture aspect ratio 2660 */ 2661 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2662 { 2663 return edid_cea_modes[video_code].picture_aspect_ratio; 2664 } 2665 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2666 2667 /* 2668 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2669 * specific block). 2670 * 2671 * It's almost like cea_mode_alternate_clock(), we just need to add an 2672 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2673 * one. 2674 */ 2675 static unsigned int 2676 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2677 { 2678 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2679 return hdmi_mode->clock; 2680 2681 return cea_mode_alternate_clock(hdmi_mode); 2682 } 2683 2684 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 2685 unsigned int clock_tolerance) 2686 { 2687 u8 vic; 2688 2689 if (!to_match->clock) 2690 return 0; 2691 2692 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2693 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2694 unsigned int clock1, clock2; 2695 2696 /* Make sure to also match alternate clocks */ 2697 clock1 = hdmi_mode->clock; 2698 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2699 2700 if (abs(to_match->clock - clock1) > clock_tolerance && 2701 abs(to_match->clock - clock2) > clock_tolerance) 2702 continue; 2703 2704 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 2705 return vic; 2706 } 2707 2708 return 0; 2709 } 2710 2711 /* 2712 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2713 * @to_match: display mode 2714 * 2715 * An HDMI mode is one defined in the HDMI vendor specific block. 2716 * 2717 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2718 */ 2719 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2720 { 2721 u8 vic; 2722 2723 if (!to_match->clock) 2724 return 0; 2725 2726 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2727 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2728 unsigned int clock1, clock2; 2729 2730 /* Make sure to also match alternate clocks */ 2731 clock1 = hdmi_mode->clock; 2732 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2733 2734 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2735 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2736 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2737 return vic; 2738 } 2739 return 0; 2740 } 2741 2742 static bool drm_valid_hdmi_vic(u8 vic) 2743 { 2744 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2745 } 2746 2747 static int 2748 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2749 { 2750 struct drm_device *dev = connector->dev; 2751 struct drm_display_mode *mode, *tmp; 2752 LINUX_LIST_HEAD(list); 2753 int modes = 0; 2754 2755 /* Don't add CEA modes if the CEA extension block is missing */ 2756 if (!drm_find_cea_extension(edid)) 2757 return 0; 2758 2759 /* 2760 * Go through all probed modes and create a new mode 2761 * with the alternate clock for certain CEA modes. 2762 */ 2763 list_for_each_entry(mode, &connector->probed_modes, head) { 2764 const struct drm_display_mode *cea_mode = NULL; 2765 struct drm_display_mode *newmode; 2766 u8 vic = drm_match_cea_mode(mode); 2767 unsigned int clock1, clock2; 2768 2769 if (drm_valid_cea_vic(vic)) { 2770 cea_mode = &edid_cea_modes[vic]; 2771 clock2 = cea_mode_alternate_clock(cea_mode); 2772 } else { 2773 vic = drm_match_hdmi_mode(mode); 2774 if (drm_valid_hdmi_vic(vic)) { 2775 cea_mode = &edid_4k_modes[vic]; 2776 clock2 = hdmi_mode_alternate_clock(cea_mode); 2777 } 2778 } 2779 2780 if (!cea_mode) 2781 continue; 2782 2783 clock1 = cea_mode->clock; 2784 2785 if (clock1 == clock2) 2786 continue; 2787 2788 if (mode->clock != clock1 && mode->clock != clock2) 2789 continue; 2790 2791 newmode = drm_mode_duplicate(dev, cea_mode); 2792 if (!newmode) 2793 continue; 2794 2795 /* Carry over the stereo flags */ 2796 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2797 2798 /* 2799 * The current mode could be either variant. Make 2800 * sure to pick the "other" clock for the new mode. 2801 */ 2802 if (mode->clock != clock1) 2803 newmode->clock = clock1; 2804 else 2805 newmode->clock = clock2; 2806 2807 list_add_tail(&newmode->head, &list); 2808 } 2809 2810 list_for_each_entry_safe(mode, tmp, &list, head) { 2811 list_del(&mode->head); 2812 drm_mode_probed_add(connector, mode); 2813 modes++; 2814 } 2815 2816 return modes; 2817 } 2818 2819 static struct drm_display_mode * 2820 drm_display_mode_from_vic_index(struct drm_connector *connector, 2821 const u8 *video_db, u8 video_len, 2822 u8 video_index) 2823 { 2824 struct drm_device *dev = connector->dev; 2825 struct drm_display_mode *newmode; 2826 u8 vic; 2827 2828 if (video_db == NULL || video_index >= video_len) 2829 return NULL; 2830 2831 /* CEA modes are numbered 1..127 */ 2832 vic = (video_db[video_index] & 127); 2833 if (!drm_valid_cea_vic(vic)) 2834 return NULL; 2835 2836 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 2837 if (!newmode) 2838 return NULL; 2839 2840 newmode->vrefresh = 0; 2841 2842 return newmode; 2843 } 2844 2845 static int 2846 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2847 { 2848 int i, modes = 0; 2849 2850 for (i = 0; i < len; i++) { 2851 struct drm_display_mode *mode; 2852 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2853 if (mode) { 2854 drm_mode_probed_add(connector, mode); 2855 modes++; 2856 } 2857 } 2858 2859 return modes; 2860 } 2861 2862 struct stereo_mandatory_mode { 2863 int width, height, vrefresh; 2864 unsigned int flags; 2865 }; 2866 2867 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2868 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2869 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2870 { 1920, 1080, 50, 2871 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2872 { 1920, 1080, 60, 2873 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2874 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2875 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2876 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2877 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2878 }; 2879 2880 static bool 2881 stereo_match_mandatory(const struct drm_display_mode *mode, 2882 const struct stereo_mandatory_mode *stereo_mode) 2883 { 2884 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2885 2886 return mode->hdisplay == stereo_mode->width && 2887 mode->vdisplay == stereo_mode->height && 2888 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2889 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2890 } 2891 2892 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2893 { 2894 struct drm_device *dev = connector->dev; 2895 const struct drm_display_mode *mode; 2896 struct list_head stereo_modes; 2897 int modes = 0, i; 2898 2899 INIT_LIST_HEAD(&stereo_modes); 2900 2901 list_for_each_entry(mode, &connector->probed_modes, head) { 2902 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2903 const struct stereo_mandatory_mode *mandatory; 2904 struct drm_display_mode *new_mode; 2905 2906 if (!stereo_match_mandatory(mode, 2907 &stereo_mandatory_modes[i])) 2908 continue; 2909 2910 mandatory = &stereo_mandatory_modes[i]; 2911 new_mode = drm_mode_duplicate(dev, mode); 2912 if (!new_mode) 2913 continue; 2914 2915 new_mode->flags |= mandatory->flags; 2916 list_add_tail(&new_mode->head, &stereo_modes); 2917 modes++; 2918 } 2919 } 2920 2921 list_splice_tail(&stereo_modes, &connector->probed_modes); 2922 2923 return modes; 2924 } 2925 2926 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2927 { 2928 struct drm_device *dev = connector->dev; 2929 struct drm_display_mode *newmode; 2930 2931 if (!drm_valid_hdmi_vic(vic)) { 2932 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2933 return 0; 2934 } 2935 2936 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2937 if (!newmode) 2938 return 0; 2939 2940 drm_mode_probed_add(connector, newmode); 2941 2942 return 1; 2943 } 2944 2945 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2946 const u8 *video_db, u8 video_len, u8 video_index) 2947 { 2948 struct drm_display_mode *newmode; 2949 int modes = 0; 2950 2951 if (structure & (1 << 0)) { 2952 newmode = drm_display_mode_from_vic_index(connector, video_db, 2953 video_len, 2954 video_index); 2955 if (newmode) { 2956 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2957 drm_mode_probed_add(connector, newmode); 2958 modes++; 2959 } 2960 } 2961 if (structure & (1 << 6)) { 2962 newmode = drm_display_mode_from_vic_index(connector, video_db, 2963 video_len, 2964 video_index); 2965 if (newmode) { 2966 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2967 drm_mode_probed_add(connector, newmode); 2968 modes++; 2969 } 2970 } 2971 if (structure & (1 << 8)) { 2972 newmode = drm_display_mode_from_vic_index(connector, video_db, 2973 video_len, 2974 video_index); 2975 if (newmode) { 2976 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2977 drm_mode_probed_add(connector, newmode); 2978 modes++; 2979 } 2980 } 2981 2982 return modes; 2983 } 2984 2985 /* 2986 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2987 * @connector: connector corresponding to the HDMI sink 2988 * @db: start of the CEA vendor specific block 2989 * @len: length of the CEA block payload, ie. one can access up to db[len] 2990 * 2991 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2992 * also adds the stereo 3d modes when applicable. 2993 */ 2994 static int 2995 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2996 const u8 *video_db, u8 video_len) 2997 { 2998 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2999 u8 vic_len, hdmi_3d_len = 0; 3000 u16 mask; 3001 u16 structure_all; 3002 3003 if (len < 8) 3004 goto out; 3005 3006 /* no HDMI_Video_Present */ 3007 if (!(db[8] & (1 << 5))) 3008 goto out; 3009 3010 /* Latency_Fields_Present */ 3011 if (db[8] & (1 << 7)) 3012 offset += 2; 3013 3014 /* I_Latency_Fields_Present */ 3015 if (db[8] & (1 << 6)) 3016 offset += 2; 3017 3018 /* the declared length is not long enough for the 2 first bytes 3019 * of additional video format capabilities */ 3020 if (len < (8 + offset + 2)) 3021 goto out; 3022 3023 /* 3D_Present */ 3024 offset++; 3025 if (db[8 + offset] & (1 << 7)) { 3026 modes += add_hdmi_mandatory_stereo_modes(connector); 3027 3028 /* 3D_Multi_present */ 3029 multi_present = (db[8 + offset] & 0x60) >> 5; 3030 } 3031 3032 offset++; 3033 vic_len = db[8 + offset] >> 5; 3034 hdmi_3d_len = db[8 + offset] & 0x1f; 3035 3036 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3037 u8 vic; 3038 3039 vic = db[9 + offset + i]; 3040 modes += add_hdmi_mode(connector, vic); 3041 } 3042 offset += 1 + vic_len; 3043 3044 if (multi_present == 1) 3045 multi_len = 2; 3046 else if (multi_present == 2) 3047 multi_len = 4; 3048 else 3049 multi_len = 0; 3050 3051 if (len < (8 + offset + hdmi_3d_len - 1)) 3052 goto out; 3053 3054 if (hdmi_3d_len < multi_len) 3055 goto out; 3056 3057 if (multi_present == 1 || multi_present == 2) { 3058 /* 3D_Structure_ALL */ 3059 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3060 3061 /* check if 3D_MASK is present */ 3062 if (multi_present == 2) 3063 mask = (db[10 + offset] << 8) | db[11 + offset]; 3064 else 3065 mask = 0xffff; 3066 3067 for (i = 0; i < 16; i++) { 3068 if (mask & (1 << i)) 3069 modes += add_3d_struct_modes(connector, 3070 structure_all, 3071 video_db, 3072 video_len, i); 3073 } 3074 } 3075 3076 offset += multi_len; 3077 3078 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3079 int vic_index; 3080 struct drm_display_mode *newmode = NULL; 3081 unsigned int newflag = 0; 3082 bool detail_present; 3083 3084 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3085 3086 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3087 break; 3088 3089 /* 2D_VIC_order_X */ 3090 vic_index = db[8 + offset + i] >> 4; 3091 3092 /* 3D_Structure_X */ 3093 switch (db[8 + offset + i] & 0x0f) { 3094 case 0: 3095 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3096 break; 3097 case 6: 3098 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3099 break; 3100 case 8: 3101 /* 3D_Detail_X */ 3102 if ((db[9 + offset + i] >> 4) == 1) 3103 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3104 break; 3105 } 3106 3107 if (newflag != 0) { 3108 newmode = drm_display_mode_from_vic_index(connector, 3109 video_db, 3110 video_len, 3111 vic_index); 3112 3113 if (newmode) { 3114 newmode->flags |= newflag; 3115 drm_mode_probed_add(connector, newmode); 3116 modes++; 3117 } 3118 } 3119 3120 if (detail_present) 3121 i++; 3122 } 3123 3124 out: 3125 return modes; 3126 } 3127 3128 static int 3129 cea_db_payload_len(const u8 *db) 3130 { 3131 return db[0] & 0x1f; 3132 } 3133 3134 static int 3135 cea_db_tag(const u8 *db) 3136 { 3137 return db[0] >> 5; 3138 } 3139 3140 static int 3141 cea_revision(const u8 *cea) 3142 { 3143 return cea[1]; 3144 } 3145 3146 static int 3147 cea_db_offsets(const u8 *cea, int *start, int *end) 3148 { 3149 /* Data block offset in CEA extension block */ 3150 *start = 4; 3151 *end = cea[2]; 3152 if (*end == 0) 3153 *end = 127; 3154 if (*end < 4 || *end > 127) 3155 return -ERANGE; 3156 return 0; 3157 } 3158 3159 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3160 { 3161 int hdmi_id; 3162 3163 if (cea_db_tag(db) != VENDOR_BLOCK) 3164 return false; 3165 3166 if (cea_db_payload_len(db) < 5) 3167 return false; 3168 3169 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3170 3171 return hdmi_id == HDMI_IEEE_OUI; 3172 } 3173 3174 #define for_each_cea_db(cea, i, start, end) \ 3175 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3176 3177 static int 3178 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3179 { 3180 const u8 *cea = drm_find_cea_extension(edid); 3181 const u8 *db, *hdmi = NULL, *video = NULL; 3182 u8 dbl, hdmi_len, video_len = 0; 3183 int modes = 0; 3184 3185 if (cea && cea_revision(cea) >= 3) { 3186 int i, start, end; 3187 3188 if (cea_db_offsets(cea, &start, &end)) 3189 return 0; 3190 3191 for_each_cea_db(cea, i, start, end) { 3192 db = &cea[i]; 3193 dbl = cea_db_payload_len(db); 3194 3195 if (cea_db_tag(db) == VIDEO_BLOCK) { 3196 video = db + 1; 3197 video_len = dbl; 3198 modes += do_cea_modes(connector, video, dbl); 3199 } 3200 else if (cea_db_is_hdmi_vsdb(db)) { 3201 hdmi = db; 3202 hdmi_len = dbl; 3203 } 3204 } 3205 } 3206 3207 /* 3208 * We parse the HDMI VSDB after having added the cea modes as we will 3209 * be patching their flags when the sink supports stereo 3D. 3210 */ 3211 if (hdmi) 3212 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3213 video_len); 3214 3215 return modes; 3216 } 3217 3218 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3219 { 3220 const struct drm_display_mode *cea_mode; 3221 int clock1, clock2, clock; 3222 u8 vic; 3223 const char *type; 3224 3225 /* 3226 * allow 5kHz clock difference either way to account for 3227 * the 10kHz clock resolution limit of detailed timings. 3228 */ 3229 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3230 if (drm_valid_cea_vic(vic)) { 3231 type = "CEA"; 3232 cea_mode = &edid_cea_modes[vic]; 3233 clock1 = cea_mode->clock; 3234 clock2 = cea_mode_alternate_clock(cea_mode); 3235 } else { 3236 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3237 if (drm_valid_hdmi_vic(vic)) { 3238 type = "HDMI"; 3239 cea_mode = &edid_4k_modes[vic]; 3240 clock1 = cea_mode->clock; 3241 clock2 = hdmi_mode_alternate_clock(cea_mode); 3242 } else { 3243 return; 3244 } 3245 } 3246 3247 /* pick whichever is closest */ 3248 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3249 clock = clock1; 3250 else 3251 clock = clock2; 3252 3253 if (mode->clock == clock) 3254 return; 3255 3256 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3257 type, vic, mode->clock, clock); 3258 mode->clock = clock; 3259 } 3260 3261 static void 3262 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3263 { 3264 u8 len = cea_db_payload_len(db); 3265 3266 if (len >= 6) 3267 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3268 if (len >= 8) { 3269 connector->latency_present[0] = db[8] >> 7; 3270 connector->latency_present[1] = (db[8] >> 6) & 1; 3271 } 3272 if (len >= 9) 3273 connector->video_latency[0] = db[9]; 3274 if (len >= 10) 3275 connector->audio_latency[0] = db[10]; 3276 if (len >= 11) 3277 connector->video_latency[1] = db[11]; 3278 if (len >= 12) 3279 connector->audio_latency[1] = db[12]; 3280 3281 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3282 "video latency %d %d, " 3283 "audio latency %d %d\n", 3284 connector->latency_present[0], 3285 connector->latency_present[1], 3286 connector->video_latency[0], 3287 connector->video_latency[1], 3288 connector->audio_latency[0], 3289 connector->audio_latency[1]); 3290 } 3291 3292 static void 3293 monitor_name(struct detailed_timing *t, void *data) 3294 { 3295 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3296 *(u8 **)data = t->data.other_data.data.str.str; 3297 } 3298 3299 static int get_monitor_name(struct edid *edid, char name[13]) 3300 { 3301 char *edid_name = NULL; 3302 int mnl; 3303 3304 if (!edid || !name) 3305 return 0; 3306 3307 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3308 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3309 if (edid_name[mnl] == 0x0a) 3310 break; 3311 3312 name[mnl] = edid_name[mnl]; 3313 } 3314 3315 return mnl; 3316 } 3317 3318 /** 3319 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3320 * @edid: monitor EDID information 3321 * @name: pointer to a character array to hold the name of the monitor 3322 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3323 * 3324 */ 3325 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3326 { 3327 int name_length; 3328 char buf[13]; 3329 3330 if (bufsize <= 0) 3331 return; 3332 3333 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3334 memcpy(name, buf, name_length); 3335 name[name_length] = '\0'; 3336 } 3337 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3338 3339 /** 3340 * drm_edid_to_eld - build ELD from EDID 3341 * @connector: connector corresponding to the HDMI/DP sink 3342 * @edid: EDID to parse 3343 * 3344 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3345 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3346 * fill in. 3347 */ 3348 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3349 { 3350 uint8_t *eld = connector->eld; 3351 u8 *cea; 3352 u8 *db; 3353 int total_sad_count = 0; 3354 int mnl; 3355 int dbl; 3356 3357 memset(eld, 0, sizeof(connector->eld)); 3358 3359 connector->latency_present[0] = false; 3360 connector->latency_present[1] = false; 3361 connector->video_latency[0] = 0; 3362 connector->audio_latency[0] = 0; 3363 connector->video_latency[1] = 0; 3364 connector->audio_latency[1] = 0; 3365 3366 cea = drm_find_cea_extension(edid); 3367 if (!cea) { 3368 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3369 return; 3370 } 3371 3372 mnl = get_monitor_name(edid, eld + 20); 3373 3374 eld[4] = (cea[1] << 5) | mnl; 3375 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3376 3377 eld[0] = 2 << 3; /* ELD version: 2 */ 3378 3379 eld[16] = edid->mfg_id[0]; 3380 eld[17] = edid->mfg_id[1]; 3381 eld[18] = edid->prod_code[0]; 3382 eld[19] = edid->prod_code[1]; 3383 3384 if (cea_revision(cea) >= 3) { 3385 int i, start, end; 3386 3387 if (cea_db_offsets(cea, &start, &end)) { 3388 start = 0; 3389 end = 0; 3390 } 3391 3392 for_each_cea_db(cea, i, start, end) { 3393 db = &cea[i]; 3394 dbl = cea_db_payload_len(db); 3395 3396 switch (cea_db_tag(db)) { 3397 int sad_count; 3398 3399 case AUDIO_BLOCK: 3400 /* Audio Data Block, contains SADs */ 3401 sad_count = min(dbl / 3, 15 - total_sad_count); 3402 if (sad_count >= 1) 3403 memcpy(eld + 20 + mnl + total_sad_count * 3, 3404 &db[1], sad_count * 3); 3405 total_sad_count += sad_count; 3406 break; 3407 case SPEAKER_BLOCK: 3408 /* Speaker Allocation Data Block */ 3409 if (dbl >= 1) 3410 eld[7] = db[1]; 3411 break; 3412 case VENDOR_BLOCK: 3413 /* HDMI Vendor-Specific Data Block */ 3414 if (cea_db_is_hdmi_vsdb(db)) 3415 drm_parse_hdmi_vsdb_audio(connector, db); 3416 break; 3417 default: 3418 break; 3419 } 3420 } 3421 } 3422 eld[5] |= total_sad_count << 4; 3423 3424 eld[DRM_ELD_BASELINE_ELD_LEN] = 3425 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3426 3427 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3428 drm_eld_size(eld), total_sad_count); 3429 } 3430 EXPORT_SYMBOL(drm_edid_to_eld); 3431 3432 /** 3433 * drm_edid_to_sad - extracts SADs from EDID 3434 * @edid: EDID to parse 3435 * @sads: pointer that will be set to the extracted SADs 3436 * 3437 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3438 * 3439 * Note: The returned pointer needs to be freed using kfree(). 3440 * 3441 * Return: The number of found SADs or negative number on error. 3442 */ 3443 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3444 { 3445 int count = 0; 3446 int i, start, end, dbl; 3447 u8 *cea; 3448 3449 cea = drm_find_cea_extension(edid); 3450 if (!cea) { 3451 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3452 return -ENOENT; 3453 } 3454 3455 if (cea_revision(cea) < 3) { 3456 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3457 return -ENOTSUPP; 3458 } 3459 3460 if (cea_db_offsets(cea, &start, &end)) { 3461 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3462 return -EPROTO; 3463 } 3464 3465 for_each_cea_db(cea, i, start, end) { 3466 u8 *db = &cea[i]; 3467 3468 if (cea_db_tag(db) == AUDIO_BLOCK) { 3469 int j; 3470 dbl = cea_db_payload_len(db); 3471 3472 count = dbl / 3; /* SAD is 3B */ 3473 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3474 if (!*sads) 3475 return -ENOMEM; 3476 for (j = 0; j < count; j++) { 3477 u8 *sad = &db[1 + j * 3]; 3478 3479 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3480 (*sads)[j].channels = sad[0] & 0x7; 3481 (*sads)[j].freq = sad[1] & 0x7F; 3482 (*sads)[j].byte2 = sad[2]; 3483 } 3484 break; 3485 } 3486 } 3487 3488 return count; 3489 } 3490 EXPORT_SYMBOL(drm_edid_to_sad); 3491 3492 /** 3493 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3494 * @edid: EDID to parse 3495 * @sadb: pointer to the speaker block 3496 * 3497 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3498 * 3499 * Note: The returned pointer needs to be freed using kfree(). 3500 * 3501 * Return: The number of found Speaker Allocation Blocks or negative number on 3502 * error. 3503 */ 3504 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3505 { 3506 int count = 0; 3507 int i, start, end, dbl; 3508 const u8 *cea; 3509 3510 cea = drm_find_cea_extension(edid); 3511 if (!cea) { 3512 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3513 return -ENOENT; 3514 } 3515 3516 if (cea_revision(cea) < 3) { 3517 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3518 return -ENOTSUPP; 3519 } 3520 3521 if (cea_db_offsets(cea, &start, &end)) { 3522 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3523 return -EPROTO; 3524 } 3525 3526 for_each_cea_db(cea, i, start, end) { 3527 const u8 *db = &cea[i]; 3528 3529 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3530 dbl = cea_db_payload_len(db); 3531 3532 /* Speaker Allocation Data Block */ 3533 if (dbl == 3) { 3534 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3535 if (!*sadb) 3536 return -ENOMEM; 3537 count = dbl; 3538 break; 3539 } 3540 } 3541 } 3542 3543 return count; 3544 } 3545 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3546 3547 /** 3548 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3549 * @connector: connector associated with the HDMI/DP sink 3550 * @mode: the display mode 3551 * 3552 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3553 * the sink doesn't support audio or video. 3554 */ 3555 int drm_av_sync_delay(struct drm_connector *connector, 3556 const struct drm_display_mode *mode) 3557 { 3558 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3559 int a, v; 3560 3561 if (!connector->latency_present[0]) 3562 return 0; 3563 if (!connector->latency_present[1]) 3564 i = 0; 3565 3566 a = connector->audio_latency[i]; 3567 v = connector->video_latency[i]; 3568 3569 /* 3570 * HDMI/DP sink doesn't support audio or video? 3571 */ 3572 if (a == 255 || v == 255) 3573 return 0; 3574 3575 /* 3576 * Convert raw EDID values to millisecond. 3577 * Treat unknown latency as 0ms. 3578 */ 3579 if (a) 3580 a = min(2 * (a - 1), 500); 3581 if (v) 3582 v = min(2 * (v - 1), 500); 3583 3584 return max(v - a, 0); 3585 } 3586 EXPORT_SYMBOL(drm_av_sync_delay); 3587 3588 /** 3589 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3590 * @encoder: the encoder just changed display mode 3591 * 3592 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3593 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3594 * 3595 * Return: The connector associated with the first HDMI/DP sink that has ELD 3596 * attached to it. 3597 */ 3598 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3599 { 3600 struct drm_connector *connector; 3601 struct drm_device *dev = encoder->dev; 3602 3603 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3604 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3605 3606 drm_for_each_connector(connector, dev) 3607 if (connector->encoder == encoder && connector->eld[0]) 3608 return connector; 3609 3610 return NULL; 3611 } 3612 EXPORT_SYMBOL(drm_select_eld); 3613 3614 /** 3615 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3616 * @edid: monitor EDID information 3617 * 3618 * Parse the CEA extension according to CEA-861-B. 3619 * 3620 * Return: True if the monitor is HDMI, false if not or unknown. 3621 */ 3622 bool drm_detect_hdmi_monitor(struct edid *edid) 3623 { 3624 u8 *edid_ext; 3625 int i; 3626 int start_offset, end_offset; 3627 3628 edid_ext = drm_find_cea_extension(edid); 3629 if (!edid_ext) 3630 return false; 3631 3632 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3633 return false; 3634 3635 /* 3636 * Because HDMI identifier is in Vendor Specific Block, 3637 * search it from all data blocks of CEA extension. 3638 */ 3639 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3640 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3641 return true; 3642 } 3643 3644 return false; 3645 } 3646 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3647 3648 /** 3649 * drm_detect_monitor_audio - check monitor audio capability 3650 * @edid: EDID block to scan 3651 * 3652 * Monitor should have CEA extension block. 3653 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3654 * audio' only. If there is any audio extension block and supported 3655 * audio format, assume at least 'basic audio' support, even if 'basic 3656 * audio' is not defined in EDID. 3657 * 3658 * Return: True if the monitor supports audio, false otherwise. 3659 */ 3660 bool drm_detect_monitor_audio(struct edid *edid) 3661 { 3662 u8 *edid_ext; 3663 int i, j; 3664 bool has_audio = false; 3665 int start_offset, end_offset; 3666 3667 edid_ext = drm_find_cea_extension(edid); 3668 if (!edid_ext) 3669 goto end; 3670 3671 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3672 3673 if (has_audio) { 3674 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3675 goto end; 3676 } 3677 3678 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3679 goto end; 3680 3681 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3682 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3683 has_audio = true; 3684 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3685 DRM_DEBUG_KMS("CEA audio format %d\n", 3686 (edid_ext[i + j] >> 3) & 0xf); 3687 goto end; 3688 } 3689 } 3690 end: 3691 return has_audio; 3692 } 3693 EXPORT_SYMBOL(drm_detect_monitor_audio); 3694 3695 /** 3696 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3697 * @edid: EDID block to scan 3698 * 3699 * Check whether the monitor reports the RGB quantization range selection 3700 * as supported. The AVI infoframe can then be used to inform the monitor 3701 * which quantization range (full or limited) is used. 3702 * 3703 * Return: True if the RGB quantization range is selectable, false otherwise. 3704 */ 3705 bool drm_rgb_quant_range_selectable(struct edid *edid) 3706 { 3707 u8 *edid_ext; 3708 int i, start, end; 3709 3710 edid_ext = drm_find_cea_extension(edid); 3711 if (!edid_ext) 3712 return false; 3713 3714 if (cea_db_offsets(edid_ext, &start, &end)) 3715 return false; 3716 3717 for_each_cea_db(edid_ext, i, start, end) { 3718 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3719 cea_db_payload_len(&edid_ext[i]) == 2) { 3720 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3721 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3722 } 3723 } 3724 3725 return false; 3726 } 3727 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3728 3729 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 3730 const u8 *hdmi) 3731 { 3732 struct drm_display_info *info = &connector->display_info; 3733 unsigned int dc_bpc = 0; 3734 3735 /* HDMI supports at least 8 bpc */ 3736 info->bpc = 8; 3737 3738 if (cea_db_payload_len(hdmi) < 6) 3739 return; 3740 3741 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3742 dc_bpc = 10; 3743 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3744 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3745 connector->name); 3746 } 3747 3748 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3749 dc_bpc = 12; 3750 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3751 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3752 connector->name); 3753 } 3754 3755 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3756 dc_bpc = 16; 3757 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3758 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3759 connector->name); 3760 } 3761 3762 if (dc_bpc == 0) { 3763 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3764 connector->name); 3765 return; 3766 } 3767 3768 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3769 connector->name, dc_bpc); 3770 info->bpc = dc_bpc; 3771 3772 /* 3773 * Deep color support mandates RGB444 support for all video 3774 * modes and forbids YCRCB422 support for all video modes per 3775 * HDMI 1.3 spec. 3776 */ 3777 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3778 3779 /* YCRCB444 is optional according to spec. */ 3780 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3781 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3782 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3783 connector->name); 3784 } 3785 3786 /* 3787 * Spec says that if any deep color mode is supported at all, 3788 * then deep color 36 bit must be supported. 3789 */ 3790 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3791 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3792 connector->name); 3793 } 3794 } 3795 3796 static void 3797 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 3798 { 3799 struct drm_display_info *info = &connector->display_info; 3800 u8 len = cea_db_payload_len(db); 3801 3802 if (len >= 6) 3803 info->dvi_dual = db[6] & 1; 3804 if (len >= 7) 3805 info->max_tmds_clock = db[7] * 5000; 3806 3807 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3808 "max TMDS clock %d kHz\n", 3809 info->dvi_dual, 3810 info->max_tmds_clock); 3811 3812 drm_parse_hdmi_deep_color_info(connector, db); 3813 } 3814 3815 static void drm_parse_cea_ext(struct drm_connector *connector, 3816 struct edid *edid) 3817 { 3818 struct drm_display_info *info = &connector->display_info; 3819 const u8 *edid_ext; 3820 int i, start, end; 3821 3822 edid_ext = drm_find_cea_extension(edid); 3823 if (!edid_ext) 3824 return; 3825 3826 info->cea_rev = edid_ext[1]; 3827 3828 /* The existence of a CEA block should imply RGB support */ 3829 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3830 if (edid_ext[3] & EDID_CEA_YCRCB444) 3831 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3832 if (edid_ext[3] & EDID_CEA_YCRCB422) 3833 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3834 3835 if (cea_db_offsets(edid_ext, &start, &end)) 3836 return; 3837 3838 for_each_cea_db(edid_ext, i, start, end) { 3839 const u8 *db = &edid_ext[i]; 3840 3841 if (cea_db_is_hdmi_vsdb(db)) 3842 drm_parse_hdmi_vsdb_video(connector, db); 3843 } 3844 } 3845 3846 static void drm_add_display_info(struct drm_connector *connector, 3847 struct edid *edid) 3848 { 3849 struct drm_display_info *info = &connector->display_info; 3850 3851 info->width_mm = edid->width_cm * 10; 3852 info->height_mm = edid->height_cm * 10; 3853 3854 /* driver figures it out in this case */ 3855 info->bpc = 0; 3856 info->color_formats = 0; 3857 info->cea_rev = 0; 3858 info->max_tmds_clock = 0; 3859 info->dvi_dual = false; 3860 3861 if (edid->revision < 3) 3862 return; 3863 3864 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3865 return; 3866 3867 drm_parse_cea_ext(connector, edid); 3868 3869 /* 3870 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3871 * 3872 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3873 * tells us to assume 8 bpc color depth if the EDID doesn't have 3874 * extensions which tell otherwise. 3875 */ 3876 if ((info->bpc == 0) && (edid->revision < 4) && 3877 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3878 info->bpc = 8; 3879 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 3880 connector->name, info->bpc); 3881 } 3882 3883 /* Only defined for 1.4 with digital displays */ 3884 if (edid->revision < 4) 3885 return; 3886 3887 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3888 case DRM_EDID_DIGITAL_DEPTH_6: 3889 info->bpc = 6; 3890 break; 3891 case DRM_EDID_DIGITAL_DEPTH_8: 3892 info->bpc = 8; 3893 break; 3894 case DRM_EDID_DIGITAL_DEPTH_10: 3895 info->bpc = 10; 3896 break; 3897 case DRM_EDID_DIGITAL_DEPTH_12: 3898 info->bpc = 12; 3899 break; 3900 case DRM_EDID_DIGITAL_DEPTH_14: 3901 info->bpc = 14; 3902 break; 3903 case DRM_EDID_DIGITAL_DEPTH_16: 3904 info->bpc = 16; 3905 break; 3906 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3907 default: 3908 info->bpc = 0; 3909 break; 3910 } 3911 3912 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3913 connector->name, info->bpc); 3914 3915 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3916 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3917 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3918 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3919 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3920 } 3921 3922 static int validate_displayid(u8 *displayid, int length, int idx) 3923 { 3924 int i; 3925 u8 csum = 0; 3926 struct displayid_hdr *base; 3927 3928 base = (struct displayid_hdr *)&displayid[idx]; 3929 3930 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 3931 base->rev, base->bytes, base->prod_id, base->ext_count); 3932 3933 if (base->bytes + 5 > length - idx) 3934 return -EINVAL; 3935 for (i = idx; i <= base->bytes + 5; i++) { 3936 csum += displayid[i]; 3937 } 3938 if (csum) { 3939 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); 3940 return -EINVAL; 3941 } 3942 return 0; 3943 } 3944 3945 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 3946 struct displayid_detailed_timings_1 *timings) 3947 { 3948 struct drm_display_mode *mode; 3949 unsigned pixel_clock = (timings->pixel_clock[0] | 3950 (timings->pixel_clock[1] << 8) | 3951 (timings->pixel_clock[2] << 16)); 3952 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 3953 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 3954 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 3955 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 3956 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 3957 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 3958 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 3959 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 3960 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 3961 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 3962 mode = drm_mode_create(dev); 3963 if (!mode) 3964 return NULL; 3965 3966 mode->clock = pixel_clock * 10; 3967 mode->hdisplay = hactive; 3968 mode->hsync_start = mode->hdisplay + hsync; 3969 mode->hsync_end = mode->hsync_start + hsync_width; 3970 mode->htotal = mode->hdisplay + hblank; 3971 3972 mode->vdisplay = vactive; 3973 mode->vsync_start = mode->vdisplay + vsync; 3974 mode->vsync_end = mode->vsync_start + vsync_width; 3975 mode->vtotal = mode->vdisplay + vblank; 3976 3977 mode->flags = 0; 3978 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3979 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3980 mode->type = DRM_MODE_TYPE_DRIVER; 3981 3982 if (timings->flags & 0x80) 3983 mode->type |= DRM_MODE_TYPE_PREFERRED; 3984 mode->vrefresh = drm_mode_vrefresh(mode); 3985 drm_mode_set_name(mode); 3986 3987 return mode; 3988 } 3989 3990 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 3991 struct displayid_block *block) 3992 { 3993 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 3994 int i; 3995 int num_timings; 3996 struct drm_display_mode *newmode; 3997 int num_modes = 0; 3998 /* blocks must be multiple of 20 bytes length */ 3999 if (block->num_bytes % 20) 4000 return 0; 4001 4002 num_timings = block->num_bytes / 20; 4003 for (i = 0; i < num_timings; i++) { 4004 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4005 4006 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4007 if (!newmode) 4008 continue; 4009 4010 drm_mode_probed_add(connector, newmode); 4011 num_modes++; 4012 } 4013 return num_modes; 4014 } 4015 4016 static int add_displayid_detailed_modes(struct drm_connector *connector, 4017 struct edid *edid) 4018 { 4019 u8 *displayid; 4020 int ret; 4021 int idx = 1; 4022 int length = EDID_LENGTH; 4023 struct displayid_block *block; 4024 int num_modes = 0; 4025 4026 displayid = drm_find_displayid_extension(edid); 4027 if (!displayid) 4028 return 0; 4029 4030 ret = validate_displayid(displayid, length, idx); 4031 if (ret) 4032 return 0; 4033 4034 idx += sizeof(struct displayid_hdr); 4035 while (block = (struct displayid_block *)&displayid[idx], 4036 idx + sizeof(struct displayid_block) <= length && 4037 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4038 block->num_bytes > 0) { 4039 idx += block->num_bytes + sizeof(struct displayid_block); 4040 switch (block->tag) { 4041 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4042 num_modes += add_displayid_detailed_1_modes(connector, block); 4043 break; 4044 } 4045 } 4046 return num_modes; 4047 } 4048 4049 /** 4050 * drm_add_edid_modes - add modes from EDID data, if available 4051 * @connector: connector we're probing 4052 * @edid: EDID data 4053 * 4054 * Add the specified modes to the connector's mode list. Also fills out the 4055 * &drm_display_info structure in @connector with any information which can be 4056 * derived from the edid. 4057 * 4058 * Return: The number of modes added or 0 if we couldn't find any. 4059 */ 4060 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4061 { 4062 int num_modes = 0; 4063 u32 quirks; 4064 4065 if (edid == NULL) { 4066 return 0; 4067 } 4068 if (!drm_edid_is_valid(edid)) { 4069 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4070 connector->name); 4071 return 0; 4072 } 4073 4074 quirks = edid_get_quirks(edid); 4075 4076 /* 4077 * EDID spec says modes should be preferred in this order: 4078 * - preferred detailed mode 4079 * - other detailed modes from base block 4080 * - detailed modes from extension blocks 4081 * - CVT 3-byte code modes 4082 * - standard timing codes 4083 * - established timing codes 4084 * - modes inferred from GTF or CVT range information 4085 * 4086 * We get this pretty much right. 4087 * 4088 * XXX order for additional mode types in extension blocks? 4089 */ 4090 num_modes += add_detailed_modes(connector, edid, quirks); 4091 num_modes += add_cvt_modes(connector, edid); 4092 num_modes += add_standard_modes(connector, edid); 4093 num_modes += add_established_modes(connector, edid); 4094 num_modes += add_cea_modes(connector, edid); 4095 num_modes += add_alternate_cea_modes(connector, edid); 4096 num_modes += add_displayid_detailed_modes(connector, edid); 4097 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4098 num_modes += add_inferred_modes(connector, edid); 4099 4100 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4101 edid_fixup_preferred(connector, quirks); 4102 4103 drm_add_display_info(connector, edid); 4104 4105 if (quirks & EDID_QUIRK_FORCE_6BPC) 4106 connector->display_info.bpc = 6; 4107 4108 if (quirks & EDID_QUIRK_FORCE_8BPC) 4109 connector->display_info.bpc = 8; 4110 4111 if (quirks & EDID_QUIRK_FORCE_12BPC) 4112 connector->display_info.bpc = 12; 4113 4114 return num_modes; 4115 } 4116 EXPORT_SYMBOL(drm_add_edid_modes); 4117 4118 /** 4119 * drm_add_modes_noedid - add modes for the connectors without EDID 4120 * @connector: connector we're probing 4121 * @hdisplay: the horizontal display limit 4122 * @vdisplay: the vertical display limit 4123 * 4124 * Add the specified modes to the connector's mode list. Only when the 4125 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4126 * 4127 * Return: The number of modes added or 0 if we couldn't find any. 4128 */ 4129 int drm_add_modes_noedid(struct drm_connector *connector, 4130 int hdisplay, int vdisplay) 4131 { 4132 int i, count, num_modes = 0; 4133 struct drm_display_mode *mode; 4134 struct drm_device *dev = connector->dev; 4135 4136 count = ARRAY_SIZE(drm_dmt_modes); 4137 if (hdisplay < 0) 4138 hdisplay = 0; 4139 if (vdisplay < 0) 4140 vdisplay = 0; 4141 4142 for (i = 0; i < count; i++) { 4143 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4144 if (hdisplay && vdisplay) { 4145 /* 4146 * Only when two are valid, they will be used to check 4147 * whether the mode should be added to the mode list of 4148 * the connector. 4149 */ 4150 if (ptr->hdisplay > hdisplay || 4151 ptr->vdisplay > vdisplay) 4152 continue; 4153 } 4154 if (drm_mode_vrefresh(ptr) > 61) 4155 continue; 4156 mode = drm_mode_duplicate(dev, ptr); 4157 if (mode) { 4158 drm_mode_probed_add(connector, mode); 4159 num_modes++; 4160 } 4161 } 4162 return num_modes; 4163 } 4164 EXPORT_SYMBOL(drm_add_modes_noedid); 4165 4166 /** 4167 * drm_set_preferred_mode - Sets the preferred mode of a connector 4168 * @connector: connector whose mode list should be processed 4169 * @hpref: horizontal resolution of preferred mode 4170 * @vpref: vertical resolution of preferred mode 4171 * 4172 * Marks a mode as preferred if it matches the resolution specified by @hpref 4173 * and @vpref. 4174 */ 4175 void drm_set_preferred_mode(struct drm_connector *connector, 4176 int hpref, int vpref) 4177 { 4178 struct drm_display_mode *mode; 4179 4180 list_for_each_entry(mode, &connector->probed_modes, head) { 4181 if (mode->hdisplay == hpref && 4182 mode->vdisplay == vpref) 4183 mode->type |= DRM_MODE_TYPE_PREFERRED; 4184 } 4185 } 4186 EXPORT_SYMBOL(drm_set_preferred_mode); 4187 4188 /** 4189 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4190 * data from a DRM display mode 4191 * @frame: HDMI AVI infoframe 4192 * @mode: DRM display mode 4193 * 4194 * Return: 0 on success or a negative error code on failure. 4195 */ 4196 int 4197 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4198 const struct drm_display_mode *mode) 4199 { 4200 int err; 4201 4202 if (!frame || !mode) 4203 return -EINVAL; 4204 4205 err = hdmi_avi_infoframe_init(frame); 4206 if (err < 0) 4207 return err; 4208 4209 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4210 frame->pixel_repeat = 1; 4211 4212 frame->video_code = drm_match_cea_mode(mode); 4213 4214 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4215 4216 /* 4217 * Populate picture aspect ratio from either 4218 * user input (if specified) or from the CEA mode list. 4219 */ 4220 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4221 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4222 frame->picture_aspect = mode->picture_aspect_ratio; 4223 else if (frame->video_code > 0) 4224 frame->picture_aspect = drm_get_cea_aspect_ratio( 4225 frame->video_code); 4226 4227 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4228 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4229 4230 return 0; 4231 } 4232 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4233 4234 static enum hdmi_3d_structure 4235 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4236 { 4237 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4238 4239 switch (layout) { 4240 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4241 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4242 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4243 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4244 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4245 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4246 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4247 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4248 case DRM_MODE_FLAG_3D_L_DEPTH: 4249 return HDMI_3D_STRUCTURE_L_DEPTH; 4250 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4251 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4252 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4253 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4254 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4255 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4256 default: 4257 return HDMI_3D_STRUCTURE_INVALID; 4258 } 4259 } 4260 4261 /** 4262 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4263 * data from a DRM display mode 4264 * @frame: HDMI vendor infoframe 4265 * @mode: DRM display mode 4266 * 4267 * Note that there's is a need to send HDMI vendor infoframes only when using a 4268 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4269 * function will return -EINVAL, error that can be safely ignored. 4270 * 4271 * Return: 0 on success or a negative error code on failure. 4272 */ 4273 int 4274 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4275 const struct drm_display_mode *mode) 4276 { 4277 int err; 4278 u32 s3d_flags; 4279 u8 vic; 4280 4281 if (!frame || !mode) 4282 return -EINVAL; 4283 4284 vic = drm_match_hdmi_mode(mode); 4285 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4286 4287 if (!vic && !s3d_flags) 4288 return -EINVAL; 4289 4290 if (vic && s3d_flags) 4291 return -EINVAL; 4292 4293 err = hdmi_vendor_infoframe_init(frame); 4294 if (err < 0) 4295 return err; 4296 4297 if (vic) 4298 frame->vic = vic; 4299 else 4300 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4301 4302 return 0; 4303 } 4304 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4305 4306 static int drm_parse_tiled_block(struct drm_connector *connector, 4307 struct displayid_block *block) 4308 { 4309 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4310 u16 w, h; 4311 u8 tile_v_loc, tile_h_loc; 4312 u8 num_v_tile, num_h_tile; 4313 struct drm_tile_group *tg; 4314 4315 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4316 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4317 4318 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4319 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4320 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4321 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4322 4323 connector->has_tile = true; 4324 if (tile->tile_cap & 0x80) 4325 connector->tile_is_single_monitor = true; 4326 4327 connector->num_h_tile = num_h_tile + 1; 4328 connector->num_v_tile = num_v_tile + 1; 4329 connector->tile_h_loc = tile_h_loc; 4330 connector->tile_v_loc = tile_v_loc; 4331 connector->tile_h_size = w + 1; 4332 connector->tile_v_size = h + 1; 4333 4334 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4335 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4336 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4337 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4338 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4339 4340 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4341 if (!tg) { 4342 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4343 } 4344 if (!tg) 4345 return -ENOMEM; 4346 4347 if (connector->tile_group != tg) { 4348 /* if we haven't got a pointer, 4349 take the reference, drop ref to old tile group */ 4350 if (connector->tile_group) { 4351 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4352 } 4353 connector->tile_group = tg; 4354 } else 4355 /* if same tile group, then release the ref we just took. */ 4356 drm_mode_put_tile_group(connector->dev, tg); 4357 return 0; 4358 } 4359 4360 static int drm_parse_display_id(struct drm_connector *connector, 4361 u8 *displayid, int length, 4362 bool is_edid_extension) 4363 { 4364 /* if this is an EDID extension the first byte will be 0x70 */ 4365 int idx = 0; 4366 struct displayid_block *block; 4367 int ret; 4368 4369 if (is_edid_extension) 4370 idx = 1; 4371 4372 ret = validate_displayid(displayid, length, idx); 4373 if (ret) 4374 return ret; 4375 4376 idx += sizeof(struct displayid_hdr); 4377 while (block = (struct displayid_block *)&displayid[idx], 4378 idx + sizeof(struct displayid_block) <= length && 4379 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4380 block->num_bytes > 0) { 4381 idx += block->num_bytes + sizeof(struct displayid_block); 4382 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 4383 block->tag, block->rev, block->num_bytes); 4384 4385 switch (block->tag) { 4386 case DATA_BLOCK_TILED_DISPLAY: 4387 ret = drm_parse_tiled_block(connector, block); 4388 if (ret) 4389 return ret; 4390 break; 4391 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4392 /* handled in mode gathering code. */ 4393 break; 4394 default: 4395 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 4396 break; 4397 } 4398 } 4399 return 0; 4400 } 4401 4402 static void drm_get_displayid(struct drm_connector *connector, 4403 struct edid *edid) 4404 { 4405 void *displayid = NULL; 4406 int ret; 4407 connector->has_tile = false; 4408 displayid = drm_find_displayid_extension(edid); 4409 if (!displayid) { 4410 /* drop reference to any tile group we had */ 4411 goto out_drop_ref; 4412 } 4413 4414 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4415 if (ret < 0) 4416 goto out_drop_ref; 4417 if (!connector->has_tile) 4418 goto out_drop_ref; 4419 return; 4420 out_drop_ref: 4421 if (connector->tile_group) { 4422 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4423 connector->tile_group = NULL; 4424 } 4425 return; 4426 } 4427