1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/module.h> 34 #include <drm/drmP.h> 35 #include <drm/drm_edid.h> 36 #include <linux/string.h> 37 38 #include <bus/iicbus/iic.h> 39 #include <bus/iicbus/iiconf.h> 40 #include "iicbus_if.h" 41 42 #define version_greater(edid, maj, min) \ 43 (((edid)->version > (maj)) || \ 44 ((edid)->version == (maj) && (edid)->revision > (min))) 45 46 #define EDID_EST_TIMINGS 16 47 #define EDID_STD_TIMINGS 8 48 #define EDID_DETAILED_TIMINGS 4 49 50 /* 51 * EDID blocks out in the wild have a variety of bugs, try to collect 52 * them here (note that userspace may work around broken monitors first, 53 * but fixes should make their way here so that the kernel "just works" 54 * on as many displays as possible). 55 */ 56 57 /* First detailed mode wrong, use largest 60Hz mode */ 58 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 59 /* Reported 135MHz pixel clock is too high, needs adjustment */ 60 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 61 /* Prefer the largest mode at 75 Hz */ 62 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 63 /* Detail timing is in cm not mm */ 64 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 65 /* Detailed timing descriptors have bogus size values, so just take the 66 * maximum size and use that. 67 */ 68 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 69 /* Monitor forgot to set the first detailed is preferred bit. */ 70 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 71 /* use +hsync +vsync for detailed mode */ 72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 73 /* Force reduced-blanking timings for detailed modes */ 74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 75 /* Force 8bpc */ 76 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 77 /* Force 12bpc */ 78 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 79 80 struct detailed_mode_closure { 81 struct drm_connector *connector; 82 struct edid *edid; 83 bool preferred; 84 u32 quirks; 85 int modes; 86 }; 87 88 #define LEVEL_DMT 0 89 #define LEVEL_GTF 1 90 #define LEVEL_GTF2 2 91 #define LEVEL_CVT 3 92 93 static struct edid_quirk { 94 char vendor[4]; 95 int product_id; 96 u32 quirks; 97 } edid_quirk_list[] = { 98 /* Acer AL1706 */ 99 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 100 /* Acer F51 */ 101 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 102 /* Unknown Acer */ 103 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 104 105 /* Belinea 10 15 55 */ 106 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 107 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 108 109 /* Envision Peripherals, Inc. EN-7100e */ 110 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 111 /* Envision EN2028 */ 112 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 113 114 /* Funai Electronics PM36B */ 115 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 116 EDID_QUIRK_DETAILED_IN_CM }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 }; 146 147 /* 148 * Autogenerated from the DMT spec. 149 * This table is copied from xfree86/modes/xf86EdidModes.c. 150 */ 151 static const struct drm_display_mode drm_dmt_modes[] = { 152 /* 0x01 - 640x350@85Hz */ 153 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 154 736, 832, 0, 350, 382, 385, 445, 0, 155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 156 /* 0x02 - 640x400@85Hz */ 157 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 158 736, 832, 0, 400, 401, 404, 445, 0, 159 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 160 /* 0x03 - 720x400@85Hz */ 161 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 162 828, 936, 0, 400, 401, 404, 446, 0, 163 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 164 /* 0x04 - 640x480@60Hz */ 165 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 166 752, 800, 0, 480, 490, 492, 525, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 168 /* 0x05 - 640x480@72Hz */ 169 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 170 704, 832, 0, 480, 489, 492, 520, 0, 171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 172 /* 0x06 - 640x480@75Hz */ 173 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 174 720, 840, 0, 480, 481, 484, 500, 0, 175 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 176 /* 0x07 - 640x480@85Hz */ 177 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 178 752, 832, 0, 480, 481, 484, 509, 0, 179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 180 /* 0x08 - 800x600@56Hz */ 181 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 182 896, 1024, 0, 600, 601, 603, 625, 0, 183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 184 /* 0x09 - 800x600@60Hz */ 185 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 186 968, 1056, 0, 600, 601, 605, 628, 0, 187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 188 /* 0x0a - 800x600@72Hz */ 189 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 190 976, 1040, 0, 600, 637, 643, 666, 0, 191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 192 /* 0x0b - 800x600@75Hz */ 193 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 194 896, 1056, 0, 600, 601, 604, 625, 0, 195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 196 /* 0x0c - 800x600@85Hz */ 197 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 198 896, 1048, 0, 600, 601, 604, 631, 0, 199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 200 /* 0x0d - 800x600@120Hz RB */ 201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 202 880, 960, 0, 600, 603, 607, 636, 0, 203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 204 /* 0x0e - 848x480@60Hz */ 205 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 206 976, 1088, 0, 480, 486, 494, 517, 0, 207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 208 /* 0x0f - 1024x768@43Hz, interlace */ 209 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 210 1208, 1264, 0, 768, 768, 772, 817, 0, 211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 212 DRM_MODE_FLAG_INTERLACE) }, 213 /* 0x10 - 1024x768@60Hz */ 214 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 215 1184, 1344, 0, 768, 771, 777, 806, 0, 216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 217 /* 0x11 - 1024x768@70Hz */ 218 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 219 1184, 1328, 0, 768, 771, 777, 806, 0, 220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 221 /* 0x12 - 1024x768@75Hz */ 222 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 223 1136, 1312, 0, 768, 769, 772, 800, 0, 224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 225 /* 0x13 - 1024x768@85Hz */ 226 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 227 1168, 1376, 0, 768, 769, 772, 808, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 229 /* 0x14 - 1024x768@120Hz RB */ 230 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 231 1104, 1184, 0, 768, 771, 775, 813, 0, 232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 233 /* 0x15 - 1152x864@75Hz */ 234 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 235 1344, 1600, 0, 864, 865, 868, 900, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x55 - 1280x720@60Hz */ 238 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 239 1430, 1650, 0, 720, 725, 730, 750, 0, 240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 241 /* 0x16 - 1280x768@60Hz RB */ 242 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 243 1360, 1440, 0, 768, 771, 778, 790, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x17 - 1280x768@60Hz */ 246 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 247 1472, 1664, 0, 768, 771, 778, 798, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x18 - 1280x768@75Hz */ 250 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 251 1488, 1696, 0, 768, 771, 778, 805, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 0x19 - 1280x768@85Hz */ 254 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 255 1496, 1712, 0, 768, 771, 778, 809, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x1a - 1280x768@120Hz RB */ 258 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 259 1360, 1440, 0, 768, 771, 778, 813, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x1b - 1280x800@60Hz RB */ 262 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 263 1360, 1440, 0, 800, 803, 809, 823, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 0x1c - 1280x800@60Hz */ 266 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 267 1480, 1680, 0, 800, 803, 809, 831, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x1d - 1280x800@75Hz */ 270 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 271 1488, 1696, 0, 800, 803, 809, 838, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x1e - 1280x800@85Hz */ 274 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 275 1496, 1712, 0, 800, 803, 809, 843, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x1f - 1280x800@120Hz RB */ 278 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 279 1360, 1440, 0, 800, 803, 809, 847, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 281 /* 0x20 - 1280x960@60Hz */ 282 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 283 1488, 1800, 0, 960, 961, 964, 1000, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 0x21 - 1280x960@85Hz */ 286 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 287 1504, 1728, 0, 960, 961, 964, 1011, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x22 - 1280x960@120Hz RB */ 290 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 291 1360, 1440, 0, 960, 963, 967, 1017, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x23 - 1280x1024@60Hz */ 294 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 295 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x24 - 1280x1024@75Hz */ 298 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 299 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x25 - 1280x1024@85Hz */ 302 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 303 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 0x26 - 1280x1024@120Hz RB */ 306 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 307 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x27 - 1360x768@60Hz */ 310 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 311 1536, 1792, 0, 768, 771, 777, 795, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x28 - 1360x768@120Hz RB */ 314 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 315 1440, 1520, 0, 768, 771, 776, 813, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 0x51 - 1366x768@60Hz */ 318 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 319 1579, 1792, 0, 768, 771, 774, 798, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x56 - 1366x768@60Hz */ 322 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 323 1436, 1500, 0, 768, 769, 772, 800, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x29 - 1400x1050@60Hz RB */ 326 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 327 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 329 /* 0x2a - 1400x1050@60Hz */ 330 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 331 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 332 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x2b - 1400x1050@75Hz */ 334 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 335 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 337 /* 0x2c - 1400x1050@85Hz */ 338 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 339 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x2d - 1400x1050@120Hz RB */ 342 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 343 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 345 /* 0x2e - 1440x900@60Hz RB */ 346 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 347 1520, 1600, 0, 900, 903, 909, 926, 0, 348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 349 /* 0x2f - 1440x900@60Hz */ 350 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 351 1672, 1904, 0, 900, 903, 909, 934, 0, 352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 353 /* 0x30 - 1440x900@75Hz */ 354 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 355 1688, 1936, 0, 900, 903, 909, 942, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x31 - 1440x900@85Hz */ 358 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 359 1696, 1952, 0, 900, 903, 909, 948, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x32 - 1440x900@120Hz RB */ 362 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 363 1520, 1600, 0, 900, 903, 909, 953, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 365 /* 0x53 - 1600x900@60Hz */ 366 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 367 1704, 1800, 0, 900, 901, 904, 1000, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x33 - 1600x1200@60Hz */ 370 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 371 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x34 - 1600x1200@65Hz */ 374 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 375 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x35 - 1600x1200@70Hz */ 378 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 379 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x36 - 1600x1200@75Hz */ 382 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 383 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x37 - 1600x1200@85Hz */ 386 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 387 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x38 - 1600x1200@120Hz RB */ 390 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 391 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 393 /* 0x39 - 1680x1050@60Hz RB */ 394 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 395 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 397 /* 0x3a - 1680x1050@60Hz */ 398 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 399 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 400 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 0x3b - 1680x1050@75Hz */ 402 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 403 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x3c - 1680x1050@85Hz */ 406 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 407 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x3d - 1680x1050@120Hz RB */ 410 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 411 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 413 /* 0x3e - 1792x1344@60Hz */ 414 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 415 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x3f - 1792x1344@75Hz */ 418 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 419 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 421 /* 0x40 - 1792x1344@120Hz RB */ 422 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 423 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 425 /* 0x41 - 1856x1392@60Hz */ 426 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 427 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x42 - 1856x1392@75Hz */ 430 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 431 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x43 - 1856x1392@120Hz RB */ 434 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 435 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x52 - 1920x1080@60Hz */ 438 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 439 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 441 /* 0x44 - 1920x1200@60Hz RB */ 442 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 443 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 445 /* 0x45 - 1920x1200@60Hz */ 446 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 447 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x46 - 1920x1200@75Hz */ 450 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 451 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x47 - 1920x1200@85Hz */ 454 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 455 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x48 - 1920x1200@120Hz RB */ 458 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 459 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 461 /* 0x49 - 1920x1440@60Hz */ 462 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 463 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x4a - 1920x1440@75Hz */ 466 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 467 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 0x4b - 1920x1440@120Hz RB */ 470 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 471 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 473 /* 0x54 - 2048x1152@60Hz */ 474 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 475 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x4c - 2560x1600@60Hz RB */ 478 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 479 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 481 /* 0x4d - 2560x1600@60Hz */ 482 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 483 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 485 /* 0x4e - 2560x1600@75Hz */ 486 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 487 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x4f - 2560x1600@85Hz */ 490 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 491 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x50 - 2560x1600@120Hz RB */ 494 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 495 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 497 /* 0x57 - 4096x2160@60Hz RB */ 498 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 499 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 501 /* 0x58 - 4096x2160@59.94Hz RB */ 502 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 503 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 505 }; 506 507 /* 508 * These more or less come from the DMT spec. The 720x400 modes are 509 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 510 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 511 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 512 * mode. 513 * 514 * The DMT modes have been fact-checked; the rest are mild guesses. 515 */ 516 static const struct drm_display_mode edid_est_modes[] = { 517 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 518 968, 1056, 0, 600, 601, 605, 628, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 520 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 521 896, 1024, 0, 600, 601, 603, 625, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 523 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 524 720, 840, 0, 480, 481, 484, 500, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 526 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 527 704, 832, 0, 480, 489, 491, 520, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 529 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 530 768, 864, 0, 480, 483, 486, 525, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 533 752, 800, 0, 480, 490, 492, 525, 0, 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 535 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 536 846, 900, 0, 400, 421, 423, 449, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 538 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 539 846, 900, 0, 400, 412, 414, 449, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 541 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 542 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 544 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 545 1136, 1312, 0, 768, 769, 772, 800, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 547 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 548 1184, 1328, 0, 768, 771, 777, 806, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 550 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 551 1184, 1344, 0, 768, 771, 777, 806, 0, 552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 553 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 554 1208, 1264, 0, 768, 768, 776, 817, 0, 555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 556 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 557 928, 1152, 0, 624, 625, 628, 667, 0, 558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 559 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 560 896, 1056, 0, 600, 601, 604, 625, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 562 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 563 976, 1040, 0, 600, 637, 643, 666, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 565 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 566 1344, 1600, 0, 864, 865, 868, 900, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 568 }; 569 570 struct minimode { 571 short w; 572 short h; 573 short r; 574 short rb; 575 }; 576 577 static const struct minimode est3_modes[] = { 578 /* byte 6 */ 579 { 640, 350, 85, 0 }, 580 { 640, 400, 85, 0 }, 581 { 720, 400, 85, 0 }, 582 { 640, 480, 85, 0 }, 583 { 848, 480, 60, 0 }, 584 { 800, 600, 85, 0 }, 585 { 1024, 768, 85, 0 }, 586 { 1152, 864, 75, 0 }, 587 /* byte 7 */ 588 { 1280, 768, 60, 1 }, 589 { 1280, 768, 60, 0 }, 590 { 1280, 768, 75, 0 }, 591 { 1280, 768, 85, 0 }, 592 { 1280, 960, 60, 0 }, 593 { 1280, 960, 85, 0 }, 594 { 1280, 1024, 60, 0 }, 595 { 1280, 1024, 85, 0 }, 596 /* byte 8 */ 597 { 1360, 768, 60, 0 }, 598 { 1440, 900, 60, 1 }, 599 { 1440, 900, 60, 0 }, 600 { 1440, 900, 75, 0 }, 601 { 1440, 900, 85, 0 }, 602 { 1400, 1050, 60, 1 }, 603 { 1400, 1050, 60, 0 }, 604 { 1400, 1050, 75, 0 }, 605 /* byte 9 */ 606 { 1400, 1050, 85, 0 }, 607 { 1680, 1050, 60, 1 }, 608 { 1680, 1050, 60, 0 }, 609 { 1680, 1050, 75, 0 }, 610 { 1680, 1050, 85, 0 }, 611 { 1600, 1200, 60, 0 }, 612 { 1600, 1200, 65, 0 }, 613 { 1600, 1200, 70, 0 }, 614 /* byte 10 */ 615 { 1600, 1200, 75, 0 }, 616 { 1600, 1200, 85, 0 }, 617 { 1792, 1344, 60, 0 }, 618 { 1792, 1344, 75, 0 }, 619 { 1856, 1392, 60, 0 }, 620 { 1856, 1392, 75, 0 }, 621 { 1920, 1200, 60, 1 }, 622 { 1920, 1200, 60, 0 }, 623 /* byte 11 */ 624 { 1920, 1200, 75, 0 }, 625 { 1920, 1200, 85, 0 }, 626 { 1920, 1440, 60, 0 }, 627 { 1920, 1440, 75, 0 }, 628 }; 629 630 static const struct minimode extra_modes[] = { 631 { 1024, 576, 60, 0 }, 632 { 1366, 768, 60, 0 }, 633 { 1600, 900, 60, 0 }, 634 { 1680, 945, 60, 0 }, 635 { 1920, 1080, 60, 0 }, 636 { 2048, 1152, 60, 0 }, 637 { 2048, 1536, 60, 0 }, 638 }; 639 640 /* 641 * Probably taken from CEA-861 spec. 642 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 643 */ 644 static const struct drm_display_mode edid_cea_modes[] = { 645 /* 1 - 640x480@60Hz */ 646 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 647 752, 800, 0, 480, 490, 492, 525, 0, 648 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 649 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 650 /* 2 - 720x480@60Hz */ 651 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 652 798, 858, 0, 480, 489, 495, 525, 0, 653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 654 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 655 /* 3 - 720x480@60Hz */ 656 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 657 798, 858, 0, 480, 489, 495, 525, 0, 658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 660 /* 4 - 1280x720@60Hz */ 661 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 662 1430, 1650, 0, 720, 725, 730, 750, 0, 663 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 664 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 665 /* 5 - 1920x1080i@60Hz */ 666 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 667 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 669 DRM_MODE_FLAG_INTERLACE), 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 671 /* 6 - 720(1440)x480i@60Hz */ 672 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 673 801, 858, 0, 480, 488, 494, 525, 0, 674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 675 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 677 /* 7 - 720(1440)x480i@60Hz */ 678 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 679 801, 858, 0, 480, 488, 494, 525, 0, 680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 681 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 682 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 683 /* 8 - 720(1440)x240@60Hz */ 684 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 685 801, 858, 0, 240, 244, 247, 262, 0, 686 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 687 DRM_MODE_FLAG_DBLCLK), 688 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 689 /* 9 - 720(1440)x240@60Hz */ 690 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 691 801, 858, 0, 240, 244, 247, 262, 0, 692 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 693 DRM_MODE_FLAG_DBLCLK), 694 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 695 /* 10 - 2880x480i@60Hz */ 696 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 697 3204, 3432, 0, 480, 488, 494, 525, 0, 698 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 699 DRM_MODE_FLAG_INTERLACE), 700 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 701 /* 11 - 2880x480i@60Hz */ 702 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 703 3204, 3432, 0, 480, 488, 494, 525, 0, 704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 705 DRM_MODE_FLAG_INTERLACE), 706 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 707 /* 12 - 2880x240@60Hz */ 708 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 709 3204, 3432, 0, 240, 244, 247, 262, 0, 710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 711 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 712 /* 13 - 2880x240@60Hz */ 713 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 714 3204, 3432, 0, 240, 244, 247, 262, 0, 715 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 717 /* 14 - 1440x480@60Hz */ 718 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 719 1596, 1716, 0, 480, 489, 495, 525, 0, 720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 722 /* 15 - 1440x480@60Hz */ 723 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 724 1596, 1716, 0, 480, 489, 495, 525, 0, 725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 726 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 727 /* 16 - 1920x1080@60Hz */ 728 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 729 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 730 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 732 /* 17 - 720x576@50Hz */ 733 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 734 796, 864, 0, 576, 581, 586, 625, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 736 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 737 /* 18 - 720x576@50Hz */ 738 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 739 796, 864, 0, 576, 581, 586, 625, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 741 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 742 /* 19 - 1280x720@50Hz */ 743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 744 1760, 1980, 0, 720, 725, 730, 750, 0, 745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 746 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 747 /* 20 - 1920x1080i@50Hz */ 748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 749 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 751 DRM_MODE_FLAG_INTERLACE), 752 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 21 - 720(1440)x576i@50Hz */ 754 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 755 795, 864, 0, 576, 580, 586, 625, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 758 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 759 /* 22 - 720(1440)x576i@50Hz */ 760 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 761 795, 864, 0, 576, 580, 586, 625, 0, 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 764 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 765 /* 23 - 720(1440)x288@50Hz */ 766 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 767 795, 864, 0, 288, 290, 293, 312, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 769 DRM_MODE_FLAG_DBLCLK), 770 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 771 /* 24 - 720(1440)x288@50Hz */ 772 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 773 795, 864, 0, 288, 290, 293, 312, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 775 DRM_MODE_FLAG_DBLCLK), 776 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 777 /* 25 - 2880x576i@50Hz */ 778 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 779 3180, 3456, 0, 576, 580, 586, 625, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 781 DRM_MODE_FLAG_INTERLACE), 782 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 783 /* 26 - 2880x576i@50Hz */ 784 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 785 3180, 3456, 0, 576, 580, 586, 625, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 787 DRM_MODE_FLAG_INTERLACE), 788 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 789 /* 27 - 2880x288@50Hz */ 790 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 791 3180, 3456, 0, 288, 290, 293, 312, 0, 792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 793 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 794 /* 28 - 2880x288@50Hz */ 795 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 796 3180, 3456, 0, 288, 290, 293, 312, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 798 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 799 /* 29 - 1440x576@50Hz */ 800 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 801 1592, 1728, 0, 576, 581, 586, 625, 0, 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 804 /* 30 - 1440x576@50Hz */ 805 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 806 1592, 1728, 0, 576, 581, 586, 625, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 809 /* 31 - 1920x1080@50Hz */ 810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 811 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 814 /* 32 - 1920x1080@24Hz */ 815 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 816 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 818 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 819 /* 33 - 1920x1080@25Hz */ 820 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 821 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 823 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 824 /* 34 - 1920x1080@30Hz */ 825 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 826 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 35 - 2880x480@60Hz */ 830 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 831 3192, 3432, 0, 480, 489, 495, 525, 0, 832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 833 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 834 /* 36 - 2880x480@60Hz */ 835 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 836 3192, 3432, 0, 480, 489, 495, 525, 0, 837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 838 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 37 - 2880x576@50Hz */ 840 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 841 3184, 3456, 0, 576, 581, 586, 625, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 844 /* 38 - 2880x576@50Hz */ 845 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 846 3184, 3456, 0, 576, 581, 586, 625, 0, 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 848 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 39 - 1920x1080i@50Hz */ 850 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 851 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 853 DRM_MODE_FLAG_INTERLACE), 854 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 855 /* 40 - 1920x1080i@100Hz */ 856 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 857 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 859 DRM_MODE_FLAG_INTERLACE), 860 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 861 /* 41 - 1280x720@100Hz */ 862 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 863 1760, 1980, 0, 720, 725, 730, 750, 0, 864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 865 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 866 /* 42 - 720x576@100Hz */ 867 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 868 796, 864, 0, 576, 581, 586, 625, 0, 869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 870 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 871 /* 43 - 720x576@100Hz */ 872 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 873 796, 864, 0, 576, 581, 586, 625, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 875 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 876 /* 44 - 720(1440)x576i@100Hz */ 877 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 878 795, 864, 0, 576, 580, 586, 625, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 880 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 881 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 882 /* 45 - 720(1440)x576i@100Hz */ 883 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 884 795, 864, 0, 576, 580, 586, 625, 0, 885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 886 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 887 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 46 - 1920x1080i@120Hz */ 889 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 890 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 892 DRM_MODE_FLAG_INTERLACE), 893 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 894 /* 47 - 1280x720@120Hz */ 895 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 896 1430, 1650, 0, 720, 725, 730, 750, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 48 - 720x480@120Hz */ 900 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 901 798, 858, 0, 480, 489, 495, 525, 0, 902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 903 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 904 /* 49 - 720x480@120Hz */ 905 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 906 798, 858, 0, 480, 489, 495, 525, 0, 907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 50 - 720(1440)x480i@120Hz */ 910 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 911 801, 858, 0, 480, 488, 494, 525, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 913 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 914 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 915 /* 51 - 720(1440)x480i@120Hz */ 916 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 917 801, 858, 0, 480, 488, 494, 525, 0, 918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 919 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 920 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 52 - 720x576@200Hz */ 922 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 923 796, 864, 0, 576, 581, 586, 625, 0, 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 925 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 926 /* 53 - 720x576@200Hz */ 927 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 928 796, 864, 0, 576, 581, 586, 625, 0, 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 930 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 54 - 720(1440)x576i@200Hz */ 932 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 933 795, 864, 0, 576, 580, 586, 625, 0, 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 935 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 936 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 937 /* 55 - 720(1440)x576i@200Hz */ 938 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 939 795, 864, 0, 576, 580, 586, 625, 0, 940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 941 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 942 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 943 /* 56 - 720x480@240Hz */ 944 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 945 798, 858, 0, 480, 489, 495, 525, 0, 946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 947 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 948 /* 57 - 720x480@240Hz */ 949 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 950 798, 858, 0, 480, 489, 495, 525, 0, 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 952 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 953 /* 58 - 720(1440)x480i@240 */ 954 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 955 801, 858, 0, 480, 488, 494, 525, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 957 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 958 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 959 /* 59 - 720(1440)x480i@240 */ 960 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 961 801, 858, 0, 480, 488, 494, 525, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 963 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 964 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 965 /* 60 - 1280x720@24Hz */ 966 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 967 3080, 3300, 0, 720, 725, 730, 750, 0, 968 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 969 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 970 /* 61 - 1280x720@25Hz */ 971 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 972 3740, 3960, 0, 720, 725, 730, 750, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 974 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 975 /* 62 - 1280x720@30Hz */ 976 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 977 3080, 3300, 0, 720, 725, 730, 750, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 979 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 980 /* 63 - 1920x1080@120Hz */ 981 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 982 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 984 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 64 - 1920x1080@100Hz */ 986 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 987 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 989 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 990 }; 991 992 /* 993 * HDMI 1.4 4k modes. 994 */ 995 static const struct drm_display_mode edid_4k_modes[] = { 996 /* 1 - 3840x2160@30Hz */ 997 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 998 3840, 4016, 4104, 4400, 0, 999 2160, 2168, 2178, 2250, 0, 1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1001 .vrefresh = 30, }, 1002 /* 2 - 3840x2160@25Hz */ 1003 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1004 3840, 4896, 4984, 5280, 0, 1005 2160, 2168, 2178, 2250, 0, 1006 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1007 .vrefresh = 25, }, 1008 /* 3 - 3840x2160@24Hz */ 1009 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1010 3840, 5116, 5204, 5500, 0, 1011 2160, 2168, 2178, 2250, 0, 1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1013 .vrefresh = 24, }, 1014 /* 4 - 4096x2160@24Hz (SMPTE) */ 1015 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1016 4096, 5116, 5204, 5500, 0, 1017 2160, 2168, 2178, 2250, 0, 1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1019 .vrefresh = 24, }, 1020 }; 1021 1022 /*** DDC fetch and block validation ***/ 1023 1024 static const u8 edid_header[] = { 1025 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1026 }; 1027 1028 /** 1029 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1030 * @raw_edid: pointer to raw base EDID block 1031 * 1032 * Sanity check the header of the base EDID block. 1033 * 1034 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1035 */ 1036 int drm_edid_header_is_valid(const u8 *raw_edid) 1037 { 1038 int i, score = 0; 1039 1040 for (i = 0; i < sizeof(edid_header); i++) 1041 if (raw_edid[i] == edid_header[i]) 1042 score++; 1043 1044 return score; 1045 } 1046 EXPORT_SYMBOL(drm_edid_header_is_valid); 1047 1048 static int edid_fixup __read_mostly = 6; 1049 module_param_named(edid_fixup, edid_fixup, int, 0400); 1050 MODULE_PARM_DESC(edid_fixup, 1051 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1052 1053 static int drm_edid_block_checksum(const u8 *raw_edid) 1054 { 1055 int i; 1056 u8 csum = 0; 1057 for (i = 0; i < EDID_LENGTH; i++) 1058 csum += raw_edid[i]; 1059 1060 return csum; 1061 } 1062 1063 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1064 { 1065 if (memchr_inv(in_edid, 0, length)) 1066 return false; 1067 1068 return true; 1069 } 1070 1071 /** 1072 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1073 * @raw_edid: pointer to raw EDID block 1074 * @block: type of block to validate (0 for base, extension otherwise) 1075 * @print_bad_edid: if true, dump bad EDID blocks to the console 1076 * @edid_corrupt: if true, the header or checksum is invalid 1077 * 1078 * Validate a base or extension EDID block and optionally dump bad blocks to 1079 * the console. 1080 * 1081 * Return: True if the block is valid, false otherwise. 1082 */ 1083 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1084 bool *edid_corrupt) 1085 { 1086 int i; 1087 u8 csum; 1088 struct edid *edid = (struct edid *)raw_edid; 1089 1090 if (WARN_ON(!raw_edid)) 1091 return false; 1092 1093 if (edid_fixup > 8 || edid_fixup < 0) 1094 edid_fixup = 6; 1095 1096 if (block == 0) { 1097 int score = drm_edid_header_is_valid(raw_edid); 1098 if (score == 8) { 1099 if (edid_corrupt) 1100 *edid_corrupt = false; 1101 } else if (score >= edid_fixup) { 1102 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1103 * The corrupt flag needs to be set here otherwise, the 1104 * fix-up code here will correct the problem, the 1105 * checksum is correct and the test fails 1106 */ 1107 if (edid_corrupt) 1108 *edid_corrupt = true; 1109 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1110 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1111 } else { 1112 if (edid_corrupt) 1113 *edid_corrupt = true; 1114 goto bad; 1115 } 1116 } 1117 1118 csum = drm_edid_block_checksum(raw_edid); 1119 if (csum) { 1120 if (print_bad_edid) { 1121 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1122 } 1123 1124 if (edid_corrupt) 1125 *edid_corrupt = true; 1126 1127 /* allow CEA to slide through, switches mangle this */ 1128 if (raw_edid[0] != 0x02) 1129 goto bad; 1130 } 1131 1132 /* per-block-type checks */ 1133 switch (raw_edid[0]) { 1134 case 0: /* base */ 1135 if (edid->version != 1) { 1136 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1137 goto bad; 1138 } 1139 1140 if (edid->revision > 4) 1141 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1142 break; 1143 1144 default: 1145 break; 1146 } 1147 1148 return true; 1149 1150 bad: 1151 if (print_bad_edid) { 1152 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1153 printk(KERN_ERR "EDID block is all zeroes\n"); 1154 } else { 1155 printk(KERN_ERR "Raw EDID:\n"); 1156 for (i = 0; i < EDID_LENGTH; ) { 1157 kprintf("%02x", raw_edid[i]); 1158 i++; 1159 if (i % 16 == 0 || i == EDID_LENGTH) 1160 kprintf("\n"); 1161 else if (i % 8 == 0) 1162 kprintf(" "); 1163 else 1164 kprintf(" "); 1165 } 1166 } 1167 } 1168 return false; 1169 } 1170 EXPORT_SYMBOL(drm_edid_block_valid); 1171 1172 /** 1173 * drm_edid_is_valid - sanity check EDID data 1174 * @edid: EDID data 1175 * 1176 * Sanity-check an entire EDID record (including extensions) 1177 * 1178 * Return: True if the EDID data is valid, false otherwise. 1179 */ 1180 bool drm_edid_is_valid(struct edid *edid) 1181 { 1182 int i; 1183 u8 *raw = (u8 *)edid; 1184 1185 if (!edid) 1186 return false; 1187 1188 for (i = 0; i <= edid->extensions; i++) 1189 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1190 return false; 1191 1192 return true; 1193 } 1194 EXPORT_SYMBOL(drm_edid_is_valid); 1195 1196 #define DDC_SEGMENT_ADDR 0x30 1197 /** 1198 * drm_do_probe_ddc_edid() - get EDID information via I2C 1199 * @data: I2C device adapter 1200 * @buf: EDID data buffer to be filled 1201 * @block: 128 byte EDID block to start fetching from 1202 * @len: EDID data buffer length to fetch 1203 * 1204 * Try to fetch EDID information by calling I2C driver functions. 1205 * 1206 * Return: 0 on success or -1 on failure. 1207 */ 1208 static int 1209 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1210 { 1211 struct i2c_adapter *adapter = data; 1212 unsigned char start = block * EDID_LENGTH; 1213 unsigned char segment = block >> 1; 1214 unsigned char xfers = segment ? 3 : 2; 1215 int ret, retries = 5; 1216 1217 /* 1218 * The core I2C driver will automatically retry the transfer if the 1219 * adapter reports EAGAIN. However, we find that bit-banging transfers 1220 * are susceptible to errors under a heavily loaded machine and 1221 * generate spurious NAKs and timeouts. Retrying the transfer 1222 * of the individual block a few times seems to overcome this. 1223 */ 1224 do { 1225 struct i2c_msg msgs[] = { 1226 { 1227 .slave = DDC_SEGMENT_ADDR << 1, 1228 .flags = 0, 1229 .len = 1, 1230 .buf = &segment, 1231 }, { 1232 .slave = DDC_ADDR << 1, 1233 .flags = 0, 1234 .len = 1, 1235 .buf = &start, 1236 }, { 1237 .slave = DDC_ADDR << 1, 1238 .flags = I2C_M_RD, 1239 .len = len, 1240 .buf = buf, 1241 } 1242 }; 1243 1244 /* 1245 * Avoid sending the segment addr to not upset non-compliant 1246 * DDC monitors. 1247 */ 1248 ret = iicbus_transfer(adapter, &msgs[3 - xfers], xfers); 1249 1250 if (ret != 0) 1251 DRM_DEBUG_KMS("iicbus_transfer countdown %d error %d\n", 1252 retries, ret); 1253 } while (ret != 0 && --retries); 1254 1255 return (ret == 0 ? 0 : -1); 1256 } 1257 1258 /** 1259 * drm_do_get_edid - get EDID data using a custom EDID block read function 1260 * @connector: connector we're probing 1261 * @get_edid_block: EDID block read function 1262 * @data: private data passed to the block read function 1263 * 1264 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1265 * exposes a different interface to read EDID blocks this function can be used 1266 * to get EDID data using a custom block read function. 1267 * 1268 * As in the general case the DDC bus is accessible by the kernel at the I2C 1269 * level, drivers must make all reasonable efforts to expose it as an I2C 1270 * adapter and use drm_get_edid() instead of abusing this function. 1271 * 1272 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1273 */ 1274 struct edid *drm_do_get_edid(struct drm_connector *connector, 1275 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1276 size_t len), 1277 void *data) 1278 { 1279 int i, j = 0, valid_extensions = 0; 1280 u8 *block, *new; 1281 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1282 1283 if ((block = kmalloc(EDID_LENGTH, M_DRM, M_WAITOK)) == NULL) 1284 return NULL; 1285 1286 /* base block fetch */ 1287 for (i = 0; i < 4; i++) { 1288 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1289 goto out; 1290 if (drm_edid_block_valid(block, 0, print_bad_edid, 1291 &connector->edid_corrupt)) 1292 break; 1293 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1294 connector->null_edid_counter++; 1295 goto carp; 1296 } 1297 } 1298 if (i == 4) 1299 goto carp; 1300 1301 /* if there's no extensions, we're done */ 1302 if (block[0x7e] == 0) 1303 return (struct edid *)block; 1304 1305 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1306 if (!new) 1307 goto out; 1308 block = new; 1309 1310 for (j = 1; j <= block[0x7e]; j++) { 1311 for (i = 0; i < 4; i++) { 1312 if (get_edid_block(data, 1313 block + (valid_extensions + 1) * EDID_LENGTH, 1314 j, EDID_LENGTH)) 1315 goto out; 1316 if (drm_edid_block_valid(block + (valid_extensions + 1) 1317 * EDID_LENGTH, j, 1318 print_bad_edid, 1319 NULL)) { 1320 valid_extensions++; 1321 break; 1322 } 1323 } 1324 1325 if (i == 4 && print_bad_edid) { 1326 dev_warn(connector->dev->dev, 1327 "%s: Ignoring invalid EDID block %d.\n", 1328 connector->name, j); 1329 1330 connector->bad_edid_counter++; 1331 } 1332 } 1333 1334 if (valid_extensions != block[0x7e]) { 1335 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1336 block[0x7e] = valid_extensions; 1337 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1338 if (!new) 1339 goto out; 1340 block = new; 1341 } 1342 1343 return (struct edid *)block; 1344 1345 carp: 1346 if (print_bad_edid) { 1347 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1348 connector->name, j); 1349 } 1350 connector->bad_edid_counter++; 1351 1352 out: 1353 kfree(block); 1354 return NULL; 1355 } 1356 1357 /** 1358 * drm_probe_ddc() - probe DDC presence 1359 * @adapter: I2C adapter to probe 1360 * 1361 * Return: True on success, false on failure. 1362 */ 1363 bool 1364 drm_probe_ddc(struct device *adapter) 1365 { 1366 unsigned char out; 1367 1368 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1369 } 1370 EXPORT_SYMBOL(drm_probe_ddc); 1371 1372 /** 1373 * drm_get_edid - get EDID data, if available 1374 * @connector: connector we're probing 1375 * @adapter: I2C adapter to use for DDC 1376 * 1377 * Poke the given I2C channel to grab EDID data if possible. If found, 1378 * attach it to the connector. 1379 * 1380 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1381 */ 1382 struct edid *drm_get_edid(struct drm_connector *connector, 1383 struct device *adapter) 1384 { 1385 if (!drm_probe_ddc(adapter)) 1386 return NULL; 1387 1388 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1389 } 1390 EXPORT_SYMBOL(drm_get_edid); 1391 1392 /** 1393 * drm_edid_duplicate - duplicate an EDID and the extensions 1394 * @edid: EDID to duplicate 1395 * 1396 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1397 */ 1398 struct edid *drm_edid_duplicate(const struct edid *edid) 1399 { 1400 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1401 } 1402 EXPORT_SYMBOL(drm_edid_duplicate); 1403 1404 /*** EDID parsing ***/ 1405 1406 /** 1407 * edid_vendor - match a string against EDID's obfuscated vendor field 1408 * @edid: EDID to match 1409 * @vendor: vendor string 1410 * 1411 * Returns true if @vendor is in @edid, false otherwise 1412 */ 1413 static bool edid_vendor(struct edid *edid, char *vendor) 1414 { 1415 char edid_vendor[3]; 1416 1417 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1418 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1419 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1420 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1421 1422 return !strncmp(edid_vendor, vendor, 3); 1423 } 1424 1425 /** 1426 * edid_get_quirks - return quirk flags for a given EDID 1427 * @edid: EDID to process 1428 * 1429 * This tells subsequent routines what fixes they need to apply. 1430 */ 1431 static u32 edid_get_quirks(struct edid *edid) 1432 { 1433 struct edid_quirk *quirk; 1434 int i; 1435 1436 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1437 quirk = &edid_quirk_list[i]; 1438 1439 if (edid_vendor(edid, quirk->vendor) && 1440 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1441 return quirk->quirks; 1442 } 1443 1444 return 0; 1445 } 1446 1447 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1448 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1449 1450 /** 1451 * edid_fixup_preferred - set preferred modes based on quirk list 1452 * @connector: has mode list to fix up 1453 * @quirks: quirks list 1454 * 1455 * Walk the mode list for @connector, clearing the preferred status 1456 * on existing modes and setting it anew for the right mode ala @quirks. 1457 */ 1458 static void edid_fixup_preferred(struct drm_connector *connector, 1459 u32 quirks) 1460 { 1461 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1462 int target_refresh = 0; 1463 int cur_vrefresh, preferred_vrefresh; 1464 1465 if (list_empty(&connector->probed_modes)) 1466 return; 1467 1468 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1469 target_refresh = 60; 1470 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1471 target_refresh = 75; 1472 1473 preferred_mode = list_first_entry(&connector->probed_modes, 1474 struct drm_display_mode, head); 1475 1476 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1477 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1478 1479 if (cur_mode == preferred_mode) 1480 continue; 1481 1482 /* Largest mode is preferred */ 1483 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1484 preferred_mode = cur_mode; 1485 1486 cur_vrefresh = cur_mode->vrefresh ? 1487 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1488 preferred_vrefresh = preferred_mode->vrefresh ? 1489 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1490 /* At a given size, try to get closest to target refresh */ 1491 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1492 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1493 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1494 preferred_mode = cur_mode; 1495 } 1496 } 1497 1498 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1499 } 1500 1501 static bool 1502 mode_is_rb(const struct drm_display_mode *mode) 1503 { 1504 return (mode->htotal - mode->hdisplay == 160) && 1505 (mode->hsync_end - mode->hdisplay == 80) && 1506 (mode->hsync_end - mode->hsync_start == 32) && 1507 (mode->vsync_start - mode->vdisplay == 3); 1508 } 1509 1510 /* 1511 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1512 * @dev: Device to duplicate against 1513 * @hsize: Mode width 1514 * @vsize: Mode height 1515 * @fresh: Mode refresh rate 1516 * @rb: Mode reduced-blanking-ness 1517 * 1518 * Walk the DMT mode list looking for a match for the given parameters. 1519 * 1520 * Return: A newly allocated copy of the mode, or NULL if not found. 1521 */ 1522 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1523 int hsize, int vsize, int fresh, 1524 bool rb) 1525 { 1526 int i; 1527 1528 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1529 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1530 if (hsize != ptr->hdisplay) 1531 continue; 1532 if (vsize != ptr->vdisplay) 1533 continue; 1534 if (fresh != drm_mode_vrefresh(ptr)) 1535 continue; 1536 if (rb != mode_is_rb(ptr)) 1537 continue; 1538 1539 return drm_mode_duplicate(dev, ptr); 1540 } 1541 1542 return NULL; 1543 } 1544 EXPORT_SYMBOL(drm_mode_find_dmt); 1545 1546 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1547 1548 static void 1549 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1550 { 1551 int i, n = 0; 1552 u8 d = ext[0x02]; 1553 u8 *det_base = ext + d; 1554 1555 n = (127 - d) / 18; 1556 for (i = 0; i < n; i++) 1557 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1558 } 1559 1560 static void 1561 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1562 { 1563 unsigned int i, n = min((int)ext[0x02], 6); 1564 u8 *det_base = ext + 5; 1565 1566 if (ext[0x01] != 1) 1567 return; /* unknown version */ 1568 1569 for (i = 0; i < n; i++) 1570 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1571 } 1572 1573 static void 1574 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1575 { 1576 int i; 1577 struct edid *edid = (struct edid *)raw_edid; 1578 1579 if (edid == NULL) 1580 return; 1581 1582 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1583 cb(&(edid->detailed_timings[i]), closure); 1584 1585 for (i = 1; i <= raw_edid[0x7e]; i++) { 1586 u8 *ext = raw_edid + (i * EDID_LENGTH); 1587 switch (*ext) { 1588 case CEA_EXT: 1589 cea_for_each_detailed_block(ext, cb, closure); 1590 break; 1591 case VTB_EXT: 1592 vtb_for_each_detailed_block(ext, cb, closure); 1593 break; 1594 default: 1595 break; 1596 } 1597 } 1598 } 1599 1600 static void 1601 is_rb(struct detailed_timing *t, void *data) 1602 { 1603 u8 *r = (u8 *)t; 1604 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1605 if (r[15] & 0x10) 1606 *(bool *)data = true; 1607 } 1608 1609 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1610 static bool 1611 drm_monitor_supports_rb(struct edid *edid) 1612 { 1613 if (edid->revision >= 4) { 1614 bool ret = false; 1615 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1616 return ret; 1617 } 1618 1619 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1620 } 1621 1622 static void 1623 find_gtf2(struct detailed_timing *t, void *data) 1624 { 1625 u8 *r = (u8 *)t; 1626 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1627 *(u8 **)data = r; 1628 } 1629 1630 /* Secondary GTF curve kicks in above some break frequency */ 1631 static int 1632 drm_gtf2_hbreak(struct edid *edid) 1633 { 1634 u8 *r = NULL; 1635 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1636 return r ? (r[12] * 2) : 0; 1637 } 1638 1639 static int 1640 drm_gtf2_2c(struct edid *edid) 1641 { 1642 u8 *r = NULL; 1643 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1644 return r ? r[13] : 0; 1645 } 1646 1647 static int 1648 drm_gtf2_m(struct edid *edid) 1649 { 1650 u8 *r = NULL; 1651 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1652 return r ? (r[15] << 8) + r[14] : 0; 1653 } 1654 1655 static int 1656 drm_gtf2_k(struct edid *edid) 1657 { 1658 u8 *r = NULL; 1659 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1660 return r ? r[16] : 0; 1661 } 1662 1663 static int 1664 drm_gtf2_2j(struct edid *edid) 1665 { 1666 u8 *r = NULL; 1667 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1668 return r ? r[17] : 0; 1669 } 1670 1671 /** 1672 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1673 * @edid: EDID block to scan 1674 */ 1675 static int standard_timing_level(struct edid *edid) 1676 { 1677 if (edid->revision >= 2) { 1678 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1679 return LEVEL_CVT; 1680 if (drm_gtf2_hbreak(edid)) 1681 return LEVEL_GTF2; 1682 return LEVEL_GTF; 1683 } 1684 return LEVEL_DMT; 1685 } 1686 1687 /* 1688 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1689 * monitors fill with ascii space (0x20) instead. 1690 */ 1691 static int 1692 bad_std_timing(u8 a, u8 b) 1693 { 1694 return (a == 0x00 && b == 0x00) || 1695 (a == 0x01 && b == 0x01) || 1696 (a == 0x20 && b == 0x20); 1697 } 1698 1699 /** 1700 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1701 * @connector: connector of for the EDID block 1702 * @edid: EDID block to scan 1703 * @t: standard timing params 1704 * 1705 * Take the standard timing params (in this case width, aspect, and refresh) 1706 * and convert them into a real mode using CVT/GTF/DMT. 1707 */ 1708 static struct drm_display_mode * 1709 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1710 struct std_timing *t) 1711 { 1712 struct drm_device *dev = connector->dev; 1713 struct drm_display_mode *m, *mode = NULL; 1714 int hsize, vsize; 1715 int vrefresh_rate; 1716 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1717 >> EDID_TIMING_ASPECT_SHIFT; 1718 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1719 >> EDID_TIMING_VFREQ_SHIFT; 1720 int timing_level = standard_timing_level(edid); 1721 1722 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1723 return NULL; 1724 1725 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1726 hsize = t->hsize * 8 + 248; 1727 /* vrefresh_rate = vfreq + 60 */ 1728 vrefresh_rate = vfreq + 60; 1729 /* the vdisplay is calculated based on the aspect ratio */ 1730 if (aspect_ratio == 0) { 1731 if (edid->revision < 3) 1732 vsize = hsize; 1733 else 1734 vsize = (hsize * 10) / 16; 1735 } else if (aspect_ratio == 1) 1736 vsize = (hsize * 3) / 4; 1737 else if (aspect_ratio == 2) 1738 vsize = (hsize * 4) / 5; 1739 else 1740 vsize = (hsize * 9) / 16; 1741 1742 /* HDTV hack, part 1 */ 1743 if (vrefresh_rate == 60 && 1744 ((hsize == 1360 && vsize == 765) || 1745 (hsize == 1368 && vsize == 769))) { 1746 hsize = 1366; 1747 vsize = 768; 1748 } 1749 1750 /* 1751 * If this connector already has a mode for this size and refresh 1752 * rate (because it came from detailed or CVT info), use that 1753 * instead. This way we don't have to guess at interlace or 1754 * reduced blanking. 1755 */ 1756 list_for_each_entry(m, &connector->probed_modes, head) 1757 if (m->hdisplay == hsize && m->vdisplay == vsize && 1758 drm_mode_vrefresh(m) == vrefresh_rate) 1759 return NULL; 1760 1761 /* HDTV hack, part 2 */ 1762 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1763 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1764 false); 1765 mode->hdisplay = 1366; 1766 mode->hsync_start = mode->hsync_start - 1; 1767 mode->hsync_end = mode->hsync_end - 1; 1768 return mode; 1769 } 1770 1771 /* check whether it can be found in default mode table */ 1772 if (drm_monitor_supports_rb(edid)) { 1773 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1774 true); 1775 if (mode) 1776 return mode; 1777 } 1778 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1779 if (mode) 1780 return mode; 1781 1782 /* okay, generate it */ 1783 switch (timing_level) { 1784 case LEVEL_DMT: 1785 break; 1786 case LEVEL_GTF: 1787 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1788 break; 1789 case LEVEL_GTF2: 1790 /* 1791 * This is potentially wrong if there's ever a monitor with 1792 * more than one ranges section, each claiming a different 1793 * secondary GTF curve. Please don't do that. 1794 */ 1795 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1796 if (!mode) 1797 return NULL; 1798 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1799 drm_mode_destroy(dev, mode); 1800 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1801 vrefresh_rate, 0, 0, 1802 drm_gtf2_m(edid), 1803 drm_gtf2_2c(edid), 1804 drm_gtf2_k(edid), 1805 drm_gtf2_2j(edid)); 1806 } 1807 break; 1808 case LEVEL_CVT: 1809 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1810 false); 1811 break; 1812 } 1813 return mode; 1814 } 1815 1816 /* 1817 * EDID is delightfully ambiguous about how interlaced modes are to be 1818 * encoded. Our internal representation is of frame height, but some 1819 * HDTV detailed timings are encoded as field height. 1820 * 1821 * The format list here is from CEA, in frame size. Technically we 1822 * should be checking refresh rate too. Whatever. 1823 */ 1824 static void 1825 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1826 struct detailed_pixel_timing *pt) 1827 { 1828 int i; 1829 static const struct { 1830 int w, h; 1831 } cea_interlaced[] = { 1832 { 1920, 1080 }, 1833 { 720, 480 }, 1834 { 1440, 480 }, 1835 { 2880, 480 }, 1836 { 720, 576 }, 1837 { 1440, 576 }, 1838 { 2880, 576 }, 1839 }; 1840 1841 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1842 return; 1843 1844 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1845 if ((mode->hdisplay == cea_interlaced[i].w) && 1846 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1847 mode->vdisplay *= 2; 1848 mode->vsync_start *= 2; 1849 mode->vsync_end *= 2; 1850 mode->vtotal *= 2; 1851 mode->vtotal |= 1; 1852 } 1853 } 1854 1855 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1856 } 1857 1858 /** 1859 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1860 * @dev: DRM device (needed to create new mode) 1861 * @edid: EDID block 1862 * @timing: EDID detailed timing info 1863 * @quirks: quirks to apply 1864 * 1865 * An EDID detailed timing block contains enough info for us to create and 1866 * return a new struct drm_display_mode. 1867 */ 1868 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1869 struct edid *edid, 1870 struct detailed_timing *timing, 1871 u32 quirks) 1872 { 1873 struct drm_display_mode *mode; 1874 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1875 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1876 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1877 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1878 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1879 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1880 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1881 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1882 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1883 1884 /* ignore tiny modes */ 1885 if (hactive < 64 || vactive < 64) 1886 return NULL; 1887 1888 if (pt->misc & DRM_EDID_PT_STEREO) { 1889 DRM_DEBUG_KMS("stereo mode not supported\n"); 1890 return NULL; 1891 } 1892 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1893 DRM_DEBUG_KMS("composite sync not supported\n"); 1894 } 1895 1896 /* it is incorrect if hsync/vsync width is zero */ 1897 if (!hsync_pulse_width || !vsync_pulse_width) { 1898 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1899 "Wrong Hsync/Vsync pulse width\n"); 1900 return NULL; 1901 } 1902 1903 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1904 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1905 if (!mode) 1906 return NULL; 1907 1908 goto set_size; 1909 } 1910 1911 mode = drm_mode_create(dev); 1912 if (!mode) 1913 return NULL; 1914 1915 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1916 timing->pixel_clock = cpu_to_le16(1088); 1917 1918 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1919 1920 mode->hdisplay = hactive; 1921 mode->hsync_start = mode->hdisplay + hsync_offset; 1922 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1923 mode->htotal = mode->hdisplay + hblank; 1924 1925 mode->vdisplay = vactive; 1926 mode->vsync_start = mode->vdisplay + vsync_offset; 1927 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1928 mode->vtotal = mode->vdisplay + vblank; 1929 1930 /* Some EDIDs have bogus h/vtotal values */ 1931 if (mode->hsync_end > mode->htotal) 1932 mode->htotal = mode->hsync_end + 1; 1933 if (mode->vsync_end > mode->vtotal) 1934 mode->vtotal = mode->vsync_end + 1; 1935 1936 drm_mode_do_interlace_quirk(mode, pt); 1937 1938 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1939 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1940 } 1941 1942 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1943 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1944 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1945 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1946 1947 set_size: 1948 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1949 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1950 1951 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1952 mode->width_mm *= 10; 1953 mode->height_mm *= 10; 1954 } 1955 1956 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1957 mode->width_mm = edid->width_cm * 10; 1958 mode->height_mm = edid->height_cm * 10; 1959 } 1960 1961 mode->type = DRM_MODE_TYPE_DRIVER; 1962 mode->vrefresh = drm_mode_vrefresh(mode); 1963 drm_mode_set_name(mode); 1964 1965 return mode; 1966 } 1967 1968 static bool 1969 mode_in_hsync_range(const struct drm_display_mode *mode, 1970 struct edid *edid, u8 *t) 1971 { 1972 int hsync, hmin, hmax; 1973 1974 hmin = t[7]; 1975 if (edid->revision >= 4) 1976 hmin += ((t[4] & 0x04) ? 255 : 0); 1977 hmax = t[8]; 1978 if (edid->revision >= 4) 1979 hmax += ((t[4] & 0x08) ? 255 : 0); 1980 hsync = drm_mode_hsync(mode); 1981 1982 return (hsync <= hmax && hsync >= hmin); 1983 } 1984 1985 static bool 1986 mode_in_vsync_range(const struct drm_display_mode *mode, 1987 struct edid *edid, u8 *t) 1988 { 1989 int vsync, vmin, vmax; 1990 1991 vmin = t[5]; 1992 if (edid->revision >= 4) 1993 vmin += ((t[4] & 0x01) ? 255 : 0); 1994 vmax = t[6]; 1995 if (edid->revision >= 4) 1996 vmax += ((t[4] & 0x02) ? 255 : 0); 1997 vsync = drm_mode_vrefresh(mode); 1998 1999 return (vsync <= vmax && vsync >= vmin); 2000 } 2001 2002 static u32 2003 range_pixel_clock(struct edid *edid, u8 *t) 2004 { 2005 /* unspecified */ 2006 if (t[9] == 0 || t[9] == 255) 2007 return 0; 2008 2009 /* 1.4 with CVT support gives us real precision, yay */ 2010 if (edid->revision >= 4 && t[10] == 0x04) 2011 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2012 2013 /* 1.3 is pathetic, so fuzz up a bit */ 2014 return t[9] * 10000 + 5001; 2015 } 2016 2017 static bool 2018 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2019 struct detailed_timing *timing) 2020 { 2021 u32 max_clock; 2022 u8 *t = (u8 *)timing; 2023 2024 if (!mode_in_hsync_range(mode, edid, t)) 2025 return false; 2026 2027 if (!mode_in_vsync_range(mode, edid, t)) 2028 return false; 2029 2030 if ((max_clock = range_pixel_clock(edid, t))) 2031 if (mode->clock > max_clock) 2032 return false; 2033 2034 /* 1.4 max horizontal check */ 2035 if (edid->revision >= 4 && t[10] == 0x04) 2036 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2037 return false; 2038 2039 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2040 return false; 2041 2042 return true; 2043 } 2044 2045 static bool valid_inferred_mode(const struct drm_connector *connector, 2046 const struct drm_display_mode *mode) 2047 { 2048 struct drm_display_mode *m; 2049 bool ok = false; 2050 2051 list_for_each_entry(m, &connector->probed_modes, head) { 2052 if (mode->hdisplay == m->hdisplay && 2053 mode->vdisplay == m->vdisplay && 2054 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2055 return false; /* duplicated */ 2056 if (mode->hdisplay <= m->hdisplay && 2057 mode->vdisplay <= m->vdisplay) 2058 ok = true; 2059 } 2060 return ok; 2061 } 2062 2063 static int 2064 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2065 struct detailed_timing *timing) 2066 { 2067 int i, modes = 0; 2068 struct drm_display_mode *newmode; 2069 struct drm_device *dev = connector->dev; 2070 2071 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2072 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2073 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2074 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2075 if (newmode) { 2076 drm_mode_probed_add(connector, newmode); 2077 modes++; 2078 } 2079 } 2080 } 2081 2082 return modes; 2083 } 2084 2085 /* fix up 1366x768 mode from 1368x768; 2086 * GFT/CVT can't express 1366 width which isn't dividable by 8 2087 */ 2088 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2089 { 2090 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2091 mode->hdisplay = 1366; 2092 mode->hsync_start--; 2093 mode->hsync_end--; 2094 drm_mode_set_name(mode); 2095 } 2096 } 2097 2098 static int 2099 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2100 struct detailed_timing *timing) 2101 { 2102 int i, modes = 0; 2103 struct drm_display_mode *newmode; 2104 struct drm_device *dev = connector->dev; 2105 2106 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2107 const struct minimode *m = &extra_modes[i]; 2108 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2109 if (!newmode) 2110 return modes; 2111 2112 fixup_mode_1366x768(newmode); 2113 if (!mode_in_range(newmode, edid, timing) || 2114 !valid_inferred_mode(connector, newmode)) { 2115 drm_mode_destroy(dev, newmode); 2116 continue; 2117 } 2118 2119 drm_mode_probed_add(connector, newmode); 2120 modes++; 2121 } 2122 2123 return modes; 2124 } 2125 2126 static int 2127 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2128 struct detailed_timing *timing) 2129 { 2130 int i, modes = 0; 2131 struct drm_display_mode *newmode; 2132 struct drm_device *dev = connector->dev; 2133 bool rb = drm_monitor_supports_rb(edid); 2134 2135 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2136 const struct minimode *m = &extra_modes[i]; 2137 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2138 if (!newmode) 2139 return modes; 2140 2141 fixup_mode_1366x768(newmode); 2142 if (!mode_in_range(newmode, edid, timing) || 2143 !valid_inferred_mode(connector, newmode)) { 2144 drm_mode_destroy(dev, newmode); 2145 continue; 2146 } 2147 2148 drm_mode_probed_add(connector, newmode); 2149 modes++; 2150 } 2151 2152 return modes; 2153 } 2154 2155 static void 2156 do_inferred_modes(struct detailed_timing *timing, void *c) 2157 { 2158 struct detailed_mode_closure *closure = c; 2159 struct detailed_non_pixel *data = &timing->data.other_data; 2160 struct detailed_data_monitor_range *range = &data->data.range; 2161 2162 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2163 return; 2164 2165 closure->modes += drm_dmt_modes_for_range(closure->connector, 2166 closure->edid, 2167 timing); 2168 2169 if (!version_greater(closure->edid, 1, 1)) 2170 return; /* GTF not defined yet */ 2171 2172 switch (range->flags) { 2173 case 0x02: /* secondary gtf, XXX could do more */ 2174 case 0x00: /* default gtf */ 2175 closure->modes += drm_gtf_modes_for_range(closure->connector, 2176 closure->edid, 2177 timing); 2178 break; 2179 case 0x04: /* cvt, only in 1.4+ */ 2180 if (!version_greater(closure->edid, 1, 3)) 2181 break; 2182 2183 closure->modes += drm_cvt_modes_for_range(closure->connector, 2184 closure->edid, 2185 timing); 2186 break; 2187 case 0x01: /* just the ranges, no formula */ 2188 default: 2189 break; 2190 } 2191 } 2192 2193 static int 2194 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2195 { 2196 struct detailed_mode_closure closure = { 2197 .connector = connector, 2198 .edid = edid, 2199 }; 2200 2201 if (version_greater(edid, 1, 0)) 2202 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2203 &closure); 2204 2205 return closure.modes; 2206 } 2207 2208 static int 2209 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2210 { 2211 int i, j, m, modes = 0; 2212 struct drm_display_mode *mode; 2213 u8 *est = ((u8 *)timing) + 5; 2214 2215 for (i = 0; i < 6; i++) { 2216 for (j = 7; j >= 0; j--) { 2217 m = (i * 8) + (7 - j); 2218 if (m >= ARRAY_SIZE(est3_modes)) 2219 break; 2220 if (est[i] & (1 << j)) { 2221 mode = drm_mode_find_dmt(connector->dev, 2222 est3_modes[m].w, 2223 est3_modes[m].h, 2224 est3_modes[m].r, 2225 est3_modes[m].rb); 2226 if (mode) { 2227 drm_mode_probed_add(connector, mode); 2228 modes++; 2229 } 2230 } 2231 } 2232 } 2233 2234 return modes; 2235 } 2236 2237 static void 2238 do_established_modes(struct detailed_timing *timing, void *c) 2239 { 2240 struct detailed_mode_closure *closure = c; 2241 struct detailed_non_pixel *data = &timing->data.other_data; 2242 2243 if (data->type == EDID_DETAIL_EST_TIMINGS) 2244 closure->modes += drm_est3_modes(closure->connector, timing); 2245 } 2246 2247 /** 2248 * add_established_modes - get est. modes from EDID and add them 2249 * @connector: connector to add mode(s) to 2250 * @edid: EDID block to scan 2251 * 2252 * Each EDID block contains a bitmap of the supported "established modes" list 2253 * (defined above). Tease them out and add them to the global modes list. 2254 */ 2255 static int 2256 add_established_modes(struct drm_connector *connector, struct edid *edid) 2257 { 2258 struct drm_device *dev = connector->dev; 2259 unsigned long est_bits = edid->established_timings.t1 | 2260 (edid->established_timings.t2 << 8) | 2261 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2262 int i, modes = 0; 2263 struct detailed_mode_closure closure = { 2264 .connector = connector, 2265 .edid = edid, 2266 }; 2267 2268 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2269 if (est_bits & (1<<i)) { 2270 struct drm_display_mode *newmode; 2271 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2272 if (newmode) { 2273 drm_mode_probed_add(connector, newmode); 2274 modes++; 2275 } 2276 } 2277 } 2278 2279 if (version_greater(edid, 1, 0)) 2280 drm_for_each_detailed_block((u8 *)edid, 2281 do_established_modes, &closure); 2282 2283 return modes + closure.modes; 2284 } 2285 2286 static void 2287 do_standard_modes(struct detailed_timing *timing, void *c) 2288 { 2289 struct detailed_mode_closure *closure = c; 2290 struct detailed_non_pixel *data = &timing->data.other_data; 2291 struct drm_connector *connector = closure->connector; 2292 struct edid *edid = closure->edid; 2293 2294 if (data->type == EDID_DETAIL_STD_MODES) { 2295 int i; 2296 for (i = 0; i < 6; i++) { 2297 struct std_timing *std; 2298 struct drm_display_mode *newmode; 2299 2300 std = &data->data.timings[i]; 2301 newmode = drm_mode_std(connector, edid, std); 2302 if (newmode) { 2303 drm_mode_probed_add(connector, newmode); 2304 closure->modes++; 2305 } 2306 } 2307 } 2308 } 2309 2310 /** 2311 * add_standard_modes - get std. modes from EDID and add them 2312 * @connector: connector to add mode(s) to 2313 * @edid: EDID block to scan 2314 * 2315 * Standard modes can be calculated using the appropriate standard (DMT, 2316 * GTF or CVT. Grab them from @edid and add them to the list. 2317 */ 2318 static int 2319 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2320 { 2321 int i, modes = 0; 2322 struct detailed_mode_closure closure = { 2323 .connector = connector, 2324 .edid = edid, 2325 }; 2326 2327 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2328 struct drm_display_mode *newmode; 2329 2330 newmode = drm_mode_std(connector, edid, 2331 &edid->standard_timings[i]); 2332 if (newmode) { 2333 drm_mode_probed_add(connector, newmode); 2334 modes++; 2335 } 2336 } 2337 2338 if (version_greater(edid, 1, 0)) 2339 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2340 &closure); 2341 2342 /* XXX should also look for standard codes in VTB blocks */ 2343 2344 return modes + closure.modes; 2345 } 2346 2347 static int drm_cvt_modes(struct drm_connector *connector, 2348 struct detailed_timing *timing) 2349 { 2350 int i, j, modes = 0; 2351 struct drm_display_mode *newmode; 2352 struct drm_device *dev = connector->dev; 2353 struct cvt_timing *cvt; 2354 const int rates[] = { 60, 85, 75, 60, 50 }; 2355 const u8 empty[3] = { 0, 0, 0 }; 2356 2357 for (i = 0; i < 4; i++) { 2358 int width = 0, height; 2359 cvt = &(timing->data.other_data.data.cvt[i]); 2360 2361 if (!memcmp(cvt->code, empty, 3)) 2362 continue; 2363 2364 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2365 switch (cvt->code[1] & 0x0c) { 2366 case 0x00: 2367 width = height * 4 / 3; 2368 break; 2369 case 0x04: 2370 width = height * 16 / 9; 2371 break; 2372 case 0x08: 2373 width = height * 16 / 10; 2374 break; 2375 case 0x0c: 2376 width = height * 15 / 9; 2377 break; 2378 } 2379 2380 for (j = 1; j < 5; j++) { 2381 if (cvt->code[2] & (1 << j)) { 2382 newmode = drm_cvt_mode(dev, width, height, 2383 rates[j], j == 0, 2384 false, false); 2385 if (newmode) { 2386 drm_mode_probed_add(connector, newmode); 2387 modes++; 2388 } 2389 } 2390 } 2391 } 2392 2393 return modes; 2394 } 2395 2396 static void 2397 do_cvt_mode(struct detailed_timing *timing, void *c) 2398 { 2399 struct detailed_mode_closure *closure = c; 2400 struct detailed_non_pixel *data = &timing->data.other_data; 2401 2402 if (data->type == EDID_DETAIL_CVT_3BYTE) 2403 closure->modes += drm_cvt_modes(closure->connector, timing); 2404 } 2405 2406 static int 2407 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2408 { 2409 struct detailed_mode_closure closure = { 2410 .connector = connector, 2411 .edid = edid, 2412 }; 2413 2414 if (version_greater(edid, 1, 2)) 2415 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2416 2417 /* XXX should also look for CVT codes in VTB blocks */ 2418 2419 return closure.modes; 2420 } 2421 2422 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2423 2424 static void 2425 do_detailed_mode(struct detailed_timing *timing, void *c) 2426 { 2427 struct detailed_mode_closure *closure = c; 2428 struct drm_display_mode *newmode; 2429 2430 if (timing->pixel_clock) { 2431 newmode = drm_mode_detailed(closure->connector->dev, 2432 closure->edid, timing, 2433 closure->quirks); 2434 if (!newmode) 2435 return; 2436 2437 if (closure->preferred) 2438 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2439 2440 /* 2441 * Detailed modes are limited to 10kHz pixel clock resolution, 2442 * so fix up anything that looks like CEA/HDMI mode, but the clock 2443 * is just slightly off. 2444 */ 2445 fixup_detailed_cea_mode_clock(newmode); 2446 2447 drm_mode_probed_add(closure->connector, newmode); 2448 closure->modes++; 2449 closure->preferred = 0; 2450 } 2451 } 2452 2453 /* 2454 * add_detailed_modes - Add modes from detailed timings 2455 * @connector: attached connector 2456 * @edid: EDID block to scan 2457 * @quirks: quirks to apply 2458 */ 2459 static int 2460 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2461 u32 quirks) 2462 { 2463 struct detailed_mode_closure closure = { 2464 .connector = connector, 2465 .edid = edid, 2466 .preferred = 1, 2467 .quirks = quirks, 2468 }; 2469 2470 if (closure.preferred && !version_greater(edid, 1, 3)) 2471 closure.preferred = 2472 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2473 2474 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2475 2476 return closure.modes; 2477 } 2478 2479 #define AUDIO_BLOCK 0x01 2480 #define VIDEO_BLOCK 0x02 2481 #define VENDOR_BLOCK 0x03 2482 #define SPEAKER_BLOCK 0x04 2483 #define VIDEO_CAPABILITY_BLOCK 0x07 2484 #define EDID_BASIC_AUDIO (1 << 6) 2485 #define EDID_CEA_YCRCB444 (1 << 5) 2486 #define EDID_CEA_YCRCB422 (1 << 4) 2487 #define EDID_CEA_VCDB_QS (1 << 6) 2488 2489 /* 2490 * Search EDID for CEA extension block. 2491 */ 2492 static u8 *drm_find_cea_extension(struct edid *edid) 2493 { 2494 u8 *edid_ext = NULL; 2495 int i; 2496 2497 /* No EDID or EDID extensions */ 2498 if (edid == NULL || edid->extensions == 0) 2499 return NULL; 2500 2501 /* Find CEA extension */ 2502 for (i = 0; i < edid->extensions; i++) { 2503 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2504 if (edid_ext[0] == CEA_EXT) 2505 break; 2506 } 2507 2508 if (i == edid->extensions) 2509 return NULL; 2510 2511 return edid_ext; 2512 } 2513 2514 /* 2515 * Calculate the alternate clock for the CEA mode 2516 * (60Hz vs. 59.94Hz etc.) 2517 */ 2518 static unsigned int 2519 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2520 { 2521 unsigned int clock = cea_mode->clock; 2522 2523 if (cea_mode->vrefresh % 6 != 0) 2524 return clock; 2525 2526 /* 2527 * edid_cea_modes contains the 59.94Hz 2528 * variant for 240 and 480 line modes, 2529 * and the 60Hz variant otherwise. 2530 */ 2531 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2532 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2533 else 2534 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2535 2536 return clock; 2537 } 2538 2539 /** 2540 * drm_match_cea_mode - look for a CEA mode matching given mode 2541 * @to_match: display mode 2542 * 2543 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2544 * mode. 2545 */ 2546 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2547 { 2548 u8 mode; 2549 2550 if (!to_match->clock) 2551 return 0; 2552 2553 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2554 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2555 unsigned int clock1, clock2; 2556 2557 /* Check both 60Hz and 59.94Hz */ 2558 clock1 = cea_mode->clock; 2559 clock2 = cea_mode_alternate_clock(cea_mode); 2560 2561 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2562 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2563 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2564 return mode + 1; 2565 } 2566 return 0; 2567 } 2568 EXPORT_SYMBOL(drm_match_cea_mode); 2569 2570 /** 2571 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2572 * the input VIC from the CEA mode list 2573 * @video_code: ID given to each of the CEA modes 2574 * 2575 * Returns picture aspect ratio 2576 */ 2577 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2578 { 2579 /* return picture aspect ratio for video_code - 1 to access the 2580 * right array element 2581 */ 2582 return edid_cea_modes[video_code-1].picture_aspect_ratio; 2583 } 2584 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2585 2586 /* 2587 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2588 * specific block). 2589 * 2590 * It's almost like cea_mode_alternate_clock(), we just need to add an 2591 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2592 * one. 2593 */ 2594 static unsigned int 2595 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2596 { 2597 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2598 return hdmi_mode->clock; 2599 2600 return cea_mode_alternate_clock(hdmi_mode); 2601 } 2602 2603 /* 2604 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2605 * @to_match: display mode 2606 * 2607 * An HDMI mode is one defined in the HDMI vendor specific block. 2608 * 2609 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2610 */ 2611 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2612 { 2613 u8 mode; 2614 2615 if (!to_match->clock) 2616 return 0; 2617 2618 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2619 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2620 unsigned int clock1, clock2; 2621 2622 /* Make sure to also match alternate clocks */ 2623 clock1 = hdmi_mode->clock; 2624 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2625 2626 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2627 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2628 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2629 return mode + 1; 2630 } 2631 return 0; 2632 } 2633 2634 static int 2635 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2636 { 2637 struct drm_device *dev = connector->dev; 2638 struct drm_display_mode *mode, *tmp; 2639 LINUX_LIST_HEAD(list); 2640 int modes = 0; 2641 2642 /* Don't add CEA modes if the CEA extension block is missing */ 2643 if (!drm_find_cea_extension(edid)) 2644 return 0; 2645 2646 /* 2647 * Go through all probed modes and create a new mode 2648 * with the alternate clock for certain CEA modes. 2649 */ 2650 list_for_each_entry(mode, &connector->probed_modes, head) { 2651 const struct drm_display_mode *cea_mode = NULL; 2652 struct drm_display_mode *newmode; 2653 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2654 unsigned int clock1, clock2; 2655 2656 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2657 cea_mode = &edid_cea_modes[mode_idx]; 2658 clock2 = cea_mode_alternate_clock(cea_mode); 2659 } else { 2660 mode_idx = drm_match_hdmi_mode(mode) - 1; 2661 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2662 cea_mode = &edid_4k_modes[mode_idx]; 2663 clock2 = hdmi_mode_alternate_clock(cea_mode); 2664 } 2665 } 2666 2667 if (!cea_mode) 2668 continue; 2669 2670 clock1 = cea_mode->clock; 2671 2672 if (clock1 == clock2) 2673 continue; 2674 2675 if (mode->clock != clock1 && mode->clock != clock2) 2676 continue; 2677 2678 newmode = drm_mode_duplicate(dev, cea_mode); 2679 if (!newmode) 2680 continue; 2681 2682 /* Carry over the stereo flags */ 2683 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2684 2685 /* 2686 * The current mode could be either variant. Make 2687 * sure to pick the "other" clock for the new mode. 2688 */ 2689 if (mode->clock != clock1) 2690 newmode->clock = clock1; 2691 else 2692 newmode->clock = clock2; 2693 2694 list_add_tail(&newmode->head, &list); 2695 } 2696 2697 list_for_each_entry_safe(mode, tmp, &list, head) { 2698 list_del(&mode->head); 2699 drm_mode_probed_add(connector, mode); 2700 modes++; 2701 } 2702 2703 return modes; 2704 } 2705 2706 static struct drm_display_mode * 2707 drm_display_mode_from_vic_index(struct drm_connector *connector, 2708 const u8 *video_db, u8 video_len, 2709 u8 video_index) 2710 { 2711 struct drm_device *dev = connector->dev; 2712 struct drm_display_mode *newmode; 2713 u8 cea_mode; 2714 2715 if (video_db == NULL || video_index >= video_len) 2716 return NULL; 2717 2718 /* CEA modes are numbered 1..127 */ 2719 cea_mode = (video_db[video_index] & 127) - 1; 2720 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2721 return NULL; 2722 2723 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2724 if (!newmode) 2725 return NULL; 2726 2727 newmode->vrefresh = 0; 2728 2729 return newmode; 2730 } 2731 2732 static int 2733 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2734 { 2735 int i, modes = 0; 2736 2737 for (i = 0; i < len; i++) { 2738 struct drm_display_mode *mode; 2739 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2740 if (mode) { 2741 drm_mode_probed_add(connector, mode); 2742 modes++; 2743 } 2744 } 2745 2746 return modes; 2747 } 2748 2749 struct stereo_mandatory_mode { 2750 int width, height, vrefresh; 2751 unsigned int flags; 2752 }; 2753 2754 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2755 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2756 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2757 { 1920, 1080, 50, 2758 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2759 { 1920, 1080, 60, 2760 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2761 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2762 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2763 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2764 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2765 }; 2766 2767 static bool 2768 stereo_match_mandatory(const struct drm_display_mode *mode, 2769 const struct stereo_mandatory_mode *stereo_mode) 2770 { 2771 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2772 2773 return mode->hdisplay == stereo_mode->width && 2774 mode->vdisplay == stereo_mode->height && 2775 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2776 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2777 } 2778 2779 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2780 { 2781 struct drm_device *dev = connector->dev; 2782 struct drm_display_mode *mode; 2783 struct list_head stereo_modes; 2784 int modes = 0, i; 2785 2786 INIT_LIST_HEAD(&stereo_modes); 2787 2788 list_for_each_entry(mode, &connector->probed_modes, head) { 2789 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2790 const struct stereo_mandatory_mode *mandatory; 2791 struct drm_display_mode *new_mode; 2792 2793 if (!stereo_match_mandatory(mode, 2794 &stereo_mandatory_modes[i])) 2795 continue; 2796 2797 mandatory = &stereo_mandatory_modes[i]; 2798 new_mode = drm_mode_duplicate(dev, mode); 2799 if (!new_mode) 2800 continue; 2801 2802 new_mode->flags |= mandatory->flags; 2803 list_add_tail(&new_mode->head, &stereo_modes); 2804 modes++; 2805 } 2806 } 2807 2808 list_splice_tail(&stereo_modes, &connector->probed_modes); 2809 2810 return modes; 2811 } 2812 2813 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2814 { 2815 struct drm_device *dev = connector->dev; 2816 struct drm_display_mode *newmode; 2817 2818 vic--; /* VICs start at 1 */ 2819 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2820 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2821 return 0; 2822 } 2823 2824 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2825 if (!newmode) 2826 return 0; 2827 2828 drm_mode_probed_add(connector, newmode); 2829 2830 return 1; 2831 } 2832 2833 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2834 const u8 *video_db, u8 video_len, u8 video_index) 2835 { 2836 struct drm_display_mode *newmode; 2837 int modes = 0; 2838 2839 if (structure & (1 << 0)) { 2840 newmode = drm_display_mode_from_vic_index(connector, video_db, 2841 video_len, 2842 video_index); 2843 if (newmode) { 2844 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2845 drm_mode_probed_add(connector, newmode); 2846 modes++; 2847 } 2848 } 2849 if (structure & (1 << 6)) { 2850 newmode = drm_display_mode_from_vic_index(connector, video_db, 2851 video_len, 2852 video_index); 2853 if (newmode) { 2854 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2855 drm_mode_probed_add(connector, newmode); 2856 modes++; 2857 } 2858 } 2859 if (structure & (1 << 8)) { 2860 newmode = drm_display_mode_from_vic_index(connector, video_db, 2861 video_len, 2862 video_index); 2863 if (newmode) { 2864 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2865 drm_mode_probed_add(connector, newmode); 2866 modes++; 2867 } 2868 } 2869 2870 return modes; 2871 } 2872 2873 /* 2874 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2875 * @connector: connector corresponding to the HDMI sink 2876 * @db: start of the CEA vendor specific block 2877 * @len: length of the CEA block payload, ie. one can access up to db[len] 2878 * 2879 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2880 * also adds the stereo 3d modes when applicable. 2881 */ 2882 static int 2883 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2884 const u8 *video_db, u8 video_len) 2885 { 2886 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2887 u8 vic_len, hdmi_3d_len = 0; 2888 u16 mask; 2889 u16 structure_all; 2890 2891 if (len < 8) 2892 goto out; 2893 2894 /* no HDMI_Video_Present */ 2895 if (!(db[8] & (1 << 5))) 2896 goto out; 2897 2898 /* Latency_Fields_Present */ 2899 if (db[8] & (1 << 7)) 2900 offset += 2; 2901 2902 /* I_Latency_Fields_Present */ 2903 if (db[8] & (1 << 6)) 2904 offset += 2; 2905 2906 /* the declared length is not long enough for the 2 first bytes 2907 * of additional video format capabilities */ 2908 if (len < (8 + offset + 2)) 2909 goto out; 2910 2911 /* 3D_Present */ 2912 offset++; 2913 if (db[8 + offset] & (1 << 7)) { 2914 modes += add_hdmi_mandatory_stereo_modes(connector); 2915 2916 /* 3D_Multi_present */ 2917 multi_present = (db[8 + offset] & 0x60) >> 5; 2918 } 2919 2920 offset++; 2921 vic_len = db[8 + offset] >> 5; 2922 hdmi_3d_len = db[8 + offset] & 0x1f; 2923 2924 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2925 u8 vic; 2926 2927 vic = db[9 + offset + i]; 2928 modes += add_hdmi_mode(connector, vic); 2929 } 2930 offset += 1 + vic_len; 2931 2932 if (multi_present == 1) 2933 multi_len = 2; 2934 else if (multi_present == 2) 2935 multi_len = 4; 2936 else 2937 multi_len = 0; 2938 2939 if (len < (8 + offset + hdmi_3d_len - 1)) 2940 goto out; 2941 2942 if (hdmi_3d_len < multi_len) 2943 goto out; 2944 2945 if (multi_present == 1 || multi_present == 2) { 2946 /* 3D_Structure_ALL */ 2947 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2948 2949 /* check if 3D_MASK is present */ 2950 if (multi_present == 2) 2951 mask = (db[10 + offset] << 8) | db[11 + offset]; 2952 else 2953 mask = 0xffff; 2954 2955 for (i = 0; i < 16; i++) { 2956 if (mask & (1 << i)) 2957 modes += add_3d_struct_modes(connector, 2958 structure_all, 2959 video_db, 2960 video_len, i); 2961 } 2962 } 2963 2964 offset += multi_len; 2965 2966 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2967 int vic_index; 2968 struct drm_display_mode *newmode = NULL; 2969 unsigned int newflag = 0; 2970 bool detail_present; 2971 2972 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2973 2974 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2975 break; 2976 2977 /* 2D_VIC_order_X */ 2978 vic_index = db[8 + offset + i] >> 4; 2979 2980 /* 3D_Structure_X */ 2981 switch (db[8 + offset + i] & 0x0f) { 2982 case 0: 2983 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2984 break; 2985 case 6: 2986 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2987 break; 2988 case 8: 2989 /* 3D_Detail_X */ 2990 if ((db[9 + offset + i] >> 4) == 1) 2991 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2992 break; 2993 } 2994 2995 if (newflag != 0) { 2996 newmode = drm_display_mode_from_vic_index(connector, 2997 video_db, 2998 video_len, 2999 vic_index); 3000 3001 if (newmode) { 3002 newmode->flags |= newflag; 3003 drm_mode_probed_add(connector, newmode); 3004 modes++; 3005 } 3006 } 3007 3008 if (detail_present) 3009 i++; 3010 } 3011 3012 out: 3013 return modes; 3014 } 3015 3016 static int 3017 cea_db_payload_len(const u8 *db) 3018 { 3019 return db[0] & 0x1f; 3020 } 3021 3022 static int 3023 cea_db_tag(const u8 *db) 3024 { 3025 return db[0] >> 5; 3026 } 3027 3028 static int 3029 cea_revision(const u8 *cea) 3030 { 3031 return cea[1]; 3032 } 3033 3034 static int 3035 cea_db_offsets(const u8 *cea, int *start, int *end) 3036 { 3037 /* Data block offset in CEA extension block */ 3038 *start = 4; 3039 *end = cea[2]; 3040 if (*end == 0) 3041 *end = 127; 3042 if (*end < 4 || *end > 127) 3043 return -ERANGE; 3044 return 0; 3045 } 3046 3047 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3048 { 3049 int hdmi_id; 3050 3051 if (cea_db_tag(db) != VENDOR_BLOCK) 3052 return false; 3053 3054 if (cea_db_payload_len(db) < 5) 3055 return false; 3056 3057 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3058 3059 return hdmi_id == HDMI_IEEE_OUI; 3060 } 3061 3062 #define for_each_cea_db(cea, i, start, end) \ 3063 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3064 3065 static int 3066 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3067 { 3068 const u8 *cea = drm_find_cea_extension(edid); 3069 const u8 *db, *hdmi = NULL, *video = NULL; 3070 u8 dbl, hdmi_len, video_len = 0; 3071 int modes = 0; 3072 3073 if (cea && cea_revision(cea) >= 3) { 3074 int i, start, end; 3075 3076 if (cea_db_offsets(cea, &start, &end)) 3077 return 0; 3078 3079 for_each_cea_db(cea, i, start, end) { 3080 db = &cea[i]; 3081 dbl = cea_db_payload_len(db); 3082 3083 if (cea_db_tag(db) == VIDEO_BLOCK) { 3084 video = db + 1; 3085 video_len = dbl; 3086 modes += do_cea_modes(connector, video, dbl); 3087 } 3088 else if (cea_db_is_hdmi_vsdb(db)) { 3089 hdmi = db; 3090 hdmi_len = dbl; 3091 } 3092 } 3093 } 3094 3095 /* 3096 * We parse the HDMI VSDB after having added the cea modes as we will 3097 * be patching their flags when the sink supports stereo 3D. 3098 */ 3099 if (hdmi) 3100 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3101 video_len); 3102 3103 return modes; 3104 } 3105 3106 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3107 { 3108 const struct drm_display_mode *cea_mode; 3109 int clock1, clock2, clock; 3110 u8 mode_idx; 3111 const char *type; 3112 3113 mode_idx = drm_match_cea_mode(mode) - 1; 3114 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 3115 type = "CEA"; 3116 cea_mode = &edid_cea_modes[mode_idx]; 3117 clock1 = cea_mode->clock; 3118 clock2 = cea_mode_alternate_clock(cea_mode); 3119 } else { 3120 mode_idx = drm_match_hdmi_mode(mode) - 1; 3121 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 3122 type = "HDMI"; 3123 cea_mode = &edid_4k_modes[mode_idx]; 3124 clock1 = cea_mode->clock; 3125 clock2 = hdmi_mode_alternate_clock(cea_mode); 3126 } else { 3127 return; 3128 } 3129 } 3130 3131 /* pick whichever is closest */ 3132 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3133 clock = clock1; 3134 else 3135 clock = clock2; 3136 3137 if (mode->clock == clock) 3138 return; 3139 3140 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3141 type, mode_idx + 1, mode->clock, clock); 3142 mode->clock = clock; 3143 } 3144 3145 static void 3146 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3147 { 3148 u8 len = cea_db_payload_len(db); 3149 3150 if (len >= 6) { 3151 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3152 connector->dvi_dual = db[6] & 1; 3153 } 3154 if (len >= 7) 3155 connector->max_tmds_clock = db[7] * 5; 3156 if (len >= 8) { 3157 connector->latency_present[0] = db[8] >> 7; 3158 connector->latency_present[1] = (db[8] >> 6) & 1; 3159 } 3160 if (len >= 9) 3161 connector->video_latency[0] = db[9]; 3162 if (len >= 10) 3163 connector->audio_latency[0] = db[10]; 3164 if (len >= 11) 3165 connector->video_latency[1] = db[11]; 3166 if (len >= 12) 3167 connector->audio_latency[1] = db[12]; 3168 3169 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3170 "max TMDS clock %d, " 3171 "latency present %d %d, " 3172 "video latency %d %d, " 3173 "audio latency %d %d\n", 3174 connector->dvi_dual, 3175 connector->max_tmds_clock, 3176 (int) connector->latency_present[0], 3177 (int) connector->latency_present[1], 3178 connector->video_latency[0], 3179 connector->video_latency[1], 3180 connector->audio_latency[0], 3181 connector->audio_latency[1]); 3182 } 3183 3184 static void 3185 monitor_name(struct detailed_timing *t, void *data) 3186 { 3187 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3188 *(u8 **)data = t->data.other_data.data.str.str; 3189 } 3190 3191 /** 3192 * drm_edid_to_eld - build ELD from EDID 3193 * @connector: connector corresponding to the HDMI/DP sink 3194 * @edid: EDID to parse 3195 * 3196 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3197 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3198 * fill in. 3199 */ 3200 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3201 { 3202 uint8_t *eld = connector->eld; 3203 u8 *cea; 3204 u8 *name; 3205 u8 *db; 3206 int sad_count = 0; 3207 int mnl; 3208 int dbl; 3209 3210 memset(eld, 0, sizeof(connector->eld)); 3211 3212 cea = drm_find_cea_extension(edid); 3213 if (!cea) { 3214 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3215 return; 3216 } 3217 3218 name = NULL; 3219 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3220 for (mnl = 0; name && mnl < 13; mnl++) { 3221 if (name[mnl] == 0x0a) 3222 break; 3223 eld[20 + mnl] = name[mnl]; 3224 } 3225 eld[4] = (cea[1] << 5) | mnl; 3226 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3227 3228 eld[0] = 2 << 3; /* ELD version: 2 */ 3229 3230 eld[16] = edid->mfg_id[0]; 3231 eld[17] = edid->mfg_id[1]; 3232 eld[18] = edid->prod_code[0]; 3233 eld[19] = edid->prod_code[1]; 3234 3235 if (cea_revision(cea) >= 3) { 3236 int i, start, end; 3237 3238 if (cea_db_offsets(cea, &start, &end)) { 3239 start = 0; 3240 end = 0; 3241 } 3242 3243 for_each_cea_db(cea, i, start, end) { 3244 db = &cea[i]; 3245 dbl = cea_db_payload_len(db); 3246 3247 switch (cea_db_tag(db)) { 3248 case AUDIO_BLOCK: 3249 /* Audio Data Block, contains SADs */ 3250 sad_count = dbl / 3; 3251 if (dbl >= 1) 3252 memcpy(eld + 20 + mnl, &db[1], dbl); 3253 break; 3254 case SPEAKER_BLOCK: 3255 /* Speaker Allocation Data Block */ 3256 if (dbl >= 1) 3257 eld[7] = db[1]; 3258 break; 3259 case VENDOR_BLOCK: 3260 /* HDMI Vendor-Specific Data Block */ 3261 if (cea_db_is_hdmi_vsdb(db)) 3262 parse_hdmi_vsdb(connector, db); 3263 break; 3264 default: 3265 break; 3266 } 3267 } 3268 } 3269 eld[5] |= sad_count << 4; 3270 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; 3271 3272 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); 3273 } 3274 EXPORT_SYMBOL(drm_edid_to_eld); 3275 3276 /** 3277 * drm_edid_to_sad - extracts SADs from EDID 3278 * @edid: EDID to parse 3279 * @sads: pointer that will be set to the extracted SADs 3280 * 3281 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3282 * 3283 * Note: The returned pointer needs to be freed using kfree(). 3284 * 3285 * Return: The number of found SADs or negative number on error. 3286 */ 3287 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3288 { 3289 int count = 0; 3290 int i, start, end, dbl; 3291 u8 *cea; 3292 3293 cea = drm_find_cea_extension(edid); 3294 if (!cea) { 3295 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3296 return -ENOENT; 3297 } 3298 3299 if (cea_revision(cea) < 3) { 3300 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3301 return -EOPNOTSUPP; 3302 } 3303 3304 if (cea_db_offsets(cea, &start, &end)) { 3305 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3306 return -EPROTO; 3307 } 3308 3309 for_each_cea_db(cea, i, start, end) { 3310 u8 *db = &cea[i]; 3311 3312 if (cea_db_tag(db) == AUDIO_BLOCK) { 3313 int j; 3314 dbl = cea_db_payload_len(db); 3315 3316 count = dbl / 3; /* SAD is 3B */ 3317 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3318 if (!*sads) 3319 return -ENOMEM; 3320 for (j = 0; j < count; j++) { 3321 u8 *sad = &db[1 + j * 3]; 3322 3323 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3324 (*sads)[j].channels = sad[0] & 0x7; 3325 (*sads)[j].freq = sad[1] & 0x7F; 3326 (*sads)[j].byte2 = sad[2]; 3327 } 3328 break; 3329 } 3330 } 3331 3332 return count; 3333 } 3334 EXPORT_SYMBOL(drm_edid_to_sad); 3335 3336 /** 3337 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3338 * @edid: EDID to parse 3339 * @sadb: pointer to the speaker block 3340 * 3341 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3342 * 3343 * Note: The returned pointer needs to be freed using kfree(). 3344 * 3345 * Return: The number of found Speaker Allocation Blocks or negative number on 3346 * error. 3347 */ 3348 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3349 { 3350 int count = 0; 3351 int i, start, end, dbl; 3352 const u8 *cea; 3353 3354 cea = drm_find_cea_extension(edid); 3355 if (!cea) { 3356 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3357 return -ENOENT; 3358 } 3359 3360 if (cea_revision(cea) < 3) { 3361 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3362 return -ENOTSUPP; 3363 } 3364 3365 if (cea_db_offsets(cea, &start, &end)) { 3366 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3367 return -EPROTO; 3368 } 3369 3370 for_each_cea_db(cea, i, start, end) { 3371 const u8 *db = &cea[i]; 3372 3373 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3374 dbl = cea_db_payload_len(db); 3375 3376 /* Speaker Allocation Data Block */ 3377 if (dbl == 3) { 3378 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3379 if (!*sadb) 3380 return -ENOMEM; 3381 count = dbl; 3382 break; 3383 } 3384 } 3385 } 3386 3387 return count; 3388 } 3389 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3390 3391 /** 3392 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3393 * @connector: connector associated with the HDMI/DP sink 3394 * @mode: the display mode 3395 * 3396 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3397 * the sink doesn't support audio or video. 3398 */ 3399 int drm_av_sync_delay(struct drm_connector *connector, 3400 const struct drm_display_mode *mode) 3401 { 3402 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3403 int a, v; 3404 3405 if (!connector->latency_present[0]) 3406 return 0; 3407 if (!connector->latency_present[1]) 3408 i = 0; 3409 3410 a = connector->audio_latency[i]; 3411 v = connector->video_latency[i]; 3412 3413 /* 3414 * HDMI/DP sink doesn't support audio or video? 3415 */ 3416 if (a == 255 || v == 255) 3417 return 0; 3418 3419 /* 3420 * Convert raw EDID values to millisecond. 3421 * Treat unknown latency as 0ms. 3422 */ 3423 if (a) 3424 a = min(2 * (a - 1), 500); 3425 if (v) 3426 v = min(2 * (v - 1), 500); 3427 3428 return max(v - a, 0); 3429 } 3430 EXPORT_SYMBOL(drm_av_sync_delay); 3431 3432 /** 3433 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3434 * @encoder: the encoder just changed display mode 3435 * 3436 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3437 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3438 * 3439 * Return: The connector associated with the first HDMI/DP sink that has ELD 3440 * attached to it. 3441 */ 3442 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3443 { 3444 struct drm_connector *connector; 3445 struct drm_device *dev = encoder->dev; 3446 3447 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3448 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3449 3450 drm_for_each_connector(connector, dev) 3451 if (connector->encoder == encoder && connector->eld[0]) 3452 return connector; 3453 3454 return NULL; 3455 } 3456 EXPORT_SYMBOL(drm_select_eld); 3457 3458 /** 3459 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3460 * @edid: monitor EDID information 3461 * 3462 * Parse the CEA extension according to CEA-861-B. 3463 * 3464 * Return: True if the monitor is HDMI, false if not or unknown. 3465 */ 3466 bool drm_detect_hdmi_monitor(struct edid *edid) 3467 { 3468 u8 *edid_ext; 3469 int i; 3470 int start_offset, end_offset; 3471 3472 edid_ext = drm_find_cea_extension(edid); 3473 if (!edid_ext) 3474 return false; 3475 3476 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3477 return false; 3478 3479 /* 3480 * Because HDMI identifier is in Vendor Specific Block, 3481 * search it from all data blocks of CEA extension. 3482 */ 3483 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3484 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3485 return true; 3486 } 3487 3488 return false; 3489 } 3490 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3491 3492 /** 3493 * drm_detect_monitor_audio - check monitor audio capability 3494 * @edid: EDID block to scan 3495 * 3496 * Monitor should have CEA extension block. 3497 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3498 * audio' only. If there is any audio extension block and supported 3499 * audio format, assume at least 'basic audio' support, even if 'basic 3500 * audio' is not defined in EDID. 3501 * 3502 * Return: True if the monitor supports audio, false otherwise. 3503 */ 3504 bool drm_detect_monitor_audio(struct edid *edid) 3505 { 3506 u8 *edid_ext; 3507 int i, j; 3508 bool has_audio = false; 3509 int start_offset, end_offset; 3510 3511 edid_ext = drm_find_cea_extension(edid); 3512 if (!edid_ext) 3513 goto end; 3514 3515 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3516 3517 if (has_audio) { 3518 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3519 goto end; 3520 } 3521 3522 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3523 goto end; 3524 3525 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3526 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3527 has_audio = true; 3528 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3529 DRM_DEBUG_KMS("CEA audio format %d\n", 3530 (edid_ext[i + j] >> 3) & 0xf); 3531 goto end; 3532 } 3533 } 3534 end: 3535 return has_audio; 3536 } 3537 EXPORT_SYMBOL(drm_detect_monitor_audio); 3538 3539 /** 3540 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3541 * @edid: EDID block to scan 3542 * 3543 * Check whether the monitor reports the RGB quantization range selection 3544 * as supported. The AVI infoframe can then be used to inform the monitor 3545 * which quantization range (full or limited) is used. 3546 * 3547 * Return: True if the RGB quantization range is selectable, false otherwise. 3548 */ 3549 bool drm_rgb_quant_range_selectable(struct edid *edid) 3550 { 3551 u8 *edid_ext; 3552 int i, start, end; 3553 3554 edid_ext = drm_find_cea_extension(edid); 3555 if (!edid_ext) 3556 return false; 3557 3558 if (cea_db_offsets(edid_ext, &start, &end)) 3559 return false; 3560 3561 for_each_cea_db(edid_ext, i, start, end) { 3562 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3563 cea_db_payload_len(&edid_ext[i]) == 2) { 3564 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3565 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3566 } 3567 } 3568 3569 return false; 3570 } 3571 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3572 3573 /** 3574 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3575 * hdmi deep color modes and update drm_display_info if so. 3576 * @edid: monitor EDID information 3577 * @info: Updated with maximum supported deep color bpc and color format 3578 * if deep color supported. 3579 * @connector: DRM connector, used only for debug output 3580 * 3581 * Parse the CEA extension according to CEA-861-B. 3582 * Return true if HDMI deep color supported, false if not or unknown. 3583 */ 3584 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3585 struct drm_display_info *info, 3586 struct drm_connector *connector) 3587 { 3588 u8 *edid_ext, *hdmi; 3589 int i; 3590 int start_offset, end_offset; 3591 unsigned int dc_bpc = 0; 3592 3593 edid_ext = drm_find_cea_extension(edid); 3594 if (!edid_ext) 3595 return false; 3596 3597 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3598 return false; 3599 3600 /* 3601 * Because HDMI identifier is in Vendor Specific Block, 3602 * search it from all data blocks of CEA extension. 3603 */ 3604 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3605 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3606 /* HDMI supports at least 8 bpc */ 3607 info->bpc = 8; 3608 3609 hdmi = &edid_ext[i]; 3610 if (cea_db_payload_len(hdmi) < 6) 3611 return false; 3612 3613 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3614 dc_bpc = 10; 3615 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3616 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3617 connector->name); 3618 } 3619 3620 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3621 dc_bpc = 12; 3622 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3623 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3624 connector->name); 3625 } 3626 3627 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3628 dc_bpc = 16; 3629 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3630 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3631 connector->name); 3632 } 3633 3634 if (dc_bpc > 0) { 3635 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3636 connector->name, dc_bpc); 3637 info->bpc = dc_bpc; 3638 3639 /* 3640 * Deep color support mandates RGB444 support for all video 3641 * modes and forbids YCRCB422 support for all video modes per 3642 * HDMI 1.3 spec. 3643 */ 3644 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3645 3646 /* YCRCB444 is optional according to spec. */ 3647 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3648 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3649 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3650 connector->name); 3651 } 3652 3653 /* 3654 * Spec says that if any deep color mode is supported at all, 3655 * then deep color 36 bit must be supported. 3656 */ 3657 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3658 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3659 connector->name); 3660 } 3661 3662 return true; 3663 } 3664 else { 3665 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3666 connector->name); 3667 } 3668 } 3669 } 3670 3671 return false; 3672 } 3673 3674 /** 3675 * drm_add_display_info - pull display info out if present 3676 * @edid: EDID data 3677 * @info: display info (attached to connector) 3678 * @connector: connector whose edid is used to build display info 3679 * 3680 * Grab any available display info and stuff it into the drm_display_info 3681 * structure that's part of the connector. Useful for tracking bpp and 3682 * color spaces. 3683 */ 3684 static void drm_add_display_info(struct edid *edid, 3685 struct drm_display_info *info, 3686 struct drm_connector *connector) 3687 { 3688 u8 *edid_ext; 3689 3690 info->width_mm = edid->width_cm * 10; 3691 info->height_mm = edid->height_cm * 10; 3692 3693 /* driver figures it out in this case */ 3694 info->bpc = 0; 3695 info->color_formats = 0; 3696 3697 if (edid->revision < 3) 3698 return; 3699 3700 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3701 return; 3702 3703 /* Get data from CEA blocks if present */ 3704 edid_ext = drm_find_cea_extension(edid); 3705 if (edid_ext) { 3706 info->cea_rev = edid_ext[1]; 3707 3708 /* The existence of a CEA block should imply RGB support */ 3709 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3710 if (edid_ext[3] & EDID_CEA_YCRCB444) 3711 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3712 if (edid_ext[3] & EDID_CEA_YCRCB422) 3713 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3714 } 3715 3716 /* HDMI deep color modes supported? Assign to info, if so */ 3717 drm_assign_hdmi_deep_color_info(edid, info, connector); 3718 3719 /* Only defined for 1.4 with digital displays */ 3720 if (edid->revision < 4) 3721 return; 3722 3723 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3724 case DRM_EDID_DIGITAL_DEPTH_6: 3725 info->bpc = 6; 3726 break; 3727 case DRM_EDID_DIGITAL_DEPTH_8: 3728 info->bpc = 8; 3729 break; 3730 case DRM_EDID_DIGITAL_DEPTH_10: 3731 info->bpc = 10; 3732 break; 3733 case DRM_EDID_DIGITAL_DEPTH_12: 3734 info->bpc = 12; 3735 break; 3736 case DRM_EDID_DIGITAL_DEPTH_14: 3737 info->bpc = 14; 3738 break; 3739 case DRM_EDID_DIGITAL_DEPTH_16: 3740 info->bpc = 16; 3741 break; 3742 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3743 default: 3744 info->bpc = 0; 3745 break; 3746 } 3747 3748 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3749 connector->name, info->bpc); 3750 3751 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3752 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3753 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3754 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3755 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3756 } 3757 3758 /** 3759 * drm_add_edid_modes - add modes from EDID data, if available 3760 * @connector: connector we're probing 3761 * @edid: EDID data 3762 * 3763 * Add the specified modes to the connector's mode list. 3764 * 3765 * Return: The number of modes added or 0 if we couldn't find any. 3766 */ 3767 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3768 { 3769 int num_modes = 0; 3770 u32 quirks; 3771 3772 if (edid == NULL) { 3773 return 0; 3774 } 3775 if (!drm_edid_is_valid(edid)) { 3776 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3777 connector->name); 3778 return 0; 3779 } 3780 3781 quirks = edid_get_quirks(edid); 3782 3783 /* 3784 * EDID spec says modes should be preferred in this order: 3785 * - preferred detailed mode 3786 * - other detailed modes from base block 3787 * - detailed modes from extension blocks 3788 * - CVT 3-byte code modes 3789 * - standard timing codes 3790 * - established timing codes 3791 * - modes inferred from GTF or CVT range information 3792 * 3793 * We get this pretty much right. 3794 * 3795 * XXX order for additional mode types in extension blocks? 3796 */ 3797 num_modes += add_detailed_modes(connector, edid, quirks); 3798 num_modes += add_cvt_modes(connector, edid); 3799 num_modes += add_standard_modes(connector, edid); 3800 num_modes += add_established_modes(connector, edid); 3801 num_modes += add_cea_modes(connector, edid); 3802 num_modes += add_alternate_cea_modes(connector, edid); 3803 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3804 num_modes += add_inferred_modes(connector, edid); 3805 3806 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3807 edid_fixup_preferred(connector, quirks); 3808 3809 drm_add_display_info(edid, &connector->display_info, connector); 3810 3811 if (quirks & EDID_QUIRK_FORCE_8BPC) 3812 connector->display_info.bpc = 8; 3813 3814 if (quirks & EDID_QUIRK_FORCE_12BPC) 3815 connector->display_info.bpc = 12; 3816 3817 return num_modes; 3818 } 3819 EXPORT_SYMBOL(drm_add_edid_modes); 3820 3821 /** 3822 * drm_add_modes_noedid - add modes for the connectors without EDID 3823 * @connector: connector we're probing 3824 * @hdisplay: the horizontal display limit 3825 * @vdisplay: the vertical display limit 3826 * 3827 * Add the specified modes to the connector's mode list. Only when the 3828 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3829 * 3830 * Return: The number of modes added or 0 if we couldn't find any. 3831 */ 3832 int drm_add_modes_noedid(struct drm_connector *connector, 3833 int hdisplay, int vdisplay) 3834 { 3835 int i, count, num_modes = 0; 3836 struct drm_display_mode *mode; 3837 struct drm_device *dev = connector->dev; 3838 3839 count = ARRAY_SIZE(drm_dmt_modes); 3840 if (hdisplay < 0) 3841 hdisplay = 0; 3842 if (vdisplay < 0) 3843 vdisplay = 0; 3844 3845 for (i = 0; i < count; i++) { 3846 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3847 if (hdisplay && vdisplay) { 3848 /* 3849 * Only when two are valid, they will be used to check 3850 * whether the mode should be added to the mode list of 3851 * the connector. 3852 */ 3853 if (ptr->hdisplay > hdisplay || 3854 ptr->vdisplay > vdisplay) 3855 continue; 3856 } 3857 if (drm_mode_vrefresh(ptr) > 61) 3858 continue; 3859 mode = drm_mode_duplicate(dev, ptr); 3860 if (mode) { 3861 drm_mode_probed_add(connector, mode); 3862 num_modes++; 3863 } 3864 } 3865 return num_modes; 3866 } 3867 EXPORT_SYMBOL(drm_add_modes_noedid); 3868 3869 /** 3870 * drm_set_preferred_mode - Sets the preferred mode of a connector 3871 * @connector: connector whose mode list should be processed 3872 * @hpref: horizontal resolution of preferred mode 3873 * @vpref: vertical resolution of preferred mode 3874 * 3875 * Marks a mode as preferred if it matches the resolution specified by @hpref 3876 * and @vpref. 3877 */ 3878 void drm_set_preferred_mode(struct drm_connector *connector, 3879 int hpref, int vpref) 3880 { 3881 struct drm_display_mode *mode; 3882 3883 list_for_each_entry(mode, &connector->probed_modes, head) { 3884 if (mode->hdisplay == hpref && 3885 mode->vdisplay == vpref) 3886 mode->type |= DRM_MODE_TYPE_PREFERRED; 3887 } 3888 } 3889 EXPORT_SYMBOL(drm_set_preferred_mode); 3890 3891 /** 3892 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3893 * data from a DRM display mode 3894 * @frame: HDMI AVI infoframe 3895 * @mode: DRM display mode 3896 * 3897 * Return: 0 on success or a negative error code on failure. 3898 */ 3899 int 3900 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3901 const struct drm_display_mode *mode) 3902 { 3903 int err; 3904 3905 if (!frame || !mode) 3906 return -EINVAL; 3907 3908 err = hdmi_avi_infoframe_init(frame); 3909 if (err < 0) 3910 return err; 3911 3912 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3913 frame->pixel_repeat = 1; 3914 3915 frame->video_code = drm_match_cea_mode(mode); 3916 3917 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3918 3919 /* 3920 * Populate picture aspect ratio from either 3921 * user input (if specified) or from the CEA mode list. 3922 */ 3923 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 3924 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 3925 frame->picture_aspect = mode->picture_aspect_ratio; 3926 else if (frame->video_code > 0) 3927 frame->picture_aspect = drm_get_cea_aspect_ratio( 3928 frame->video_code); 3929 3930 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3931 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 3932 3933 return 0; 3934 } 3935 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3936 3937 static enum hdmi_3d_structure 3938 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 3939 { 3940 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 3941 3942 switch (layout) { 3943 case DRM_MODE_FLAG_3D_FRAME_PACKING: 3944 return HDMI_3D_STRUCTURE_FRAME_PACKING; 3945 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 3946 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 3947 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 3948 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 3949 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 3950 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 3951 case DRM_MODE_FLAG_3D_L_DEPTH: 3952 return HDMI_3D_STRUCTURE_L_DEPTH; 3953 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 3954 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 3955 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 3956 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 3957 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 3958 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 3959 default: 3960 return HDMI_3D_STRUCTURE_INVALID; 3961 } 3962 } 3963 3964 /** 3965 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 3966 * data from a DRM display mode 3967 * @frame: HDMI vendor infoframe 3968 * @mode: DRM display mode 3969 * 3970 * Note that there's is a need to send HDMI vendor infoframes only when using a 3971 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 3972 * function will return -EINVAL, error that can be safely ignored. 3973 * 3974 * Return: 0 on success or a negative error code on failure. 3975 */ 3976 int 3977 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 3978 const struct drm_display_mode *mode) 3979 { 3980 int err; 3981 u32 s3d_flags; 3982 u8 vic; 3983 3984 if (!frame || !mode) 3985 return -EINVAL; 3986 3987 vic = drm_match_hdmi_mode(mode); 3988 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 3989 3990 if (!vic && !s3d_flags) 3991 return -EINVAL; 3992 3993 if (vic && s3d_flags) 3994 return -EINVAL; 3995 3996 err = hdmi_vendor_infoframe_init(frame); 3997 if (err < 0) 3998 return err; 3999 4000 if (vic) 4001 frame->vic = vic; 4002 else 4003 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4004 4005 return 0; 4006 } 4007 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4008