1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/module.h> 34 #include <drm/drmP.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_displayid.h> 37 #include <linux/string.h> 38 39 #include <bus/iicbus/iic.h> 40 #include <bus/iicbus/iiconf.h> 41 #include "iicbus_if.h" 42 43 #define version_greater(edid, maj, min) \ 44 (((edid)->version > (maj)) || \ 45 ((edid)->version == (maj) && (edid)->revision > (min))) 46 47 #define EDID_EST_TIMINGS 16 48 #define EDID_STD_TIMINGS 8 49 #define EDID_DETAILED_TIMINGS 4 50 51 /* 52 * EDID blocks out in the wild have a variety of bugs, try to collect 53 * them here (note that userspace may work around broken monitors first, 54 * but fixes should make their way here so that the kernel "just works" 55 * on as many displays as possible). 56 */ 57 58 /* First detailed mode wrong, use largest 60Hz mode */ 59 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 60 /* Reported 135MHz pixel clock is too high, needs adjustment */ 61 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 62 /* Prefer the largest mode at 75 Hz */ 63 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 64 /* Detail timing is in cm not mm */ 65 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 66 /* Detailed timing descriptors have bogus size values, so just take the 67 * maximum size and use that. 68 */ 69 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 70 /* Monitor forgot to set the first detailed is preferred bit. */ 71 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 72 /* use +hsync +vsync for detailed mode */ 73 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 74 /* Force reduced-blanking timings for detailed modes */ 75 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 76 /* Force 8bpc */ 77 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 78 /* Force 12bpc */ 79 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 80 /* Force 6bpc */ 81 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 82 83 struct detailed_mode_closure { 84 struct drm_connector *connector; 85 struct edid *edid; 86 bool preferred; 87 u32 quirks; 88 int modes; 89 }; 90 91 #define LEVEL_DMT 0 92 #define LEVEL_GTF 1 93 #define LEVEL_GTF2 2 94 #define LEVEL_CVT 3 95 96 static struct edid_quirk { 97 char vendor[4]; 98 int product_id; 99 u32 quirks; 100 } edid_quirk_list[] = { 101 /* Acer AL1706 */ 102 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 103 /* Acer F51 */ 104 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 105 /* Unknown Acer */ 106 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 107 108 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 109 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 110 111 /* Belinea 10 15 55 */ 112 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 113 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 114 115 /* Envision Peripherals, Inc. EN-7100e */ 116 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 117 /* Envision EN2028 */ 118 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 119 120 /* Funai Electronics PM36B */ 121 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 122 EDID_QUIRK_DETAILED_IN_CM }, 123 124 /* LG Philips LCD LP154W01-A5 */ 125 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 126 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 127 128 /* Philips 107p5 CRT */ 129 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 130 131 /* Proview AY765C */ 132 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 133 134 /* Samsung SyncMaster 205BW. Note: irony */ 135 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 136 /* Samsung SyncMaster 22[5-6]BW */ 137 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 138 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 139 140 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 141 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 142 143 /* ViewSonic VA2026w */ 144 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 145 146 /* Medion MD 30217 PG */ 147 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 148 149 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 150 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 151 }; 152 153 /* 154 * Autogenerated from the DMT spec. 155 * This table is copied from xfree86/modes/xf86EdidModes.c. 156 */ 157 static const struct drm_display_mode drm_dmt_modes[] = { 158 /* 0x01 - 640x350@85Hz */ 159 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 160 736, 832, 0, 350, 382, 385, 445, 0, 161 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 162 /* 0x02 - 640x400@85Hz */ 163 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 164 736, 832, 0, 400, 401, 404, 445, 0, 165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 166 /* 0x03 - 720x400@85Hz */ 167 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 168 828, 936, 0, 400, 401, 404, 446, 0, 169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 170 /* 0x04 - 640x480@60Hz */ 171 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 172 752, 800, 0, 480, 490, 492, 525, 0, 173 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 174 /* 0x05 - 640x480@72Hz */ 175 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 176 704, 832, 0, 480, 489, 492, 520, 0, 177 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 178 /* 0x06 - 640x480@75Hz */ 179 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 180 720, 840, 0, 480, 481, 484, 500, 0, 181 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 182 /* 0x07 - 640x480@85Hz */ 183 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 184 752, 832, 0, 480, 481, 484, 509, 0, 185 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 186 /* 0x08 - 800x600@56Hz */ 187 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 188 896, 1024, 0, 600, 601, 603, 625, 0, 189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 190 /* 0x09 - 800x600@60Hz */ 191 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 192 968, 1056, 0, 600, 601, 605, 628, 0, 193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 194 /* 0x0a - 800x600@72Hz */ 195 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 196 976, 1040, 0, 600, 637, 643, 666, 0, 197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 198 /* 0x0b - 800x600@75Hz */ 199 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 200 896, 1056, 0, 600, 601, 604, 625, 0, 201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 202 /* 0x0c - 800x600@85Hz */ 203 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 204 896, 1048, 0, 600, 601, 604, 631, 0, 205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 206 /* 0x0d - 800x600@120Hz RB */ 207 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 208 880, 960, 0, 600, 603, 607, 636, 0, 209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 210 /* 0x0e - 848x480@60Hz */ 211 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 212 976, 1088, 0, 480, 486, 494, 517, 0, 213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 214 /* 0x0f - 1024x768@43Hz, interlace */ 215 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 216 1208, 1264, 0, 768, 768, 776, 817, 0, 217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 218 DRM_MODE_FLAG_INTERLACE) }, 219 /* 0x10 - 1024x768@60Hz */ 220 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 221 1184, 1344, 0, 768, 771, 777, 806, 0, 222 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 223 /* 0x11 - 1024x768@70Hz */ 224 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 225 1184, 1328, 0, 768, 771, 777, 806, 0, 226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 227 /* 0x12 - 1024x768@75Hz */ 228 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 229 1136, 1312, 0, 768, 769, 772, 800, 0, 230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 231 /* 0x13 - 1024x768@85Hz */ 232 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 233 1168, 1376, 0, 768, 769, 772, 808, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 235 /* 0x14 - 1024x768@120Hz RB */ 236 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 237 1104, 1184, 0, 768, 771, 775, 813, 0, 238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 239 /* 0x15 - 1152x864@75Hz */ 240 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 241 1344, 1600, 0, 864, 865, 868, 900, 0, 242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 243 /* 0x55 - 1280x720@60Hz */ 244 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 245 1430, 1650, 0, 720, 725, 730, 750, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 247 /* 0x16 - 1280x768@60Hz RB */ 248 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 249 1360, 1440, 0, 768, 771, 778, 790, 0, 250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 251 /* 0x17 - 1280x768@60Hz */ 252 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 253 1472, 1664, 0, 768, 771, 778, 798, 0, 254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 255 /* 0x18 - 1280x768@75Hz */ 256 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 257 1488, 1696, 0, 768, 771, 778, 805, 0, 258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 259 /* 0x19 - 1280x768@85Hz */ 260 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 261 1496, 1712, 0, 768, 771, 778, 809, 0, 262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 263 /* 0x1a - 1280x768@120Hz RB */ 264 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 265 1360, 1440, 0, 768, 771, 778, 813, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 267 /* 0x1b - 1280x800@60Hz RB */ 268 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 269 1360, 1440, 0, 800, 803, 809, 823, 0, 270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 271 /* 0x1c - 1280x800@60Hz */ 272 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 273 1480, 1680, 0, 800, 803, 809, 831, 0, 274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 275 /* 0x1d - 1280x800@75Hz */ 276 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 277 1488, 1696, 0, 800, 803, 809, 838, 0, 278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 279 /* 0x1e - 1280x800@85Hz */ 280 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 281 1496, 1712, 0, 800, 803, 809, 843, 0, 282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 283 /* 0x1f - 1280x800@120Hz RB */ 284 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 285 1360, 1440, 0, 800, 803, 809, 847, 0, 286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 287 /* 0x20 - 1280x960@60Hz */ 288 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 289 1488, 1800, 0, 960, 961, 964, 1000, 0, 290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 291 /* 0x21 - 1280x960@85Hz */ 292 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 293 1504, 1728, 0, 960, 961, 964, 1011, 0, 294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 295 /* 0x22 - 1280x960@120Hz RB */ 296 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 297 1360, 1440, 0, 960, 963, 967, 1017, 0, 298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 299 /* 0x23 - 1280x1024@60Hz */ 300 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 301 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 303 /* 0x24 - 1280x1024@75Hz */ 304 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 305 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 307 /* 0x25 - 1280x1024@85Hz */ 308 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 309 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 311 /* 0x26 - 1280x1024@120Hz RB */ 312 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 313 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 315 /* 0x27 - 1360x768@60Hz */ 316 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 317 1536, 1792, 0, 768, 771, 777, 795, 0, 318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 319 /* 0x28 - 1360x768@120Hz RB */ 320 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 321 1440, 1520, 0, 768, 771, 776, 813, 0, 322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 323 /* 0x51 - 1366x768@60Hz */ 324 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 325 1579, 1792, 0, 768, 771, 774, 798, 0, 326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 327 /* 0x56 - 1366x768@60Hz */ 328 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 329 1436, 1500, 0, 768, 769, 772, 800, 0, 330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 331 /* 0x29 - 1400x1050@60Hz RB */ 332 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 333 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 335 /* 0x2a - 1400x1050@60Hz */ 336 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 337 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 339 /* 0x2b - 1400x1050@75Hz */ 340 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 341 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 343 /* 0x2c - 1400x1050@85Hz */ 344 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 345 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 347 /* 0x2d - 1400x1050@120Hz RB */ 348 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 349 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 351 /* 0x2e - 1440x900@60Hz RB */ 352 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 353 1520, 1600, 0, 900, 903, 909, 926, 0, 354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 355 /* 0x2f - 1440x900@60Hz */ 356 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 357 1672, 1904, 0, 900, 903, 909, 934, 0, 358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 359 /* 0x30 - 1440x900@75Hz */ 360 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 361 1688, 1936, 0, 900, 903, 909, 942, 0, 362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 363 /* 0x31 - 1440x900@85Hz */ 364 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 365 1696, 1952, 0, 900, 903, 909, 948, 0, 366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 367 /* 0x32 - 1440x900@120Hz RB */ 368 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 369 1520, 1600, 0, 900, 903, 909, 953, 0, 370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 371 /* 0x53 - 1600x900@60Hz */ 372 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 373 1704, 1800, 0, 900, 901, 904, 1000, 0, 374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 375 /* 0x33 - 1600x1200@60Hz */ 376 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 377 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 379 /* 0x34 - 1600x1200@65Hz */ 380 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 381 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 383 /* 0x35 - 1600x1200@70Hz */ 384 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 385 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 387 /* 0x36 - 1600x1200@75Hz */ 388 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 389 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 391 /* 0x37 - 1600x1200@85Hz */ 392 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 393 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 395 /* 0x38 - 1600x1200@120Hz RB */ 396 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 397 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 399 /* 0x39 - 1680x1050@60Hz RB */ 400 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 401 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 403 /* 0x3a - 1680x1050@60Hz */ 404 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 405 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 407 /* 0x3b - 1680x1050@75Hz */ 408 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 409 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 411 /* 0x3c - 1680x1050@85Hz */ 412 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 413 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 415 /* 0x3d - 1680x1050@120Hz RB */ 416 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 417 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 419 /* 0x3e - 1792x1344@60Hz */ 420 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 421 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 422 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 423 /* 0x3f - 1792x1344@75Hz */ 424 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 425 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 427 /* 0x40 - 1792x1344@120Hz RB */ 428 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 429 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 431 /* 0x41 - 1856x1392@60Hz */ 432 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 433 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 435 /* 0x42 - 1856x1392@75Hz */ 436 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 437 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 439 /* 0x43 - 1856x1392@120Hz RB */ 440 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 441 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 443 /* 0x52 - 1920x1080@60Hz */ 444 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 445 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 447 /* 0x44 - 1920x1200@60Hz RB */ 448 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 449 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 451 /* 0x45 - 1920x1200@60Hz */ 452 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 453 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 454 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 455 /* 0x46 - 1920x1200@75Hz */ 456 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 457 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 459 /* 0x47 - 1920x1200@85Hz */ 460 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 461 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 463 /* 0x48 - 1920x1200@120Hz RB */ 464 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 465 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 467 /* 0x49 - 1920x1440@60Hz */ 468 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 469 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 471 /* 0x4a - 1920x1440@75Hz */ 472 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 473 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 475 /* 0x4b - 1920x1440@120Hz RB */ 476 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 477 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 479 /* 0x54 - 2048x1152@60Hz */ 480 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 481 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 483 /* 0x4c - 2560x1600@60Hz RB */ 484 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 485 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 487 /* 0x4d - 2560x1600@60Hz */ 488 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 489 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 490 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 491 /* 0x4e - 2560x1600@75Hz */ 492 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 493 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 495 /* 0x4f - 2560x1600@85Hz */ 496 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 497 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 499 /* 0x50 - 2560x1600@120Hz RB */ 500 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 501 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 503 /* 0x57 - 4096x2160@60Hz RB */ 504 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 505 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 507 /* 0x58 - 4096x2160@59.94Hz RB */ 508 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 509 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 511 }; 512 513 /* 514 * These more or less come from the DMT spec. The 720x400 modes are 515 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 516 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 517 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 518 * mode. 519 * 520 * The DMT modes have been fact-checked; the rest are mild guesses. 521 */ 522 static const struct drm_display_mode edid_est_modes[] = { 523 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 524 968, 1056, 0, 600, 601, 605, 628, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 526 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 527 896, 1024, 0, 600, 601, 603, 625, 0, 528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 529 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 530 720, 840, 0, 480, 481, 484, 500, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 533 704, 832, 0, 480, 489, 492, 520, 0, 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 535 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 536 768, 864, 0, 480, 483, 486, 525, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 538 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 539 752, 800, 0, 480, 490, 492, 525, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 541 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 542 846, 900, 0, 400, 421, 423, 449, 0, 543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 544 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 545 846, 900, 0, 400, 412, 414, 449, 0, 546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 547 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 548 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 550 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 551 1136, 1312, 0, 768, 769, 772, 800, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 553 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 554 1184, 1328, 0, 768, 771, 777, 806, 0, 555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 556 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 557 1184, 1344, 0, 768, 771, 777, 806, 0, 558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 559 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 560 1208, 1264, 0, 768, 768, 776, 817, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 562 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 563 928, 1152, 0, 624, 625, 628, 667, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 565 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 566 896, 1056, 0, 600, 601, 604, 625, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 568 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 569 976, 1040, 0, 600, 637, 643, 666, 0, 570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 571 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 572 1344, 1600, 0, 864, 865, 868, 900, 0, 573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 574 }; 575 576 struct minimode { 577 short w; 578 short h; 579 short r; 580 short rb; 581 }; 582 583 static const struct minimode est3_modes[] = { 584 /* byte 6 */ 585 { 640, 350, 85, 0 }, 586 { 640, 400, 85, 0 }, 587 { 720, 400, 85, 0 }, 588 { 640, 480, 85, 0 }, 589 { 848, 480, 60, 0 }, 590 { 800, 600, 85, 0 }, 591 { 1024, 768, 85, 0 }, 592 { 1152, 864, 75, 0 }, 593 /* byte 7 */ 594 { 1280, 768, 60, 1 }, 595 { 1280, 768, 60, 0 }, 596 { 1280, 768, 75, 0 }, 597 { 1280, 768, 85, 0 }, 598 { 1280, 960, 60, 0 }, 599 { 1280, 960, 85, 0 }, 600 { 1280, 1024, 60, 0 }, 601 { 1280, 1024, 85, 0 }, 602 /* byte 8 */ 603 { 1360, 768, 60, 0 }, 604 { 1440, 900, 60, 1 }, 605 { 1440, 900, 60, 0 }, 606 { 1440, 900, 75, 0 }, 607 { 1440, 900, 85, 0 }, 608 { 1400, 1050, 60, 1 }, 609 { 1400, 1050, 60, 0 }, 610 { 1400, 1050, 75, 0 }, 611 /* byte 9 */ 612 { 1400, 1050, 85, 0 }, 613 { 1680, 1050, 60, 1 }, 614 { 1680, 1050, 60, 0 }, 615 { 1680, 1050, 75, 0 }, 616 { 1680, 1050, 85, 0 }, 617 { 1600, 1200, 60, 0 }, 618 { 1600, 1200, 65, 0 }, 619 { 1600, 1200, 70, 0 }, 620 /* byte 10 */ 621 { 1600, 1200, 75, 0 }, 622 { 1600, 1200, 85, 0 }, 623 { 1792, 1344, 60, 0 }, 624 { 1792, 1344, 75, 0 }, 625 { 1856, 1392, 60, 0 }, 626 { 1856, 1392, 75, 0 }, 627 { 1920, 1200, 60, 1 }, 628 { 1920, 1200, 60, 0 }, 629 /* byte 11 */ 630 { 1920, 1200, 75, 0 }, 631 { 1920, 1200, 85, 0 }, 632 { 1920, 1440, 60, 0 }, 633 { 1920, 1440, 75, 0 }, 634 }; 635 636 static const struct minimode extra_modes[] = { 637 { 1024, 576, 60, 0 }, 638 { 1366, 768, 60, 0 }, 639 { 1600, 900, 60, 0 }, 640 { 1680, 945, 60, 0 }, 641 { 1920, 1080, 60, 0 }, 642 { 2048, 1152, 60, 0 }, 643 { 2048, 1536, 60, 0 }, 644 }; 645 646 /* 647 * Probably taken from CEA-861 spec. 648 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 649 * 650 * Index using the VIC. 651 */ 652 static const struct drm_display_mode edid_cea_modes[] = { 653 /* 0 - dummy, VICs start at 1 */ 654 { }, 655 /* 1 - 640x480@60Hz */ 656 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 657 752, 800, 0, 480, 490, 492, 525, 0, 658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 660 /* 2 - 720x480@60Hz */ 661 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 662 798, 858, 0, 480, 489, 495, 525, 0, 663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 664 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 665 /* 3 - 720x480@60Hz */ 666 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 667 798, 858, 0, 480, 489, 495, 525, 0, 668 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 669 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 670 /* 4 - 1280x720@60Hz */ 671 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 672 1430, 1650, 0, 720, 725, 730, 750, 0, 673 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 674 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 675 /* 5 - 1920x1080i@60Hz */ 676 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 677 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 678 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 679 DRM_MODE_FLAG_INTERLACE), 680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 681 /* 6 - 720(1440)x480i@60Hz */ 682 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 683 801, 858, 0, 480, 488, 494, 525, 0, 684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 685 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 687 /* 7 - 720(1440)x480i@60Hz */ 688 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 689 801, 858, 0, 480, 488, 494, 525, 0, 690 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 691 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 692 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 693 /* 8 - 720(1440)x240@60Hz */ 694 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 695 801, 858, 0, 240, 244, 247, 262, 0, 696 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 697 DRM_MODE_FLAG_DBLCLK), 698 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 699 /* 9 - 720(1440)x240@60Hz */ 700 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 701 801, 858, 0, 240, 244, 247, 262, 0, 702 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 703 DRM_MODE_FLAG_DBLCLK), 704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 705 /* 10 - 2880x480i@60Hz */ 706 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 707 3204, 3432, 0, 480, 488, 494, 525, 0, 708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 709 DRM_MODE_FLAG_INTERLACE), 710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 711 /* 11 - 2880x480i@60Hz */ 712 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 713 3204, 3432, 0, 480, 488, 494, 525, 0, 714 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 715 DRM_MODE_FLAG_INTERLACE), 716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 717 /* 12 - 2880x240@60Hz */ 718 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 719 3204, 3432, 0, 240, 244, 247, 262, 0, 720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 722 /* 13 - 2880x240@60Hz */ 723 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 724 3204, 3432, 0, 240, 244, 247, 262, 0, 725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 726 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 727 /* 14 - 1440x480@60Hz */ 728 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 729 1596, 1716, 0, 480, 489, 495, 525, 0, 730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 732 /* 15 - 1440x480@60Hz */ 733 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 734 1596, 1716, 0, 480, 489, 495, 525, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 736 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 737 /* 16 - 1920x1080@60Hz */ 738 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 739 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 740 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 741 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 742 /* 17 - 720x576@50Hz */ 743 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 744 796, 864, 0, 576, 581, 586, 625, 0, 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 746 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 747 /* 18 - 720x576@50Hz */ 748 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 749 796, 864, 0, 576, 581, 586, 625, 0, 750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 751 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 752 /* 19 - 1280x720@50Hz */ 753 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 754 1760, 1980, 0, 720, 725, 730, 750, 0, 755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 756 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 20 - 1920x1080i@50Hz */ 758 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 759 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 761 DRM_MODE_FLAG_INTERLACE), 762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 763 /* 21 - 720(1440)x576i@50Hz */ 764 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 765 795, 864, 0, 576, 580, 586, 625, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 769 /* 22 - 720(1440)x576i@50Hz */ 770 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 771 795, 864, 0, 576, 580, 586, 625, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 774 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 775 /* 23 - 720(1440)x288@50Hz */ 776 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 777 795, 864, 0, 288, 290, 293, 312, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_DBLCLK), 780 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 781 /* 24 - 720(1440)x288@50Hz */ 782 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 783 795, 864, 0, 288, 290, 293, 312, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 785 DRM_MODE_FLAG_DBLCLK), 786 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 787 /* 25 - 2880x576i@50Hz */ 788 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 789 3180, 3456, 0, 576, 580, 586, 625, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 791 DRM_MODE_FLAG_INTERLACE), 792 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 793 /* 26 - 2880x576i@50Hz */ 794 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 795 3180, 3456, 0, 576, 580, 586, 625, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 797 DRM_MODE_FLAG_INTERLACE), 798 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 799 /* 27 - 2880x288@50Hz */ 800 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 801 3180, 3456, 0, 288, 290, 293, 312, 0, 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 804 /* 28 - 2880x288@50Hz */ 805 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 806 3180, 3456, 0, 288, 290, 293, 312, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 809 /* 29 - 1440x576@50Hz */ 810 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 811 1592, 1728, 0, 576, 581, 586, 625, 0, 812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 814 /* 30 - 1440x576@50Hz */ 815 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 816 1592, 1728, 0, 576, 581, 586, 625, 0, 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 818 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 819 /* 31 - 1920x1080@50Hz */ 820 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 821 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 823 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 824 /* 32 - 1920x1080@24Hz */ 825 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 826 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 33 - 1920x1080@25Hz */ 830 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 831 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 833 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 34 - 1920x1080@30Hz */ 835 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 836 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 838 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 35 - 2880x480@60Hz */ 840 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 841 3192, 3432, 0, 480, 489, 495, 525, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 843 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 844 /* 36 - 2880x480@60Hz */ 845 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 846 3192, 3432, 0, 480, 489, 495, 525, 0, 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 848 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 37 - 2880x576@50Hz */ 850 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 851 3184, 3456, 0, 576, 581, 586, 625, 0, 852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 854 /* 38 - 2880x576@50Hz */ 855 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 856 3184, 3456, 0, 576, 581, 586, 625, 0, 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 39 - 1920x1080i@50Hz */ 860 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 861 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 863 DRM_MODE_FLAG_INTERLACE), 864 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 865 /* 40 - 1920x1080i@100Hz */ 866 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 867 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 869 DRM_MODE_FLAG_INTERLACE), 870 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 871 /* 41 - 1280x720@100Hz */ 872 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 873 1760, 1980, 0, 720, 725, 730, 750, 0, 874 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 875 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 876 /* 42 - 720x576@100Hz */ 877 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 878 796, 864, 0, 576, 581, 586, 625, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 880 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 881 /* 43 - 720x576@100Hz */ 882 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 883 796, 864, 0, 576, 581, 586, 625, 0, 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 885 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 886 /* 44 - 720(1440)x576i@100Hz */ 887 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 888 795, 864, 0, 576, 580, 586, 625, 0, 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 890 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 891 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 892 /* 45 - 720(1440)x576i@100Hz */ 893 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 894 795, 864, 0, 576, 580, 586, 625, 0, 895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 896 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 897 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 46 - 1920x1080i@120Hz */ 899 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 900 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 902 DRM_MODE_FLAG_INTERLACE), 903 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 47 - 1280x720@120Hz */ 905 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 906 1430, 1650, 0, 720, 725, 730, 750, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 48 - 720x480@120Hz */ 910 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 911 798, 858, 0, 480, 489, 495, 525, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 913 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 914 /* 49 - 720x480@120Hz */ 915 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 916 798, 858, 0, 480, 489, 495, 525, 0, 917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 918 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 50 - 720(1440)x480i@120Hz */ 920 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 921 801, 858, 0, 480, 488, 494, 525, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 923 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 924 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 925 /* 51 - 720(1440)x480i@120Hz */ 926 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 927 801, 858, 0, 480, 488, 494, 525, 0, 928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 929 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 930 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 52 - 720x576@200Hz */ 932 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 933 796, 864, 0, 576, 581, 586, 625, 0, 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 935 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 936 /* 53 - 720x576@200Hz */ 937 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 938 796, 864, 0, 576, 581, 586, 625, 0, 939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 940 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 941 /* 54 - 720(1440)x576i@200Hz */ 942 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 943 795, 864, 0, 576, 580, 586, 625, 0, 944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 945 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 946 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 947 /* 55 - 720(1440)x576i@200Hz */ 948 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 949 795, 864, 0, 576, 580, 586, 625, 0, 950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 951 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 952 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 953 /* 56 - 720x480@240Hz */ 954 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 955 798, 858, 0, 480, 489, 495, 525, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 957 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 958 /* 57 - 720x480@240Hz */ 959 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 960 798, 858, 0, 480, 489, 495, 525, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 962 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 963 /* 58 - 720(1440)x480i@240 */ 964 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 965 801, 858, 0, 480, 488, 494, 525, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 968 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 969 /* 59 - 720(1440)x480i@240 */ 970 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 971 801, 858, 0, 480, 488, 494, 525, 0, 972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 974 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 975 /* 60 - 1280x720@24Hz */ 976 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 977 3080, 3300, 0, 720, 725, 730, 750, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 979 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 980 /* 61 - 1280x720@25Hz */ 981 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 982 3740, 3960, 0, 720, 725, 730, 750, 0, 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 984 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 62 - 1280x720@30Hz */ 986 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 987 3080, 3300, 0, 720, 725, 730, 750, 0, 988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 989 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 990 /* 63 - 1920x1080@120Hz */ 991 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 992 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 994 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 64 - 1920x1080@100Hz */ 996 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 997 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 999 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1000 }; 1001 1002 /* 1003 * HDMI 1.4 4k modes. Index using the VIC. 1004 */ 1005 static const struct drm_display_mode edid_4k_modes[] = { 1006 /* 0 - dummy, VICs start at 1 */ 1007 { }, 1008 /* 1 - 3840x2160@30Hz */ 1009 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1010 3840, 4016, 4104, 4400, 0, 1011 2160, 2168, 2178, 2250, 0, 1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1013 .vrefresh = 30, }, 1014 /* 2 - 3840x2160@25Hz */ 1015 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1016 3840, 4896, 4984, 5280, 0, 1017 2160, 2168, 2178, 2250, 0, 1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1019 .vrefresh = 25, }, 1020 /* 3 - 3840x2160@24Hz */ 1021 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1022 3840, 5116, 5204, 5500, 0, 1023 2160, 2168, 2178, 2250, 0, 1024 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1025 .vrefresh = 24, }, 1026 /* 4 - 4096x2160@24Hz (SMPTE) */ 1027 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1028 4096, 5116, 5204, 5500, 0, 1029 2160, 2168, 2178, 2250, 0, 1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1031 .vrefresh = 24, }, 1032 }; 1033 1034 /*** DDC fetch and block validation ***/ 1035 1036 static const u8 edid_header[] = { 1037 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1038 }; 1039 1040 /** 1041 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1042 * @raw_edid: pointer to raw base EDID block 1043 * 1044 * Sanity check the header of the base EDID block. 1045 * 1046 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1047 */ 1048 int drm_edid_header_is_valid(const u8 *raw_edid) 1049 { 1050 int i, score = 0; 1051 1052 for (i = 0; i < sizeof(edid_header); i++) 1053 if (raw_edid[i] == edid_header[i]) 1054 score++; 1055 1056 return score; 1057 } 1058 EXPORT_SYMBOL(drm_edid_header_is_valid); 1059 1060 static int edid_fixup __read_mostly = 6; 1061 module_param_named(edid_fixup, edid_fixup, int, 0400); 1062 MODULE_PARM_DESC(edid_fixup, 1063 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1064 1065 static void drm_get_displayid(struct drm_connector *connector, 1066 struct edid *edid); 1067 1068 static int drm_edid_block_checksum(const u8 *raw_edid) 1069 { 1070 int i; 1071 u8 csum = 0; 1072 for (i = 0; i < EDID_LENGTH; i++) 1073 csum += raw_edid[i]; 1074 1075 return csum; 1076 } 1077 1078 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1079 { 1080 if (memchr_inv(in_edid, 0, length)) 1081 return false; 1082 1083 return true; 1084 } 1085 1086 /** 1087 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1088 * @raw_edid: pointer to raw EDID block 1089 * @block: type of block to validate (0 for base, extension otherwise) 1090 * @print_bad_edid: if true, dump bad EDID blocks to the console 1091 * @edid_corrupt: if true, the header or checksum is invalid 1092 * 1093 * Validate a base or extension EDID block and optionally dump bad blocks to 1094 * the console. 1095 * 1096 * Return: True if the block is valid, false otherwise. 1097 */ 1098 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1099 bool *edid_corrupt) 1100 { 1101 u8 csum; 1102 struct edid *edid = (struct edid *)raw_edid; 1103 1104 if (WARN_ON(!raw_edid)) 1105 return false; 1106 1107 if (edid_fixup > 8 || edid_fixup < 0) 1108 edid_fixup = 6; 1109 1110 if (block == 0) { 1111 int score = drm_edid_header_is_valid(raw_edid); 1112 if (score == 8) { 1113 if (edid_corrupt) 1114 *edid_corrupt = false; 1115 } else if (score >= edid_fixup) { 1116 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1117 * The corrupt flag needs to be set here otherwise, the 1118 * fix-up code here will correct the problem, the 1119 * checksum is correct and the test fails 1120 */ 1121 if (edid_corrupt) 1122 *edid_corrupt = true; 1123 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1124 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1125 } else { 1126 if (edid_corrupt) 1127 *edid_corrupt = true; 1128 goto bad; 1129 } 1130 } 1131 1132 csum = drm_edid_block_checksum(raw_edid); 1133 if (csum) { 1134 if (print_bad_edid) { 1135 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1136 } 1137 1138 if (edid_corrupt) 1139 *edid_corrupt = true; 1140 1141 /* allow CEA to slide through, switches mangle this */ 1142 if (raw_edid[0] != 0x02) 1143 goto bad; 1144 } 1145 1146 /* per-block-type checks */ 1147 switch (raw_edid[0]) { 1148 case 0: /* base */ 1149 if (edid->version != 1) { 1150 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1151 goto bad; 1152 } 1153 1154 if (edid->revision > 4) 1155 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1156 break; 1157 1158 default: 1159 break; 1160 } 1161 1162 return true; 1163 1164 bad: 1165 if (print_bad_edid) { 1166 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1167 printk(KERN_ERR "EDID block is all zeroes\n"); 1168 } else { 1169 printk(KERN_ERR "Raw EDID:\n"); 1170 for (int i = 0; i < EDID_LENGTH; ) { 1171 kprintf("%02x", raw_edid[i]); 1172 i++; 1173 if (i % 16 == 0 || i == EDID_LENGTH) 1174 kprintf("\n"); 1175 else if (i % 8 == 0) 1176 kprintf(" "); 1177 else 1178 kprintf(" "); 1179 } 1180 } 1181 } 1182 return false; 1183 } 1184 EXPORT_SYMBOL(drm_edid_block_valid); 1185 1186 /** 1187 * drm_edid_is_valid - sanity check EDID data 1188 * @edid: EDID data 1189 * 1190 * Sanity-check an entire EDID record (including extensions) 1191 * 1192 * Return: True if the EDID data is valid, false otherwise. 1193 */ 1194 bool drm_edid_is_valid(struct edid *edid) 1195 { 1196 int i; 1197 u8 *raw = (u8 *)edid; 1198 1199 if (!edid) 1200 return false; 1201 1202 for (i = 0; i <= edid->extensions; i++) 1203 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1204 return false; 1205 1206 return true; 1207 } 1208 EXPORT_SYMBOL(drm_edid_is_valid); 1209 1210 #define DDC_SEGMENT_ADDR 0x30 1211 /** 1212 * drm_do_probe_ddc_edid() - get EDID information via I2C 1213 * @data: I2C device adapter 1214 * @buf: EDID data buffer to be filled 1215 * @block: 128 byte EDID block to start fetching from 1216 * @len: EDID data buffer length to fetch 1217 * 1218 * Try to fetch EDID information by calling I2C driver functions. 1219 * 1220 * Return: 0 on success or -1 on failure. 1221 */ 1222 static int 1223 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1224 { 1225 struct i2c_adapter *adapter = data; 1226 unsigned char start = block * EDID_LENGTH; 1227 unsigned char segment = block >> 1; 1228 unsigned char xfers = segment ? 3 : 2; 1229 int ret, retries = 5; 1230 1231 /* 1232 * The core I2C driver will automatically retry the transfer if the 1233 * adapter reports EAGAIN. However, we find that bit-banging transfers 1234 * are susceptible to errors under a heavily loaded machine and 1235 * generate spurious NAKs and timeouts. Retrying the transfer 1236 * of the individual block a few times seems to overcome this. 1237 */ 1238 do { 1239 struct i2c_msg msgs[] = { 1240 { 1241 .addr = DDC_SEGMENT_ADDR, 1242 .flags = 0, 1243 .len = 1, 1244 .buf = &segment, 1245 }, { 1246 .addr = DDC_ADDR, 1247 .flags = 0, 1248 .len = 1, 1249 .buf = &start, 1250 }, { 1251 .addr = DDC_ADDR, 1252 .flags = I2C_M_RD, 1253 .len = len, 1254 .buf = buf, 1255 } 1256 }; 1257 1258 /* 1259 * Avoid sending the segment addr to not upset non-compliant 1260 * DDC monitors. 1261 */ 1262 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1263 1264 if (ret == -ENXIO) { 1265 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1266 adapter->name); 1267 break; 1268 } 1269 } while (ret != xfers && --retries); 1270 1271 return ret == xfers ? 0 : -1; 1272 } 1273 1274 /* 1275 * Old version of drm_do_probe_ddc_edid, still using 1276 * the FreeBSD/DragonFly iic API 1277 */ 1278 static int 1279 drm_do_probe_ddc_edid_iic(void *data, u8 *buf, unsigned int block, size_t len) 1280 { 1281 device_t adapter = data; 1282 unsigned char start = block * EDID_LENGTH; 1283 unsigned char segment = block >> 1; 1284 unsigned char xfers = segment ? 3 : 2; 1285 int ret, retries = 5; 1286 1287 /* 1288 * The core I2C driver will automatically retry the transfer if the 1289 * adapter reports EAGAIN. However, we find that bit-banging transfers 1290 * are susceptible to errors under a heavily loaded machine and 1291 * generate spurious NAKs and timeouts. Retrying the transfer 1292 * of the individual block a few times seems to overcome this. 1293 */ 1294 do { 1295 struct iic_msg msgs[] = { 1296 { 1297 .slave = DDC_SEGMENT_ADDR << 1, 1298 .flags = 0, 1299 .len = 1, 1300 .buf = &segment, 1301 }, { 1302 .slave = DDC_ADDR << 1, 1303 .flags = 0, 1304 .len = 1, 1305 .buf = &start, 1306 }, { 1307 .slave = DDC_ADDR << 1, 1308 .flags = I2C_M_RD, 1309 .len = len, 1310 .buf = buf, 1311 } 1312 }; 1313 1314 /* 1315 * Avoid sending the segment addr to not upset non-compliant 1316 * DDC monitors. 1317 */ 1318 ret = iicbus_transfer(adapter, &msgs[3 - xfers], xfers); 1319 if (ret != 0) 1320 DRM_DEBUG_KMS("iicbus_transfer countdown %d error %d\n", 1321 retries, ret); 1322 } while (ret != 0 && --retries); 1323 1324 return (ret == 0 ? 0 : -1); 1325 } 1326 1327 /* 1328 * Old version of drm_probe_ddc(), still using 1329 * the FreeBSD/DragonFly iic API 1330 */ 1331 static bool 1332 drm_probe_ddc_iic(device_t adapter) 1333 { 1334 unsigned char out; 1335 1336 return (drm_do_probe_ddc_edid_iic(adapter, &out, 0, 1) == 0); 1337 } 1338 1339 /* 1340 * Old version of drm_get_edid(), still using 1341 * the FreeBSD/DragonFly iic API 1342 */ 1343 struct edid *drm_get_edid_iic(struct drm_connector *connector, 1344 device_t adapter) 1345 { 1346 if (!drm_probe_ddc_iic(adapter)) 1347 return NULL; 1348 1349 return drm_do_get_edid(connector, drm_do_probe_ddc_edid_iic, adapter); 1350 } 1351 1352 /** 1353 * drm_do_get_edid - get EDID data using a custom EDID block read function 1354 * @connector: connector we're probing 1355 * @get_edid_block: EDID block read function 1356 * @data: private data passed to the block read function 1357 * 1358 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1359 * exposes a different interface to read EDID blocks this function can be used 1360 * to get EDID data using a custom block read function. 1361 * 1362 * As in the general case the DDC bus is accessible by the kernel at the I2C 1363 * level, drivers must make all reasonable efforts to expose it as an I2C 1364 * adapter and use drm_get_edid() instead of abusing this function. 1365 * 1366 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1367 */ 1368 struct edid *drm_do_get_edid(struct drm_connector *connector, 1369 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1370 size_t len), 1371 void *data) 1372 { 1373 int i, j = 0, valid_extensions = 0; 1374 u8 *block, *new; 1375 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1376 1377 if ((block = kmalloc(EDID_LENGTH, M_DRM, M_WAITOK)) == NULL) 1378 return NULL; 1379 1380 /* base block fetch */ 1381 for (i = 0; i < 4; i++) { 1382 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1383 goto out; 1384 if (drm_edid_block_valid(block, 0, print_bad_edid, 1385 &connector->edid_corrupt)) 1386 break; 1387 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1388 connector->null_edid_counter++; 1389 goto carp; 1390 } 1391 } 1392 if (i == 4) 1393 goto carp; 1394 1395 /* if there's no extensions, we're done */ 1396 if (block[0x7e] == 0) 1397 return (struct edid *)block; 1398 1399 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1400 if (!new) 1401 goto out; 1402 block = new; 1403 1404 for (j = 1; j <= block[0x7e]; j++) { 1405 for (i = 0; i < 4; i++) { 1406 if (get_edid_block(data, 1407 block + (valid_extensions + 1) * EDID_LENGTH, 1408 j, EDID_LENGTH)) 1409 goto out; 1410 if (drm_edid_block_valid(block + (valid_extensions + 1) 1411 * EDID_LENGTH, j, 1412 print_bad_edid, 1413 NULL)) { 1414 valid_extensions++; 1415 break; 1416 } 1417 } 1418 1419 if (i == 4 && print_bad_edid) { 1420 dev_warn(connector->dev->dev, 1421 "%s: Ignoring invalid EDID block %d.\n", 1422 connector->name, j); 1423 1424 connector->bad_edid_counter++; 1425 } 1426 } 1427 1428 if (valid_extensions != block[0x7e]) { 1429 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1430 block[0x7e] = valid_extensions; 1431 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1432 if (!new) 1433 goto out; 1434 block = new; 1435 } 1436 1437 return (struct edid *)block; 1438 1439 carp: 1440 if (print_bad_edid) { 1441 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1442 connector->name, j); 1443 } 1444 connector->bad_edid_counter++; 1445 1446 out: 1447 kfree(block); 1448 return NULL; 1449 } 1450 1451 /** 1452 * drm_probe_ddc() - probe DDC presence 1453 * @adapter: I2C adapter to probe 1454 * 1455 * Return: True on success, false on failure. 1456 */ 1457 bool 1458 drm_probe_ddc(struct i2c_adapter *adapter) 1459 { 1460 unsigned char out; 1461 1462 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1463 } 1464 EXPORT_SYMBOL(drm_probe_ddc); 1465 1466 /** 1467 * drm_get_edid - get EDID data, if available 1468 * @connector: connector we're probing 1469 * @adapter: I2C adapter to use for DDC 1470 * 1471 * Poke the given I2C channel to grab EDID data if possible. If found, 1472 * attach it to the connector. 1473 * 1474 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1475 */ 1476 struct edid *drm_get_edid(struct drm_connector *connector, 1477 struct i2c_adapter *adapter) 1478 { 1479 struct edid *edid; 1480 1481 if (!drm_probe_ddc(adapter)) 1482 return NULL; 1483 1484 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1485 if (edid) 1486 drm_get_displayid(connector, edid); 1487 return edid; 1488 } 1489 EXPORT_SYMBOL(drm_get_edid); 1490 1491 /** 1492 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1493 * @connector: connector we're probing 1494 * @adapter: I2C adapter to use for DDC 1495 * 1496 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1497 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1498 * switch DDC to the GPU which is retrieving EDID. 1499 * 1500 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1501 */ 1502 #if 0 1503 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1504 struct i2c_adapter *adapter) 1505 { 1506 struct pci_dev *pdev = connector->dev->pdev; 1507 struct edid *edid; 1508 1509 vga_switcheroo_lock_ddc(pdev); 1510 edid = drm_get_edid(connector, adapter); 1511 vga_switcheroo_unlock_ddc(pdev); 1512 1513 return edid; 1514 } 1515 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1516 #endif 1517 1518 /** 1519 * drm_edid_duplicate - duplicate an EDID and the extensions 1520 * @edid: EDID to duplicate 1521 * 1522 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1523 */ 1524 struct edid *drm_edid_duplicate(const struct edid *edid) 1525 { 1526 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1527 } 1528 EXPORT_SYMBOL(drm_edid_duplicate); 1529 1530 /*** EDID parsing ***/ 1531 1532 /** 1533 * edid_vendor - match a string against EDID's obfuscated vendor field 1534 * @edid: EDID to match 1535 * @vendor: vendor string 1536 * 1537 * Returns true if @vendor is in @edid, false otherwise 1538 */ 1539 static bool edid_vendor(struct edid *edid, char *vendor) 1540 { 1541 char edid_vendor[3]; 1542 1543 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1544 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1545 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1546 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1547 1548 return !strncmp(edid_vendor, vendor, 3); 1549 } 1550 1551 /** 1552 * edid_get_quirks - return quirk flags for a given EDID 1553 * @edid: EDID to process 1554 * 1555 * This tells subsequent routines what fixes they need to apply. 1556 */ 1557 static u32 edid_get_quirks(struct edid *edid) 1558 { 1559 struct edid_quirk *quirk; 1560 int i; 1561 1562 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1563 quirk = &edid_quirk_list[i]; 1564 1565 if (edid_vendor(edid, quirk->vendor) && 1566 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1567 return quirk->quirks; 1568 } 1569 1570 return 0; 1571 } 1572 1573 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1574 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1575 1576 /** 1577 * edid_fixup_preferred - set preferred modes based on quirk list 1578 * @connector: has mode list to fix up 1579 * @quirks: quirks list 1580 * 1581 * Walk the mode list for @connector, clearing the preferred status 1582 * on existing modes and setting it anew for the right mode ala @quirks. 1583 */ 1584 static void edid_fixup_preferred(struct drm_connector *connector, 1585 u32 quirks) 1586 { 1587 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1588 int target_refresh = 0; 1589 int cur_vrefresh, preferred_vrefresh; 1590 1591 if (list_empty(&connector->probed_modes)) 1592 return; 1593 1594 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1595 target_refresh = 60; 1596 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1597 target_refresh = 75; 1598 1599 preferred_mode = list_first_entry(&connector->probed_modes, 1600 struct drm_display_mode, head); 1601 1602 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1603 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1604 1605 if (cur_mode == preferred_mode) 1606 continue; 1607 1608 /* Largest mode is preferred */ 1609 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1610 preferred_mode = cur_mode; 1611 1612 cur_vrefresh = cur_mode->vrefresh ? 1613 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1614 preferred_vrefresh = preferred_mode->vrefresh ? 1615 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1616 /* At a given size, try to get closest to target refresh */ 1617 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1618 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1619 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1620 preferred_mode = cur_mode; 1621 } 1622 } 1623 1624 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1625 } 1626 1627 static bool 1628 mode_is_rb(const struct drm_display_mode *mode) 1629 { 1630 return (mode->htotal - mode->hdisplay == 160) && 1631 (mode->hsync_end - mode->hdisplay == 80) && 1632 (mode->hsync_end - mode->hsync_start == 32) && 1633 (mode->vsync_start - mode->vdisplay == 3); 1634 } 1635 1636 /* 1637 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1638 * @dev: Device to duplicate against 1639 * @hsize: Mode width 1640 * @vsize: Mode height 1641 * @fresh: Mode refresh rate 1642 * @rb: Mode reduced-blanking-ness 1643 * 1644 * Walk the DMT mode list looking for a match for the given parameters. 1645 * 1646 * Return: A newly allocated copy of the mode, or NULL if not found. 1647 */ 1648 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1649 int hsize, int vsize, int fresh, 1650 bool rb) 1651 { 1652 int i; 1653 1654 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1655 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1656 if (hsize != ptr->hdisplay) 1657 continue; 1658 if (vsize != ptr->vdisplay) 1659 continue; 1660 if (fresh != drm_mode_vrefresh(ptr)) 1661 continue; 1662 if (rb != mode_is_rb(ptr)) 1663 continue; 1664 1665 return drm_mode_duplicate(dev, ptr); 1666 } 1667 1668 return NULL; 1669 } 1670 EXPORT_SYMBOL(drm_mode_find_dmt); 1671 1672 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1673 1674 static void 1675 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1676 { 1677 int i, n = 0; 1678 u8 d = ext[0x02]; 1679 u8 *det_base = ext + d; 1680 1681 n = (127 - d) / 18; 1682 for (i = 0; i < n; i++) 1683 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1684 } 1685 1686 static void 1687 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1688 { 1689 unsigned int i, n = min((int)ext[0x02], 6); 1690 u8 *det_base = ext + 5; 1691 1692 if (ext[0x01] != 1) 1693 return; /* unknown version */ 1694 1695 for (i = 0; i < n; i++) 1696 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1697 } 1698 1699 static void 1700 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1701 { 1702 int i; 1703 struct edid *edid = (struct edid *)raw_edid; 1704 1705 if (edid == NULL) 1706 return; 1707 1708 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1709 cb(&(edid->detailed_timings[i]), closure); 1710 1711 for (i = 1; i <= raw_edid[0x7e]; i++) { 1712 u8 *ext = raw_edid + (i * EDID_LENGTH); 1713 switch (*ext) { 1714 case CEA_EXT: 1715 cea_for_each_detailed_block(ext, cb, closure); 1716 break; 1717 case VTB_EXT: 1718 vtb_for_each_detailed_block(ext, cb, closure); 1719 break; 1720 default: 1721 break; 1722 } 1723 } 1724 } 1725 1726 static void 1727 is_rb(struct detailed_timing *t, void *data) 1728 { 1729 u8 *r = (u8 *)t; 1730 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1731 if (r[15] & 0x10) 1732 *(bool *)data = true; 1733 } 1734 1735 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1736 static bool 1737 drm_monitor_supports_rb(struct edid *edid) 1738 { 1739 if (edid->revision >= 4) { 1740 bool ret = false; 1741 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1742 return ret; 1743 } 1744 1745 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1746 } 1747 1748 static void 1749 find_gtf2(struct detailed_timing *t, void *data) 1750 { 1751 u8 *r = (u8 *)t; 1752 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1753 *(u8 **)data = r; 1754 } 1755 1756 /* Secondary GTF curve kicks in above some break frequency */ 1757 static int 1758 drm_gtf2_hbreak(struct edid *edid) 1759 { 1760 u8 *r = NULL; 1761 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1762 return r ? (r[12] * 2) : 0; 1763 } 1764 1765 static int 1766 drm_gtf2_2c(struct edid *edid) 1767 { 1768 u8 *r = NULL; 1769 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1770 return r ? r[13] : 0; 1771 } 1772 1773 static int 1774 drm_gtf2_m(struct edid *edid) 1775 { 1776 u8 *r = NULL; 1777 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1778 return r ? (r[15] << 8) + r[14] : 0; 1779 } 1780 1781 static int 1782 drm_gtf2_k(struct edid *edid) 1783 { 1784 u8 *r = NULL; 1785 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1786 return r ? r[16] : 0; 1787 } 1788 1789 static int 1790 drm_gtf2_2j(struct edid *edid) 1791 { 1792 u8 *r = NULL; 1793 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1794 return r ? r[17] : 0; 1795 } 1796 1797 /** 1798 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1799 * @edid: EDID block to scan 1800 */ 1801 static int standard_timing_level(struct edid *edid) 1802 { 1803 if (edid->revision >= 2) { 1804 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1805 return LEVEL_CVT; 1806 if (drm_gtf2_hbreak(edid)) 1807 return LEVEL_GTF2; 1808 return LEVEL_GTF; 1809 } 1810 return LEVEL_DMT; 1811 } 1812 1813 /* 1814 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1815 * monitors fill with ascii space (0x20) instead. 1816 */ 1817 static int 1818 bad_std_timing(u8 a, u8 b) 1819 { 1820 return (a == 0x00 && b == 0x00) || 1821 (a == 0x01 && b == 0x01) || 1822 (a == 0x20 && b == 0x20); 1823 } 1824 1825 /** 1826 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1827 * @connector: connector of for the EDID block 1828 * @edid: EDID block to scan 1829 * @t: standard timing params 1830 * 1831 * Take the standard timing params (in this case width, aspect, and refresh) 1832 * and convert them into a real mode using CVT/GTF/DMT. 1833 */ 1834 static struct drm_display_mode * 1835 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1836 struct std_timing *t) 1837 { 1838 struct drm_device *dev = connector->dev; 1839 struct drm_display_mode *m, *mode = NULL; 1840 int hsize, vsize; 1841 int vrefresh_rate; 1842 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1843 >> EDID_TIMING_ASPECT_SHIFT; 1844 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1845 >> EDID_TIMING_VFREQ_SHIFT; 1846 int timing_level = standard_timing_level(edid); 1847 1848 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1849 return NULL; 1850 1851 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1852 hsize = t->hsize * 8 + 248; 1853 /* vrefresh_rate = vfreq + 60 */ 1854 vrefresh_rate = vfreq + 60; 1855 /* the vdisplay is calculated based on the aspect ratio */ 1856 if (aspect_ratio == 0) { 1857 if (edid->revision < 3) 1858 vsize = hsize; 1859 else 1860 vsize = (hsize * 10) / 16; 1861 } else if (aspect_ratio == 1) 1862 vsize = (hsize * 3) / 4; 1863 else if (aspect_ratio == 2) 1864 vsize = (hsize * 4) / 5; 1865 else 1866 vsize = (hsize * 9) / 16; 1867 1868 /* HDTV hack, part 1 */ 1869 if (vrefresh_rate == 60 && 1870 ((hsize == 1360 && vsize == 765) || 1871 (hsize == 1368 && vsize == 769))) { 1872 hsize = 1366; 1873 vsize = 768; 1874 } 1875 1876 /* 1877 * If this connector already has a mode for this size and refresh 1878 * rate (because it came from detailed or CVT info), use that 1879 * instead. This way we don't have to guess at interlace or 1880 * reduced blanking. 1881 */ 1882 list_for_each_entry(m, &connector->probed_modes, head) 1883 if (m->hdisplay == hsize && m->vdisplay == vsize && 1884 drm_mode_vrefresh(m) == vrefresh_rate) 1885 return NULL; 1886 1887 /* HDTV hack, part 2 */ 1888 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1889 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1890 false); 1891 mode->hdisplay = 1366; 1892 mode->hsync_start = mode->hsync_start - 1; 1893 mode->hsync_end = mode->hsync_end - 1; 1894 return mode; 1895 } 1896 1897 /* check whether it can be found in default mode table */ 1898 if (drm_monitor_supports_rb(edid)) { 1899 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1900 true); 1901 if (mode) 1902 return mode; 1903 } 1904 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1905 if (mode) 1906 return mode; 1907 1908 /* okay, generate it */ 1909 switch (timing_level) { 1910 case LEVEL_DMT: 1911 break; 1912 case LEVEL_GTF: 1913 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1914 break; 1915 case LEVEL_GTF2: 1916 /* 1917 * This is potentially wrong if there's ever a monitor with 1918 * more than one ranges section, each claiming a different 1919 * secondary GTF curve. Please don't do that. 1920 */ 1921 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1922 if (!mode) 1923 return NULL; 1924 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1925 drm_mode_destroy(dev, mode); 1926 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1927 vrefresh_rate, 0, 0, 1928 drm_gtf2_m(edid), 1929 drm_gtf2_2c(edid), 1930 drm_gtf2_k(edid), 1931 drm_gtf2_2j(edid)); 1932 } 1933 break; 1934 case LEVEL_CVT: 1935 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1936 false); 1937 break; 1938 } 1939 return mode; 1940 } 1941 1942 /* 1943 * EDID is delightfully ambiguous about how interlaced modes are to be 1944 * encoded. Our internal representation is of frame height, but some 1945 * HDTV detailed timings are encoded as field height. 1946 * 1947 * The format list here is from CEA, in frame size. Technically we 1948 * should be checking refresh rate too. Whatever. 1949 */ 1950 static void 1951 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1952 struct detailed_pixel_timing *pt) 1953 { 1954 int i; 1955 static const struct { 1956 int w, h; 1957 } cea_interlaced[] = { 1958 { 1920, 1080 }, 1959 { 720, 480 }, 1960 { 1440, 480 }, 1961 { 2880, 480 }, 1962 { 720, 576 }, 1963 { 1440, 576 }, 1964 { 2880, 576 }, 1965 }; 1966 1967 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1968 return; 1969 1970 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1971 if ((mode->hdisplay == cea_interlaced[i].w) && 1972 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1973 mode->vdisplay *= 2; 1974 mode->vsync_start *= 2; 1975 mode->vsync_end *= 2; 1976 mode->vtotal *= 2; 1977 mode->vtotal |= 1; 1978 } 1979 } 1980 1981 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1982 } 1983 1984 /** 1985 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1986 * @dev: DRM device (needed to create new mode) 1987 * @edid: EDID block 1988 * @timing: EDID detailed timing info 1989 * @quirks: quirks to apply 1990 * 1991 * An EDID detailed timing block contains enough info for us to create and 1992 * return a new struct drm_display_mode. 1993 */ 1994 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1995 struct edid *edid, 1996 struct detailed_timing *timing, 1997 u32 quirks) 1998 { 1999 struct drm_display_mode *mode; 2000 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2001 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2002 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2003 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2004 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2005 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2006 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2007 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2008 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2009 2010 /* ignore tiny modes */ 2011 if (hactive < 64 || vactive < 64) 2012 return NULL; 2013 2014 if (pt->misc & DRM_EDID_PT_STEREO) { 2015 DRM_DEBUG_KMS("stereo mode not supported\n"); 2016 return NULL; 2017 } 2018 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2019 DRM_DEBUG_KMS("composite sync not supported\n"); 2020 } 2021 2022 /* it is incorrect if hsync/vsync width is zero */ 2023 if (!hsync_pulse_width || !vsync_pulse_width) { 2024 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2025 "Wrong Hsync/Vsync pulse width\n"); 2026 return NULL; 2027 } 2028 2029 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2030 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2031 if (!mode) 2032 return NULL; 2033 2034 goto set_size; 2035 } 2036 2037 mode = drm_mode_create(dev); 2038 if (!mode) 2039 return NULL; 2040 2041 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2042 timing->pixel_clock = cpu_to_le16(1088); 2043 2044 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2045 2046 mode->hdisplay = hactive; 2047 mode->hsync_start = mode->hdisplay + hsync_offset; 2048 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2049 mode->htotal = mode->hdisplay + hblank; 2050 2051 mode->vdisplay = vactive; 2052 mode->vsync_start = mode->vdisplay + vsync_offset; 2053 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2054 mode->vtotal = mode->vdisplay + vblank; 2055 2056 /* Some EDIDs have bogus h/vtotal values */ 2057 if (mode->hsync_end > mode->htotal) 2058 mode->htotal = mode->hsync_end + 1; 2059 if (mode->vsync_end > mode->vtotal) 2060 mode->vtotal = mode->vsync_end + 1; 2061 2062 drm_mode_do_interlace_quirk(mode, pt); 2063 2064 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2065 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2066 } 2067 2068 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2069 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2070 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2071 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2072 2073 set_size: 2074 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2075 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2076 2077 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2078 mode->width_mm *= 10; 2079 mode->height_mm *= 10; 2080 } 2081 2082 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2083 mode->width_mm = edid->width_cm * 10; 2084 mode->height_mm = edid->height_cm * 10; 2085 } 2086 2087 mode->type = DRM_MODE_TYPE_DRIVER; 2088 mode->vrefresh = drm_mode_vrefresh(mode); 2089 drm_mode_set_name(mode); 2090 2091 return mode; 2092 } 2093 2094 static bool 2095 mode_in_hsync_range(const struct drm_display_mode *mode, 2096 struct edid *edid, u8 *t) 2097 { 2098 int hsync, hmin, hmax; 2099 2100 hmin = t[7]; 2101 if (edid->revision >= 4) 2102 hmin += ((t[4] & 0x04) ? 255 : 0); 2103 hmax = t[8]; 2104 if (edid->revision >= 4) 2105 hmax += ((t[4] & 0x08) ? 255 : 0); 2106 hsync = drm_mode_hsync(mode); 2107 2108 return (hsync <= hmax && hsync >= hmin); 2109 } 2110 2111 static bool 2112 mode_in_vsync_range(const struct drm_display_mode *mode, 2113 struct edid *edid, u8 *t) 2114 { 2115 int vsync, vmin, vmax; 2116 2117 vmin = t[5]; 2118 if (edid->revision >= 4) 2119 vmin += ((t[4] & 0x01) ? 255 : 0); 2120 vmax = t[6]; 2121 if (edid->revision >= 4) 2122 vmax += ((t[4] & 0x02) ? 255 : 0); 2123 vsync = drm_mode_vrefresh(mode); 2124 2125 return (vsync <= vmax && vsync >= vmin); 2126 } 2127 2128 static u32 2129 range_pixel_clock(struct edid *edid, u8 *t) 2130 { 2131 /* unspecified */ 2132 if (t[9] == 0 || t[9] == 255) 2133 return 0; 2134 2135 /* 1.4 with CVT support gives us real precision, yay */ 2136 if (edid->revision >= 4 && t[10] == 0x04) 2137 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2138 2139 /* 1.3 is pathetic, so fuzz up a bit */ 2140 return t[9] * 10000 + 5001; 2141 } 2142 2143 static bool 2144 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2145 struct detailed_timing *timing) 2146 { 2147 u32 max_clock; 2148 u8 *t = (u8 *)timing; 2149 2150 if (!mode_in_hsync_range(mode, edid, t)) 2151 return false; 2152 2153 if (!mode_in_vsync_range(mode, edid, t)) 2154 return false; 2155 2156 if ((max_clock = range_pixel_clock(edid, t))) 2157 if (mode->clock > max_clock) 2158 return false; 2159 2160 /* 1.4 max horizontal check */ 2161 if (edid->revision >= 4 && t[10] == 0x04) 2162 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2163 return false; 2164 2165 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2166 return false; 2167 2168 return true; 2169 } 2170 2171 static bool valid_inferred_mode(const struct drm_connector *connector, 2172 const struct drm_display_mode *mode) 2173 { 2174 struct drm_display_mode *m; 2175 bool ok = false; 2176 2177 list_for_each_entry(m, &connector->probed_modes, head) { 2178 if (mode->hdisplay == m->hdisplay && 2179 mode->vdisplay == m->vdisplay && 2180 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2181 return false; /* duplicated */ 2182 if (mode->hdisplay <= m->hdisplay && 2183 mode->vdisplay <= m->vdisplay) 2184 ok = true; 2185 } 2186 return ok; 2187 } 2188 2189 static int 2190 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2191 struct detailed_timing *timing) 2192 { 2193 int i, modes = 0; 2194 struct drm_display_mode *newmode; 2195 struct drm_device *dev = connector->dev; 2196 2197 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2198 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2199 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2200 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2201 if (newmode) { 2202 drm_mode_probed_add(connector, newmode); 2203 modes++; 2204 } 2205 } 2206 } 2207 2208 return modes; 2209 } 2210 2211 /* fix up 1366x768 mode from 1368x768; 2212 * GFT/CVT can't express 1366 width which isn't dividable by 8 2213 */ 2214 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2215 { 2216 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2217 mode->hdisplay = 1366; 2218 mode->hsync_start--; 2219 mode->hsync_end--; 2220 drm_mode_set_name(mode); 2221 } 2222 } 2223 2224 static int 2225 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2226 struct detailed_timing *timing) 2227 { 2228 int i, modes = 0; 2229 struct drm_display_mode *newmode; 2230 struct drm_device *dev = connector->dev; 2231 2232 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2233 const struct minimode *m = &extra_modes[i]; 2234 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2235 if (!newmode) 2236 return modes; 2237 2238 fixup_mode_1366x768(newmode); 2239 if (!mode_in_range(newmode, edid, timing) || 2240 !valid_inferred_mode(connector, newmode)) { 2241 drm_mode_destroy(dev, newmode); 2242 continue; 2243 } 2244 2245 drm_mode_probed_add(connector, newmode); 2246 modes++; 2247 } 2248 2249 return modes; 2250 } 2251 2252 static int 2253 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2254 struct detailed_timing *timing) 2255 { 2256 int i, modes = 0; 2257 struct drm_display_mode *newmode; 2258 struct drm_device *dev = connector->dev; 2259 bool rb = drm_monitor_supports_rb(edid); 2260 2261 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2262 const struct minimode *m = &extra_modes[i]; 2263 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2264 if (!newmode) 2265 return modes; 2266 2267 fixup_mode_1366x768(newmode); 2268 if (!mode_in_range(newmode, edid, timing) || 2269 !valid_inferred_mode(connector, newmode)) { 2270 drm_mode_destroy(dev, newmode); 2271 continue; 2272 } 2273 2274 drm_mode_probed_add(connector, newmode); 2275 modes++; 2276 } 2277 2278 return modes; 2279 } 2280 2281 static void 2282 do_inferred_modes(struct detailed_timing *timing, void *c) 2283 { 2284 struct detailed_mode_closure *closure = c; 2285 struct detailed_non_pixel *data = &timing->data.other_data; 2286 struct detailed_data_monitor_range *range = &data->data.range; 2287 2288 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2289 return; 2290 2291 closure->modes += drm_dmt_modes_for_range(closure->connector, 2292 closure->edid, 2293 timing); 2294 2295 if (!version_greater(closure->edid, 1, 1)) 2296 return; /* GTF not defined yet */ 2297 2298 switch (range->flags) { 2299 case 0x02: /* secondary gtf, XXX could do more */ 2300 case 0x00: /* default gtf */ 2301 closure->modes += drm_gtf_modes_for_range(closure->connector, 2302 closure->edid, 2303 timing); 2304 break; 2305 case 0x04: /* cvt, only in 1.4+ */ 2306 if (!version_greater(closure->edid, 1, 3)) 2307 break; 2308 2309 closure->modes += drm_cvt_modes_for_range(closure->connector, 2310 closure->edid, 2311 timing); 2312 break; 2313 case 0x01: /* just the ranges, no formula */ 2314 default: 2315 break; 2316 } 2317 } 2318 2319 static int 2320 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2321 { 2322 struct detailed_mode_closure closure = { 2323 .connector = connector, 2324 .edid = edid, 2325 }; 2326 2327 if (version_greater(edid, 1, 0)) 2328 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2329 &closure); 2330 2331 return closure.modes; 2332 } 2333 2334 static int 2335 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2336 { 2337 int i, j, m, modes = 0; 2338 struct drm_display_mode *mode; 2339 u8 *est = ((u8 *)timing) + 6; 2340 2341 for (i = 0; i < 6; i++) { 2342 for (j = 7; j >= 0; j--) { 2343 m = (i * 8) + (7 - j); 2344 if (m >= ARRAY_SIZE(est3_modes)) 2345 break; 2346 if (est[i] & (1 << j)) { 2347 mode = drm_mode_find_dmt(connector->dev, 2348 est3_modes[m].w, 2349 est3_modes[m].h, 2350 est3_modes[m].r, 2351 est3_modes[m].rb); 2352 if (mode) { 2353 drm_mode_probed_add(connector, mode); 2354 modes++; 2355 } 2356 } 2357 } 2358 } 2359 2360 return modes; 2361 } 2362 2363 static void 2364 do_established_modes(struct detailed_timing *timing, void *c) 2365 { 2366 struct detailed_mode_closure *closure = c; 2367 struct detailed_non_pixel *data = &timing->data.other_data; 2368 2369 if (data->type == EDID_DETAIL_EST_TIMINGS) 2370 closure->modes += drm_est3_modes(closure->connector, timing); 2371 } 2372 2373 /** 2374 * add_established_modes - get est. modes from EDID and add them 2375 * @connector: connector to add mode(s) to 2376 * @edid: EDID block to scan 2377 * 2378 * Each EDID block contains a bitmap of the supported "established modes" list 2379 * (defined above). Tease them out and add them to the global modes list. 2380 */ 2381 static int 2382 add_established_modes(struct drm_connector *connector, struct edid *edid) 2383 { 2384 struct drm_device *dev = connector->dev; 2385 unsigned long est_bits = edid->established_timings.t1 | 2386 (edid->established_timings.t2 << 8) | 2387 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2388 int i, modes = 0; 2389 struct detailed_mode_closure closure = { 2390 .connector = connector, 2391 .edid = edid, 2392 }; 2393 2394 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2395 if (est_bits & (1<<i)) { 2396 struct drm_display_mode *newmode; 2397 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2398 if (newmode) { 2399 drm_mode_probed_add(connector, newmode); 2400 modes++; 2401 } 2402 } 2403 } 2404 2405 if (version_greater(edid, 1, 0)) 2406 drm_for_each_detailed_block((u8 *)edid, 2407 do_established_modes, &closure); 2408 2409 return modes + closure.modes; 2410 } 2411 2412 static void 2413 do_standard_modes(struct detailed_timing *timing, void *c) 2414 { 2415 struct detailed_mode_closure *closure = c; 2416 struct detailed_non_pixel *data = &timing->data.other_data; 2417 struct drm_connector *connector = closure->connector; 2418 struct edid *edid = closure->edid; 2419 2420 if (data->type == EDID_DETAIL_STD_MODES) { 2421 int i; 2422 for (i = 0; i < 6; i++) { 2423 struct std_timing *std; 2424 struct drm_display_mode *newmode; 2425 2426 std = &data->data.timings[i]; 2427 newmode = drm_mode_std(connector, edid, std); 2428 if (newmode) { 2429 drm_mode_probed_add(connector, newmode); 2430 closure->modes++; 2431 } 2432 } 2433 } 2434 } 2435 2436 /** 2437 * add_standard_modes - get std. modes from EDID and add them 2438 * @connector: connector to add mode(s) to 2439 * @edid: EDID block to scan 2440 * 2441 * Standard modes can be calculated using the appropriate standard (DMT, 2442 * GTF or CVT. Grab them from @edid and add them to the list. 2443 */ 2444 static int 2445 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2446 { 2447 int i, modes = 0; 2448 struct detailed_mode_closure closure = { 2449 .connector = connector, 2450 .edid = edid, 2451 }; 2452 2453 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2454 struct drm_display_mode *newmode; 2455 2456 newmode = drm_mode_std(connector, edid, 2457 &edid->standard_timings[i]); 2458 if (newmode) { 2459 drm_mode_probed_add(connector, newmode); 2460 modes++; 2461 } 2462 } 2463 2464 if (version_greater(edid, 1, 0)) 2465 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2466 &closure); 2467 2468 /* XXX should also look for standard codes in VTB blocks */ 2469 2470 return modes + closure.modes; 2471 } 2472 2473 static int drm_cvt_modes(struct drm_connector *connector, 2474 struct detailed_timing *timing) 2475 { 2476 int i, j, modes = 0; 2477 struct drm_display_mode *newmode; 2478 struct drm_device *dev = connector->dev; 2479 struct cvt_timing *cvt; 2480 const int rates[] = { 60, 85, 75, 60, 50 }; 2481 const u8 empty[3] = { 0, 0, 0 }; 2482 2483 for (i = 0; i < 4; i++) { 2484 int width = 0, height; 2485 cvt = &(timing->data.other_data.data.cvt[i]); 2486 2487 if (!memcmp(cvt->code, empty, 3)) 2488 continue; 2489 2490 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2491 switch (cvt->code[1] & 0x0c) { 2492 case 0x00: 2493 width = height * 4 / 3; 2494 break; 2495 case 0x04: 2496 width = height * 16 / 9; 2497 break; 2498 case 0x08: 2499 width = height * 16 / 10; 2500 break; 2501 case 0x0c: 2502 width = height * 15 / 9; 2503 break; 2504 } 2505 2506 for (j = 1; j < 5; j++) { 2507 if (cvt->code[2] & (1 << j)) { 2508 newmode = drm_cvt_mode(dev, width, height, 2509 rates[j], j == 0, 2510 false, false); 2511 if (newmode) { 2512 drm_mode_probed_add(connector, newmode); 2513 modes++; 2514 } 2515 } 2516 } 2517 } 2518 2519 return modes; 2520 } 2521 2522 static void 2523 do_cvt_mode(struct detailed_timing *timing, void *c) 2524 { 2525 struct detailed_mode_closure *closure = c; 2526 struct detailed_non_pixel *data = &timing->data.other_data; 2527 2528 if (data->type == EDID_DETAIL_CVT_3BYTE) 2529 closure->modes += drm_cvt_modes(closure->connector, timing); 2530 } 2531 2532 static int 2533 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2534 { 2535 struct detailed_mode_closure closure = { 2536 .connector = connector, 2537 .edid = edid, 2538 }; 2539 2540 if (version_greater(edid, 1, 2)) 2541 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2542 2543 /* XXX should also look for CVT codes in VTB blocks */ 2544 2545 return closure.modes; 2546 } 2547 2548 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2549 2550 static void 2551 do_detailed_mode(struct detailed_timing *timing, void *c) 2552 { 2553 struct detailed_mode_closure *closure = c; 2554 struct drm_display_mode *newmode; 2555 2556 if (timing->pixel_clock) { 2557 newmode = drm_mode_detailed(closure->connector->dev, 2558 closure->edid, timing, 2559 closure->quirks); 2560 if (!newmode) 2561 return; 2562 2563 if (closure->preferred) 2564 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2565 2566 /* 2567 * Detailed modes are limited to 10kHz pixel clock resolution, 2568 * so fix up anything that looks like CEA/HDMI mode, but the clock 2569 * is just slightly off. 2570 */ 2571 fixup_detailed_cea_mode_clock(newmode); 2572 2573 drm_mode_probed_add(closure->connector, newmode); 2574 closure->modes++; 2575 closure->preferred = 0; 2576 } 2577 } 2578 2579 /* 2580 * add_detailed_modes - Add modes from detailed timings 2581 * @connector: attached connector 2582 * @edid: EDID block to scan 2583 * @quirks: quirks to apply 2584 */ 2585 static int 2586 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2587 u32 quirks) 2588 { 2589 struct detailed_mode_closure closure = { 2590 .connector = connector, 2591 .edid = edid, 2592 .preferred = 1, 2593 .quirks = quirks, 2594 }; 2595 2596 if (closure.preferred && !version_greater(edid, 1, 3)) 2597 closure.preferred = 2598 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2599 2600 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2601 2602 return closure.modes; 2603 } 2604 2605 #define AUDIO_BLOCK 0x01 2606 #define VIDEO_BLOCK 0x02 2607 #define VENDOR_BLOCK 0x03 2608 #define SPEAKER_BLOCK 0x04 2609 #define VIDEO_CAPABILITY_BLOCK 0x07 2610 #define EDID_BASIC_AUDIO (1 << 6) 2611 #define EDID_CEA_YCRCB444 (1 << 5) 2612 #define EDID_CEA_YCRCB422 (1 << 4) 2613 #define EDID_CEA_VCDB_QS (1 << 6) 2614 2615 /* 2616 * Search EDID for CEA extension block. 2617 */ 2618 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2619 { 2620 u8 *edid_ext = NULL; 2621 int i; 2622 2623 /* No EDID or EDID extensions */ 2624 if (edid == NULL || edid->extensions == 0) 2625 return NULL; 2626 2627 /* Find CEA extension */ 2628 for (i = 0; i < edid->extensions; i++) { 2629 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2630 if (edid_ext[0] == ext_id) 2631 break; 2632 } 2633 2634 if (i == edid->extensions) 2635 return NULL; 2636 2637 return edid_ext; 2638 } 2639 2640 static u8 *drm_find_cea_extension(struct edid *edid) 2641 { 2642 return drm_find_edid_extension(edid, CEA_EXT); 2643 } 2644 2645 static u8 *drm_find_displayid_extension(struct edid *edid) 2646 { 2647 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2648 } 2649 2650 /* 2651 * Calculate the alternate clock for the CEA mode 2652 * (60Hz vs. 59.94Hz etc.) 2653 */ 2654 static unsigned int 2655 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2656 { 2657 unsigned int clock = cea_mode->clock; 2658 2659 if (cea_mode->vrefresh % 6 != 0) 2660 return clock; 2661 2662 /* 2663 * edid_cea_modes contains the 59.94Hz 2664 * variant for 240 and 480 line modes, 2665 * and the 60Hz variant otherwise. 2666 */ 2667 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2668 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2669 else 2670 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2671 2672 return clock; 2673 } 2674 2675 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2676 unsigned int clock_tolerance) 2677 { 2678 u8 vic; 2679 2680 if (!to_match->clock) 2681 return 0; 2682 2683 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2684 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2685 unsigned int clock1, clock2; 2686 2687 /* Check both 60Hz and 59.94Hz */ 2688 clock1 = cea_mode->clock; 2689 clock2 = cea_mode_alternate_clock(cea_mode); 2690 2691 if (abs(to_match->clock - clock1) > clock_tolerance && 2692 abs(to_match->clock - clock2) > clock_tolerance) 2693 continue; 2694 2695 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 2696 return vic; 2697 } 2698 2699 return 0; 2700 } 2701 2702 /** 2703 * drm_match_cea_mode - look for a CEA mode matching given mode 2704 * @to_match: display mode 2705 * 2706 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2707 * mode. 2708 */ 2709 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2710 { 2711 u8 vic; 2712 2713 if (!to_match->clock) 2714 return 0; 2715 2716 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2717 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2718 unsigned int clock1, clock2; 2719 2720 /* Check both 60Hz and 59.94Hz */ 2721 clock1 = cea_mode->clock; 2722 clock2 = cea_mode_alternate_clock(cea_mode); 2723 2724 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2725 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2726 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2727 return vic; 2728 } 2729 return 0; 2730 } 2731 EXPORT_SYMBOL(drm_match_cea_mode); 2732 2733 static bool drm_valid_cea_vic(u8 vic) 2734 { 2735 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2736 } 2737 2738 /** 2739 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2740 * the input VIC from the CEA mode list 2741 * @video_code: ID given to each of the CEA modes 2742 * 2743 * Returns picture aspect ratio 2744 */ 2745 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2746 { 2747 return edid_cea_modes[video_code].picture_aspect_ratio; 2748 } 2749 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2750 2751 /* 2752 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2753 * specific block). 2754 * 2755 * It's almost like cea_mode_alternate_clock(), we just need to add an 2756 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2757 * one. 2758 */ 2759 static unsigned int 2760 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2761 { 2762 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2763 return hdmi_mode->clock; 2764 2765 return cea_mode_alternate_clock(hdmi_mode); 2766 } 2767 2768 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 2769 unsigned int clock_tolerance) 2770 { 2771 u8 vic; 2772 2773 if (!to_match->clock) 2774 return 0; 2775 2776 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2777 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2778 unsigned int clock1, clock2; 2779 2780 /* Make sure to also match alternate clocks */ 2781 clock1 = hdmi_mode->clock; 2782 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2783 2784 if (abs(to_match->clock - clock1) > clock_tolerance && 2785 abs(to_match->clock - clock2) > clock_tolerance) 2786 continue; 2787 2788 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 2789 return vic; 2790 } 2791 2792 return 0; 2793 } 2794 2795 /* 2796 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2797 * @to_match: display mode 2798 * 2799 * An HDMI mode is one defined in the HDMI vendor specific block. 2800 * 2801 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2802 */ 2803 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2804 { 2805 u8 vic; 2806 2807 if (!to_match->clock) 2808 return 0; 2809 2810 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2811 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2812 unsigned int clock1, clock2; 2813 2814 /* Make sure to also match alternate clocks */ 2815 clock1 = hdmi_mode->clock; 2816 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2817 2818 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2819 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2820 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2821 return vic; 2822 } 2823 return 0; 2824 } 2825 2826 static bool drm_valid_hdmi_vic(u8 vic) 2827 { 2828 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2829 } 2830 2831 static int 2832 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2833 { 2834 struct drm_device *dev = connector->dev; 2835 struct drm_display_mode *mode, *tmp; 2836 LINUX_LIST_HEAD(list); 2837 int modes = 0; 2838 2839 /* Don't add CEA modes if the CEA extension block is missing */ 2840 if (!drm_find_cea_extension(edid)) 2841 return 0; 2842 2843 /* 2844 * Go through all probed modes and create a new mode 2845 * with the alternate clock for certain CEA modes. 2846 */ 2847 list_for_each_entry(mode, &connector->probed_modes, head) { 2848 const struct drm_display_mode *cea_mode = NULL; 2849 struct drm_display_mode *newmode; 2850 u8 vic = drm_match_cea_mode(mode); 2851 unsigned int clock1, clock2; 2852 2853 if (drm_valid_cea_vic(vic)) { 2854 cea_mode = &edid_cea_modes[vic]; 2855 clock2 = cea_mode_alternate_clock(cea_mode); 2856 } else { 2857 vic = drm_match_hdmi_mode(mode); 2858 if (drm_valid_hdmi_vic(vic)) { 2859 cea_mode = &edid_4k_modes[vic]; 2860 clock2 = hdmi_mode_alternate_clock(cea_mode); 2861 } 2862 } 2863 2864 if (!cea_mode) 2865 continue; 2866 2867 clock1 = cea_mode->clock; 2868 2869 if (clock1 == clock2) 2870 continue; 2871 2872 if (mode->clock != clock1 && mode->clock != clock2) 2873 continue; 2874 2875 newmode = drm_mode_duplicate(dev, cea_mode); 2876 if (!newmode) 2877 continue; 2878 2879 /* Carry over the stereo flags */ 2880 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2881 2882 /* 2883 * The current mode could be either variant. Make 2884 * sure to pick the "other" clock for the new mode. 2885 */ 2886 if (mode->clock != clock1) 2887 newmode->clock = clock1; 2888 else 2889 newmode->clock = clock2; 2890 2891 list_add_tail(&newmode->head, &list); 2892 } 2893 2894 list_for_each_entry_safe(mode, tmp, &list, head) { 2895 list_del(&mode->head); 2896 drm_mode_probed_add(connector, mode); 2897 modes++; 2898 } 2899 2900 return modes; 2901 } 2902 2903 static struct drm_display_mode * 2904 drm_display_mode_from_vic_index(struct drm_connector *connector, 2905 const u8 *video_db, u8 video_len, 2906 u8 video_index) 2907 { 2908 struct drm_device *dev = connector->dev; 2909 struct drm_display_mode *newmode; 2910 u8 vic; 2911 2912 if (video_db == NULL || video_index >= video_len) 2913 return NULL; 2914 2915 /* CEA modes are numbered 1..127 */ 2916 vic = (video_db[video_index] & 127); 2917 if (!drm_valid_cea_vic(vic)) 2918 return NULL; 2919 2920 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 2921 if (!newmode) 2922 return NULL; 2923 2924 newmode->vrefresh = 0; 2925 2926 return newmode; 2927 } 2928 2929 static int 2930 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2931 { 2932 int i, modes = 0; 2933 2934 for (i = 0; i < len; i++) { 2935 struct drm_display_mode *mode; 2936 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2937 if (mode) { 2938 drm_mode_probed_add(connector, mode); 2939 modes++; 2940 } 2941 } 2942 2943 return modes; 2944 } 2945 2946 struct stereo_mandatory_mode { 2947 int width, height, vrefresh; 2948 unsigned int flags; 2949 }; 2950 2951 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2952 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2953 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2954 { 1920, 1080, 50, 2955 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2956 { 1920, 1080, 60, 2957 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2958 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2959 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2960 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2961 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2962 }; 2963 2964 static bool 2965 stereo_match_mandatory(const struct drm_display_mode *mode, 2966 const struct stereo_mandatory_mode *stereo_mode) 2967 { 2968 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2969 2970 return mode->hdisplay == stereo_mode->width && 2971 mode->vdisplay == stereo_mode->height && 2972 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2973 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2974 } 2975 2976 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2977 { 2978 struct drm_device *dev = connector->dev; 2979 struct drm_display_mode *mode; 2980 struct list_head stereo_modes; 2981 int modes = 0, i; 2982 2983 INIT_LIST_HEAD(&stereo_modes); 2984 2985 list_for_each_entry(mode, &connector->probed_modes, head) { 2986 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2987 const struct stereo_mandatory_mode *mandatory; 2988 struct drm_display_mode *new_mode; 2989 2990 if (!stereo_match_mandatory(mode, 2991 &stereo_mandatory_modes[i])) 2992 continue; 2993 2994 mandatory = &stereo_mandatory_modes[i]; 2995 new_mode = drm_mode_duplicate(dev, mode); 2996 if (!new_mode) 2997 continue; 2998 2999 new_mode->flags |= mandatory->flags; 3000 list_add_tail(&new_mode->head, &stereo_modes); 3001 modes++; 3002 } 3003 } 3004 3005 list_splice_tail(&stereo_modes, &connector->probed_modes); 3006 3007 return modes; 3008 } 3009 3010 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3011 { 3012 struct drm_device *dev = connector->dev; 3013 struct drm_display_mode *newmode; 3014 3015 if (!drm_valid_hdmi_vic(vic)) { 3016 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3017 return 0; 3018 } 3019 3020 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3021 if (!newmode) 3022 return 0; 3023 3024 drm_mode_probed_add(connector, newmode); 3025 3026 return 1; 3027 } 3028 3029 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3030 const u8 *video_db, u8 video_len, u8 video_index) 3031 { 3032 struct drm_display_mode *newmode; 3033 int modes = 0; 3034 3035 if (structure & (1 << 0)) { 3036 newmode = drm_display_mode_from_vic_index(connector, video_db, 3037 video_len, 3038 video_index); 3039 if (newmode) { 3040 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3041 drm_mode_probed_add(connector, newmode); 3042 modes++; 3043 } 3044 } 3045 if (structure & (1 << 6)) { 3046 newmode = drm_display_mode_from_vic_index(connector, video_db, 3047 video_len, 3048 video_index); 3049 if (newmode) { 3050 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3051 drm_mode_probed_add(connector, newmode); 3052 modes++; 3053 } 3054 } 3055 if (structure & (1 << 8)) { 3056 newmode = drm_display_mode_from_vic_index(connector, video_db, 3057 video_len, 3058 video_index); 3059 if (newmode) { 3060 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3061 drm_mode_probed_add(connector, newmode); 3062 modes++; 3063 } 3064 } 3065 3066 return modes; 3067 } 3068 3069 /* 3070 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3071 * @connector: connector corresponding to the HDMI sink 3072 * @db: start of the CEA vendor specific block 3073 * @len: length of the CEA block payload, ie. one can access up to db[len] 3074 * 3075 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3076 * also adds the stereo 3d modes when applicable. 3077 */ 3078 static int 3079 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3080 const u8 *video_db, u8 video_len) 3081 { 3082 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3083 u8 vic_len, hdmi_3d_len = 0; 3084 u16 mask; 3085 u16 structure_all; 3086 3087 if (len < 8) 3088 goto out; 3089 3090 /* no HDMI_Video_Present */ 3091 if (!(db[8] & (1 << 5))) 3092 goto out; 3093 3094 /* Latency_Fields_Present */ 3095 if (db[8] & (1 << 7)) 3096 offset += 2; 3097 3098 /* I_Latency_Fields_Present */ 3099 if (db[8] & (1 << 6)) 3100 offset += 2; 3101 3102 /* the declared length is not long enough for the 2 first bytes 3103 * of additional video format capabilities */ 3104 if (len < (8 + offset + 2)) 3105 goto out; 3106 3107 /* 3D_Present */ 3108 offset++; 3109 if (db[8 + offset] & (1 << 7)) { 3110 modes += add_hdmi_mandatory_stereo_modes(connector); 3111 3112 /* 3D_Multi_present */ 3113 multi_present = (db[8 + offset] & 0x60) >> 5; 3114 } 3115 3116 offset++; 3117 vic_len = db[8 + offset] >> 5; 3118 hdmi_3d_len = db[8 + offset] & 0x1f; 3119 3120 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3121 u8 vic; 3122 3123 vic = db[9 + offset + i]; 3124 modes += add_hdmi_mode(connector, vic); 3125 } 3126 offset += 1 + vic_len; 3127 3128 if (multi_present == 1) 3129 multi_len = 2; 3130 else if (multi_present == 2) 3131 multi_len = 4; 3132 else 3133 multi_len = 0; 3134 3135 if (len < (8 + offset + hdmi_3d_len - 1)) 3136 goto out; 3137 3138 if (hdmi_3d_len < multi_len) 3139 goto out; 3140 3141 if (multi_present == 1 || multi_present == 2) { 3142 /* 3D_Structure_ALL */ 3143 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3144 3145 /* check if 3D_MASK is present */ 3146 if (multi_present == 2) 3147 mask = (db[10 + offset] << 8) | db[11 + offset]; 3148 else 3149 mask = 0xffff; 3150 3151 for (i = 0; i < 16; i++) { 3152 if (mask & (1 << i)) 3153 modes += add_3d_struct_modes(connector, 3154 structure_all, 3155 video_db, 3156 video_len, i); 3157 } 3158 } 3159 3160 offset += multi_len; 3161 3162 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3163 int vic_index; 3164 struct drm_display_mode *newmode = NULL; 3165 unsigned int newflag = 0; 3166 bool detail_present; 3167 3168 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3169 3170 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3171 break; 3172 3173 /* 2D_VIC_order_X */ 3174 vic_index = db[8 + offset + i] >> 4; 3175 3176 /* 3D_Structure_X */ 3177 switch (db[8 + offset + i] & 0x0f) { 3178 case 0: 3179 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3180 break; 3181 case 6: 3182 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3183 break; 3184 case 8: 3185 /* 3D_Detail_X */ 3186 if ((db[9 + offset + i] >> 4) == 1) 3187 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3188 break; 3189 } 3190 3191 if (newflag != 0) { 3192 newmode = drm_display_mode_from_vic_index(connector, 3193 video_db, 3194 video_len, 3195 vic_index); 3196 3197 if (newmode) { 3198 newmode->flags |= newflag; 3199 drm_mode_probed_add(connector, newmode); 3200 modes++; 3201 } 3202 } 3203 3204 if (detail_present) 3205 i++; 3206 } 3207 3208 out: 3209 return modes; 3210 } 3211 3212 static int 3213 cea_db_payload_len(const u8 *db) 3214 { 3215 return db[0] & 0x1f; 3216 } 3217 3218 static int 3219 cea_db_tag(const u8 *db) 3220 { 3221 return db[0] >> 5; 3222 } 3223 3224 static int 3225 cea_revision(const u8 *cea) 3226 { 3227 return cea[1]; 3228 } 3229 3230 static int 3231 cea_db_offsets(const u8 *cea, int *start, int *end) 3232 { 3233 /* Data block offset in CEA extension block */ 3234 *start = 4; 3235 *end = cea[2]; 3236 if (*end == 0) 3237 *end = 127; 3238 if (*end < 4 || *end > 127) 3239 return -ERANGE; 3240 return 0; 3241 } 3242 3243 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3244 { 3245 int hdmi_id; 3246 3247 if (cea_db_tag(db) != VENDOR_BLOCK) 3248 return false; 3249 3250 if (cea_db_payload_len(db) < 5) 3251 return false; 3252 3253 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3254 3255 return hdmi_id == HDMI_IEEE_OUI; 3256 } 3257 3258 #define for_each_cea_db(cea, i, start, end) \ 3259 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3260 3261 static int 3262 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3263 { 3264 const u8 *cea = drm_find_cea_extension(edid); 3265 const u8 *db, *hdmi = NULL, *video = NULL; 3266 u8 dbl, hdmi_len, video_len = 0; 3267 int modes = 0; 3268 3269 if (cea && cea_revision(cea) >= 3) { 3270 int i, start, end; 3271 3272 if (cea_db_offsets(cea, &start, &end)) 3273 return 0; 3274 3275 for_each_cea_db(cea, i, start, end) { 3276 db = &cea[i]; 3277 dbl = cea_db_payload_len(db); 3278 3279 if (cea_db_tag(db) == VIDEO_BLOCK) { 3280 video = db + 1; 3281 video_len = dbl; 3282 modes += do_cea_modes(connector, video, dbl); 3283 } 3284 else if (cea_db_is_hdmi_vsdb(db)) { 3285 hdmi = db; 3286 hdmi_len = dbl; 3287 } 3288 } 3289 } 3290 3291 /* 3292 * We parse the HDMI VSDB after having added the cea modes as we will 3293 * be patching their flags when the sink supports stereo 3D. 3294 */ 3295 if (hdmi) 3296 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3297 video_len); 3298 3299 return modes; 3300 } 3301 3302 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3303 { 3304 const struct drm_display_mode *cea_mode; 3305 int clock1, clock2, clock; 3306 u8 vic; 3307 const char *type; 3308 3309 /* 3310 * allow 5kHz clock difference either way to account for 3311 * the 10kHz clock resolution limit of detailed timings. 3312 */ 3313 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3314 if (drm_valid_cea_vic(vic)) { 3315 type = "CEA"; 3316 cea_mode = &edid_cea_modes[vic]; 3317 clock1 = cea_mode->clock; 3318 clock2 = cea_mode_alternate_clock(cea_mode); 3319 } else { 3320 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3321 if (drm_valid_hdmi_vic(vic)) { 3322 type = "HDMI"; 3323 cea_mode = &edid_4k_modes[vic]; 3324 clock1 = cea_mode->clock; 3325 clock2 = hdmi_mode_alternate_clock(cea_mode); 3326 } else { 3327 return; 3328 } 3329 } 3330 3331 /* pick whichever is closest */ 3332 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3333 clock = clock1; 3334 else 3335 clock = clock2; 3336 3337 if (mode->clock == clock) 3338 return; 3339 3340 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3341 type, vic, mode->clock, clock); 3342 mode->clock = clock; 3343 } 3344 3345 static void 3346 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3347 { 3348 u8 len = cea_db_payload_len(db); 3349 3350 if (len >= 6) { 3351 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3352 connector->dvi_dual = db[6] & 1; 3353 } 3354 if (len >= 7) 3355 connector->max_tmds_clock = db[7] * 5; 3356 if (len >= 8) { 3357 connector->latency_present[0] = db[8] >> 7; 3358 connector->latency_present[1] = (db[8] >> 6) & 1; 3359 } 3360 if (len >= 9) 3361 connector->video_latency[0] = db[9]; 3362 if (len >= 10) 3363 connector->audio_latency[0] = db[10]; 3364 if (len >= 11) 3365 connector->video_latency[1] = db[11]; 3366 if (len >= 12) 3367 connector->audio_latency[1] = db[12]; 3368 3369 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3370 "max TMDS clock %d, " 3371 "latency present %d %d, " 3372 "video latency %d %d, " 3373 "audio latency %d %d\n", 3374 connector->dvi_dual, 3375 connector->max_tmds_clock, 3376 (int) connector->latency_present[0], 3377 (int) connector->latency_present[1], 3378 connector->video_latency[0], 3379 connector->video_latency[1], 3380 connector->audio_latency[0], 3381 connector->audio_latency[1]); 3382 } 3383 3384 static void 3385 monitor_name(struct detailed_timing *t, void *data) 3386 { 3387 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3388 *(u8 **)data = t->data.other_data.data.str.str; 3389 } 3390 3391 static int get_monitor_name(struct edid *edid, char name[13]) 3392 { 3393 char *edid_name = NULL; 3394 int mnl; 3395 3396 if (!edid || !name) 3397 return 0; 3398 3399 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3400 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3401 if (edid_name[mnl] == 0x0a) 3402 break; 3403 3404 name[mnl] = edid_name[mnl]; 3405 } 3406 3407 return mnl; 3408 } 3409 3410 /** 3411 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3412 * @edid: monitor EDID information 3413 * @name: pointer to a character array to hold the name of the monitor 3414 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3415 * 3416 */ 3417 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3418 { 3419 int name_length; 3420 char buf[13]; 3421 3422 if (bufsize <= 0) 3423 return; 3424 3425 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3426 memcpy(name, buf, name_length); 3427 name[name_length] = '\0'; 3428 } 3429 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3430 3431 /** 3432 * drm_edid_to_eld - build ELD from EDID 3433 * @connector: connector corresponding to the HDMI/DP sink 3434 * @edid: EDID to parse 3435 * 3436 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3437 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3438 * fill in. 3439 */ 3440 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3441 { 3442 uint8_t *eld = connector->eld; 3443 u8 *cea; 3444 u8 *db; 3445 int total_sad_count = 0; 3446 int mnl; 3447 int dbl; 3448 3449 memset(eld, 0, sizeof(connector->eld)); 3450 3451 cea = drm_find_cea_extension(edid); 3452 if (!cea) { 3453 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3454 return; 3455 } 3456 3457 mnl = get_monitor_name(edid, eld + 20); 3458 3459 eld[4] = (cea[1] << 5) | mnl; 3460 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3461 3462 eld[0] = 2 << 3; /* ELD version: 2 */ 3463 3464 eld[16] = edid->mfg_id[0]; 3465 eld[17] = edid->mfg_id[1]; 3466 eld[18] = edid->prod_code[0]; 3467 eld[19] = edid->prod_code[1]; 3468 3469 if (cea_revision(cea) >= 3) { 3470 int i, start, end; 3471 3472 if (cea_db_offsets(cea, &start, &end)) { 3473 start = 0; 3474 end = 0; 3475 } 3476 3477 for_each_cea_db(cea, i, start, end) { 3478 db = &cea[i]; 3479 dbl = cea_db_payload_len(db); 3480 3481 switch (cea_db_tag(db)) { 3482 int sad_count; 3483 3484 case AUDIO_BLOCK: 3485 /* Audio Data Block, contains SADs */ 3486 sad_count = min(dbl / 3, 15 - total_sad_count); 3487 if (sad_count >= 1) 3488 memcpy(eld + 20 + mnl + total_sad_count * 3, 3489 &db[1], sad_count * 3); 3490 total_sad_count += sad_count; 3491 break; 3492 case SPEAKER_BLOCK: 3493 /* Speaker Allocation Data Block */ 3494 if (dbl >= 1) 3495 eld[7] = db[1]; 3496 break; 3497 case VENDOR_BLOCK: 3498 /* HDMI Vendor-Specific Data Block */ 3499 if (cea_db_is_hdmi_vsdb(db)) 3500 parse_hdmi_vsdb(connector, db); 3501 break; 3502 default: 3503 break; 3504 } 3505 } 3506 } 3507 eld[5] |= total_sad_count << 4; 3508 3509 eld[DRM_ELD_BASELINE_ELD_LEN] = 3510 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3511 3512 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3513 drm_eld_size(eld), total_sad_count); 3514 } 3515 EXPORT_SYMBOL(drm_edid_to_eld); 3516 3517 /** 3518 * drm_edid_to_sad - extracts SADs from EDID 3519 * @edid: EDID to parse 3520 * @sads: pointer that will be set to the extracted SADs 3521 * 3522 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3523 * 3524 * Note: The returned pointer needs to be freed using kfree(). 3525 * 3526 * Return: The number of found SADs or negative number on error. 3527 */ 3528 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3529 { 3530 int count = 0; 3531 int i, start, end, dbl; 3532 u8 *cea; 3533 3534 cea = drm_find_cea_extension(edid); 3535 if (!cea) { 3536 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3537 return -ENOENT; 3538 } 3539 3540 if (cea_revision(cea) < 3) { 3541 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3542 return -EOPNOTSUPP; 3543 } 3544 3545 if (cea_db_offsets(cea, &start, &end)) { 3546 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3547 return -EPROTO; 3548 } 3549 3550 for_each_cea_db(cea, i, start, end) { 3551 u8 *db = &cea[i]; 3552 3553 if (cea_db_tag(db) == AUDIO_BLOCK) { 3554 int j; 3555 dbl = cea_db_payload_len(db); 3556 3557 count = dbl / 3; /* SAD is 3B */ 3558 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3559 if (!*sads) 3560 return -ENOMEM; 3561 for (j = 0; j < count; j++) { 3562 u8 *sad = &db[1 + j * 3]; 3563 3564 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3565 (*sads)[j].channels = sad[0] & 0x7; 3566 (*sads)[j].freq = sad[1] & 0x7F; 3567 (*sads)[j].byte2 = sad[2]; 3568 } 3569 break; 3570 } 3571 } 3572 3573 return count; 3574 } 3575 EXPORT_SYMBOL(drm_edid_to_sad); 3576 3577 /** 3578 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3579 * @edid: EDID to parse 3580 * @sadb: pointer to the speaker block 3581 * 3582 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3583 * 3584 * Note: The returned pointer needs to be freed using kfree(). 3585 * 3586 * Return: The number of found Speaker Allocation Blocks or negative number on 3587 * error. 3588 */ 3589 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3590 { 3591 int count = 0; 3592 int i, start, end, dbl; 3593 const u8 *cea; 3594 3595 cea = drm_find_cea_extension(edid); 3596 if (!cea) { 3597 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3598 return -ENOENT; 3599 } 3600 3601 if (cea_revision(cea) < 3) { 3602 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3603 return -ENOTSUPP; 3604 } 3605 3606 if (cea_db_offsets(cea, &start, &end)) { 3607 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3608 return -EPROTO; 3609 } 3610 3611 for_each_cea_db(cea, i, start, end) { 3612 const u8 *db = &cea[i]; 3613 3614 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3615 dbl = cea_db_payload_len(db); 3616 3617 /* Speaker Allocation Data Block */ 3618 if (dbl == 3) { 3619 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3620 if (!*sadb) 3621 return -ENOMEM; 3622 count = dbl; 3623 break; 3624 } 3625 } 3626 } 3627 3628 return count; 3629 } 3630 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3631 3632 /** 3633 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3634 * @connector: connector associated with the HDMI/DP sink 3635 * @mode: the display mode 3636 * 3637 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3638 * the sink doesn't support audio or video. 3639 */ 3640 int drm_av_sync_delay(struct drm_connector *connector, 3641 const struct drm_display_mode *mode) 3642 { 3643 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3644 int a, v; 3645 3646 if (!connector->latency_present[0]) 3647 return 0; 3648 if (!connector->latency_present[1]) 3649 i = 0; 3650 3651 a = connector->audio_latency[i]; 3652 v = connector->video_latency[i]; 3653 3654 /* 3655 * HDMI/DP sink doesn't support audio or video? 3656 */ 3657 if (a == 255 || v == 255) 3658 return 0; 3659 3660 /* 3661 * Convert raw EDID values to millisecond. 3662 * Treat unknown latency as 0ms. 3663 */ 3664 if (a) 3665 a = min(2 * (a - 1), 500); 3666 if (v) 3667 v = min(2 * (v - 1), 500); 3668 3669 return max(v - a, 0); 3670 } 3671 EXPORT_SYMBOL(drm_av_sync_delay); 3672 3673 /** 3674 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3675 * @encoder: the encoder just changed display mode 3676 * 3677 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3678 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3679 * 3680 * Return: The connector associated with the first HDMI/DP sink that has ELD 3681 * attached to it. 3682 */ 3683 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3684 { 3685 struct drm_connector *connector; 3686 struct drm_device *dev = encoder->dev; 3687 3688 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3689 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3690 3691 drm_for_each_connector(connector, dev) 3692 if (connector->encoder == encoder && connector->eld[0]) 3693 return connector; 3694 3695 return NULL; 3696 } 3697 EXPORT_SYMBOL(drm_select_eld); 3698 3699 /** 3700 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3701 * @edid: monitor EDID information 3702 * 3703 * Parse the CEA extension according to CEA-861-B. 3704 * 3705 * Return: True if the monitor is HDMI, false if not or unknown. 3706 */ 3707 bool drm_detect_hdmi_monitor(struct edid *edid) 3708 { 3709 u8 *edid_ext; 3710 int i; 3711 int start_offset, end_offset; 3712 3713 edid_ext = drm_find_cea_extension(edid); 3714 if (!edid_ext) 3715 return false; 3716 3717 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3718 return false; 3719 3720 /* 3721 * Because HDMI identifier is in Vendor Specific Block, 3722 * search it from all data blocks of CEA extension. 3723 */ 3724 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3725 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3726 return true; 3727 } 3728 3729 return false; 3730 } 3731 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3732 3733 /** 3734 * drm_detect_monitor_audio - check monitor audio capability 3735 * @edid: EDID block to scan 3736 * 3737 * Monitor should have CEA extension block. 3738 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3739 * audio' only. If there is any audio extension block and supported 3740 * audio format, assume at least 'basic audio' support, even if 'basic 3741 * audio' is not defined in EDID. 3742 * 3743 * Return: True if the monitor supports audio, false otherwise. 3744 */ 3745 bool drm_detect_monitor_audio(struct edid *edid) 3746 { 3747 u8 *edid_ext; 3748 int i, j; 3749 bool has_audio = false; 3750 int start_offset, end_offset; 3751 3752 edid_ext = drm_find_cea_extension(edid); 3753 if (!edid_ext) 3754 goto end; 3755 3756 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3757 3758 if (has_audio) { 3759 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3760 goto end; 3761 } 3762 3763 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3764 goto end; 3765 3766 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3767 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3768 has_audio = true; 3769 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3770 DRM_DEBUG_KMS("CEA audio format %d\n", 3771 (edid_ext[i + j] >> 3) & 0xf); 3772 goto end; 3773 } 3774 } 3775 end: 3776 return has_audio; 3777 } 3778 EXPORT_SYMBOL(drm_detect_monitor_audio); 3779 3780 /** 3781 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3782 * @edid: EDID block to scan 3783 * 3784 * Check whether the monitor reports the RGB quantization range selection 3785 * as supported. The AVI infoframe can then be used to inform the monitor 3786 * which quantization range (full or limited) is used. 3787 * 3788 * Return: True if the RGB quantization range is selectable, false otherwise. 3789 */ 3790 bool drm_rgb_quant_range_selectable(struct edid *edid) 3791 { 3792 u8 *edid_ext; 3793 int i, start, end; 3794 3795 edid_ext = drm_find_cea_extension(edid); 3796 if (!edid_ext) 3797 return false; 3798 3799 if (cea_db_offsets(edid_ext, &start, &end)) 3800 return false; 3801 3802 for_each_cea_db(edid_ext, i, start, end) { 3803 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3804 cea_db_payload_len(&edid_ext[i]) == 2) { 3805 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3806 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3807 } 3808 } 3809 3810 return false; 3811 } 3812 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3813 3814 /** 3815 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3816 * hdmi deep color modes and update drm_display_info if so. 3817 * @edid: monitor EDID information 3818 * @info: Updated with maximum supported deep color bpc and color format 3819 * if deep color supported. 3820 * @connector: DRM connector, used only for debug output 3821 * 3822 * Parse the CEA extension according to CEA-861-B. 3823 * Return true if HDMI deep color supported, false if not or unknown. 3824 */ 3825 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3826 struct drm_display_info *info, 3827 struct drm_connector *connector) 3828 { 3829 u8 *edid_ext, *hdmi; 3830 int i; 3831 int start_offset, end_offset; 3832 unsigned int dc_bpc = 0; 3833 3834 edid_ext = drm_find_cea_extension(edid); 3835 if (!edid_ext) 3836 return false; 3837 3838 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3839 return false; 3840 3841 /* 3842 * Because HDMI identifier is in Vendor Specific Block, 3843 * search it from all data blocks of CEA extension. 3844 */ 3845 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3846 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3847 /* HDMI supports at least 8 bpc */ 3848 info->bpc = 8; 3849 3850 hdmi = &edid_ext[i]; 3851 if (cea_db_payload_len(hdmi) < 6) 3852 return false; 3853 3854 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3855 dc_bpc = 10; 3856 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3857 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3858 connector->name); 3859 } 3860 3861 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3862 dc_bpc = 12; 3863 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3864 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3865 connector->name); 3866 } 3867 3868 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3869 dc_bpc = 16; 3870 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3871 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3872 connector->name); 3873 } 3874 3875 if (dc_bpc > 0) { 3876 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3877 connector->name, dc_bpc); 3878 info->bpc = dc_bpc; 3879 3880 /* 3881 * Deep color support mandates RGB444 support for all video 3882 * modes and forbids YCRCB422 support for all video modes per 3883 * HDMI 1.3 spec. 3884 */ 3885 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3886 3887 /* YCRCB444 is optional according to spec. */ 3888 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3889 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3890 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3891 connector->name); 3892 } 3893 3894 /* 3895 * Spec says that if any deep color mode is supported at all, 3896 * then deep color 36 bit must be supported. 3897 */ 3898 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3899 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3900 connector->name); 3901 } 3902 3903 return true; 3904 } 3905 else { 3906 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3907 connector->name); 3908 } 3909 } 3910 } 3911 3912 return false; 3913 } 3914 3915 /** 3916 * drm_add_display_info - pull display info out if present 3917 * @edid: EDID data 3918 * @info: display info (attached to connector) 3919 * @connector: connector whose edid is used to build display info 3920 * 3921 * Grab any available display info and stuff it into the drm_display_info 3922 * structure that's part of the connector. Useful for tracking bpp and 3923 * color spaces. 3924 */ 3925 static void drm_add_display_info(struct edid *edid, 3926 struct drm_display_info *info, 3927 struct drm_connector *connector) 3928 { 3929 u8 *edid_ext; 3930 3931 info->width_mm = edid->width_cm * 10; 3932 info->height_mm = edid->height_cm * 10; 3933 3934 /* driver figures it out in this case */ 3935 info->bpc = 0; 3936 info->color_formats = 0; 3937 3938 if (edid->revision < 3) 3939 return; 3940 3941 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3942 return; 3943 3944 /* Get data from CEA blocks if present */ 3945 edid_ext = drm_find_cea_extension(edid); 3946 if (edid_ext) { 3947 info->cea_rev = edid_ext[1]; 3948 3949 /* The existence of a CEA block should imply RGB support */ 3950 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3951 if (edid_ext[3] & EDID_CEA_YCRCB444) 3952 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3953 if (edid_ext[3] & EDID_CEA_YCRCB422) 3954 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3955 } 3956 3957 /* HDMI deep color modes supported? Assign to info, if so */ 3958 drm_assign_hdmi_deep_color_info(edid, info, connector); 3959 3960 /* Only defined for 1.4 with digital displays */ 3961 if (edid->revision < 4) 3962 return; 3963 3964 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3965 case DRM_EDID_DIGITAL_DEPTH_6: 3966 info->bpc = 6; 3967 break; 3968 case DRM_EDID_DIGITAL_DEPTH_8: 3969 info->bpc = 8; 3970 break; 3971 case DRM_EDID_DIGITAL_DEPTH_10: 3972 info->bpc = 10; 3973 break; 3974 case DRM_EDID_DIGITAL_DEPTH_12: 3975 info->bpc = 12; 3976 break; 3977 case DRM_EDID_DIGITAL_DEPTH_14: 3978 info->bpc = 14; 3979 break; 3980 case DRM_EDID_DIGITAL_DEPTH_16: 3981 info->bpc = 16; 3982 break; 3983 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3984 default: 3985 info->bpc = 0; 3986 break; 3987 } 3988 3989 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3990 connector->name, info->bpc); 3991 3992 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3993 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3994 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3995 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3996 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3997 } 3998 3999 static int validate_displayid(u8 *displayid, int length, int idx) 4000 { 4001 int i; 4002 u8 csum = 0; 4003 struct displayid_hdr *base; 4004 4005 base = (struct displayid_hdr *)&displayid[idx]; 4006 4007 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4008 base->rev, base->bytes, base->prod_id, base->ext_count); 4009 4010 if (base->bytes + 5 > length - idx) 4011 return -EINVAL; 4012 for (i = idx; i <= base->bytes + 5; i++) { 4013 csum += displayid[i]; 4014 } 4015 if (csum) { 4016 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); 4017 return -EINVAL; 4018 } 4019 return 0; 4020 } 4021 4022 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4023 struct displayid_detailed_timings_1 *timings) 4024 { 4025 struct drm_display_mode *mode; 4026 unsigned pixel_clock = (timings->pixel_clock[0] | 4027 (timings->pixel_clock[1] << 8) | 4028 (timings->pixel_clock[2] << 16)); 4029 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4030 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4031 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4032 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4033 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4034 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4035 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4036 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4037 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4038 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4039 mode = drm_mode_create(dev); 4040 if (!mode) 4041 return NULL; 4042 4043 mode->clock = pixel_clock * 10; 4044 mode->hdisplay = hactive; 4045 mode->hsync_start = mode->hdisplay + hsync; 4046 mode->hsync_end = mode->hsync_start + hsync_width; 4047 mode->htotal = mode->hdisplay + hblank; 4048 4049 mode->vdisplay = vactive; 4050 mode->vsync_start = mode->vdisplay + vsync; 4051 mode->vsync_end = mode->vsync_start + vsync_width; 4052 mode->vtotal = mode->vdisplay + vblank; 4053 4054 mode->flags = 0; 4055 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4056 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4057 mode->type = DRM_MODE_TYPE_DRIVER; 4058 4059 if (timings->flags & 0x80) 4060 mode->type |= DRM_MODE_TYPE_PREFERRED; 4061 mode->vrefresh = drm_mode_vrefresh(mode); 4062 drm_mode_set_name(mode); 4063 4064 return mode; 4065 } 4066 4067 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4068 struct displayid_block *block) 4069 { 4070 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4071 int i; 4072 int num_timings; 4073 struct drm_display_mode *newmode; 4074 int num_modes = 0; 4075 /* blocks must be multiple of 20 bytes length */ 4076 if (block->num_bytes % 20) 4077 return 0; 4078 4079 num_timings = block->num_bytes / 20; 4080 for (i = 0; i < num_timings; i++) { 4081 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4082 4083 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4084 if (!newmode) 4085 continue; 4086 4087 drm_mode_probed_add(connector, newmode); 4088 num_modes++; 4089 } 4090 return num_modes; 4091 } 4092 4093 static int add_displayid_detailed_modes(struct drm_connector *connector, 4094 struct edid *edid) 4095 { 4096 u8 *displayid; 4097 int ret; 4098 int idx = 1; 4099 int length = EDID_LENGTH; 4100 struct displayid_block *block; 4101 int num_modes = 0; 4102 4103 displayid = drm_find_displayid_extension(edid); 4104 if (!displayid) 4105 return 0; 4106 4107 ret = validate_displayid(displayid, length, idx); 4108 if (ret) 4109 return 0; 4110 4111 idx += sizeof(struct displayid_hdr); 4112 while (block = (struct displayid_block *)&displayid[idx], 4113 idx + sizeof(struct displayid_block) <= length && 4114 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4115 block->num_bytes > 0) { 4116 idx += block->num_bytes + sizeof(struct displayid_block); 4117 switch (block->tag) { 4118 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4119 num_modes += add_displayid_detailed_1_modes(connector, block); 4120 break; 4121 } 4122 } 4123 return num_modes; 4124 } 4125 4126 /** 4127 * drm_add_edid_modes - add modes from EDID data, if available 4128 * @connector: connector we're probing 4129 * @edid: EDID data 4130 * 4131 * Add the specified modes to the connector's mode list. 4132 * 4133 * Return: The number of modes added or 0 if we couldn't find any. 4134 */ 4135 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4136 { 4137 int num_modes = 0; 4138 u32 quirks; 4139 4140 if (edid == NULL) { 4141 return 0; 4142 } 4143 if (!drm_edid_is_valid(edid)) { 4144 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4145 connector->name); 4146 return 0; 4147 } 4148 4149 quirks = edid_get_quirks(edid); 4150 4151 /* 4152 * EDID spec says modes should be preferred in this order: 4153 * - preferred detailed mode 4154 * - other detailed modes from base block 4155 * - detailed modes from extension blocks 4156 * - CVT 3-byte code modes 4157 * - standard timing codes 4158 * - established timing codes 4159 * - modes inferred from GTF or CVT range information 4160 * 4161 * We get this pretty much right. 4162 * 4163 * XXX order for additional mode types in extension blocks? 4164 */ 4165 num_modes += add_detailed_modes(connector, edid, quirks); 4166 num_modes += add_cvt_modes(connector, edid); 4167 num_modes += add_standard_modes(connector, edid); 4168 num_modes += add_established_modes(connector, edid); 4169 num_modes += add_cea_modes(connector, edid); 4170 num_modes += add_alternate_cea_modes(connector, edid); 4171 num_modes += add_displayid_detailed_modes(connector, edid); 4172 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4173 num_modes += add_inferred_modes(connector, edid); 4174 4175 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4176 edid_fixup_preferred(connector, quirks); 4177 4178 drm_add_display_info(edid, &connector->display_info, connector); 4179 4180 if (quirks & EDID_QUIRK_FORCE_6BPC) 4181 connector->display_info.bpc = 6; 4182 4183 if (quirks & EDID_QUIRK_FORCE_8BPC) 4184 connector->display_info.bpc = 8; 4185 4186 if (quirks & EDID_QUIRK_FORCE_12BPC) 4187 connector->display_info.bpc = 12; 4188 4189 return num_modes; 4190 } 4191 EXPORT_SYMBOL(drm_add_edid_modes); 4192 4193 /** 4194 * drm_add_modes_noedid - add modes for the connectors without EDID 4195 * @connector: connector we're probing 4196 * @hdisplay: the horizontal display limit 4197 * @vdisplay: the vertical display limit 4198 * 4199 * Add the specified modes to the connector's mode list. Only when the 4200 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4201 * 4202 * Return: The number of modes added or 0 if we couldn't find any. 4203 */ 4204 int drm_add_modes_noedid(struct drm_connector *connector, 4205 int hdisplay, int vdisplay) 4206 { 4207 int i, count, num_modes = 0; 4208 struct drm_display_mode *mode; 4209 struct drm_device *dev = connector->dev; 4210 4211 count = ARRAY_SIZE(drm_dmt_modes); 4212 if (hdisplay < 0) 4213 hdisplay = 0; 4214 if (vdisplay < 0) 4215 vdisplay = 0; 4216 4217 for (i = 0; i < count; i++) { 4218 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4219 if (hdisplay && vdisplay) { 4220 /* 4221 * Only when two are valid, they will be used to check 4222 * whether the mode should be added to the mode list of 4223 * the connector. 4224 */ 4225 if (ptr->hdisplay > hdisplay || 4226 ptr->vdisplay > vdisplay) 4227 continue; 4228 } 4229 if (drm_mode_vrefresh(ptr) > 61) 4230 continue; 4231 mode = drm_mode_duplicate(dev, ptr); 4232 if (mode) { 4233 drm_mode_probed_add(connector, mode); 4234 num_modes++; 4235 } 4236 } 4237 return num_modes; 4238 } 4239 EXPORT_SYMBOL(drm_add_modes_noedid); 4240 4241 /** 4242 * drm_set_preferred_mode - Sets the preferred mode of a connector 4243 * @connector: connector whose mode list should be processed 4244 * @hpref: horizontal resolution of preferred mode 4245 * @vpref: vertical resolution of preferred mode 4246 * 4247 * Marks a mode as preferred if it matches the resolution specified by @hpref 4248 * and @vpref. 4249 */ 4250 void drm_set_preferred_mode(struct drm_connector *connector, 4251 int hpref, int vpref) 4252 { 4253 struct drm_display_mode *mode; 4254 4255 list_for_each_entry(mode, &connector->probed_modes, head) { 4256 if (mode->hdisplay == hpref && 4257 mode->vdisplay == vpref) 4258 mode->type |= DRM_MODE_TYPE_PREFERRED; 4259 } 4260 } 4261 EXPORT_SYMBOL(drm_set_preferred_mode); 4262 4263 /** 4264 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4265 * data from a DRM display mode 4266 * @frame: HDMI AVI infoframe 4267 * @mode: DRM display mode 4268 * 4269 * Return: 0 on success or a negative error code on failure. 4270 */ 4271 int 4272 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4273 const struct drm_display_mode *mode) 4274 { 4275 int err; 4276 4277 if (!frame || !mode) 4278 return -EINVAL; 4279 4280 err = hdmi_avi_infoframe_init(frame); 4281 if (err < 0) 4282 return err; 4283 4284 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4285 frame->pixel_repeat = 1; 4286 4287 frame->video_code = drm_match_cea_mode(mode); 4288 4289 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4290 4291 /* 4292 * Populate picture aspect ratio from either 4293 * user input (if specified) or from the CEA mode list. 4294 */ 4295 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4296 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4297 frame->picture_aspect = mode->picture_aspect_ratio; 4298 else if (frame->video_code > 0) 4299 frame->picture_aspect = drm_get_cea_aspect_ratio( 4300 frame->video_code); 4301 4302 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4303 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4304 4305 return 0; 4306 } 4307 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4308 4309 static enum hdmi_3d_structure 4310 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4311 { 4312 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4313 4314 switch (layout) { 4315 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4316 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4317 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4318 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4319 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4320 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4321 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4322 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4323 case DRM_MODE_FLAG_3D_L_DEPTH: 4324 return HDMI_3D_STRUCTURE_L_DEPTH; 4325 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4326 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4327 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4328 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4329 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4330 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4331 default: 4332 return HDMI_3D_STRUCTURE_INVALID; 4333 } 4334 } 4335 4336 /** 4337 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4338 * data from a DRM display mode 4339 * @frame: HDMI vendor infoframe 4340 * @mode: DRM display mode 4341 * 4342 * Note that there's is a need to send HDMI vendor infoframes only when using a 4343 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4344 * function will return -EINVAL, error that can be safely ignored. 4345 * 4346 * Return: 0 on success or a negative error code on failure. 4347 */ 4348 int 4349 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4350 const struct drm_display_mode *mode) 4351 { 4352 int err; 4353 u32 s3d_flags; 4354 u8 vic; 4355 4356 if (!frame || !mode) 4357 return -EINVAL; 4358 4359 vic = drm_match_hdmi_mode(mode); 4360 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4361 4362 if (!vic && !s3d_flags) 4363 return -EINVAL; 4364 4365 if (vic && s3d_flags) 4366 return -EINVAL; 4367 4368 err = hdmi_vendor_infoframe_init(frame); 4369 if (err < 0) 4370 return err; 4371 4372 if (vic) 4373 frame->vic = vic; 4374 else 4375 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4376 4377 return 0; 4378 } 4379 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4380 4381 static int drm_parse_tiled_block(struct drm_connector *connector, 4382 struct displayid_block *block) 4383 { 4384 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4385 u16 w, h; 4386 u8 tile_v_loc, tile_h_loc; 4387 u8 num_v_tile, num_h_tile; 4388 struct drm_tile_group *tg; 4389 4390 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4391 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4392 4393 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4394 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4395 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4396 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4397 4398 connector->has_tile = true; 4399 if (tile->tile_cap & 0x80) 4400 connector->tile_is_single_monitor = true; 4401 4402 connector->num_h_tile = num_h_tile + 1; 4403 connector->num_v_tile = num_v_tile + 1; 4404 connector->tile_h_loc = tile_h_loc; 4405 connector->tile_v_loc = tile_v_loc; 4406 connector->tile_h_size = w + 1; 4407 connector->tile_v_size = h + 1; 4408 4409 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4410 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4411 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4412 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4413 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4414 4415 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4416 if (!tg) { 4417 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4418 } 4419 if (!tg) 4420 return -ENOMEM; 4421 4422 if (connector->tile_group != tg) { 4423 /* if we haven't got a pointer, 4424 take the reference, drop ref to old tile group */ 4425 if (connector->tile_group) { 4426 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4427 } 4428 connector->tile_group = tg; 4429 } else 4430 /* if same tile group, then release the ref we just took. */ 4431 drm_mode_put_tile_group(connector->dev, tg); 4432 return 0; 4433 } 4434 4435 static int drm_parse_display_id(struct drm_connector *connector, 4436 u8 *displayid, int length, 4437 bool is_edid_extension) 4438 { 4439 /* if this is an EDID extension the first byte will be 0x70 */ 4440 int idx = 0; 4441 struct displayid_block *block; 4442 int ret; 4443 4444 if (is_edid_extension) 4445 idx = 1; 4446 4447 ret = validate_displayid(displayid, length, idx); 4448 if (ret) 4449 return ret; 4450 4451 idx += sizeof(struct displayid_hdr); 4452 while (block = (struct displayid_block *)&displayid[idx], 4453 idx + sizeof(struct displayid_block) <= length && 4454 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4455 block->num_bytes > 0) { 4456 idx += block->num_bytes + sizeof(struct displayid_block); 4457 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 4458 block->tag, block->rev, block->num_bytes); 4459 4460 switch (block->tag) { 4461 case DATA_BLOCK_TILED_DISPLAY: 4462 ret = drm_parse_tiled_block(connector, block); 4463 if (ret) 4464 return ret; 4465 break; 4466 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4467 /* handled in mode gathering code. */ 4468 break; 4469 default: 4470 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 4471 break; 4472 } 4473 } 4474 return 0; 4475 } 4476 4477 static void drm_get_displayid(struct drm_connector *connector, 4478 struct edid *edid) 4479 { 4480 void *displayid = NULL; 4481 int ret; 4482 connector->has_tile = false; 4483 displayid = drm_find_displayid_extension(edid); 4484 if (!displayid) { 4485 /* drop reference to any tile group we had */ 4486 goto out_drop_ref; 4487 } 4488 4489 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4490 if (ret < 0) 4491 goto out_drop_ref; 4492 if (!connector->has_tile) 4493 goto out_drop_ref; 4494 return; 4495 out_drop_ref: 4496 if (connector->tile_group) { 4497 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4498 connector->tile_group = NULL; 4499 } 4500 return; 4501 } 4502