1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include "opt_drm.h" 31 32 #include <linux/kernel.h> 33 #include <linux/hdmi.h> 34 #include <linux/i2c.h> 35 #include <linux/module.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drmP.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_displayid.h> 40 #include <linux/string.h> 41 42 #define version_greater(edid, maj, min) \ 43 (((edid)->version > (maj)) || \ 44 ((edid)->version == (maj) && (edid)->revision > (min))) 45 46 #define EDID_EST_TIMINGS 16 47 #define EDID_STD_TIMINGS 8 48 #define EDID_DETAILED_TIMINGS 4 49 50 /* 51 * EDID blocks out in the wild have a variety of bugs, try to collect 52 * them here (note that userspace may work around broken monitors first, 53 * but fixes should make their way here so that the kernel "just works" 54 * on as many displays as possible). 55 */ 56 57 /* First detailed mode wrong, use largest 60Hz mode */ 58 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 59 /* Reported 135MHz pixel clock is too high, needs adjustment */ 60 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 61 /* Prefer the largest mode at 75 Hz */ 62 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 63 /* Detail timing is in cm not mm */ 64 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 65 /* Detailed timing descriptors have bogus size values, so just take the 66 * maximum size and use that. 67 */ 68 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 69 /* Monitor forgot to set the first detailed is preferred bit. */ 70 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 71 /* use +hsync +vsync for detailed mode */ 72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 73 /* Force reduced-blanking timings for detailed modes */ 74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 75 /* Force 8bpc */ 76 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 77 /* Force 12bpc */ 78 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 79 /* Force 6bpc */ 80 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 81 82 struct detailed_mode_closure { 83 struct drm_connector *connector; 84 struct edid *edid; 85 bool preferred; 86 u32 quirks; 87 int modes; 88 }; 89 90 #define LEVEL_DMT 0 91 #define LEVEL_GTF 1 92 #define LEVEL_GTF2 2 93 #define LEVEL_CVT 3 94 95 static struct edid_quirk { 96 char vendor[4]; 97 int product_id; 98 u32 quirks; 99 } edid_quirk_list[] = { 100 /* Acer AL1706 */ 101 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 102 /* Acer F51 */ 103 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 104 /* Unknown Acer */ 105 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 106 107 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 108 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 109 110 /* Belinea 10 15 55 */ 111 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 112 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 113 114 /* Envision Peripherals, Inc. EN-7100e */ 115 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 116 /* Envision EN2028 */ 117 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 118 119 /* Funai Electronics PM36B */ 120 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 121 EDID_QUIRK_DETAILED_IN_CM }, 122 123 /* LG Philips LCD LP154W01-A5 */ 124 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 125 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 126 127 /* Philips 107p5 CRT */ 128 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 129 130 /* Proview AY765C */ 131 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 132 133 /* Samsung SyncMaster 205BW. Note: irony */ 134 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 135 /* Samsung SyncMaster 22[5-6]BW */ 136 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 137 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 138 139 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 140 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 141 142 /* ViewSonic VA2026w */ 143 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 144 145 /* Medion MD 30217 PG */ 146 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 147 148 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 149 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 150 }; 151 152 /* 153 * Autogenerated from the DMT spec. 154 * This table is copied from xfree86/modes/xf86EdidModes.c. 155 */ 156 static const struct drm_display_mode drm_dmt_modes[] = { 157 /* 0x01 - 640x350@85Hz */ 158 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 159 736, 832, 0, 350, 382, 385, 445, 0, 160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 161 /* 0x02 - 640x400@85Hz */ 162 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 163 736, 832, 0, 400, 401, 404, 445, 0, 164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 165 /* 0x03 - 720x400@85Hz */ 166 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 167 828, 936, 0, 400, 401, 404, 446, 0, 168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 169 /* 0x04 - 640x480@60Hz */ 170 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 171 752, 800, 0, 480, 490, 492, 525, 0, 172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 173 /* 0x05 - 640x480@72Hz */ 174 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 175 704, 832, 0, 480, 489, 492, 520, 0, 176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 177 /* 0x06 - 640x480@75Hz */ 178 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 179 720, 840, 0, 480, 481, 484, 500, 0, 180 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 181 /* 0x07 - 640x480@85Hz */ 182 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 183 752, 832, 0, 480, 481, 484, 509, 0, 184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 185 /* 0x08 - 800x600@56Hz */ 186 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 187 896, 1024, 0, 600, 601, 603, 625, 0, 188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 189 /* 0x09 - 800x600@60Hz */ 190 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 191 968, 1056, 0, 600, 601, 605, 628, 0, 192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 193 /* 0x0a - 800x600@72Hz */ 194 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 195 976, 1040, 0, 600, 637, 643, 666, 0, 196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 197 /* 0x0b - 800x600@75Hz */ 198 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 199 896, 1056, 0, 600, 601, 604, 625, 0, 200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 201 /* 0x0c - 800x600@85Hz */ 202 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 203 896, 1048, 0, 600, 601, 604, 631, 0, 204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 205 /* 0x0d - 800x600@120Hz RB */ 206 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 207 880, 960, 0, 600, 603, 607, 636, 0, 208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 209 /* 0x0e - 848x480@60Hz */ 210 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 211 976, 1088, 0, 480, 486, 494, 517, 0, 212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 213 /* 0x0f - 1024x768@43Hz, interlace */ 214 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 215 1208, 1264, 0, 768, 768, 776, 817, 0, 216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 217 DRM_MODE_FLAG_INTERLACE) }, 218 /* 0x10 - 1024x768@60Hz */ 219 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 220 1184, 1344, 0, 768, 771, 777, 806, 0, 221 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 222 /* 0x11 - 1024x768@70Hz */ 223 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 224 1184, 1328, 0, 768, 771, 777, 806, 0, 225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 226 /* 0x12 - 1024x768@75Hz */ 227 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 228 1136, 1312, 0, 768, 769, 772, 800, 0, 229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 230 /* 0x13 - 1024x768@85Hz */ 231 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 232 1168, 1376, 0, 768, 769, 772, 808, 0, 233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 234 /* 0x14 - 1024x768@120Hz RB */ 235 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 236 1104, 1184, 0, 768, 771, 775, 813, 0, 237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 238 /* 0x15 - 1152x864@75Hz */ 239 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 240 1344, 1600, 0, 864, 865, 868, 900, 0, 241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 242 /* 0x55 - 1280x720@60Hz */ 243 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 244 1430, 1650, 0, 720, 725, 730, 750, 0, 245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 246 /* 0x16 - 1280x768@60Hz RB */ 247 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 248 1360, 1440, 0, 768, 771, 778, 790, 0, 249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 250 /* 0x17 - 1280x768@60Hz */ 251 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 252 1472, 1664, 0, 768, 771, 778, 798, 0, 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 254 /* 0x18 - 1280x768@75Hz */ 255 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 256 1488, 1696, 0, 768, 771, 778, 805, 0, 257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 258 /* 0x19 - 1280x768@85Hz */ 259 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 260 1496, 1712, 0, 768, 771, 778, 809, 0, 261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 262 /* 0x1a - 1280x768@120Hz RB */ 263 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 264 1360, 1440, 0, 768, 771, 778, 813, 0, 265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 266 /* 0x1b - 1280x800@60Hz RB */ 267 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 268 1360, 1440, 0, 800, 803, 809, 823, 0, 269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 270 /* 0x1c - 1280x800@60Hz */ 271 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 272 1480, 1680, 0, 800, 803, 809, 831, 0, 273 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 274 /* 0x1d - 1280x800@75Hz */ 275 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 276 1488, 1696, 0, 800, 803, 809, 838, 0, 277 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 278 /* 0x1e - 1280x800@85Hz */ 279 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 280 1496, 1712, 0, 800, 803, 809, 843, 0, 281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 282 /* 0x1f - 1280x800@120Hz RB */ 283 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 284 1360, 1440, 0, 800, 803, 809, 847, 0, 285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 286 /* 0x20 - 1280x960@60Hz */ 287 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 288 1488, 1800, 0, 960, 961, 964, 1000, 0, 289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 290 /* 0x21 - 1280x960@85Hz */ 291 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 292 1504, 1728, 0, 960, 961, 964, 1011, 0, 293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 294 /* 0x22 - 1280x960@120Hz RB */ 295 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 296 1360, 1440, 0, 960, 963, 967, 1017, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 298 /* 0x23 - 1280x1024@60Hz */ 299 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 300 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x24 - 1280x1024@75Hz */ 303 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 304 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 306 /* 0x25 - 1280x1024@85Hz */ 307 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 308 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x26 - 1280x1024@120Hz RB */ 311 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 312 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 314 /* 0x27 - 1360x768@60Hz */ 315 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 316 1536, 1792, 0, 768, 771, 777, 795, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x28 - 1360x768@120Hz RB */ 319 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 320 1440, 1520, 0, 768, 771, 776, 813, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 322 /* 0x51 - 1366x768@60Hz */ 323 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 324 1579, 1792, 0, 768, 771, 774, 798, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x56 - 1366x768@60Hz */ 327 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 328 1436, 1500, 0, 768, 769, 772, 800, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x29 - 1400x1050@60Hz RB */ 331 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 332 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x2a - 1400x1050@60Hz */ 335 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 336 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x2b - 1400x1050@75Hz */ 339 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 340 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x2c - 1400x1050@85Hz */ 343 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 344 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x2d - 1400x1050@120Hz RB */ 347 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 348 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x2e - 1440x900@60Hz RB */ 351 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 352 1520, 1600, 0, 900, 903, 909, 926, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x2f - 1440x900@60Hz */ 355 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 356 1672, 1904, 0, 900, 903, 909, 934, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x30 - 1440x900@75Hz */ 359 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 360 1688, 1936, 0, 900, 903, 909, 942, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x31 - 1440x900@85Hz */ 363 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 364 1696, 1952, 0, 900, 903, 909, 948, 0, 365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x32 - 1440x900@120Hz RB */ 367 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 368 1520, 1600, 0, 900, 903, 909, 953, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 370 /* 0x53 - 1600x900@60Hz */ 371 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 372 1704, 1800, 0, 900, 901, 904, 1000, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x33 - 1600x1200@60Hz */ 375 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 376 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x34 - 1600x1200@65Hz */ 379 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 380 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x35 - 1600x1200@70Hz */ 383 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 384 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x36 - 1600x1200@75Hz */ 387 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 388 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x37 - 1600x1200@85Hz */ 391 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 392 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x38 - 1600x1200@120Hz RB */ 395 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 396 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x39 - 1680x1050@60Hz RB */ 399 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 400 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x3a - 1680x1050@60Hz */ 403 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 404 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x3b - 1680x1050@75Hz */ 407 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 408 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x3c - 1680x1050@85Hz */ 411 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 412 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x3d - 1680x1050@120Hz RB */ 415 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 416 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x3e - 1792x1344@60Hz */ 419 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 420 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x3f - 1792x1344@75Hz */ 423 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 424 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x40 - 1792x1344@120Hz RB */ 427 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 428 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 430 /* 0x41 - 1856x1392@60Hz */ 431 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 432 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x42 - 1856x1392@75Hz */ 435 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 436 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x43 - 1856x1392@120Hz RB */ 439 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 440 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 442 /* 0x52 - 1920x1080@60Hz */ 443 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 444 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 446 /* 0x44 - 1920x1200@60Hz RB */ 447 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 448 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 450 /* 0x45 - 1920x1200@60Hz */ 451 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 452 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x46 - 1920x1200@75Hz */ 455 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 456 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x47 - 1920x1200@85Hz */ 459 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 460 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x48 - 1920x1200@120Hz RB */ 463 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 464 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x49 - 1920x1440@60Hz */ 467 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 468 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x4a - 1920x1440@75Hz */ 471 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 472 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x4b - 1920x1440@120Hz RB */ 475 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 476 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 478 /* 0x54 - 2048x1152@60Hz */ 479 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 480 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x4c - 2560x1600@60Hz RB */ 483 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 484 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x4d - 2560x1600@60Hz */ 487 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 488 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x4e - 2560x1600@75Hz */ 491 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 492 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x4f - 2560x1600@85Hz */ 495 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 496 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x50 - 2560x1600@120Hz RB */ 499 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 500 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 502 /* 0x57 - 4096x2160@60Hz RB */ 503 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 504 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 506 /* 0x58 - 4096x2160@59.94Hz RB */ 507 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 508 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 }; 511 512 /* 513 * These more or less come from the DMT spec. The 720x400 modes are 514 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 515 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 516 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 517 * mode. 518 * 519 * The DMT modes have been fact-checked; the rest are mild guesses. 520 */ 521 static const struct drm_display_mode edid_est_modes[] = { 522 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 523 968, 1056, 0, 600, 601, 605, 628, 0, 524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 525 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 526 896, 1024, 0, 600, 601, 603, 625, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 528 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 529 720, 840, 0, 480, 481, 484, 500, 0, 530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 531 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 532 704, 832, 0, 480, 489, 492, 520, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 534 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 535 768, 864, 0, 480, 483, 486, 525, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 537 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 538 752, 800, 0, 480, 490, 492, 525, 0, 539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 540 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 541 846, 900, 0, 400, 421, 423, 449, 0, 542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 543 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 544 846, 900, 0, 400, 412, 414, 449, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 546 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 547 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 549 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 550 1136, 1312, 0, 768, 769, 772, 800, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 552 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 553 1184, 1328, 0, 768, 771, 777, 806, 0, 554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 555 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 556 1184, 1344, 0, 768, 771, 777, 806, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 558 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 559 1208, 1264, 0, 768, 768, 776, 817, 0, 560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 561 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 562 928, 1152, 0, 624, 625, 628, 667, 0, 563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 564 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 565 896, 1056, 0, 600, 601, 604, 625, 0, 566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 567 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 568 976, 1040, 0, 600, 637, 643, 666, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 570 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 571 1344, 1600, 0, 864, 865, 868, 900, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 573 }; 574 575 struct minimode { 576 short w; 577 short h; 578 short r; 579 short rb; 580 }; 581 582 static const struct minimode est3_modes[] = { 583 /* byte 6 */ 584 { 640, 350, 85, 0 }, 585 { 640, 400, 85, 0 }, 586 { 720, 400, 85, 0 }, 587 { 640, 480, 85, 0 }, 588 { 848, 480, 60, 0 }, 589 { 800, 600, 85, 0 }, 590 { 1024, 768, 85, 0 }, 591 { 1152, 864, 75, 0 }, 592 /* byte 7 */ 593 { 1280, 768, 60, 1 }, 594 { 1280, 768, 60, 0 }, 595 { 1280, 768, 75, 0 }, 596 { 1280, 768, 85, 0 }, 597 { 1280, 960, 60, 0 }, 598 { 1280, 960, 85, 0 }, 599 { 1280, 1024, 60, 0 }, 600 { 1280, 1024, 85, 0 }, 601 /* byte 8 */ 602 { 1360, 768, 60, 0 }, 603 { 1440, 900, 60, 1 }, 604 { 1440, 900, 60, 0 }, 605 { 1440, 900, 75, 0 }, 606 { 1440, 900, 85, 0 }, 607 { 1400, 1050, 60, 1 }, 608 { 1400, 1050, 60, 0 }, 609 { 1400, 1050, 75, 0 }, 610 /* byte 9 */ 611 { 1400, 1050, 85, 0 }, 612 { 1680, 1050, 60, 1 }, 613 { 1680, 1050, 60, 0 }, 614 { 1680, 1050, 75, 0 }, 615 { 1680, 1050, 85, 0 }, 616 { 1600, 1200, 60, 0 }, 617 { 1600, 1200, 65, 0 }, 618 { 1600, 1200, 70, 0 }, 619 /* byte 10 */ 620 { 1600, 1200, 75, 0 }, 621 { 1600, 1200, 85, 0 }, 622 { 1792, 1344, 60, 0 }, 623 { 1792, 1344, 75, 0 }, 624 { 1856, 1392, 60, 0 }, 625 { 1856, 1392, 75, 0 }, 626 { 1920, 1200, 60, 1 }, 627 { 1920, 1200, 60, 0 }, 628 /* byte 11 */ 629 { 1920, 1200, 75, 0 }, 630 { 1920, 1200, 85, 0 }, 631 { 1920, 1440, 60, 0 }, 632 { 1920, 1440, 75, 0 }, 633 }; 634 635 static const struct minimode extra_modes[] = { 636 { 1024, 576, 60, 0 }, 637 { 1366, 768, 60, 0 }, 638 { 1600, 900, 60, 0 }, 639 { 1680, 945, 60, 0 }, 640 { 1920, 1080, 60, 0 }, 641 { 2048, 1152, 60, 0 }, 642 { 2048, 1536, 60, 0 }, 643 }; 644 645 /* 646 * Probably taken from CEA-861 spec. 647 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 648 * 649 * Index using the VIC. 650 */ 651 static const struct drm_display_mode edid_cea_modes[] = { 652 /* 0 - dummy, VICs start at 1 */ 653 { }, 654 /* 1 - 640x480@60Hz */ 655 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 656 752, 800, 0, 480, 490, 492, 525, 0, 657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 658 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 659 /* 2 - 720x480@60Hz */ 660 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 661 798, 858, 0, 480, 489, 495, 525, 0, 662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 663 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 664 /* 3 - 720x480@60Hz */ 665 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 666 798, 858, 0, 480, 489, 495, 525, 0, 667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 669 /* 4 - 1280x720@60Hz */ 670 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 671 1430, 1650, 0, 720, 725, 730, 750, 0, 672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 674 /* 5 - 1920x1080i@60Hz */ 675 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 676 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 678 DRM_MODE_FLAG_INTERLACE), 679 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 680 /* 6 - 720(1440)x480i@60Hz */ 681 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 682 801, 858, 0, 480, 488, 494, 525, 0, 683 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 684 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 686 /* 7 - 720(1440)x480i@60Hz */ 687 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 688 801, 858, 0, 480, 488, 494, 525, 0, 689 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 690 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 692 /* 8 - 720(1440)x240@60Hz */ 693 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 694 801, 858, 0, 240, 244, 247, 262, 0, 695 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 696 DRM_MODE_FLAG_DBLCLK), 697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 698 /* 9 - 720(1440)x240@60Hz */ 699 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 700 801, 858, 0, 240, 244, 247, 262, 0, 701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 702 DRM_MODE_FLAG_DBLCLK), 703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 704 /* 10 - 2880x480i@60Hz */ 705 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 706 3204, 3432, 0, 480, 488, 494, 525, 0, 707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 708 DRM_MODE_FLAG_INTERLACE), 709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 710 /* 11 - 2880x480i@60Hz */ 711 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 712 3204, 3432, 0, 480, 488, 494, 525, 0, 713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 714 DRM_MODE_FLAG_INTERLACE), 715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 716 /* 12 - 2880x240@60Hz */ 717 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 718 3204, 3432, 0, 240, 244, 247, 262, 0, 719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 721 /* 13 - 2880x240@60Hz */ 722 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 723 3204, 3432, 0, 240, 244, 247, 262, 0, 724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 726 /* 14 - 1440x480@60Hz */ 727 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 728 1596, 1716, 0, 480, 489, 495, 525, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 731 /* 15 - 1440x480@60Hz */ 732 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 733 1596, 1716, 0, 480, 489, 495, 525, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 736 /* 16 - 1920x1080@60Hz */ 737 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 738 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 17 - 720x576@50Hz */ 742 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 743 796, 864, 0, 576, 581, 586, 625, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 745 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 746 /* 18 - 720x576@50Hz */ 747 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 748 796, 864, 0, 576, 581, 586, 625, 0, 749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 750 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 751 /* 19 - 1280x720@50Hz */ 752 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 753 1760, 1980, 0, 720, 725, 730, 750, 0, 754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 755 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 20 - 1920x1080i@50Hz */ 757 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 758 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 760 DRM_MODE_FLAG_INTERLACE), 761 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 762 /* 21 - 720(1440)x576i@50Hz */ 763 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 764 795, 864, 0, 576, 580, 586, 625, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 766 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 768 /* 22 - 720(1440)x576i@50Hz */ 769 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 770 795, 864, 0, 576, 580, 586, 625, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 772 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 774 /* 23 - 720(1440)x288@50Hz */ 775 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 776 795, 864, 0, 288, 290, 293, 312, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 778 DRM_MODE_FLAG_DBLCLK), 779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 780 /* 24 - 720(1440)x288@50Hz */ 781 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 782 795, 864, 0, 288, 290, 293, 312, 0, 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 784 DRM_MODE_FLAG_DBLCLK), 785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 786 /* 25 - 2880x576i@50Hz */ 787 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 788 3180, 3456, 0, 576, 580, 586, 625, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 790 DRM_MODE_FLAG_INTERLACE), 791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 792 /* 26 - 2880x576i@50Hz */ 793 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 794 3180, 3456, 0, 576, 580, 586, 625, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 796 DRM_MODE_FLAG_INTERLACE), 797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 798 /* 27 - 2880x288@50Hz */ 799 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 800 3180, 3456, 0, 288, 290, 293, 312, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 803 /* 28 - 2880x288@50Hz */ 804 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 805 3180, 3456, 0, 288, 290, 293, 312, 0, 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 808 /* 29 - 1440x576@50Hz */ 809 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 810 1592, 1728, 0, 576, 581, 586, 625, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 813 /* 30 - 1440x576@50Hz */ 814 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 815 1592, 1728, 0, 576, 581, 586, 625, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 818 /* 31 - 1920x1080@50Hz */ 819 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 820 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 32 - 1920x1080@24Hz */ 824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 825 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 827 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 33 - 1920x1080@25Hz */ 829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 830 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 832 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 34 - 1920x1080@30Hz */ 834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 835 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 837 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 35 - 2880x480@60Hz */ 839 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 840 3192, 3432, 0, 480, 489, 495, 525, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 842 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 843 /* 36 - 2880x480@60Hz */ 844 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 845 3192, 3432, 0, 480, 489, 495, 525, 0, 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 847 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 848 /* 37 - 2880x576@50Hz */ 849 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 850 3184, 3456, 0, 576, 581, 586, 625, 0, 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 853 /* 38 - 2880x576@50Hz */ 854 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 855 3184, 3456, 0, 576, 581, 586, 625, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 857 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 39 - 1920x1080i@50Hz */ 859 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 860 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_INTERLACE), 863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 40 - 1920x1080i@100Hz */ 865 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 866 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 868 DRM_MODE_FLAG_INTERLACE), 869 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 41 - 1280x720@100Hz */ 871 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 872 1760, 1980, 0, 720, 725, 730, 750, 0, 873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 874 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 875 /* 42 - 720x576@100Hz */ 876 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 877 796, 864, 0, 576, 581, 586, 625, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 880 /* 43 - 720x576@100Hz */ 881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 882 796, 864, 0, 576, 581, 586, 625, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 44 - 720(1440)x576i@100Hz */ 886 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 887 795, 864, 0, 576, 580, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 889 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 890 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 891 /* 45 - 720(1440)x576i@100Hz */ 892 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 893 795, 864, 0, 576, 580, 586, 625, 0, 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 895 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 896 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 897 /* 46 - 1920x1080i@120Hz */ 898 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 899 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 901 DRM_MODE_FLAG_INTERLACE), 902 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 47 - 1280x720@120Hz */ 904 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 905 1430, 1650, 0, 720, 725, 730, 750, 0, 906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 907 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 908 /* 48 - 720x480@120Hz */ 909 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 910 798, 858, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 913 /* 49 - 720x480@120Hz */ 914 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 915 798, 858, 0, 480, 489, 495, 525, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 918 /* 50 - 720(1440)x480i@120Hz */ 919 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 920 801, 858, 0, 480, 488, 494, 525, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 922 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 923 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 924 /* 51 - 720(1440)x480i@120Hz */ 925 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 926 801, 858, 0, 480, 488, 494, 525, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 928 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 929 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 930 /* 52 - 720x576@200Hz */ 931 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 932 796, 864, 0, 576, 581, 586, 625, 0, 933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 934 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 935 /* 53 - 720x576@200Hz */ 936 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 937 796, 864, 0, 576, 581, 586, 625, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 939 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 54 - 720(1440)x576i@200Hz */ 941 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 942 795, 864, 0, 576, 580, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 944 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 945 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 946 /* 55 - 720(1440)x576i@200Hz */ 947 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 948 795, 864, 0, 576, 580, 586, 625, 0, 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 950 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 951 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 952 /* 56 - 720x480@240Hz */ 953 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 954 798, 858, 0, 480, 489, 495, 525, 0, 955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 956 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 957 /* 57 - 720x480@240Hz */ 958 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 959 798, 858, 0, 480, 489, 495, 525, 0, 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 961 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 58 - 720(1440)x480i@240 */ 963 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 964 801, 858, 0, 480, 488, 494, 525, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 966 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 967 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 968 /* 59 - 720(1440)x480i@240 */ 969 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 970 801, 858, 0, 480, 488, 494, 525, 0, 971 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 972 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 973 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 974 /* 60 - 1280x720@24Hz */ 975 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 976 3080, 3300, 0, 720, 725, 730, 750, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 978 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 979 /* 61 - 1280x720@25Hz */ 980 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 981 3740, 3960, 0, 720, 725, 730, 750, 0, 982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 983 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 62 - 1280x720@30Hz */ 985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 986 3080, 3300, 0, 720, 725, 730, 750, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 988 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 63 - 1920x1080@120Hz */ 990 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 991 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 64 - 1920x1080@100Hz */ 995 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 996 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 998 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 }; 1000 1001 /* 1002 * HDMI 1.4 4k modes. Index using the VIC. 1003 */ 1004 static const struct drm_display_mode edid_4k_modes[] = { 1005 /* 0 - dummy, VICs start at 1 */ 1006 { }, 1007 /* 1 - 3840x2160@30Hz */ 1008 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1009 3840, 4016, 4104, 4400, 0, 1010 2160, 2168, 2178, 2250, 0, 1011 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1012 .vrefresh = 30, }, 1013 /* 2 - 3840x2160@25Hz */ 1014 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1015 3840, 4896, 4984, 5280, 0, 1016 2160, 2168, 2178, 2250, 0, 1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1018 .vrefresh = 25, }, 1019 /* 3 - 3840x2160@24Hz */ 1020 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1021 3840, 5116, 5204, 5500, 0, 1022 2160, 2168, 2178, 2250, 0, 1023 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1024 .vrefresh = 24, }, 1025 /* 4 - 4096x2160@24Hz (SMPTE) */ 1026 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1027 4096, 5116, 5204, 5500, 0, 1028 2160, 2168, 2178, 2250, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1030 .vrefresh = 24, }, 1031 }; 1032 1033 /*** DDC fetch and block validation ***/ 1034 1035 static const u8 edid_header[] = { 1036 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1037 }; 1038 1039 /** 1040 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1041 * @raw_edid: pointer to raw base EDID block 1042 * 1043 * Sanity check the header of the base EDID block. 1044 * 1045 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1046 */ 1047 int drm_edid_header_is_valid(const u8 *raw_edid) 1048 { 1049 int i, score = 0; 1050 1051 for (i = 0; i < sizeof(edid_header); i++) 1052 if (raw_edid[i] == edid_header[i]) 1053 score++; 1054 1055 return score; 1056 } 1057 EXPORT_SYMBOL(drm_edid_header_is_valid); 1058 1059 static int edid_fixup __read_mostly = 6; 1060 module_param_named(edid_fixup, edid_fixup, int, 0400); 1061 MODULE_PARM_DESC(edid_fixup, 1062 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1063 1064 static void drm_get_displayid(struct drm_connector *connector, 1065 struct edid *edid); 1066 1067 static int drm_edid_block_checksum(const u8 *raw_edid) 1068 { 1069 int i; 1070 u8 csum = 0; 1071 for (i = 0; i < EDID_LENGTH; i++) 1072 csum += raw_edid[i]; 1073 1074 return csum; 1075 } 1076 1077 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1078 { 1079 if (memchr_inv(in_edid, 0, length)) 1080 return false; 1081 1082 return true; 1083 } 1084 1085 /** 1086 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1087 * @raw_edid: pointer to raw EDID block 1088 * @block: type of block to validate (0 for base, extension otherwise) 1089 * @print_bad_edid: if true, dump bad EDID blocks to the console 1090 * @edid_corrupt: if true, the header or checksum is invalid 1091 * 1092 * Validate a base or extension EDID block and optionally dump bad blocks to 1093 * the console. 1094 * 1095 * Return: True if the block is valid, false otherwise. 1096 */ 1097 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1098 bool *edid_corrupt) 1099 { 1100 u8 csum; 1101 struct edid *edid = (struct edid *)raw_edid; 1102 1103 if (WARN_ON(!raw_edid)) 1104 return false; 1105 1106 if (edid_fixup > 8 || edid_fixup < 0) 1107 edid_fixup = 6; 1108 1109 if (block == 0) { 1110 int score = drm_edid_header_is_valid(raw_edid); 1111 if (score == 8) { 1112 if (edid_corrupt) 1113 *edid_corrupt = false; 1114 } else if (score >= edid_fixup) { 1115 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1116 * The corrupt flag needs to be set here otherwise, the 1117 * fix-up code here will correct the problem, the 1118 * checksum is correct and the test fails 1119 */ 1120 if (edid_corrupt) 1121 *edid_corrupt = true; 1122 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1123 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1124 } else { 1125 if (edid_corrupt) 1126 *edid_corrupt = true; 1127 goto bad; 1128 } 1129 } 1130 1131 csum = drm_edid_block_checksum(raw_edid); 1132 if (csum) { 1133 if (print_bad_edid) { 1134 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1135 } 1136 1137 if (edid_corrupt) 1138 *edid_corrupt = true; 1139 1140 /* allow CEA to slide through, switches mangle this */ 1141 if (raw_edid[0] != 0x02) 1142 goto bad; 1143 } 1144 1145 /* per-block-type checks */ 1146 switch (raw_edid[0]) { 1147 case 0: /* base */ 1148 if (edid->version != 1) { 1149 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1150 goto bad; 1151 } 1152 1153 if (edid->revision > 4) 1154 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1155 break; 1156 1157 default: 1158 break; 1159 } 1160 1161 return true; 1162 1163 bad: 1164 if (print_bad_edid) { 1165 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1166 printk(KERN_ERR "EDID block is all zeroes\n"); 1167 } else { 1168 printk(KERN_ERR "Raw EDID:\n"); 1169 print_hex_dump(KERN_NOTICE, 1170 " \t", DUMP_PREFIX_NONE, 16, 1, 1171 raw_edid, EDID_LENGTH, false); 1172 } 1173 } 1174 return false; 1175 } 1176 EXPORT_SYMBOL(drm_edid_block_valid); 1177 1178 /** 1179 * drm_edid_is_valid - sanity check EDID data 1180 * @edid: EDID data 1181 * 1182 * Sanity-check an entire EDID record (including extensions) 1183 * 1184 * Return: True if the EDID data is valid, false otherwise. 1185 */ 1186 bool drm_edid_is_valid(struct edid *edid) 1187 { 1188 int i; 1189 u8 *raw = (u8 *)edid; 1190 1191 if (!edid) 1192 return false; 1193 1194 for (i = 0; i <= edid->extensions; i++) 1195 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1196 return false; 1197 1198 return true; 1199 } 1200 EXPORT_SYMBOL(drm_edid_is_valid); 1201 1202 #define DDC_SEGMENT_ADDR 0x30 1203 /** 1204 * drm_do_probe_ddc_edid() - get EDID information via I2C 1205 * @data: I2C device adapter 1206 * @buf: EDID data buffer to be filled 1207 * @block: 128 byte EDID block to start fetching from 1208 * @len: EDID data buffer length to fetch 1209 * 1210 * Try to fetch EDID information by calling I2C driver functions. 1211 * 1212 * Return: 0 on success or -1 on failure. 1213 */ 1214 static int 1215 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1216 { 1217 struct i2c_adapter *adapter = data; 1218 unsigned char start = block * EDID_LENGTH; 1219 unsigned char segment = block >> 1; 1220 unsigned char xfers = segment ? 3 : 2; 1221 int ret, retries = 5; 1222 1223 /* 1224 * The core I2C driver will automatically retry the transfer if the 1225 * adapter reports EAGAIN. However, we find that bit-banging transfers 1226 * are susceptible to errors under a heavily loaded machine and 1227 * generate spurious NAKs and timeouts. Retrying the transfer 1228 * of the individual block a few times seems to overcome this. 1229 */ 1230 do { 1231 struct i2c_msg msgs[] = { 1232 { 1233 .addr = DDC_SEGMENT_ADDR, 1234 .flags = 0, 1235 .len = 1, 1236 .buf = &segment, 1237 }, { 1238 .addr = DDC_ADDR, 1239 .flags = 0, 1240 .len = 1, 1241 .buf = &start, 1242 }, { 1243 .addr = DDC_ADDR, 1244 .flags = I2C_M_RD, 1245 .len = len, 1246 .buf = buf, 1247 } 1248 }; 1249 1250 /* 1251 * Avoid sending the segment addr to not upset non-compliant 1252 * DDC monitors. 1253 */ 1254 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1255 1256 if (ret == -ENXIO) { 1257 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1258 adapter->name); 1259 break; 1260 } 1261 } while (ret != xfers && --retries); 1262 1263 return ret == xfers ? 0 : -1; 1264 } 1265 1266 /** 1267 * drm_do_get_edid - get EDID data using a custom EDID block read function 1268 * @connector: connector we're probing 1269 * @get_edid_block: EDID block read function 1270 * @data: private data passed to the block read function 1271 * 1272 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1273 * exposes a different interface to read EDID blocks this function can be used 1274 * to get EDID data using a custom block read function. 1275 * 1276 * As in the general case the DDC bus is accessible by the kernel at the I2C 1277 * level, drivers must make all reasonable efforts to expose it as an I2C 1278 * adapter and use drm_get_edid() instead of abusing this function. 1279 * 1280 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1281 */ 1282 struct edid *drm_do_get_edid(struct drm_connector *connector, 1283 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1284 size_t len), 1285 void *data) 1286 { 1287 int i, j = 0, valid_extensions = 0; 1288 u8 *block, *new; 1289 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1290 1291 if ((block = kmalloc(EDID_LENGTH, M_DRM, M_WAITOK)) == NULL) 1292 return NULL; 1293 1294 /* base block fetch */ 1295 for (i = 0; i < 4; i++) { 1296 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1297 goto out; 1298 if (drm_edid_block_valid(block, 0, print_bad_edid, 1299 &connector->edid_corrupt)) 1300 break; 1301 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1302 connector->null_edid_counter++; 1303 goto carp; 1304 } 1305 } 1306 if (i == 4) 1307 goto carp; 1308 1309 /* if there's no extensions, we're done */ 1310 if (block[0x7e] == 0) 1311 return (struct edid *)block; 1312 1313 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1314 if (!new) 1315 goto out; 1316 block = new; 1317 1318 for (j = 1; j <= block[0x7e]; j++) { 1319 for (i = 0; i < 4; i++) { 1320 if (get_edid_block(data, 1321 block + (valid_extensions + 1) * EDID_LENGTH, 1322 j, EDID_LENGTH)) 1323 goto out; 1324 if (drm_edid_block_valid(block + (valid_extensions + 1) 1325 * EDID_LENGTH, j, 1326 print_bad_edid, 1327 NULL)) { 1328 valid_extensions++; 1329 break; 1330 } 1331 } 1332 1333 if (i == 4 && print_bad_edid) { 1334 dev_warn(connector->dev->dev, 1335 "%s: Ignoring invalid EDID block %d.\n", 1336 connector->name, j); 1337 1338 connector->bad_edid_counter++; 1339 } 1340 } 1341 1342 if (valid_extensions != block[0x7e]) { 1343 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1344 block[0x7e] = valid_extensions; 1345 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1346 if (!new) 1347 goto out; 1348 block = new; 1349 } 1350 1351 return (struct edid *)block; 1352 1353 carp: 1354 if (print_bad_edid) { 1355 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1356 connector->name, j); 1357 } 1358 connector->bad_edid_counter++; 1359 1360 out: 1361 kfree(block); 1362 return NULL; 1363 } 1364 1365 /** 1366 * drm_probe_ddc() - probe DDC presence 1367 * @adapter: I2C adapter to probe 1368 * 1369 * Return: True on success, false on failure. 1370 */ 1371 bool 1372 drm_probe_ddc(struct i2c_adapter *adapter) 1373 { 1374 unsigned char out; 1375 1376 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1377 } 1378 EXPORT_SYMBOL(drm_probe_ddc); 1379 1380 /** 1381 * drm_get_edid - get EDID data, if available 1382 * @connector: connector we're probing 1383 * @adapter: I2C adapter to use for DDC 1384 * 1385 * Poke the given I2C channel to grab EDID data if possible. If found, 1386 * attach it to the connector. 1387 * 1388 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1389 */ 1390 struct edid *drm_get_edid(struct drm_connector *connector, 1391 struct i2c_adapter *adapter) 1392 { 1393 struct edid *edid; 1394 1395 if (!drm_probe_ddc(adapter)) 1396 return NULL; 1397 1398 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1399 if (edid) 1400 drm_get_displayid(connector, edid); 1401 return edid; 1402 } 1403 EXPORT_SYMBOL(drm_get_edid); 1404 1405 /** 1406 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1407 * @connector: connector we're probing 1408 * @adapter: I2C adapter to use for DDC 1409 * 1410 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1411 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1412 * switch DDC to the GPU which is retrieving EDID. 1413 * 1414 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1415 */ 1416 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1417 struct i2c_adapter *adapter) 1418 { 1419 struct pci_dev *pdev = connector->dev->pdev; 1420 struct edid *edid; 1421 1422 vga_switcheroo_lock_ddc(pdev); 1423 edid = drm_get_edid(connector, adapter); 1424 vga_switcheroo_unlock_ddc(pdev); 1425 1426 return edid; 1427 } 1428 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1429 1430 /** 1431 * drm_edid_duplicate - duplicate an EDID and the extensions 1432 * @edid: EDID to duplicate 1433 * 1434 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1435 */ 1436 struct edid *drm_edid_duplicate(const struct edid *edid) 1437 { 1438 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1439 } 1440 EXPORT_SYMBOL(drm_edid_duplicate); 1441 1442 /*** EDID parsing ***/ 1443 1444 /** 1445 * edid_vendor - match a string against EDID's obfuscated vendor field 1446 * @edid: EDID to match 1447 * @vendor: vendor string 1448 * 1449 * Returns true if @vendor is in @edid, false otherwise 1450 */ 1451 static bool edid_vendor(struct edid *edid, char *vendor) 1452 { 1453 char edid_vendor[3]; 1454 1455 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1456 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1457 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1458 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1459 1460 return !strncmp(edid_vendor, vendor, 3); 1461 } 1462 1463 /** 1464 * edid_get_quirks - return quirk flags for a given EDID 1465 * @edid: EDID to process 1466 * 1467 * This tells subsequent routines what fixes they need to apply. 1468 */ 1469 static u32 edid_get_quirks(struct edid *edid) 1470 { 1471 struct edid_quirk *quirk; 1472 int i; 1473 1474 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1475 quirk = &edid_quirk_list[i]; 1476 1477 if (edid_vendor(edid, quirk->vendor) && 1478 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1479 return quirk->quirks; 1480 } 1481 1482 return 0; 1483 } 1484 1485 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1486 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1487 1488 /** 1489 * edid_fixup_preferred - set preferred modes based on quirk list 1490 * @connector: has mode list to fix up 1491 * @quirks: quirks list 1492 * 1493 * Walk the mode list for @connector, clearing the preferred status 1494 * on existing modes and setting it anew for the right mode ala @quirks. 1495 */ 1496 static void edid_fixup_preferred(struct drm_connector *connector, 1497 u32 quirks) 1498 { 1499 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1500 int target_refresh = 0; 1501 int cur_vrefresh, preferred_vrefresh; 1502 1503 if (list_empty(&connector->probed_modes)) 1504 return; 1505 1506 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1507 target_refresh = 60; 1508 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1509 target_refresh = 75; 1510 1511 preferred_mode = list_first_entry(&connector->probed_modes, 1512 struct drm_display_mode, head); 1513 1514 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1515 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1516 1517 if (cur_mode == preferred_mode) 1518 continue; 1519 1520 /* Largest mode is preferred */ 1521 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1522 preferred_mode = cur_mode; 1523 1524 cur_vrefresh = cur_mode->vrefresh ? 1525 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1526 preferred_vrefresh = preferred_mode->vrefresh ? 1527 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1528 /* At a given size, try to get closest to target refresh */ 1529 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1530 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1531 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1532 preferred_mode = cur_mode; 1533 } 1534 } 1535 1536 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1537 } 1538 1539 static bool 1540 mode_is_rb(const struct drm_display_mode *mode) 1541 { 1542 return (mode->htotal - mode->hdisplay == 160) && 1543 (mode->hsync_end - mode->hdisplay == 80) && 1544 (mode->hsync_end - mode->hsync_start == 32) && 1545 (mode->vsync_start - mode->vdisplay == 3); 1546 } 1547 1548 /* 1549 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1550 * @dev: Device to duplicate against 1551 * @hsize: Mode width 1552 * @vsize: Mode height 1553 * @fresh: Mode refresh rate 1554 * @rb: Mode reduced-blanking-ness 1555 * 1556 * Walk the DMT mode list looking for a match for the given parameters. 1557 * 1558 * Return: A newly allocated copy of the mode, or NULL if not found. 1559 */ 1560 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1561 int hsize, int vsize, int fresh, 1562 bool rb) 1563 { 1564 int i; 1565 1566 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1567 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1568 if (hsize != ptr->hdisplay) 1569 continue; 1570 if (vsize != ptr->vdisplay) 1571 continue; 1572 if (fresh != drm_mode_vrefresh(ptr)) 1573 continue; 1574 if (rb != mode_is_rb(ptr)) 1575 continue; 1576 1577 return drm_mode_duplicate(dev, ptr); 1578 } 1579 1580 return NULL; 1581 } 1582 EXPORT_SYMBOL(drm_mode_find_dmt); 1583 1584 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1585 1586 static void 1587 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1588 { 1589 int i, n = 0; 1590 u8 d = ext[0x02]; 1591 u8 *det_base = ext + d; 1592 1593 n = (127 - d) / 18; 1594 for (i = 0; i < n; i++) 1595 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1596 } 1597 1598 static void 1599 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1600 { 1601 unsigned int i, n = min((int)ext[0x02], 6); 1602 u8 *det_base = ext + 5; 1603 1604 if (ext[0x01] != 1) 1605 return; /* unknown version */ 1606 1607 for (i = 0; i < n; i++) 1608 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1609 } 1610 1611 static void 1612 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1613 { 1614 int i; 1615 struct edid *edid = (struct edid *)raw_edid; 1616 1617 if (edid == NULL) 1618 return; 1619 1620 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1621 cb(&(edid->detailed_timings[i]), closure); 1622 1623 for (i = 1; i <= raw_edid[0x7e]; i++) { 1624 u8 *ext = raw_edid + (i * EDID_LENGTH); 1625 switch (*ext) { 1626 case CEA_EXT: 1627 cea_for_each_detailed_block(ext, cb, closure); 1628 break; 1629 case VTB_EXT: 1630 vtb_for_each_detailed_block(ext, cb, closure); 1631 break; 1632 default: 1633 break; 1634 } 1635 } 1636 } 1637 1638 static void 1639 is_rb(struct detailed_timing *t, void *data) 1640 { 1641 u8 *r = (u8 *)t; 1642 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1643 if (r[15] & 0x10) 1644 *(bool *)data = true; 1645 } 1646 1647 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1648 static bool 1649 drm_monitor_supports_rb(struct edid *edid) 1650 { 1651 if (edid->revision >= 4) { 1652 bool ret = false; 1653 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1654 return ret; 1655 } 1656 1657 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1658 } 1659 1660 static void 1661 find_gtf2(struct detailed_timing *t, void *data) 1662 { 1663 u8 *r = (u8 *)t; 1664 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1665 *(u8 **)data = r; 1666 } 1667 1668 /* Secondary GTF curve kicks in above some break frequency */ 1669 static int 1670 drm_gtf2_hbreak(struct edid *edid) 1671 { 1672 u8 *r = NULL; 1673 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1674 return r ? (r[12] * 2) : 0; 1675 } 1676 1677 static int 1678 drm_gtf2_2c(struct edid *edid) 1679 { 1680 u8 *r = NULL; 1681 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1682 return r ? r[13] : 0; 1683 } 1684 1685 static int 1686 drm_gtf2_m(struct edid *edid) 1687 { 1688 u8 *r = NULL; 1689 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1690 return r ? (r[15] << 8) + r[14] : 0; 1691 } 1692 1693 static int 1694 drm_gtf2_k(struct edid *edid) 1695 { 1696 u8 *r = NULL; 1697 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1698 return r ? r[16] : 0; 1699 } 1700 1701 static int 1702 drm_gtf2_2j(struct edid *edid) 1703 { 1704 u8 *r = NULL; 1705 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1706 return r ? r[17] : 0; 1707 } 1708 1709 /** 1710 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1711 * @edid: EDID block to scan 1712 */ 1713 static int standard_timing_level(struct edid *edid) 1714 { 1715 if (edid->revision >= 2) { 1716 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1717 return LEVEL_CVT; 1718 if (drm_gtf2_hbreak(edid)) 1719 return LEVEL_GTF2; 1720 return LEVEL_GTF; 1721 } 1722 return LEVEL_DMT; 1723 } 1724 1725 /* 1726 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1727 * monitors fill with ascii space (0x20) instead. 1728 */ 1729 static int 1730 bad_std_timing(u8 a, u8 b) 1731 { 1732 return (a == 0x00 && b == 0x00) || 1733 (a == 0x01 && b == 0x01) || 1734 (a == 0x20 && b == 0x20); 1735 } 1736 1737 /** 1738 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1739 * @connector: connector of for the EDID block 1740 * @edid: EDID block to scan 1741 * @t: standard timing params 1742 * 1743 * Take the standard timing params (in this case width, aspect, and refresh) 1744 * and convert them into a real mode using CVT/GTF/DMT. 1745 */ 1746 static struct drm_display_mode * 1747 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1748 struct std_timing *t) 1749 { 1750 struct drm_device *dev = connector->dev; 1751 struct drm_display_mode *m, *mode = NULL; 1752 int hsize, vsize; 1753 int vrefresh_rate; 1754 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1755 >> EDID_TIMING_ASPECT_SHIFT; 1756 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1757 >> EDID_TIMING_VFREQ_SHIFT; 1758 int timing_level = standard_timing_level(edid); 1759 1760 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1761 return NULL; 1762 1763 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1764 hsize = t->hsize * 8 + 248; 1765 /* vrefresh_rate = vfreq + 60 */ 1766 vrefresh_rate = vfreq + 60; 1767 /* the vdisplay is calculated based on the aspect ratio */ 1768 if (aspect_ratio == 0) { 1769 if (edid->revision < 3) 1770 vsize = hsize; 1771 else 1772 vsize = (hsize * 10) / 16; 1773 } else if (aspect_ratio == 1) 1774 vsize = (hsize * 3) / 4; 1775 else if (aspect_ratio == 2) 1776 vsize = (hsize * 4) / 5; 1777 else 1778 vsize = (hsize * 9) / 16; 1779 1780 /* HDTV hack, part 1 */ 1781 if (vrefresh_rate == 60 && 1782 ((hsize == 1360 && vsize == 765) || 1783 (hsize == 1368 && vsize == 769))) { 1784 hsize = 1366; 1785 vsize = 768; 1786 } 1787 1788 /* 1789 * If this connector already has a mode for this size and refresh 1790 * rate (because it came from detailed or CVT info), use that 1791 * instead. This way we don't have to guess at interlace or 1792 * reduced blanking. 1793 */ 1794 list_for_each_entry(m, &connector->probed_modes, head) 1795 if (m->hdisplay == hsize && m->vdisplay == vsize && 1796 drm_mode_vrefresh(m) == vrefresh_rate) 1797 return NULL; 1798 1799 /* HDTV hack, part 2 */ 1800 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1801 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1802 false); 1803 mode->hdisplay = 1366; 1804 mode->hsync_start = mode->hsync_start - 1; 1805 mode->hsync_end = mode->hsync_end - 1; 1806 return mode; 1807 } 1808 1809 /* check whether it can be found in default mode table */ 1810 if (drm_monitor_supports_rb(edid)) { 1811 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1812 true); 1813 if (mode) 1814 return mode; 1815 } 1816 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1817 if (mode) 1818 return mode; 1819 1820 /* okay, generate it */ 1821 switch (timing_level) { 1822 case LEVEL_DMT: 1823 break; 1824 case LEVEL_GTF: 1825 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1826 break; 1827 case LEVEL_GTF2: 1828 /* 1829 * This is potentially wrong if there's ever a monitor with 1830 * more than one ranges section, each claiming a different 1831 * secondary GTF curve. Please don't do that. 1832 */ 1833 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1834 if (!mode) 1835 return NULL; 1836 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1837 drm_mode_destroy(dev, mode); 1838 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1839 vrefresh_rate, 0, 0, 1840 drm_gtf2_m(edid), 1841 drm_gtf2_2c(edid), 1842 drm_gtf2_k(edid), 1843 drm_gtf2_2j(edid)); 1844 } 1845 break; 1846 case LEVEL_CVT: 1847 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1848 false); 1849 break; 1850 } 1851 return mode; 1852 } 1853 1854 /* 1855 * EDID is delightfully ambiguous about how interlaced modes are to be 1856 * encoded. Our internal representation is of frame height, but some 1857 * HDTV detailed timings are encoded as field height. 1858 * 1859 * The format list here is from CEA, in frame size. Technically we 1860 * should be checking refresh rate too. Whatever. 1861 */ 1862 static void 1863 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1864 struct detailed_pixel_timing *pt) 1865 { 1866 int i; 1867 static const struct { 1868 int w, h; 1869 } cea_interlaced[] = { 1870 { 1920, 1080 }, 1871 { 720, 480 }, 1872 { 1440, 480 }, 1873 { 2880, 480 }, 1874 { 720, 576 }, 1875 { 1440, 576 }, 1876 { 2880, 576 }, 1877 }; 1878 1879 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1880 return; 1881 1882 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1883 if ((mode->hdisplay == cea_interlaced[i].w) && 1884 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1885 mode->vdisplay *= 2; 1886 mode->vsync_start *= 2; 1887 mode->vsync_end *= 2; 1888 mode->vtotal *= 2; 1889 mode->vtotal |= 1; 1890 } 1891 } 1892 1893 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1894 } 1895 1896 /** 1897 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1898 * @dev: DRM device (needed to create new mode) 1899 * @edid: EDID block 1900 * @timing: EDID detailed timing info 1901 * @quirks: quirks to apply 1902 * 1903 * An EDID detailed timing block contains enough info for us to create and 1904 * return a new struct drm_display_mode. 1905 */ 1906 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1907 struct edid *edid, 1908 struct detailed_timing *timing, 1909 u32 quirks) 1910 { 1911 struct drm_display_mode *mode; 1912 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1913 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1914 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1915 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1916 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1917 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1918 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1919 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1920 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1921 1922 /* ignore tiny modes */ 1923 if (hactive < 64 || vactive < 64) 1924 return NULL; 1925 1926 if (pt->misc & DRM_EDID_PT_STEREO) { 1927 DRM_DEBUG_KMS("stereo mode not supported\n"); 1928 return NULL; 1929 } 1930 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1931 DRM_DEBUG_KMS("composite sync not supported\n"); 1932 } 1933 1934 /* it is incorrect if hsync/vsync width is zero */ 1935 if (!hsync_pulse_width || !vsync_pulse_width) { 1936 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1937 "Wrong Hsync/Vsync pulse width\n"); 1938 return NULL; 1939 } 1940 1941 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1942 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1943 if (!mode) 1944 return NULL; 1945 1946 goto set_size; 1947 } 1948 1949 mode = drm_mode_create(dev); 1950 if (!mode) 1951 return NULL; 1952 1953 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1954 timing->pixel_clock = cpu_to_le16(1088); 1955 1956 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1957 1958 mode->hdisplay = hactive; 1959 mode->hsync_start = mode->hdisplay + hsync_offset; 1960 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1961 mode->htotal = mode->hdisplay + hblank; 1962 1963 mode->vdisplay = vactive; 1964 mode->vsync_start = mode->vdisplay + vsync_offset; 1965 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1966 mode->vtotal = mode->vdisplay + vblank; 1967 1968 /* Some EDIDs have bogus h/vtotal values */ 1969 if (mode->hsync_end > mode->htotal) 1970 mode->htotal = mode->hsync_end + 1; 1971 if (mode->vsync_end > mode->vtotal) 1972 mode->vtotal = mode->vsync_end + 1; 1973 1974 drm_mode_do_interlace_quirk(mode, pt); 1975 1976 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1977 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1978 } 1979 1980 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1981 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1982 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1983 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1984 1985 set_size: 1986 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1987 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1988 1989 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1990 mode->width_mm *= 10; 1991 mode->height_mm *= 10; 1992 } 1993 1994 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1995 mode->width_mm = edid->width_cm * 10; 1996 mode->height_mm = edid->height_cm * 10; 1997 } 1998 1999 mode->type = DRM_MODE_TYPE_DRIVER; 2000 mode->vrefresh = drm_mode_vrefresh(mode); 2001 drm_mode_set_name(mode); 2002 2003 return mode; 2004 } 2005 2006 static bool 2007 mode_in_hsync_range(const struct drm_display_mode *mode, 2008 struct edid *edid, u8 *t) 2009 { 2010 int hsync, hmin, hmax; 2011 2012 hmin = t[7]; 2013 if (edid->revision >= 4) 2014 hmin += ((t[4] & 0x04) ? 255 : 0); 2015 hmax = t[8]; 2016 if (edid->revision >= 4) 2017 hmax += ((t[4] & 0x08) ? 255 : 0); 2018 hsync = drm_mode_hsync(mode); 2019 2020 return (hsync <= hmax && hsync >= hmin); 2021 } 2022 2023 static bool 2024 mode_in_vsync_range(const struct drm_display_mode *mode, 2025 struct edid *edid, u8 *t) 2026 { 2027 int vsync, vmin, vmax; 2028 2029 vmin = t[5]; 2030 if (edid->revision >= 4) 2031 vmin += ((t[4] & 0x01) ? 255 : 0); 2032 vmax = t[6]; 2033 if (edid->revision >= 4) 2034 vmax += ((t[4] & 0x02) ? 255 : 0); 2035 vsync = drm_mode_vrefresh(mode); 2036 2037 return (vsync <= vmax && vsync >= vmin); 2038 } 2039 2040 static u32 2041 range_pixel_clock(struct edid *edid, u8 *t) 2042 { 2043 /* unspecified */ 2044 if (t[9] == 0 || t[9] == 255) 2045 return 0; 2046 2047 /* 1.4 with CVT support gives us real precision, yay */ 2048 if (edid->revision >= 4 && t[10] == 0x04) 2049 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2050 2051 /* 1.3 is pathetic, so fuzz up a bit */ 2052 return t[9] * 10000 + 5001; 2053 } 2054 2055 static bool 2056 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2057 struct detailed_timing *timing) 2058 { 2059 u32 max_clock; 2060 u8 *t = (u8 *)timing; 2061 2062 if (!mode_in_hsync_range(mode, edid, t)) 2063 return false; 2064 2065 if (!mode_in_vsync_range(mode, edid, t)) 2066 return false; 2067 2068 if ((max_clock = range_pixel_clock(edid, t))) 2069 if (mode->clock > max_clock) 2070 return false; 2071 2072 /* 1.4 max horizontal check */ 2073 if (edid->revision >= 4 && t[10] == 0x04) 2074 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2075 return false; 2076 2077 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2078 return false; 2079 2080 return true; 2081 } 2082 2083 static bool valid_inferred_mode(const struct drm_connector *connector, 2084 const struct drm_display_mode *mode) 2085 { 2086 struct drm_display_mode *m; 2087 bool ok = false; 2088 2089 list_for_each_entry(m, &connector->probed_modes, head) { 2090 if (mode->hdisplay == m->hdisplay && 2091 mode->vdisplay == m->vdisplay && 2092 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2093 return false; /* duplicated */ 2094 if (mode->hdisplay <= m->hdisplay && 2095 mode->vdisplay <= m->vdisplay) 2096 ok = true; 2097 } 2098 return ok; 2099 } 2100 2101 static int 2102 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2103 struct detailed_timing *timing) 2104 { 2105 int i, modes = 0; 2106 struct drm_display_mode *newmode; 2107 struct drm_device *dev = connector->dev; 2108 2109 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2110 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2111 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2112 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2113 if (newmode) { 2114 drm_mode_probed_add(connector, newmode); 2115 modes++; 2116 } 2117 } 2118 } 2119 2120 return modes; 2121 } 2122 2123 /* fix up 1366x768 mode from 1368x768; 2124 * GFT/CVT can't express 1366 width which isn't dividable by 8 2125 */ 2126 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2127 { 2128 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2129 mode->hdisplay = 1366; 2130 mode->hsync_start--; 2131 mode->hsync_end--; 2132 drm_mode_set_name(mode); 2133 } 2134 } 2135 2136 static int 2137 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2138 struct detailed_timing *timing) 2139 { 2140 int i, modes = 0; 2141 struct drm_display_mode *newmode; 2142 struct drm_device *dev = connector->dev; 2143 2144 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2145 const struct minimode *m = &extra_modes[i]; 2146 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2147 if (!newmode) 2148 return modes; 2149 2150 fixup_mode_1366x768(newmode); 2151 if (!mode_in_range(newmode, edid, timing) || 2152 !valid_inferred_mode(connector, newmode)) { 2153 drm_mode_destroy(dev, newmode); 2154 continue; 2155 } 2156 2157 drm_mode_probed_add(connector, newmode); 2158 modes++; 2159 } 2160 2161 return modes; 2162 } 2163 2164 static int 2165 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2166 struct detailed_timing *timing) 2167 { 2168 int i, modes = 0; 2169 struct drm_display_mode *newmode; 2170 struct drm_device *dev = connector->dev; 2171 bool rb = drm_monitor_supports_rb(edid); 2172 2173 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2174 const struct minimode *m = &extra_modes[i]; 2175 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2176 if (!newmode) 2177 return modes; 2178 2179 fixup_mode_1366x768(newmode); 2180 if (!mode_in_range(newmode, edid, timing) || 2181 !valid_inferred_mode(connector, newmode)) { 2182 drm_mode_destroy(dev, newmode); 2183 continue; 2184 } 2185 2186 drm_mode_probed_add(connector, newmode); 2187 modes++; 2188 } 2189 2190 return modes; 2191 } 2192 2193 static void 2194 do_inferred_modes(struct detailed_timing *timing, void *c) 2195 { 2196 struct detailed_mode_closure *closure = c; 2197 struct detailed_non_pixel *data = &timing->data.other_data; 2198 struct detailed_data_monitor_range *range = &data->data.range; 2199 2200 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2201 return; 2202 2203 closure->modes += drm_dmt_modes_for_range(closure->connector, 2204 closure->edid, 2205 timing); 2206 2207 if (!version_greater(closure->edid, 1, 1)) 2208 return; /* GTF not defined yet */ 2209 2210 switch (range->flags) { 2211 case 0x02: /* secondary gtf, XXX could do more */ 2212 case 0x00: /* default gtf */ 2213 closure->modes += drm_gtf_modes_for_range(closure->connector, 2214 closure->edid, 2215 timing); 2216 break; 2217 case 0x04: /* cvt, only in 1.4+ */ 2218 if (!version_greater(closure->edid, 1, 3)) 2219 break; 2220 2221 closure->modes += drm_cvt_modes_for_range(closure->connector, 2222 closure->edid, 2223 timing); 2224 break; 2225 case 0x01: /* just the ranges, no formula */ 2226 default: 2227 break; 2228 } 2229 } 2230 2231 static int 2232 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2233 { 2234 struct detailed_mode_closure closure = { 2235 .connector = connector, 2236 .edid = edid, 2237 }; 2238 2239 if (version_greater(edid, 1, 0)) 2240 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2241 &closure); 2242 2243 return closure.modes; 2244 } 2245 2246 static int 2247 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2248 { 2249 int i, j, m, modes = 0; 2250 struct drm_display_mode *mode; 2251 u8 *est = ((u8 *)timing) + 6; 2252 2253 for (i = 0; i < 6; i++) { 2254 for (j = 7; j >= 0; j--) { 2255 m = (i * 8) + (7 - j); 2256 if (m >= ARRAY_SIZE(est3_modes)) 2257 break; 2258 if (est[i] & (1 << j)) { 2259 mode = drm_mode_find_dmt(connector->dev, 2260 est3_modes[m].w, 2261 est3_modes[m].h, 2262 est3_modes[m].r, 2263 est3_modes[m].rb); 2264 if (mode) { 2265 drm_mode_probed_add(connector, mode); 2266 modes++; 2267 } 2268 } 2269 } 2270 } 2271 2272 return modes; 2273 } 2274 2275 static void 2276 do_established_modes(struct detailed_timing *timing, void *c) 2277 { 2278 struct detailed_mode_closure *closure = c; 2279 struct detailed_non_pixel *data = &timing->data.other_data; 2280 2281 if (data->type == EDID_DETAIL_EST_TIMINGS) 2282 closure->modes += drm_est3_modes(closure->connector, timing); 2283 } 2284 2285 /** 2286 * add_established_modes - get est. modes from EDID and add them 2287 * @connector: connector to add mode(s) to 2288 * @edid: EDID block to scan 2289 * 2290 * Each EDID block contains a bitmap of the supported "established modes" list 2291 * (defined above). Tease them out and add them to the global modes list. 2292 */ 2293 static int 2294 add_established_modes(struct drm_connector *connector, struct edid *edid) 2295 { 2296 struct drm_device *dev = connector->dev; 2297 unsigned long est_bits = edid->established_timings.t1 | 2298 (edid->established_timings.t2 << 8) | 2299 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2300 int i, modes = 0; 2301 struct detailed_mode_closure closure = { 2302 .connector = connector, 2303 .edid = edid, 2304 }; 2305 2306 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2307 if (est_bits & (1<<i)) { 2308 struct drm_display_mode *newmode; 2309 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2310 if (newmode) { 2311 drm_mode_probed_add(connector, newmode); 2312 modes++; 2313 } 2314 } 2315 } 2316 2317 if (version_greater(edid, 1, 0)) 2318 drm_for_each_detailed_block((u8 *)edid, 2319 do_established_modes, &closure); 2320 2321 return modes + closure.modes; 2322 } 2323 2324 static void 2325 do_standard_modes(struct detailed_timing *timing, void *c) 2326 { 2327 struct detailed_mode_closure *closure = c; 2328 struct detailed_non_pixel *data = &timing->data.other_data; 2329 struct drm_connector *connector = closure->connector; 2330 struct edid *edid = closure->edid; 2331 2332 if (data->type == EDID_DETAIL_STD_MODES) { 2333 int i; 2334 for (i = 0; i < 6; i++) { 2335 struct std_timing *std; 2336 struct drm_display_mode *newmode; 2337 2338 std = &data->data.timings[i]; 2339 newmode = drm_mode_std(connector, edid, std); 2340 if (newmode) { 2341 drm_mode_probed_add(connector, newmode); 2342 closure->modes++; 2343 } 2344 } 2345 } 2346 } 2347 2348 /** 2349 * add_standard_modes - get std. modes from EDID and add them 2350 * @connector: connector to add mode(s) to 2351 * @edid: EDID block to scan 2352 * 2353 * Standard modes can be calculated using the appropriate standard (DMT, 2354 * GTF or CVT. Grab them from @edid and add them to the list. 2355 */ 2356 static int 2357 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2358 { 2359 int i, modes = 0; 2360 struct detailed_mode_closure closure = { 2361 .connector = connector, 2362 .edid = edid, 2363 }; 2364 2365 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2366 struct drm_display_mode *newmode; 2367 2368 newmode = drm_mode_std(connector, edid, 2369 &edid->standard_timings[i]); 2370 if (newmode) { 2371 drm_mode_probed_add(connector, newmode); 2372 modes++; 2373 } 2374 } 2375 2376 if (version_greater(edid, 1, 0)) 2377 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2378 &closure); 2379 2380 /* XXX should also look for standard codes in VTB blocks */ 2381 2382 return modes + closure.modes; 2383 } 2384 2385 static int drm_cvt_modes(struct drm_connector *connector, 2386 struct detailed_timing *timing) 2387 { 2388 int i, j, modes = 0; 2389 struct drm_display_mode *newmode; 2390 struct drm_device *dev = connector->dev; 2391 struct cvt_timing *cvt; 2392 const int rates[] = { 60, 85, 75, 60, 50 }; 2393 const u8 empty[3] = { 0, 0, 0 }; 2394 2395 for (i = 0; i < 4; i++) { 2396 int width = 0, height; 2397 cvt = &(timing->data.other_data.data.cvt[i]); 2398 2399 if (!memcmp(cvt->code, empty, 3)) 2400 continue; 2401 2402 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2403 switch (cvt->code[1] & 0x0c) { 2404 case 0x00: 2405 width = height * 4 / 3; 2406 break; 2407 case 0x04: 2408 width = height * 16 / 9; 2409 break; 2410 case 0x08: 2411 width = height * 16 / 10; 2412 break; 2413 case 0x0c: 2414 width = height * 15 / 9; 2415 break; 2416 } 2417 2418 for (j = 1; j < 5; j++) { 2419 if (cvt->code[2] & (1 << j)) { 2420 newmode = drm_cvt_mode(dev, width, height, 2421 rates[j], j == 0, 2422 false, false); 2423 if (newmode) { 2424 drm_mode_probed_add(connector, newmode); 2425 modes++; 2426 } 2427 } 2428 } 2429 } 2430 2431 return modes; 2432 } 2433 2434 static void 2435 do_cvt_mode(struct detailed_timing *timing, void *c) 2436 { 2437 struct detailed_mode_closure *closure = c; 2438 struct detailed_non_pixel *data = &timing->data.other_data; 2439 2440 if (data->type == EDID_DETAIL_CVT_3BYTE) 2441 closure->modes += drm_cvt_modes(closure->connector, timing); 2442 } 2443 2444 static int 2445 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2446 { 2447 struct detailed_mode_closure closure = { 2448 .connector = connector, 2449 .edid = edid, 2450 }; 2451 2452 if (version_greater(edid, 1, 2)) 2453 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2454 2455 /* XXX should also look for CVT codes in VTB blocks */ 2456 2457 return closure.modes; 2458 } 2459 2460 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2461 2462 static void 2463 do_detailed_mode(struct detailed_timing *timing, void *c) 2464 { 2465 struct detailed_mode_closure *closure = c; 2466 struct drm_display_mode *newmode; 2467 2468 if (timing->pixel_clock) { 2469 newmode = drm_mode_detailed(closure->connector->dev, 2470 closure->edid, timing, 2471 closure->quirks); 2472 if (!newmode) 2473 return; 2474 2475 if (closure->preferred) 2476 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2477 2478 /* 2479 * Detailed modes are limited to 10kHz pixel clock resolution, 2480 * so fix up anything that looks like CEA/HDMI mode, but the clock 2481 * is just slightly off. 2482 */ 2483 fixup_detailed_cea_mode_clock(newmode); 2484 2485 drm_mode_probed_add(closure->connector, newmode); 2486 closure->modes++; 2487 closure->preferred = 0; 2488 } 2489 } 2490 2491 /* 2492 * add_detailed_modes - Add modes from detailed timings 2493 * @connector: attached connector 2494 * @edid: EDID block to scan 2495 * @quirks: quirks to apply 2496 */ 2497 static int 2498 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2499 u32 quirks) 2500 { 2501 struct detailed_mode_closure closure = { 2502 .connector = connector, 2503 .edid = edid, 2504 .preferred = 1, 2505 .quirks = quirks, 2506 }; 2507 2508 if (closure.preferred && !version_greater(edid, 1, 3)) 2509 closure.preferred = 2510 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2511 2512 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2513 2514 return closure.modes; 2515 } 2516 2517 #define AUDIO_BLOCK 0x01 2518 #define VIDEO_BLOCK 0x02 2519 #define VENDOR_BLOCK 0x03 2520 #define SPEAKER_BLOCK 0x04 2521 #define VIDEO_CAPABILITY_BLOCK 0x07 2522 #define EDID_BASIC_AUDIO (1 << 6) 2523 #define EDID_CEA_YCRCB444 (1 << 5) 2524 #define EDID_CEA_YCRCB422 (1 << 4) 2525 #define EDID_CEA_VCDB_QS (1 << 6) 2526 2527 /* 2528 * Search EDID for CEA extension block. 2529 */ 2530 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2531 { 2532 u8 *edid_ext = NULL; 2533 int i; 2534 2535 /* No EDID or EDID extensions */ 2536 if (edid == NULL || edid->extensions == 0) 2537 return NULL; 2538 2539 /* Find CEA extension */ 2540 for (i = 0; i < edid->extensions; i++) { 2541 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2542 if (edid_ext[0] == ext_id) 2543 break; 2544 } 2545 2546 if (i == edid->extensions) 2547 return NULL; 2548 2549 return edid_ext; 2550 } 2551 2552 static u8 *drm_find_cea_extension(struct edid *edid) 2553 { 2554 return drm_find_edid_extension(edid, CEA_EXT); 2555 } 2556 2557 static u8 *drm_find_displayid_extension(struct edid *edid) 2558 { 2559 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2560 } 2561 2562 /* 2563 * Calculate the alternate clock for the CEA mode 2564 * (60Hz vs. 59.94Hz etc.) 2565 */ 2566 static unsigned int 2567 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2568 { 2569 unsigned int clock = cea_mode->clock; 2570 2571 if (cea_mode->vrefresh % 6 != 0) 2572 return clock; 2573 2574 /* 2575 * edid_cea_modes contains the 59.94Hz 2576 * variant for 240 and 480 line modes, 2577 * and the 60Hz variant otherwise. 2578 */ 2579 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2580 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2581 else 2582 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2583 2584 return clock; 2585 } 2586 2587 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2588 unsigned int clock_tolerance) 2589 { 2590 u8 vic; 2591 2592 if (!to_match->clock) 2593 return 0; 2594 2595 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2596 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2597 unsigned int clock1, clock2; 2598 2599 /* Check both 60Hz and 59.94Hz */ 2600 clock1 = cea_mode->clock; 2601 clock2 = cea_mode_alternate_clock(cea_mode); 2602 2603 if (abs(to_match->clock - clock1) > clock_tolerance && 2604 abs(to_match->clock - clock2) > clock_tolerance) 2605 continue; 2606 2607 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 2608 return vic; 2609 } 2610 2611 return 0; 2612 } 2613 2614 /** 2615 * drm_match_cea_mode - look for a CEA mode matching given mode 2616 * @to_match: display mode 2617 * 2618 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2619 * mode. 2620 */ 2621 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2622 { 2623 u8 vic; 2624 2625 if (!to_match->clock) 2626 return 0; 2627 2628 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2629 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2630 unsigned int clock1, clock2; 2631 2632 /* Check both 60Hz and 59.94Hz */ 2633 clock1 = cea_mode->clock; 2634 clock2 = cea_mode_alternate_clock(cea_mode); 2635 2636 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2637 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2638 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2639 return vic; 2640 } 2641 return 0; 2642 } 2643 EXPORT_SYMBOL(drm_match_cea_mode); 2644 2645 static bool drm_valid_cea_vic(u8 vic) 2646 { 2647 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2648 } 2649 2650 /** 2651 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2652 * the input VIC from the CEA mode list 2653 * @video_code: ID given to each of the CEA modes 2654 * 2655 * Returns picture aspect ratio 2656 */ 2657 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2658 { 2659 return edid_cea_modes[video_code].picture_aspect_ratio; 2660 } 2661 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2662 2663 /* 2664 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2665 * specific block). 2666 * 2667 * It's almost like cea_mode_alternate_clock(), we just need to add an 2668 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2669 * one. 2670 */ 2671 static unsigned int 2672 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2673 { 2674 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2675 return hdmi_mode->clock; 2676 2677 return cea_mode_alternate_clock(hdmi_mode); 2678 } 2679 2680 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 2681 unsigned int clock_tolerance) 2682 { 2683 u8 vic; 2684 2685 if (!to_match->clock) 2686 return 0; 2687 2688 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2689 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2690 unsigned int clock1, clock2; 2691 2692 /* Make sure to also match alternate clocks */ 2693 clock1 = hdmi_mode->clock; 2694 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2695 2696 if (abs(to_match->clock - clock1) > clock_tolerance && 2697 abs(to_match->clock - clock2) > clock_tolerance) 2698 continue; 2699 2700 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 2701 return vic; 2702 } 2703 2704 return 0; 2705 } 2706 2707 /* 2708 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2709 * @to_match: display mode 2710 * 2711 * An HDMI mode is one defined in the HDMI vendor specific block. 2712 * 2713 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2714 */ 2715 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2716 { 2717 u8 vic; 2718 2719 if (!to_match->clock) 2720 return 0; 2721 2722 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2723 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2724 unsigned int clock1, clock2; 2725 2726 /* Make sure to also match alternate clocks */ 2727 clock1 = hdmi_mode->clock; 2728 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2729 2730 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2731 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2732 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2733 return vic; 2734 } 2735 return 0; 2736 } 2737 2738 static bool drm_valid_hdmi_vic(u8 vic) 2739 { 2740 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2741 } 2742 2743 static int 2744 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2745 { 2746 struct drm_device *dev = connector->dev; 2747 struct drm_display_mode *mode, *tmp; 2748 LINUX_LIST_HEAD(list); 2749 int modes = 0; 2750 2751 /* Don't add CEA modes if the CEA extension block is missing */ 2752 if (!drm_find_cea_extension(edid)) 2753 return 0; 2754 2755 /* 2756 * Go through all probed modes and create a new mode 2757 * with the alternate clock for certain CEA modes. 2758 */ 2759 list_for_each_entry(mode, &connector->probed_modes, head) { 2760 const struct drm_display_mode *cea_mode = NULL; 2761 struct drm_display_mode *newmode; 2762 u8 vic = drm_match_cea_mode(mode); 2763 unsigned int clock1, clock2; 2764 2765 if (drm_valid_cea_vic(vic)) { 2766 cea_mode = &edid_cea_modes[vic]; 2767 clock2 = cea_mode_alternate_clock(cea_mode); 2768 } else { 2769 vic = drm_match_hdmi_mode(mode); 2770 if (drm_valid_hdmi_vic(vic)) { 2771 cea_mode = &edid_4k_modes[vic]; 2772 clock2 = hdmi_mode_alternate_clock(cea_mode); 2773 } 2774 } 2775 2776 if (!cea_mode) 2777 continue; 2778 2779 clock1 = cea_mode->clock; 2780 2781 if (clock1 == clock2) 2782 continue; 2783 2784 if (mode->clock != clock1 && mode->clock != clock2) 2785 continue; 2786 2787 newmode = drm_mode_duplicate(dev, cea_mode); 2788 if (!newmode) 2789 continue; 2790 2791 /* Carry over the stereo flags */ 2792 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2793 2794 /* 2795 * The current mode could be either variant. Make 2796 * sure to pick the "other" clock for the new mode. 2797 */ 2798 if (mode->clock != clock1) 2799 newmode->clock = clock1; 2800 else 2801 newmode->clock = clock2; 2802 2803 list_add_tail(&newmode->head, &list); 2804 } 2805 2806 list_for_each_entry_safe(mode, tmp, &list, head) { 2807 list_del(&mode->head); 2808 drm_mode_probed_add(connector, mode); 2809 modes++; 2810 } 2811 2812 return modes; 2813 } 2814 2815 static struct drm_display_mode * 2816 drm_display_mode_from_vic_index(struct drm_connector *connector, 2817 const u8 *video_db, u8 video_len, 2818 u8 video_index) 2819 { 2820 struct drm_device *dev = connector->dev; 2821 struct drm_display_mode *newmode; 2822 u8 vic; 2823 2824 if (video_db == NULL || video_index >= video_len) 2825 return NULL; 2826 2827 /* CEA modes are numbered 1..127 */ 2828 vic = (video_db[video_index] & 127); 2829 if (!drm_valid_cea_vic(vic)) 2830 return NULL; 2831 2832 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 2833 if (!newmode) 2834 return NULL; 2835 2836 newmode->vrefresh = 0; 2837 2838 return newmode; 2839 } 2840 2841 static int 2842 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2843 { 2844 int i, modes = 0; 2845 2846 for (i = 0; i < len; i++) { 2847 struct drm_display_mode *mode; 2848 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2849 if (mode) { 2850 drm_mode_probed_add(connector, mode); 2851 modes++; 2852 } 2853 } 2854 2855 return modes; 2856 } 2857 2858 struct stereo_mandatory_mode { 2859 int width, height, vrefresh; 2860 unsigned int flags; 2861 }; 2862 2863 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2864 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2865 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2866 { 1920, 1080, 50, 2867 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2868 { 1920, 1080, 60, 2869 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2870 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2871 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2872 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2873 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2874 }; 2875 2876 static bool 2877 stereo_match_mandatory(const struct drm_display_mode *mode, 2878 const struct stereo_mandatory_mode *stereo_mode) 2879 { 2880 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2881 2882 return mode->hdisplay == stereo_mode->width && 2883 mode->vdisplay == stereo_mode->height && 2884 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2885 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2886 } 2887 2888 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2889 { 2890 struct drm_device *dev = connector->dev; 2891 struct drm_display_mode *mode; 2892 struct list_head stereo_modes; 2893 int modes = 0, i; 2894 2895 INIT_LIST_HEAD(&stereo_modes); 2896 2897 list_for_each_entry(mode, &connector->probed_modes, head) { 2898 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2899 const struct stereo_mandatory_mode *mandatory; 2900 struct drm_display_mode *new_mode; 2901 2902 if (!stereo_match_mandatory(mode, 2903 &stereo_mandatory_modes[i])) 2904 continue; 2905 2906 mandatory = &stereo_mandatory_modes[i]; 2907 new_mode = drm_mode_duplicate(dev, mode); 2908 if (!new_mode) 2909 continue; 2910 2911 new_mode->flags |= mandatory->flags; 2912 list_add_tail(&new_mode->head, &stereo_modes); 2913 modes++; 2914 } 2915 } 2916 2917 list_splice_tail(&stereo_modes, &connector->probed_modes); 2918 2919 return modes; 2920 } 2921 2922 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2923 { 2924 struct drm_device *dev = connector->dev; 2925 struct drm_display_mode *newmode; 2926 2927 if (!drm_valid_hdmi_vic(vic)) { 2928 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2929 return 0; 2930 } 2931 2932 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2933 if (!newmode) 2934 return 0; 2935 2936 drm_mode_probed_add(connector, newmode); 2937 2938 return 1; 2939 } 2940 2941 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2942 const u8 *video_db, u8 video_len, u8 video_index) 2943 { 2944 struct drm_display_mode *newmode; 2945 int modes = 0; 2946 2947 if (structure & (1 << 0)) { 2948 newmode = drm_display_mode_from_vic_index(connector, video_db, 2949 video_len, 2950 video_index); 2951 if (newmode) { 2952 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2953 drm_mode_probed_add(connector, newmode); 2954 modes++; 2955 } 2956 } 2957 if (structure & (1 << 6)) { 2958 newmode = drm_display_mode_from_vic_index(connector, video_db, 2959 video_len, 2960 video_index); 2961 if (newmode) { 2962 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2963 drm_mode_probed_add(connector, newmode); 2964 modes++; 2965 } 2966 } 2967 if (structure & (1 << 8)) { 2968 newmode = drm_display_mode_from_vic_index(connector, video_db, 2969 video_len, 2970 video_index); 2971 if (newmode) { 2972 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2973 drm_mode_probed_add(connector, newmode); 2974 modes++; 2975 } 2976 } 2977 2978 return modes; 2979 } 2980 2981 /* 2982 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2983 * @connector: connector corresponding to the HDMI sink 2984 * @db: start of the CEA vendor specific block 2985 * @len: length of the CEA block payload, ie. one can access up to db[len] 2986 * 2987 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2988 * also adds the stereo 3d modes when applicable. 2989 */ 2990 static int 2991 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2992 const u8 *video_db, u8 video_len) 2993 { 2994 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2995 u8 vic_len, hdmi_3d_len = 0; 2996 u16 mask; 2997 u16 structure_all; 2998 2999 if (len < 8) 3000 goto out; 3001 3002 /* no HDMI_Video_Present */ 3003 if (!(db[8] & (1 << 5))) 3004 goto out; 3005 3006 /* Latency_Fields_Present */ 3007 if (db[8] & (1 << 7)) 3008 offset += 2; 3009 3010 /* I_Latency_Fields_Present */ 3011 if (db[8] & (1 << 6)) 3012 offset += 2; 3013 3014 /* the declared length is not long enough for the 2 first bytes 3015 * of additional video format capabilities */ 3016 if (len < (8 + offset + 2)) 3017 goto out; 3018 3019 /* 3D_Present */ 3020 offset++; 3021 if (db[8 + offset] & (1 << 7)) { 3022 modes += add_hdmi_mandatory_stereo_modes(connector); 3023 3024 /* 3D_Multi_present */ 3025 multi_present = (db[8 + offset] & 0x60) >> 5; 3026 } 3027 3028 offset++; 3029 vic_len = db[8 + offset] >> 5; 3030 hdmi_3d_len = db[8 + offset] & 0x1f; 3031 3032 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3033 u8 vic; 3034 3035 vic = db[9 + offset + i]; 3036 modes += add_hdmi_mode(connector, vic); 3037 } 3038 offset += 1 + vic_len; 3039 3040 if (multi_present == 1) 3041 multi_len = 2; 3042 else if (multi_present == 2) 3043 multi_len = 4; 3044 else 3045 multi_len = 0; 3046 3047 if (len < (8 + offset + hdmi_3d_len - 1)) 3048 goto out; 3049 3050 if (hdmi_3d_len < multi_len) 3051 goto out; 3052 3053 if (multi_present == 1 || multi_present == 2) { 3054 /* 3D_Structure_ALL */ 3055 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3056 3057 /* check if 3D_MASK is present */ 3058 if (multi_present == 2) 3059 mask = (db[10 + offset] << 8) | db[11 + offset]; 3060 else 3061 mask = 0xffff; 3062 3063 for (i = 0; i < 16; i++) { 3064 if (mask & (1 << i)) 3065 modes += add_3d_struct_modes(connector, 3066 structure_all, 3067 video_db, 3068 video_len, i); 3069 } 3070 } 3071 3072 offset += multi_len; 3073 3074 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3075 int vic_index; 3076 struct drm_display_mode *newmode = NULL; 3077 unsigned int newflag = 0; 3078 bool detail_present; 3079 3080 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3081 3082 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3083 break; 3084 3085 /* 2D_VIC_order_X */ 3086 vic_index = db[8 + offset + i] >> 4; 3087 3088 /* 3D_Structure_X */ 3089 switch (db[8 + offset + i] & 0x0f) { 3090 case 0: 3091 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3092 break; 3093 case 6: 3094 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3095 break; 3096 case 8: 3097 /* 3D_Detail_X */ 3098 if ((db[9 + offset + i] >> 4) == 1) 3099 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3100 break; 3101 } 3102 3103 if (newflag != 0) { 3104 newmode = drm_display_mode_from_vic_index(connector, 3105 video_db, 3106 video_len, 3107 vic_index); 3108 3109 if (newmode) { 3110 newmode->flags |= newflag; 3111 drm_mode_probed_add(connector, newmode); 3112 modes++; 3113 } 3114 } 3115 3116 if (detail_present) 3117 i++; 3118 } 3119 3120 out: 3121 return modes; 3122 } 3123 3124 static int 3125 cea_db_payload_len(const u8 *db) 3126 { 3127 return db[0] & 0x1f; 3128 } 3129 3130 static int 3131 cea_db_tag(const u8 *db) 3132 { 3133 return db[0] >> 5; 3134 } 3135 3136 static int 3137 cea_revision(const u8 *cea) 3138 { 3139 return cea[1]; 3140 } 3141 3142 static int 3143 cea_db_offsets(const u8 *cea, int *start, int *end) 3144 { 3145 /* Data block offset in CEA extension block */ 3146 *start = 4; 3147 *end = cea[2]; 3148 if (*end == 0) 3149 *end = 127; 3150 if (*end < 4 || *end > 127) 3151 return -ERANGE; 3152 return 0; 3153 } 3154 3155 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3156 { 3157 int hdmi_id; 3158 3159 if (cea_db_tag(db) != VENDOR_BLOCK) 3160 return false; 3161 3162 if (cea_db_payload_len(db) < 5) 3163 return false; 3164 3165 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3166 3167 return hdmi_id == HDMI_IEEE_OUI; 3168 } 3169 3170 #define for_each_cea_db(cea, i, start, end) \ 3171 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3172 3173 static int 3174 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3175 { 3176 const u8 *cea = drm_find_cea_extension(edid); 3177 const u8 *db, *hdmi = NULL, *video = NULL; 3178 u8 dbl, hdmi_len, video_len = 0; 3179 int modes = 0; 3180 3181 if (cea && cea_revision(cea) >= 3) { 3182 int i, start, end; 3183 3184 if (cea_db_offsets(cea, &start, &end)) 3185 return 0; 3186 3187 for_each_cea_db(cea, i, start, end) { 3188 db = &cea[i]; 3189 dbl = cea_db_payload_len(db); 3190 3191 if (cea_db_tag(db) == VIDEO_BLOCK) { 3192 video = db + 1; 3193 video_len = dbl; 3194 modes += do_cea_modes(connector, video, dbl); 3195 } 3196 else if (cea_db_is_hdmi_vsdb(db)) { 3197 hdmi = db; 3198 hdmi_len = dbl; 3199 } 3200 } 3201 } 3202 3203 /* 3204 * We parse the HDMI VSDB after having added the cea modes as we will 3205 * be patching their flags when the sink supports stereo 3D. 3206 */ 3207 if (hdmi) 3208 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3209 video_len); 3210 3211 return modes; 3212 } 3213 3214 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3215 { 3216 const struct drm_display_mode *cea_mode; 3217 int clock1, clock2, clock; 3218 u8 vic; 3219 const char *type; 3220 3221 /* 3222 * allow 5kHz clock difference either way to account for 3223 * the 10kHz clock resolution limit of detailed timings. 3224 */ 3225 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3226 if (drm_valid_cea_vic(vic)) { 3227 type = "CEA"; 3228 cea_mode = &edid_cea_modes[vic]; 3229 clock1 = cea_mode->clock; 3230 clock2 = cea_mode_alternate_clock(cea_mode); 3231 } else { 3232 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3233 if (drm_valid_hdmi_vic(vic)) { 3234 type = "HDMI"; 3235 cea_mode = &edid_4k_modes[vic]; 3236 clock1 = cea_mode->clock; 3237 clock2 = hdmi_mode_alternate_clock(cea_mode); 3238 } else { 3239 return; 3240 } 3241 } 3242 3243 /* pick whichever is closest */ 3244 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3245 clock = clock1; 3246 else 3247 clock = clock2; 3248 3249 if (mode->clock == clock) 3250 return; 3251 3252 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3253 type, vic, mode->clock, clock); 3254 mode->clock = clock; 3255 } 3256 3257 static void 3258 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3259 { 3260 u8 len = cea_db_payload_len(db); 3261 3262 if (len >= 6) { 3263 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3264 connector->dvi_dual = db[6] & 1; 3265 } 3266 if (len >= 7) 3267 connector->max_tmds_clock = db[7] * 5; 3268 if (len >= 8) { 3269 connector->latency_present[0] = db[8] >> 7; 3270 connector->latency_present[1] = (db[8] >> 6) & 1; 3271 } 3272 if (len >= 9) 3273 connector->video_latency[0] = db[9]; 3274 if (len >= 10) 3275 connector->audio_latency[0] = db[10]; 3276 if (len >= 11) 3277 connector->video_latency[1] = db[11]; 3278 if (len >= 12) 3279 connector->audio_latency[1] = db[12]; 3280 3281 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3282 "max TMDS clock %d, " 3283 "latency present %d %d, " 3284 "video latency %d %d, " 3285 "audio latency %d %d\n", 3286 connector->dvi_dual, 3287 connector->max_tmds_clock, 3288 (int) connector->latency_present[0], 3289 (int) connector->latency_present[1], 3290 connector->video_latency[0], 3291 connector->video_latency[1], 3292 connector->audio_latency[0], 3293 connector->audio_latency[1]); 3294 } 3295 3296 static void 3297 monitor_name(struct detailed_timing *t, void *data) 3298 { 3299 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3300 *(u8 **)data = t->data.other_data.data.str.str; 3301 } 3302 3303 static int get_monitor_name(struct edid *edid, char name[13]) 3304 { 3305 char *edid_name = NULL; 3306 int mnl; 3307 3308 if (!edid || !name) 3309 return 0; 3310 3311 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3312 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3313 if (edid_name[mnl] == 0x0a) 3314 break; 3315 3316 name[mnl] = edid_name[mnl]; 3317 } 3318 3319 return mnl; 3320 } 3321 3322 /** 3323 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3324 * @edid: monitor EDID information 3325 * @name: pointer to a character array to hold the name of the monitor 3326 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3327 * 3328 */ 3329 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3330 { 3331 int name_length; 3332 char buf[13]; 3333 3334 if (bufsize <= 0) 3335 return; 3336 3337 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3338 memcpy(name, buf, name_length); 3339 name[name_length] = '\0'; 3340 } 3341 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3342 3343 /** 3344 * drm_edid_to_eld - build ELD from EDID 3345 * @connector: connector corresponding to the HDMI/DP sink 3346 * @edid: EDID to parse 3347 * 3348 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3349 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3350 * fill in. 3351 */ 3352 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3353 { 3354 uint8_t *eld = connector->eld; 3355 u8 *cea; 3356 u8 *db; 3357 int total_sad_count = 0; 3358 int mnl; 3359 int dbl; 3360 3361 memset(eld, 0, sizeof(connector->eld)); 3362 3363 cea = drm_find_cea_extension(edid); 3364 if (!cea) { 3365 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3366 return; 3367 } 3368 3369 mnl = get_monitor_name(edid, eld + 20); 3370 3371 eld[4] = (cea[1] << 5) | mnl; 3372 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3373 3374 eld[0] = 2 << 3; /* ELD version: 2 */ 3375 3376 eld[16] = edid->mfg_id[0]; 3377 eld[17] = edid->mfg_id[1]; 3378 eld[18] = edid->prod_code[0]; 3379 eld[19] = edid->prod_code[1]; 3380 3381 if (cea_revision(cea) >= 3) { 3382 int i, start, end; 3383 3384 if (cea_db_offsets(cea, &start, &end)) { 3385 start = 0; 3386 end = 0; 3387 } 3388 3389 for_each_cea_db(cea, i, start, end) { 3390 db = &cea[i]; 3391 dbl = cea_db_payload_len(db); 3392 3393 switch (cea_db_tag(db)) { 3394 int sad_count; 3395 3396 case AUDIO_BLOCK: 3397 /* Audio Data Block, contains SADs */ 3398 sad_count = min(dbl / 3, 15 - total_sad_count); 3399 if (sad_count >= 1) 3400 memcpy(eld + 20 + mnl + total_sad_count * 3, 3401 &db[1], sad_count * 3); 3402 total_sad_count += sad_count; 3403 break; 3404 case SPEAKER_BLOCK: 3405 /* Speaker Allocation Data Block */ 3406 if (dbl >= 1) 3407 eld[7] = db[1]; 3408 break; 3409 case VENDOR_BLOCK: 3410 /* HDMI Vendor-Specific Data Block */ 3411 if (cea_db_is_hdmi_vsdb(db)) 3412 parse_hdmi_vsdb(connector, db); 3413 break; 3414 default: 3415 break; 3416 } 3417 } 3418 } 3419 eld[5] |= total_sad_count << 4; 3420 3421 eld[DRM_ELD_BASELINE_ELD_LEN] = 3422 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3423 3424 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3425 drm_eld_size(eld), total_sad_count); 3426 } 3427 EXPORT_SYMBOL(drm_edid_to_eld); 3428 3429 /** 3430 * drm_edid_to_sad - extracts SADs from EDID 3431 * @edid: EDID to parse 3432 * @sads: pointer that will be set to the extracted SADs 3433 * 3434 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3435 * 3436 * Note: The returned pointer needs to be freed using kfree(). 3437 * 3438 * Return: The number of found SADs or negative number on error. 3439 */ 3440 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3441 { 3442 int count = 0; 3443 int i, start, end, dbl; 3444 u8 *cea; 3445 3446 cea = drm_find_cea_extension(edid); 3447 if (!cea) { 3448 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3449 return -ENOENT; 3450 } 3451 3452 if (cea_revision(cea) < 3) { 3453 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3454 return -EOPNOTSUPP; 3455 } 3456 3457 if (cea_db_offsets(cea, &start, &end)) { 3458 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3459 return -EPROTO; 3460 } 3461 3462 for_each_cea_db(cea, i, start, end) { 3463 u8 *db = &cea[i]; 3464 3465 if (cea_db_tag(db) == AUDIO_BLOCK) { 3466 int j; 3467 dbl = cea_db_payload_len(db); 3468 3469 count = dbl / 3; /* SAD is 3B */ 3470 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3471 if (!*sads) 3472 return -ENOMEM; 3473 for (j = 0; j < count; j++) { 3474 u8 *sad = &db[1 + j * 3]; 3475 3476 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3477 (*sads)[j].channels = sad[0] & 0x7; 3478 (*sads)[j].freq = sad[1] & 0x7F; 3479 (*sads)[j].byte2 = sad[2]; 3480 } 3481 break; 3482 } 3483 } 3484 3485 return count; 3486 } 3487 EXPORT_SYMBOL(drm_edid_to_sad); 3488 3489 /** 3490 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3491 * @edid: EDID to parse 3492 * @sadb: pointer to the speaker block 3493 * 3494 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3495 * 3496 * Note: The returned pointer needs to be freed using kfree(). 3497 * 3498 * Return: The number of found Speaker Allocation Blocks or negative number on 3499 * error. 3500 */ 3501 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3502 { 3503 int count = 0; 3504 int i, start, end, dbl; 3505 const u8 *cea; 3506 3507 cea = drm_find_cea_extension(edid); 3508 if (!cea) { 3509 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3510 return -ENOENT; 3511 } 3512 3513 if (cea_revision(cea) < 3) { 3514 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3515 return -ENOTSUPP; 3516 } 3517 3518 if (cea_db_offsets(cea, &start, &end)) { 3519 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3520 return -EPROTO; 3521 } 3522 3523 for_each_cea_db(cea, i, start, end) { 3524 const u8 *db = &cea[i]; 3525 3526 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3527 dbl = cea_db_payload_len(db); 3528 3529 /* Speaker Allocation Data Block */ 3530 if (dbl == 3) { 3531 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3532 if (!*sadb) 3533 return -ENOMEM; 3534 count = dbl; 3535 break; 3536 } 3537 } 3538 } 3539 3540 return count; 3541 } 3542 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3543 3544 /** 3545 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3546 * @connector: connector associated with the HDMI/DP sink 3547 * @mode: the display mode 3548 * 3549 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3550 * the sink doesn't support audio or video. 3551 */ 3552 int drm_av_sync_delay(struct drm_connector *connector, 3553 const struct drm_display_mode *mode) 3554 { 3555 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3556 int a, v; 3557 3558 if (!connector->latency_present[0]) 3559 return 0; 3560 if (!connector->latency_present[1]) 3561 i = 0; 3562 3563 a = connector->audio_latency[i]; 3564 v = connector->video_latency[i]; 3565 3566 /* 3567 * HDMI/DP sink doesn't support audio or video? 3568 */ 3569 if (a == 255 || v == 255) 3570 return 0; 3571 3572 /* 3573 * Convert raw EDID values to millisecond. 3574 * Treat unknown latency as 0ms. 3575 */ 3576 if (a) 3577 a = min(2 * (a - 1), 500); 3578 if (v) 3579 v = min(2 * (v - 1), 500); 3580 3581 return max(v - a, 0); 3582 } 3583 EXPORT_SYMBOL(drm_av_sync_delay); 3584 3585 /** 3586 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3587 * @encoder: the encoder just changed display mode 3588 * 3589 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3590 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3591 * 3592 * Return: The connector associated with the first HDMI/DP sink that has ELD 3593 * attached to it. 3594 */ 3595 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3596 { 3597 struct drm_connector *connector; 3598 struct drm_device *dev = encoder->dev; 3599 3600 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3601 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3602 3603 drm_for_each_connector(connector, dev) 3604 if (connector->encoder == encoder && connector->eld[0]) 3605 return connector; 3606 3607 return NULL; 3608 } 3609 EXPORT_SYMBOL(drm_select_eld); 3610 3611 /** 3612 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3613 * @edid: monitor EDID information 3614 * 3615 * Parse the CEA extension according to CEA-861-B. 3616 * 3617 * Return: True if the monitor is HDMI, false if not or unknown. 3618 */ 3619 bool drm_detect_hdmi_monitor(struct edid *edid) 3620 { 3621 u8 *edid_ext; 3622 int i; 3623 int start_offset, end_offset; 3624 3625 edid_ext = drm_find_cea_extension(edid); 3626 if (!edid_ext) 3627 return false; 3628 3629 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3630 return false; 3631 3632 /* 3633 * Because HDMI identifier is in Vendor Specific Block, 3634 * search it from all data blocks of CEA extension. 3635 */ 3636 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3637 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3638 return true; 3639 } 3640 3641 return false; 3642 } 3643 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3644 3645 /** 3646 * drm_detect_monitor_audio - check monitor audio capability 3647 * @edid: EDID block to scan 3648 * 3649 * Monitor should have CEA extension block. 3650 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3651 * audio' only. If there is any audio extension block and supported 3652 * audio format, assume at least 'basic audio' support, even if 'basic 3653 * audio' is not defined in EDID. 3654 * 3655 * Return: True if the monitor supports audio, false otherwise. 3656 */ 3657 bool drm_detect_monitor_audio(struct edid *edid) 3658 { 3659 u8 *edid_ext; 3660 int i, j; 3661 bool has_audio = false; 3662 int start_offset, end_offset; 3663 3664 edid_ext = drm_find_cea_extension(edid); 3665 if (!edid_ext) 3666 goto end; 3667 3668 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3669 3670 if (has_audio) { 3671 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3672 goto end; 3673 } 3674 3675 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3676 goto end; 3677 3678 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3679 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3680 has_audio = true; 3681 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3682 DRM_DEBUG_KMS("CEA audio format %d\n", 3683 (edid_ext[i + j] >> 3) & 0xf); 3684 goto end; 3685 } 3686 } 3687 end: 3688 return has_audio; 3689 } 3690 EXPORT_SYMBOL(drm_detect_monitor_audio); 3691 3692 /** 3693 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3694 * @edid: EDID block to scan 3695 * 3696 * Check whether the monitor reports the RGB quantization range selection 3697 * as supported. The AVI infoframe can then be used to inform the monitor 3698 * which quantization range (full or limited) is used. 3699 * 3700 * Return: True if the RGB quantization range is selectable, false otherwise. 3701 */ 3702 bool drm_rgb_quant_range_selectable(struct edid *edid) 3703 { 3704 u8 *edid_ext; 3705 int i, start, end; 3706 3707 edid_ext = drm_find_cea_extension(edid); 3708 if (!edid_ext) 3709 return false; 3710 3711 if (cea_db_offsets(edid_ext, &start, &end)) 3712 return false; 3713 3714 for_each_cea_db(edid_ext, i, start, end) { 3715 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3716 cea_db_payload_len(&edid_ext[i]) == 2) { 3717 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3718 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3719 } 3720 } 3721 3722 return false; 3723 } 3724 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3725 3726 /** 3727 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3728 * hdmi deep color modes and update drm_display_info if so. 3729 * @edid: monitor EDID information 3730 * @info: Updated with maximum supported deep color bpc and color format 3731 * if deep color supported. 3732 * @connector: DRM connector, used only for debug output 3733 * 3734 * Parse the CEA extension according to CEA-861-B. 3735 * Return true if HDMI deep color supported, false if not or unknown. 3736 */ 3737 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3738 struct drm_display_info *info, 3739 struct drm_connector *connector) 3740 { 3741 u8 *edid_ext, *hdmi; 3742 int i; 3743 int start_offset, end_offset; 3744 unsigned int dc_bpc = 0; 3745 3746 edid_ext = drm_find_cea_extension(edid); 3747 if (!edid_ext) 3748 return false; 3749 3750 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3751 return false; 3752 3753 /* 3754 * Because HDMI identifier is in Vendor Specific Block, 3755 * search it from all data blocks of CEA extension. 3756 */ 3757 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3758 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3759 /* HDMI supports at least 8 bpc */ 3760 info->bpc = 8; 3761 3762 hdmi = &edid_ext[i]; 3763 if (cea_db_payload_len(hdmi) < 6) 3764 return false; 3765 3766 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3767 dc_bpc = 10; 3768 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3769 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3770 connector->name); 3771 } 3772 3773 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3774 dc_bpc = 12; 3775 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3776 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3777 connector->name); 3778 } 3779 3780 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3781 dc_bpc = 16; 3782 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3783 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3784 connector->name); 3785 } 3786 3787 if (dc_bpc > 0) { 3788 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3789 connector->name, dc_bpc); 3790 info->bpc = dc_bpc; 3791 3792 /* 3793 * Deep color support mandates RGB444 support for all video 3794 * modes and forbids YCRCB422 support for all video modes per 3795 * HDMI 1.3 spec. 3796 */ 3797 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3798 3799 /* YCRCB444 is optional according to spec. */ 3800 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3801 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3802 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3803 connector->name); 3804 } 3805 3806 /* 3807 * Spec says that if any deep color mode is supported at all, 3808 * then deep color 36 bit must be supported. 3809 */ 3810 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3811 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3812 connector->name); 3813 } 3814 3815 return true; 3816 } 3817 else { 3818 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3819 connector->name); 3820 } 3821 } 3822 } 3823 3824 return false; 3825 } 3826 3827 /** 3828 * drm_add_display_info - pull display info out if present 3829 * @edid: EDID data 3830 * @info: display info (attached to connector) 3831 * @connector: connector whose edid is used to build display info 3832 * 3833 * Grab any available display info and stuff it into the drm_display_info 3834 * structure that's part of the connector. Useful for tracking bpp and 3835 * color spaces. 3836 */ 3837 static void drm_add_display_info(struct edid *edid, 3838 struct drm_display_info *info, 3839 struct drm_connector *connector) 3840 { 3841 u8 *edid_ext; 3842 3843 info->width_mm = edid->width_cm * 10; 3844 info->height_mm = edid->height_cm * 10; 3845 3846 /* driver figures it out in this case */ 3847 info->bpc = 0; 3848 info->color_formats = 0; 3849 3850 if (edid->revision < 3) 3851 return; 3852 3853 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3854 return; 3855 3856 /* Get data from CEA blocks if present */ 3857 edid_ext = drm_find_cea_extension(edid); 3858 if (edid_ext) { 3859 info->cea_rev = edid_ext[1]; 3860 3861 /* The existence of a CEA block should imply RGB support */ 3862 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3863 if (edid_ext[3] & EDID_CEA_YCRCB444) 3864 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3865 if (edid_ext[3] & EDID_CEA_YCRCB422) 3866 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3867 } 3868 3869 /* HDMI deep color modes supported? Assign to info, if so */ 3870 drm_assign_hdmi_deep_color_info(edid, info, connector); 3871 3872 /* Only defined for 1.4 with digital displays */ 3873 if (edid->revision < 4) 3874 return; 3875 3876 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3877 case DRM_EDID_DIGITAL_DEPTH_6: 3878 info->bpc = 6; 3879 break; 3880 case DRM_EDID_DIGITAL_DEPTH_8: 3881 info->bpc = 8; 3882 break; 3883 case DRM_EDID_DIGITAL_DEPTH_10: 3884 info->bpc = 10; 3885 break; 3886 case DRM_EDID_DIGITAL_DEPTH_12: 3887 info->bpc = 12; 3888 break; 3889 case DRM_EDID_DIGITAL_DEPTH_14: 3890 info->bpc = 14; 3891 break; 3892 case DRM_EDID_DIGITAL_DEPTH_16: 3893 info->bpc = 16; 3894 break; 3895 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3896 default: 3897 info->bpc = 0; 3898 break; 3899 } 3900 3901 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3902 connector->name, info->bpc); 3903 3904 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3905 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3906 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3907 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3908 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3909 } 3910 3911 static int validate_displayid(u8 *displayid, int length, int idx) 3912 { 3913 int i; 3914 u8 csum = 0; 3915 struct displayid_hdr *base; 3916 3917 base = (struct displayid_hdr *)&displayid[idx]; 3918 3919 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 3920 base->rev, base->bytes, base->prod_id, base->ext_count); 3921 3922 if (base->bytes + 5 > length - idx) 3923 return -EINVAL; 3924 for (i = idx; i <= base->bytes + 5; i++) { 3925 csum += displayid[i]; 3926 } 3927 if (csum) { 3928 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); 3929 return -EINVAL; 3930 } 3931 return 0; 3932 } 3933 3934 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 3935 struct displayid_detailed_timings_1 *timings) 3936 { 3937 struct drm_display_mode *mode; 3938 unsigned pixel_clock = (timings->pixel_clock[0] | 3939 (timings->pixel_clock[1] << 8) | 3940 (timings->pixel_clock[2] << 16)); 3941 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 3942 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 3943 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 3944 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 3945 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 3946 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 3947 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 3948 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 3949 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 3950 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 3951 mode = drm_mode_create(dev); 3952 if (!mode) 3953 return NULL; 3954 3955 mode->clock = pixel_clock * 10; 3956 mode->hdisplay = hactive; 3957 mode->hsync_start = mode->hdisplay + hsync; 3958 mode->hsync_end = mode->hsync_start + hsync_width; 3959 mode->htotal = mode->hdisplay + hblank; 3960 3961 mode->vdisplay = vactive; 3962 mode->vsync_start = mode->vdisplay + vsync; 3963 mode->vsync_end = mode->vsync_start + vsync_width; 3964 mode->vtotal = mode->vdisplay + vblank; 3965 3966 mode->flags = 0; 3967 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3968 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3969 mode->type = DRM_MODE_TYPE_DRIVER; 3970 3971 if (timings->flags & 0x80) 3972 mode->type |= DRM_MODE_TYPE_PREFERRED; 3973 mode->vrefresh = drm_mode_vrefresh(mode); 3974 drm_mode_set_name(mode); 3975 3976 return mode; 3977 } 3978 3979 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 3980 struct displayid_block *block) 3981 { 3982 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 3983 int i; 3984 int num_timings; 3985 struct drm_display_mode *newmode; 3986 int num_modes = 0; 3987 /* blocks must be multiple of 20 bytes length */ 3988 if (block->num_bytes % 20) 3989 return 0; 3990 3991 num_timings = block->num_bytes / 20; 3992 for (i = 0; i < num_timings; i++) { 3993 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 3994 3995 newmode = drm_mode_displayid_detailed(connector->dev, timings); 3996 if (!newmode) 3997 continue; 3998 3999 drm_mode_probed_add(connector, newmode); 4000 num_modes++; 4001 } 4002 return num_modes; 4003 } 4004 4005 static int add_displayid_detailed_modes(struct drm_connector *connector, 4006 struct edid *edid) 4007 { 4008 u8 *displayid; 4009 int ret; 4010 int idx = 1; 4011 int length = EDID_LENGTH; 4012 struct displayid_block *block; 4013 int num_modes = 0; 4014 4015 displayid = drm_find_displayid_extension(edid); 4016 if (!displayid) 4017 return 0; 4018 4019 ret = validate_displayid(displayid, length, idx); 4020 if (ret) 4021 return 0; 4022 4023 idx += sizeof(struct displayid_hdr); 4024 while (block = (struct displayid_block *)&displayid[idx], 4025 idx + sizeof(struct displayid_block) <= length && 4026 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4027 block->num_bytes > 0) { 4028 idx += block->num_bytes + sizeof(struct displayid_block); 4029 switch (block->tag) { 4030 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4031 num_modes += add_displayid_detailed_1_modes(connector, block); 4032 break; 4033 } 4034 } 4035 return num_modes; 4036 } 4037 4038 /** 4039 * drm_add_edid_modes - add modes from EDID data, if available 4040 * @connector: connector we're probing 4041 * @edid: EDID data 4042 * 4043 * Add the specified modes to the connector's mode list. 4044 * 4045 * Return: The number of modes added or 0 if we couldn't find any. 4046 */ 4047 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4048 { 4049 int num_modes = 0; 4050 u32 quirks; 4051 4052 if (edid == NULL) { 4053 return 0; 4054 } 4055 if (!drm_edid_is_valid(edid)) { 4056 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4057 connector->name); 4058 return 0; 4059 } 4060 4061 quirks = edid_get_quirks(edid); 4062 4063 /* 4064 * EDID spec says modes should be preferred in this order: 4065 * - preferred detailed mode 4066 * - other detailed modes from base block 4067 * - detailed modes from extension blocks 4068 * - CVT 3-byte code modes 4069 * - standard timing codes 4070 * - established timing codes 4071 * - modes inferred from GTF or CVT range information 4072 * 4073 * We get this pretty much right. 4074 * 4075 * XXX order for additional mode types in extension blocks? 4076 */ 4077 num_modes += add_detailed_modes(connector, edid, quirks); 4078 num_modes += add_cvt_modes(connector, edid); 4079 num_modes += add_standard_modes(connector, edid); 4080 num_modes += add_established_modes(connector, edid); 4081 num_modes += add_cea_modes(connector, edid); 4082 num_modes += add_alternate_cea_modes(connector, edid); 4083 num_modes += add_displayid_detailed_modes(connector, edid); 4084 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4085 num_modes += add_inferred_modes(connector, edid); 4086 4087 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4088 edid_fixup_preferred(connector, quirks); 4089 4090 drm_add_display_info(edid, &connector->display_info, connector); 4091 4092 if (quirks & EDID_QUIRK_FORCE_6BPC) 4093 connector->display_info.bpc = 6; 4094 4095 if (quirks & EDID_QUIRK_FORCE_8BPC) 4096 connector->display_info.bpc = 8; 4097 4098 if (quirks & EDID_QUIRK_FORCE_12BPC) 4099 connector->display_info.bpc = 12; 4100 4101 return num_modes; 4102 } 4103 EXPORT_SYMBOL(drm_add_edid_modes); 4104 4105 /** 4106 * drm_add_modes_noedid - add modes for the connectors without EDID 4107 * @connector: connector we're probing 4108 * @hdisplay: the horizontal display limit 4109 * @vdisplay: the vertical display limit 4110 * 4111 * Add the specified modes to the connector's mode list. Only when the 4112 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4113 * 4114 * Return: The number of modes added or 0 if we couldn't find any. 4115 */ 4116 int drm_add_modes_noedid(struct drm_connector *connector, 4117 int hdisplay, int vdisplay) 4118 { 4119 int i, count, num_modes = 0; 4120 struct drm_display_mode *mode; 4121 struct drm_device *dev = connector->dev; 4122 4123 count = ARRAY_SIZE(drm_dmt_modes); 4124 if (hdisplay < 0) 4125 hdisplay = 0; 4126 if (vdisplay < 0) 4127 vdisplay = 0; 4128 4129 for (i = 0; i < count; i++) { 4130 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4131 if (hdisplay && vdisplay) { 4132 /* 4133 * Only when two are valid, they will be used to check 4134 * whether the mode should be added to the mode list of 4135 * the connector. 4136 */ 4137 if (ptr->hdisplay > hdisplay || 4138 ptr->vdisplay > vdisplay) 4139 continue; 4140 } 4141 if (drm_mode_vrefresh(ptr) > 61) 4142 continue; 4143 mode = drm_mode_duplicate(dev, ptr); 4144 if (mode) { 4145 drm_mode_probed_add(connector, mode); 4146 num_modes++; 4147 } 4148 } 4149 return num_modes; 4150 } 4151 EXPORT_SYMBOL(drm_add_modes_noedid); 4152 4153 /** 4154 * drm_set_preferred_mode - Sets the preferred mode of a connector 4155 * @connector: connector whose mode list should be processed 4156 * @hpref: horizontal resolution of preferred mode 4157 * @vpref: vertical resolution of preferred mode 4158 * 4159 * Marks a mode as preferred if it matches the resolution specified by @hpref 4160 * and @vpref. 4161 */ 4162 void drm_set_preferred_mode(struct drm_connector *connector, 4163 int hpref, int vpref) 4164 { 4165 struct drm_display_mode *mode; 4166 4167 list_for_each_entry(mode, &connector->probed_modes, head) { 4168 if (mode->hdisplay == hpref && 4169 mode->vdisplay == vpref) 4170 mode->type |= DRM_MODE_TYPE_PREFERRED; 4171 } 4172 } 4173 EXPORT_SYMBOL(drm_set_preferred_mode); 4174 4175 /** 4176 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4177 * data from a DRM display mode 4178 * @frame: HDMI AVI infoframe 4179 * @mode: DRM display mode 4180 * 4181 * Return: 0 on success or a negative error code on failure. 4182 */ 4183 int 4184 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4185 const struct drm_display_mode *mode) 4186 { 4187 int err; 4188 4189 if (!frame || !mode) 4190 return -EINVAL; 4191 4192 err = hdmi_avi_infoframe_init(frame); 4193 if (err < 0) 4194 return err; 4195 4196 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4197 frame->pixel_repeat = 1; 4198 4199 frame->video_code = drm_match_cea_mode(mode); 4200 4201 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4202 4203 /* 4204 * Populate picture aspect ratio from either 4205 * user input (if specified) or from the CEA mode list. 4206 */ 4207 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4208 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4209 frame->picture_aspect = mode->picture_aspect_ratio; 4210 else if (frame->video_code > 0) 4211 frame->picture_aspect = drm_get_cea_aspect_ratio( 4212 frame->video_code); 4213 4214 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4215 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4216 4217 return 0; 4218 } 4219 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4220 4221 static enum hdmi_3d_structure 4222 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4223 { 4224 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4225 4226 switch (layout) { 4227 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4228 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4229 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4230 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4231 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4232 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4233 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4234 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4235 case DRM_MODE_FLAG_3D_L_DEPTH: 4236 return HDMI_3D_STRUCTURE_L_DEPTH; 4237 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4238 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4239 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4240 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4241 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4242 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4243 default: 4244 return HDMI_3D_STRUCTURE_INVALID; 4245 } 4246 } 4247 4248 /** 4249 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4250 * data from a DRM display mode 4251 * @frame: HDMI vendor infoframe 4252 * @mode: DRM display mode 4253 * 4254 * Note that there's is a need to send HDMI vendor infoframes only when using a 4255 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4256 * function will return -EINVAL, error that can be safely ignored. 4257 * 4258 * Return: 0 on success or a negative error code on failure. 4259 */ 4260 int 4261 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4262 const struct drm_display_mode *mode) 4263 { 4264 int err; 4265 u32 s3d_flags; 4266 u8 vic; 4267 4268 if (!frame || !mode) 4269 return -EINVAL; 4270 4271 vic = drm_match_hdmi_mode(mode); 4272 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4273 4274 if (!vic && !s3d_flags) 4275 return -EINVAL; 4276 4277 if (vic && s3d_flags) 4278 return -EINVAL; 4279 4280 err = hdmi_vendor_infoframe_init(frame); 4281 if (err < 0) 4282 return err; 4283 4284 if (vic) 4285 frame->vic = vic; 4286 else 4287 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4288 4289 return 0; 4290 } 4291 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4292 4293 static int drm_parse_tiled_block(struct drm_connector *connector, 4294 struct displayid_block *block) 4295 { 4296 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4297 u16 w, h; 4298 u8 tile_v_loc, tile_h_loc; 4299 u8 num_v_tile, num_h_tile; 4300 struct drm_tile_group *tg; 4301 4302 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4303 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4304 4305 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4306 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4307 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4308 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4309 4310 connector->has_tile = true; 4311 if (tile->tile_cap & 0x80) 4312 connector->tile_is_single_monitor = true; 4313 4314 connector->num_h_tile = num_h_tile + 1; 4315 connector->num_v_tile = num_v_tile + 1; 4316 connector->tile_h_loc = tile_h_loc; 4317 connector->tile_v_loc = tile_v_loc; 4318 connector->tile_h_size = w + 1; 4319 connector->tile_v_size = h + 1; 4320 4321 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4322 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4323 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4324 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4325 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4326 4327 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4328 if (!tg) { 4329 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4330 } 4331 if (!tg) 4332 return -ENOMEM; 4333 4334 if (connector->tile_group != tg) { 4335 /* if we haven't got a pointer, 4336 take the reference, drop ref to old tile group */ 4337 if (connector->tile_group) { 4338 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4339 } 4340 connector->tile_group = tg; 4341 } else 4342 /* if same tile group, then release the ref we just took. */ 4343 drm_mode_put_tile_group(connector->dev, tg); 4344 return 0; 4345 } 4346 4347 static int drm_parse_display_id(struct drm_connector *connector, 4348 u8 *displayid, int length, 4349 bool is_edid_extension) 4350 { 4351 /* if this is an EDID extension the first byte will be 0x70 */ 4352 int idx = 0; 4353 struct displayid_block *block; 4354 int ret; 4355 4356 if (is_edid_extension) 4357 idx = 1; 4358 4359 ret = validate_displayid(displayid, length, idx); 4360 if (ret) 4361 return ret; 4362 4363 idx += sizeof(struct displayid_hdr); 4364 while (block = (struct displayid_block *)&displayid[idx], 4365 idx + sizeof(struct displayid_block) <= length && 4366 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4367 block->num_bytes > 0) { 4368 idx += block->num_bytes + sizeof(struct displayid_block); 4369 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 4370 block->tag, block->rev, block->num_bytes); 4371 4372 switch (block->tag) { 4373 case DATA_BLOCK_TILED_DISPLAY: 4374 ret = drm_parse_tiled_block(connector, block); 4375 if (ret) 4376 return ret; 4377 break; 4378 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4379 /* handled in mode gathering code. */ 4380 break; 4381 default: 4382 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 4383 break; 4384 } 4385 } 4386 return 0; 4387 } 4388 4389 static void drm_get_displayid(struct drm_connector *connector, 4390 struct edid *edid) 4391 { 4392 void *displayid = NULL; 4393 int ret; 4394 connector->has_tile = false; 4395 displayid = drm_find_displayid_extension(edid); 4396 if (!displayid) { 4397 /* drop reference to any tile group we had */ 4398 goto out_drop_ref; 4399 } 4400 4401 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4402 if (ret < 0) 4403 goto out_drop_ref; 4404 if (!connector->has_tile) 4405 goto out_drop_ref; 4406 return; 4407 out_drop_ref: 4408 if (connector->tile_group) { 4409 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4410 connector->tile_group = NULL; 4411 } 4412 return; 4413 } 4414