1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/module.h> 34 #include <drm/drmP.h> 35 #include <drm/drm_edid.h> 36 #include <linux/string.h> 37 38 #include <bus/iicbus/iic.h> 39 #include <bus/iicbus/iiconf.h> 40 #include "iicbus_if.h" 41 42 #define version_greater(edid, maj, min) \ 43 (((edid)->version > (maj)) || \ 44 ((edid)->version == (maj) && (edid)->revision > (min))) 45 46 #define EDID_EST_TIMINGS 16 47 #define EDID_STD_TIMINGS 8 48 #define EDID_DETAILED_TIMINGS 4 49 50 /* 51 * EDID blocks out in the wild have a variety of bugs, try to collect 52 * them here (note that userspace may work around broken monitors first, 53 * but fixes should make their way here so that the kernel "just works" 54 * on as many displays as possible). 55 */ 56 57 /* First detailed mode wrong, use largest 60Hz mode */ 58 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 59 /* Reported 135MHz pixel clock is too high, needs adjustment */ 60 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 61 /* Prefer the largest mode at 75 Hz */ 62 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 63 /* Detail timing is in cm not mm */ 64 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 65 /* Detailed timing descriptors have bogus size values, so just take the 66 * maximum size and use that. 67 */ 68 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 69 /* Monitor forgot to set the first detailed is preferred bit. */ 70 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 71 /* use +hsync +vsync for detailed mode */ 72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 73 /* Force reduced-blanking timings for detailed modes */ 74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 75 /* Force 8bpc */ 76 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 77 /* Force 12bpc */ 78 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 79 80 struct detailed_mode_closure { 81 struct drm_connector *connector; 82 struct edid *edid; 83 bool preferred; 84 u32 quirks; 85 int modes; 86 }; 87 88 #define LEVEL_DMT 0 89 #define LEVEL_GTF 1 90 #define LEVEL_GTF2 2 91 #define LEVEL_CVT 3 92 93 static struct edid_quirk { 94 char vendor[4]; 95 int product_id; 96 u32 quirks; 97 } edid_quirk_list[] = { 98 /* Acer AL1706 */ 99 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 100 /* Acer F51 */ 101 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 102 /* Unknown Acer */ 103 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 104 105 /* Belinea 10 15 55 */ 106 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 107 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 108 109 /* Envision Peripherals, Inc. EN-7100e */ 110 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 111 /* Envision EN2028 */ 112 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 113 114 /* Funai Electronics PM36B */ 115 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 116 EDID_QUIRK_DETAILED_IN_CM }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 }; 146 147 /* 148 * Autogenerated from the DMT spec. 149 * This table is copied from xfree86/modes/xf86EdidModes.c. 150 */ 151 static const struct drm_display_mode drm_dmt_modes[] = { 152 /* 0x01 - 640x350@85Hz */ 153 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 154 736, 832, 0, 350, 382, 385, 445, 0, 155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 156 /* 0x02 - 640x400@85Hz */ 157 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 158 736, 832, 0, 400, 401, 404, 445, 0, 159 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 160 /* 0x03 - 720x400@85Hz */ 161 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 162 828, 936, 0, 400, 401, 404, 446, 0, 163 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 164 /* 0x04 - 640x480@60Hz */ 165 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 166 752, 800, 0, 480, 490, 492, 525, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 168 /* 0x05 - 640x480@72Hz */ 169 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 170 704, 832, 0, 480, 489, 492, 520, 0, 171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 172 /* 0x06 - 640x480@75Hz */ 173 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 174 720, 840, 0, 480, 481, 484, 500, 0, 175 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 176 /* 0x07 - 640x480@85Hz */ 177 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 178 752, 832, 0, 480, 481, 484, 509, 0, 179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 180 /* 0x08 - 800x600@56Hz */ 181 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 182 896, 1024, 0, 600, 601, 603, 625, 0, 183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 184 /* 0x09 - 800x600@60Hz */ 185 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 186 968, 1056, 0, 600, 601, 605, 628, 0, 187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 188 /* 0x0a - 800x600@72Hz */ 189 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 190 976, 1040, 0, 600, 637, 643, 666, 0, 191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 192 /* 0x0b - 800x600@75Hz */ 193 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 194 896, 1056, 0, 600, 601, 604, 625, 0, 195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 196 /* 0x0c - 800x600@85Hz */ 197 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 198 896, 1048, 0, 600, 601, 604, 631, 0, 199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 200 /* 0x0d - 800x600@120Hz RB */ 201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 202 880, 960, 0, 600, 603, 607, 636, 0, 203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 204 /* 0x0e - 848x480@60Hz */ 205 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 206 976, 1088, 0, 480, 486, 494, 517, 0, 207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 208 /* 0x0f - 1024x768@43Hz, interlace */ 209 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 210 1208, 1264, 0, 768, 768, 772, 817, 0, 211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 212 DRM_MODE_FLAG_INTERLACE) }, 213 /* 0x10 - 1024x768@60Hz */ 214 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 215 1184, 1344, 0, 768, 771, 777, 806, 0, 216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 217 /* 0x11 - 1024x768@70Hz */ 218 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 219 1184, 1328, 0, 768, 771, 777, 806, 0, 220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 221 /* 0x12 - 1024x768@75Hz */ 222 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 223 1136, 1312, 0, 768, 769, 772, 800, 0, 224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 225 /* 0x13 - 1024x768@85Hz */ 226 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 227 1168, 1376, 0, 768, 769, 772, 808, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 229 /* 0x14 - 1024x768@120Hz RB */ 230 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 231 1104, 1184, 0, 768, 771, 775, 813, 0, 232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 233 /* 0x15 - 1152x864@75Hz */ 234 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 235 1344, 1600, 0, 864, 865, 868, 900, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x55 - 1280x720@60Hz */ 238 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 239 1430, 1650, 0, 720, 725, 730, 750, 0, 240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 241 /* 0x16 - 1280x768@60Hz RB */ 242 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 243 1360, 1440, 0, 768, 771, 778, 790, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x17 - 1280x768@60Hz */ 246 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 247 1472, 1664, 0, 768, 771, 778, 798, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x18 - 1280x768@75Hz */ 250 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 251 1488, 1696, 0, 768, 771, 778, 805, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 0x19 - 1280x768@85Hz */ 254 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 255 1496, 1712, 0, 768, 771, 778, 809, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x1a - 1280x768@120Hz RB */ 258 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 259 1360, 1440, 0, 768, 771, 778, 813, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x1b - 1280x800@60Hz RB */ 262 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 263 1360, 1440, 0, 800, 803, 809, 823, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 0x1c - 1280x800@60Hz */ 266 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 267 1480, 1680, 0, 800, 803, 809, 831, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x1d - 1280x800@75Hz */ 270 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 271 1488, 1696, 0, 800, 803, 809, 838, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x1e - 1280x800@85Hz */ 274 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 275 1496, 1712, 0, 800, 803, 809, 843, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x1f - 1280x800@120Hz RB */ 278 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 279 1360, 1440, 0, 800, 803, 809, 847, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 281 /* 0x20 - 1280x960@60Hz */ 282 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 283 1488, 1800, 0, 960, 961, 964, 1000, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 0x21 - 1280x960@85Hz */ 286 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 287 1504, 1728, 0, 960, 961, 964, 1011, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x22 - 1280x960@120Hz RB */ 290 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 291 1360, 1440, 0, 960, 963, 967, 1017, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x23 - 1280x1024@60Hz */ 294 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 295 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x24 - 1280x1024@75Hz */ 298 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 299 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x25 - 1280x1024@85Hz */ 302 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 303 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 0x26 - 1280x1024@120Hz RB */ 306 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 307 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x27 - 1360x768@60Hz */ 310 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 311 1536, 1792, 0, 768, 771, 777, 795, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x28 - 1360x768@120Hz RB */ 314 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 315 1440, 1520, 0, 768, 771, 776, 813, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 0x51 - 1366x768@60Hz */ 318 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 319 1579, 1792, 0, 768, 771, 774, 798, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x56 - 1366x768@60Hz */ 322 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 323 1436, 1500, 0, 768, 769, 772, 800, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x29 - 1400x1050@60Hz RB */ 326 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 327 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 329 /* 0x2a - 1400x1050@60Hz */ 330 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 331 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 332 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x2b - 1400x1050@75Hz */ 334 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 335 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 337 /* 0x2c - 1400x1050@85Hz */ 338 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 339 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x2d - 1400x1050@120Hz RB */ 342 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 343 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 345 /* 0x2e - 1440x900@60Hz RB */ 346 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 347 1520, 1600, 0, 900, 903, 909, 926, 0, 348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 349 /* 0x2f - 1440x900@60Hz */ 350 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 351 1672, 1904, 0, 900, 903, 909, 934, 0, 352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 353 /* 0x30 - 1440x900@75Hz */ 354 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 355 1688, 1936, 0, 900, 903, 909, 942, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x31 - 1440x900@85Hz */ 358 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 359 1696, 1952, 0, 900, 903, 909, 948, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x32 - 1440x900@120Hz RB */ 362 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 363 1520, 1600, 0, 900, 903, 909, 953, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 365 /* 0x53 - 1600x900@60Hz */ 366 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 367 1704, 1800, 0, 900, 901, 904, 1000, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x33 - 1600x1200@60Hz */ 370 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 371 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x34 - 1600x1200@65Hz */ 374 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 375 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x35 - 1600x1200@70Hz */ 378 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 379 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x36 - 1600x1200@75Hz */ 382 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 383 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x37 - 1600x1200@85Hz */ 386 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 387 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x38 - 1600x1200@120Hz RB */ 390 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 391 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 393 /* 0x39 - 1680x1050@60Hz RB */ 394 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 395 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 397 /* 0x3a - 1680x1050@60Hz */ 398 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 399 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 400 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 0x3b - 1680x1050@75Hz */ 402 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 403 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x3c - 1680x1050@85Hz */ 406 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 407 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x3d - 1680x1050@120Hz RB */ 410 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 411 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 413 /* 0x3e - 1792x1344@60Hz */ 414 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 415 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x3f - 1792x1344@75Hz */ 418 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 419 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 421 /* 0x40 - 1792x1344@120Hz RB */ 422 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 423 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 425 /* 0x41 - 1856x1392@60Hz */ 426 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 427 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x42 - 1856x1392@75Hz */ 430 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 431 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x43 - 1856x1392@120Hz RB */ 434 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 435 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x52 - 1920x1080@60Hz */ 438 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 439 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 441 /* 0x44 - 1920x1200@60Hz RB */ 442 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 443 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 445 /* 0x45 - 1920x1200@60Hz */ 446 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 447 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x46 - 1920x1200@75Hz */ 450 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 451 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x47 - 1920x1200@85Hz */ 454 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 455 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x48 - 1920x1200@120Hz RB */ 458 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 459 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 461 /* 0x49 - 1920x1440@60Hz */ 462 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 463 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x4a - 1920x1440@75Hz */ 466 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 467 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 0x4b - 1920x1440@120Hz RB */ 470 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 471 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 473 /* 0x54 - 2048x1152@60Hz */ 474 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 475 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x4c - 2560x1600@60Hz RB */ 478 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 479 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 481 /* 0x4d - 2560x1600@60Hz */ 482 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 483 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 485 /* 0x4e - 2560x1600@75Hz */ 486 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 487 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x4f - 2560x1600@85Hz */ 490 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 491 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x50 - 2560x1600@120Hz RB */ 494 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 495 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 497 /* 0x57 - 4096x2160@60Hz RB */ 498 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 499 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 501 /* 0x58 - 4096x2160@59.94Hz RB */ 502 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 503 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 505 }; 506 507 /* 508 * These more or less come from the DMT spec. The 720x400 modes are 509 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 510 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 511 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 512 * mode. 513 * 514 * The DMT modes have been fact-checked; the rest are mild guesses. 515 */ 516 static const struct drm_display_mode edid_est_modes[] = { 517 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 518 968, 1056, 0, 600, 601, 605, 628, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 520 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 521 896, 1024, 0, 600, 601, 603, 625, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 523 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 524 720, 840, 0, 480, 481, 484, 500, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 526 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 527 704, 832, 0, 480, 489, 491, 520, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 529 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 530 768, 864, 0, 480, 483, 486, 525, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 533 752, 800, 0, 480, 490, 492, 525, 0, 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 535 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 536 846, 900, 0, 400, 421, 423, 449, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 538 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 539 846, 900, 0, 400, 412, 414, 449, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 541 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 542 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 544 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 545 1136, 1312, 0, 768, 769, 772, 800, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 547 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 548 1184, 1328, 0, 768, 771, 777, 806, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 550 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 551 1184, 1344, 0, 768, 771, 777, 806, 0, 552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 553 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 554 1208, 1264, 0, 768, 768, 776, 817, 0, 555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 556 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 557 928, 1152, 0, 624, 625, 628, 667, 0, 558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 559 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 560 896, 1056, 0, 600, 601, 604, 625, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 562 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 563 976, 1040, 0, 600, 637, 643, 666, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 565 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 566 1344, 1600, 0, 864, 865, 868, 900, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 568 }; 569 570 struct minimode { 571 short w; 572 short h; 573 short r; 574 short rb; 575 }; 576 577 static const struct minimode est3_modes[] = { 578 /* byte 6 */ 579 { 640, 350, 85, 0 }, 580 { 640, 400, 85, 0 }, 581 { 720, 400, 85, 0 }, 582 { 640, 480, 85, 0 }, 583 { 848, 480, 60, 0 }, 584 { 800, 600, 85, 0 }, 585 { 1024, 768, 85, 0 }, 586 { 1152, 864, 75, 0 }, 587 /* byte 7 */ 588 { 1280, 768, 60, 1 }, 589 { 1280, 768, 60, 0 }, 590 { 1280, 768, 75, 0 }, 591 { 1280, 768, 85, 0 }, 592 { 1280, 960, 60, 0 }, 593 { 1280, 960, 85, 0 }, 594 { 1280, 1024, 60, 0 }, 595 { 1280, 1024, 85, 0 }, 596 /* byte 8 */ 597 { 1360, 768, 60, 0 }, 598 { 1440, 900, 60, 1 }, 599 { 1440, 900, 60, 0 }, 600 { 1440, 900, 75, 0 }, 601 { 1440, 900, 85, 0 }, 602 { 1400, 1050, 60, 1 }, 603 { 1400, 1050, 60, 0 }, 604 { 1400, 1050, 75, 0 }, 605 /* byte 9 */ 606 { 1400, 1050, 85, 0 }, 607 { 1680, 1050, 60, 1 }, 608 { 1680, 1050, 60, 0 }, 609 { 1680, 1050, 75, 0 }, 610 { 1680, 1050, 85, 0 }, 611 { 1600, 1200, 60, 0 }, 612 { 1600, 1200, 65, 0 }, 613 { 1600, 1200, 70, 0 }, 614 /* byte 10 */ 615 { 1600, 1200, 75, 0 }, 616 { 1600, 1200, 85, 0 }, 617 { 1792, 1344, 60, 0 }, 618 { 1792, 1344, 75, 0 }, 619 { 1856, 1392, 60, 0 }, 620 { 1856, 1392, 75, 0 }, 621 { 1920, 1200, 60, 1 }, 622 { 1920, 1200, 60, 0 }, 623 /* byte 11 */ 624 { 1920, 1200, 75, 0 }, 625 { 1920, 1200, 85, 0 }, 626 { 1920, 1440, 60, 0 }, 627 { 1920, 1440, 75, 0 }, 628 }; 629 630 static const struct minimode extra_modes[] = { 631 { 1024, 576, 60, 0 }, 632 { 1366, 768, 60, 0 }, 633 { 1600, 900, 60, 0 }, 634 { 1680, 945, 60, 0 }, 635 { 1920, 1080, 60, 0 }, 636 { 2048, 1152, 60, 0 }, 637 { 2048, 1536, 60, 0 }, 638 }; 639 640 /* 641 * Probably taken from CEA-861 spec. 642 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 643 */ 644 static const struct drm_display_mode edid_cea_modes[] = { 645 /* 1 - 640x480@60Hz */ 646 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 647 752, 800, 0, 480, 490, 492, 525, 0, 648 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 649 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 650 /* 2 - 720x480@60Hz */ 651 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 652 798, 858, 0, 480, 489, 495, 525, 0, 653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 654 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 655 /* 3 - 720x480@60Hz */ 656 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 657 798, 858, 0, 480, 489, 495, 525, 0, 658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 659 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 660 /* 4 - 1280x720@60Hz */ 661 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 662 1430, 1650, 0, 720, 725, 730, 750, 0, 663 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 664 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 665 /* 5 - 1920x1080i@60Hz */ 666 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 667 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 669 DRM_MODE_FLAG_INTERLACE), 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 671 /* 6 - 720(1440)x480i@60Hz */ 672 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 673 801, 858, 0, 480, 488, 494, 525, 0, 674 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 675 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 677 /* 7 - 720(1440)x480i@60Hz */ 678 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 679 801, 858, 0, 480, 488, 494, 525, 0, 680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 681 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 682 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 683 /* 8 - 720(1440)x240@60Hz */ 684 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 685 801, 858, 0, 240, 244, 247, 262, 0, 686 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 687 DRM_MODE_FLAG_DBLCLK), 688 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 689 /* 9 - 720(1440)x240@60Hz */ 690 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 691 801, 858, 0, 240, 244, 247, 262, 0, 692 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 693 DRM_MODE_FLAG_DBLCLK), 694 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 695 /* 10 - 2880x480i@60Hz */ 696 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 697 3204, 3432, 0, 480, 488, 494, 525, 0, 698 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 699 DRM_MODE_FLAG_INTERLACE), 700 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 701 /* 11 - 2880x480i@60Hz */ 702 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 703 3204, 3432, 0, 480, 488, 494, 525, 0, 704 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 705 DRM_MODE_FLAG_INTERLACE), 706 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 707 /* 12 - 2880x240@60Hz */ 708 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 709 3204, 3432, 0, 240, 244, 247, 262, 0, 710 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 711 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 712 /* 13 - 2880x240@60Hz */ 713 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 714 3204, 3432, 0, 240, 244, 247, 262, 0, 715 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 717 /* 14 - 1440x480@60Hz */ 718 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 719 1596, 1716, 0, 480, 489, 495, 525, 0, 720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 722 /* 15 - 1440x480@60Hz */ 723 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 724 1596, 1716, 0, 480, 489, 495, 525, 0, 725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 726 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 727 /* 16 - 1920x1080@60Hz */ 728 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 729 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 730 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 732 /* 17 - 720x576@50Hz */ 733 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 734 796, 864, 0, 576, 581, 586, 625, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 736 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 737 /* 18 - 720x576@50Hz */ 738 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 739 796, 864, 0, 576, 581, 586, 625, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 741 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 742 /* 19 - 1280x720@50Hz */ 743 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 744 1760, 1980, 0, 720, 725, 730, 750, 0, 745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 746 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 747 /* 20 - 1920x1080i@50Hz */ 748 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 749 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 750 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 751 DRM_MODE_FLAG_INTERLACE), 752 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 753 /* 21 - 720(1440)x576i@50Hz */ 754 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 755 795, 864, 0, 576, 580, 586, 625, 0, 756 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 757 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 758 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 759 /* 22 - 720(1440)x576i@50Hz */ 760 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 761 795, 864, 0, 576, 580, 586, 625, 0, 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 763 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 764 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 765 /* 23 - 720(1440)x288@50Hz */ 766 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 767 795, 864, 0, 288, 290, 293, 312, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 769 DRM_MODE_FLAG_DBLCLK), 770 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 771 /* 24 - 720(1440)x288@50Hz */ 772 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 773 795, 864, 0, 288, 290, 293, 312, 0, 774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 775 DRM_MODE_FLAG_DBLCLK), 776 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 777 /* 25 - 2880x576i@50Hz */ 778 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 779 3180, 3456, 0, 576, 580, 586, 625, 0, 780 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 781 DRM_MODE_FLAG_INTERLACE), 782 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 783 /* 26 - 2880x576i@50Hz */ 784 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 785 3180, 3456, 0, 576, 580, 586, 625, 0, 786 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 787 DRM_MODE_FLAG_INTERLACE), 788 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 789 /* 27 - 2880x288@50Hz */ 790 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 791 3180, 3456, 0, 288, 290, 293, 312, 0, 792 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 793 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 794 /* 28 - 2880x288@50Hz */ 795 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 796 3180, 3456, 0, 288, 290, 293, 312, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 798 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 799 /* 29 - 1440x576@50Hz */ 800 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 801 1592, 1728, 0, 576, 581, 586, 625, 0, 802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 804 /* 30 - 1440x576@50Hz */ 805 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 806 1592, 1728, 0, 576, 581, 586, 625, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 809 /* 31 - 1920x1080@50Hz */ 810 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 811 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 812 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 814 /* 32 - 1920x1080@24Hz */ 815 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 816 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 818 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 819 /* 33 - 1920x1080@25Hz */ 820 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 821 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 823 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 824 /* 34 - 1920x1080@30Hz */ 825 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 826 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 829 /* 35 - 2880x480@60Hz */ 830 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 831 3192, 3432, 0, 480, 489, 495, 525, 0, 832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 833 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 834 /* 36 - 2880x480@60Hz */ 835 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 836 3192, 3432, 0, 480, 489, 495, 525, 0, 837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 838 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 37 - 2880x576@50Hz */ 840 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 841 3184, 3456, 0, 576, 581, 586, 625, 0, 842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 843 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 844 /* 38 - 2880x576@50Hz */ 845 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 846 3184, 3456, 0, 576, 581, 586, 625, 0, 847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 848 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 39 - 1920x1080i@50Hz */ 850 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 851 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 853 DRM_MODE_FLAG_INTERLACE), 854 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 855 /* 40 - 1920x1080i@100Hz */ 856 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 857 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 859 DRM_MODE_FLAG_INTERLACE), 860 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 861 /* 41 - 1280x720@100Hz */ 862 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 863 1760, 1980, 0, 720, 725, 730, 750, 0, 864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 865 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 866 /* 42 - 720x576@100Hz */ 867 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 868 796, 864, 0, 576, 581, 586, 625, 0, 869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 870 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 871 /* 43 - 720x576@100Hz */ 872 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 873 796, 864, 0, 576, 581, 586, 625, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 875 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 876 /* 44 - 720(1440)x576i@100Hz */ 877 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 878 795, 864, 0, 576, 580, 586, 625, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 880 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 881 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 882 /* 45 - 720(1440)x576i@100Hz */ 883 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 884 795, 864, 0, 576, 580, 586, 625, 0, 885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 886 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 887 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 46 - 1920x1080i@120Hz */ 889 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 890 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 892 DRM_MODE_FLAG_INTERLACE), 893 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 894 /* 47 - 1280x720@120Hz */ 895 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 896 1430, 1650, 0, 720, 725, 730, 750, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 899 /* 48 - 720x480@120Hz */ 900 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 901 798, 858, 0, 480, 489, 495, 525, 0, 902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 903 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 904 /* 49 - 720x480@120Hz */ 905 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 906 798, 858, 0, 480, 489, 495, 525, 0, 907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 50 - 720(1440)x480i@120Hz */ 910 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 911 801, 858, 0, 480, 488, 494, 525, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 913 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 914 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 915 /* 51 - 720(1440)x480i@120Hz */ 916 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 917 801, 858, 0, 480, 488, 494, 525, 0, 918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 919 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 920 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 52 - 720x576@200Hz */ 922 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 923 796, 864, 0, 576, 581, 586, 625, 0, 924 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 925 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 926 /* 53 - 720x576@200Hz */ 927 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 928 796, 864, 0, 576, 581, 586, 625, 0, 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 930 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 54 - 720(1440)x576i@200Hz */ 932 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 933 795, 864, 0, 576, 580, 586, 625, 0, 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 935 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 936 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 937 /* 55 - 720(1440)x576i@200Hz */ 938 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 939 795, 864, 0, 576, 580, 586, 625, 0, 940 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 941 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 942 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 943 /* 56 - 720x480@240Hz */ 944 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 945 798, 858, 0, 480, 489, 495, 525, 0, 946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 947 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 948 /* 57 - 720x480@240Hz */ 949 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 950 798, 858, 0, 480, 489, 495, 525, 0, 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 952 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 953 /* 58 - 720(1440)x480i@240 */ 954 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 955 801, 858, 0, 480, 488, 494, 525, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 957 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 958 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 959 /* 59 - 720(1440)x480i@240 */ 960 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 961 801, 858, 0, 480, 488, 494, 525, 0, 962 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 963 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 964 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 965 /* 60 - 1280x720@24Hz */ 966 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 967 3080, 3300, 0, 720, 725, 730, 750, 0, 968 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 969 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 970 /* 61 - 1280x720@25Hz */ 971 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 972 3740, 3960, 0, 720, 725, 730, 750, 0, 973 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 974 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 975 /* 62 - 1280x720@30Hz */ 976 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 977 3080, 3300, 0, 720, 725, 730, 750, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 979 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 980 /* 63 - 1920x1080@120Hz */ 981 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 982 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 984 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 64 - 1920x1080@100Hz */ 986 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 987 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 989 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 990 }; 991 992 /* 993 * HDMI 1.4 4k modes. 994 */ 995 static const struct drm_display_mode edid_4k_modes[] = { 996 /* 1 - 3840x2160@30Hz */ 997 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 998 3840, 4016, 4104, 4400, 0, 999 2160, 2168, 2178, 2250, 0, 1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1001 .vrefresh = 30, }, 1002 /* 2 - 3840x2160@25Hz */ 1003 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1004 3840, 4896, 4984, 5280, 0, 1005 2160, 2168, 2178, 2250, 0, 1006 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1007 .vrefresh = 25, }, 1008 /* 3 - 3840x2160@24Hz */ 1009 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1010 3840, 5116, 5204, 5500, 0, 1011 2160, 2168, 2178, 2250, 0, 1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1013 .vrefresh = 24, }, 1014 /* 4 - 4096x2160@24Hz (SMPTE) */ 1015 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1016 4096, 5116, 5204, 5500, 0, 1017 2160, 2168, 2178, 2250, 0, 1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1019 .vrefresh = 24, }, 1020 }; 1021 1022 /*** DDC fetch and block validation ***/ 1023 1024 static const u8 edid_header[] = { 1025 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1026 }; 1027 1028 /** 1029 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1030 * @raw_edid: pointer to raw base EDID block 1031 * 1032 * Sanity check the header of the base EDID block. 1033 * 1034 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1035 */ 1036 int drm_edid_header_is_valid(const u8 *raw_edid) 1037 { 1038 int i, score = 0; 1039 1040 for (i = 0; i < sizeof(edid_header); i++) 1041 if (raw_edid[i] == edid_header[i]) 1042 score++; 1043 1044 return score; 1045 } 1046 EXPORT_SYMBOL(drm_edid_header_is_valid); 1047 1048 static int edid_fixup __read_mostly = 6; 1049 module_param_named(edid_fixup, edid_fixup, int, 0400); 1050 MODULE_PARM_DESC(edid_fixup, 1051 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1052 1053 static int drm_edid_block_checksum(const u8 *raw_edid) 1054 { 1055 int i; 1056 u8 csum = 0; 1057 for (i = 0; i < EDID_LENGTH; i++) 1058 csum += raw_edid[i]; 1059 1060 return csum; 1061 } 1062 1063 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1064 { 1065 if (memchr_inv(in_edid, 0, length)) 1066 return false; 1067 1068 return true; 1069 } 1070 1071 /** 1072 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1073 * @raw_edid: pointer to raw EDID block 1074 * @block: type of block to validate (0 for base, extension otherwise) 1075 * @print_bad_edid: if true, dump bad EDID blocks to the console 1076 * @edid_corrupt: if true, the header or checksum is invalid 1077 * 1078 * Validate a base or extension EDID block and optionally dump bad blocks to 1079 * the console. 1080 * 1081 * Return: True if the block is valid, false otherwise. 1082 */ 1083 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1084 bool *edid_corrupt) 1085 { 1086 int i; 1087 u8 csum; 1088 struct edid *edid = (struct edid *)raw_edid; 1089 1090 if (WARN_ON(!raw_edid)) 1091 return false; 1092 1093 if (edid_fixup > 8 || edid_fixup < 0) 1094 edid_fixup = 6; 1095 1096 if (block == 0) { 1097 int score = drm_edid_header_is_valid(raw_edid); 1098 if (score == 8) { 1099 if (edid_corrupt) 1100 *edid_corrupt = false; 1101 } else if (score >= edid_fixup) { 1102 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1103 * The corrupt flag needs to be set here otherwise, the 1104 * fix-up code here will correct the problem, the 1105 * checksum is correct and the test fails 1106 */ 1107 if (edid_corrupt) 1108 *edid_corrupt = true; 1109 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1110 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1111 } else { 1112 if (edid_corrupt) 1113 *edid_corrupt = true; 1114 goto bad; 1115 } 1116 } 1117 1118 csum = drm_edid_block_checksum(raw_edid); 1119 if (csum) { 1120 if (print_bad_edid) { 1121 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1122 } 1123 1124 if (edid_corrupt) 1125 *edid_corrupt = true; 1126 1127 /* allow CEA to slide through, switches mangle this */ 1128 if (raw_edid[0] != 0x02) 1129 goto bad; 1130 } 1131 1132 /* per-block-type checks */ 1133 switch (raw_edid[0]) { 1134 case 0: /* base */ 1135 if (edid->version != 1) { 1136 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1137 goto bad; 1138 } 1139 1140 if (edid->revision > 4) 1141 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1142 break; 1143 1144 default: 1145 break; 1146 } 1147 1148 return true; 1149 1150 bad: 1151 if (print_bad_edid) { 1152 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1153 printk(KERN_ERR "EDID block is all zeroes\n"); 1154 } else { 1155 printk(KERN_ERR "Raw EDID:\n"); 1156 for (i = 0; i < EDID_LENGTH; ) { 1157 kprintf("%02x", raw_edid[i]); 1158 i++; 1159 if (i % 16 == 0 || i == EDID_LENGTH) 1160 kprintf("\n"); 1161 else if (i % 8 == 0) 1162 kprintf(" "); 1163 else 1164 kprintf(" "); 1165 } 1166 } 1167 } 1168 return false; 1169 } 1170 EXPORT_SYMBOL(drm_edid_block_valid); 1171 1172 /** 1173 * drm_edid_is_valid - sanity check EDID data 1174 * @edid: EDID data 1175 * 1176 * Sanity-check an entire EDID record (including extensions) 1177 * 1178 * Return: True if the EDID data is valid, false otherwise. 1179 */ 1180 bool drm_edid_is_valid(struct edid *edid) 1181 { 1182 int i; 1183 u8 *raw = (u8 *)edid; 1184 1185 if (!edid) 1186 return false; 1187 1188 for (i = 0; i <= edid->extensions; i++) 1189 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1190 return false; 1191 1192 return true; 1193 } 1194 EXPORT_SYMBOL(drm_edid_is_valid); 1195 1196 #define DDC_SEGMENT_ADDR 0x30 1197 /** 1198 * drm_do_probe_ddc_edid() - get EDID information via I2C 1199 * @data: I2C device adapter 1200 * @buf: EDID data buffer to be filled 1201 * @block: 128 byte EDID block to start fetching from 1202 * @len: EDID data buffer length to fetch 1203 * 1204 * Try to fetch EDID information by calling I2C driver functions. 1205 * 1206 * Return: 0 on success or -1 on failure. 1207 */ 1208 static int 1209 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1210 { 1211 struct i2c_adapter *adapter = data; 1212 unsigned char start = block * EDID_LENGTH; 1213 unsigned char segment = block >> 1; 1214 unsigned char xfers = segment ? 3 : 2; 1215 int ret, retries = 5; 1216 1217 /* 1218 * The core I2C driver will automatically retry the transfer if the 1219 * adapter reports EAGAIN. However, we find that bit-banging transfers 1220 * are susceptible to errors under a heavily loaded machine and 1221 * generate spurious NAKs and timeouts. Retrying the transfer 1222 * of the individual block a few times seems to overcome this. 1223 */ 1224 do { 1225 struct i2c_msg msgs[] = { 1226 { 1227 .addr = DDC_SEGMENT_ADDR, 1228 .flags = 0, 1229 .len = 1, 1230 .buf = &segment, 1231 }, { 1232 .addr = DDC_ADDR, 1233 .flags = 0, 1234 .len = 1, 1235 .buf = &start, 1236 }, { 1237 .addr = DDC_ADDR, 1238 .flags = I2C_M_RD, 1239 .len = len, 1240 .buf = buf, 1241 } 1242 }; 1243 1244 /* 1245 * Avoid sending the segment addr to not upset non-compliant 1246 * DDC monitors. 1247 */ 1248 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1249 1250 if (ret == -ENXIO) { 1251 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1252 adapter->name); 1253 break; 1254 } 1255 } while (ret != xfers && --retries); 1256 1257 return ret == xfers ? 0 : -1; 1258 } 1259 1260 /* 1261 * Old version of drm_do_probe_ddc_edid, still using 1262 * the FreeBSD/DragonFly iic API 1263 */ 1264 static int 1265 drm_do_probe_ddc_edid_iic(void *data, u8 *buf, unsigned int block, size_t len) 1266 { 1267 device_t adapter = data; 1268 unsigned char start = block * EDID_LENGTH; 1269 unsigned char segment = block >> 1; 1270 unsigned char xfers = segment ? 3 : 2; 1271 int ret, retries = 5; 1272 1273 /* 1274 * The core I2C driver will automatically retry the transfer if the 1275 * adapter reports EAGAIN. However, we find that bit-banging transfers 1276 * are susceptible to errors under a heavily loaded machine and 1277 * generate spurious NAKs and timeouts. Retrying the transfer 1278 * of the individual block a few times seems to overcome this. 1279 */ 1280 do { 1281 struct iic_msg msgs[] = { 1282 { 1283 .slave = DDC_SEGMENT_ADDR << 1, 1284 .flags = 0, 1285 .len = 1, 1286 .buf = &segment, 1287 }, { 1288 .slave = DDC_ADDR << 1, 1289 .flags = 0, 1290 .len = 1, 1291 .buf = &start, 1292 }, { 1293 .slave = DDC_ADDR << 1, 1294 .flags = I2C_M_RD, 1295 .len = len, 1296 .buf = buf, 1297 } 1298 }; 1299 1300 /* 1301 * Avoid sending the segment addr to not upset non-compliant 1302 * DDC monitors. 1303 */ 1304 ret = iicbus_transfer(adapter, &msgs[3 - xfers], xfers); 1305 1306 if (ret != 0) 1307 DRM_DEBUG_KMS("iicbus_transfer countdown %d error %d\n", 1308 retries, ret); 1309 } while (ret != 0 && --retries); 1310 1311 return (ret == 0 ? 0 : -1); 1312 } 1313 1314 /** 1315 * drm_do_get_edid - get EDID data using a custom EDID block read function 1316 * @connector: connector we're probing 1317 * @get_edid_block: EDID block read function 1318 * @data: private data passed to the block read function 1319 * 1320 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1321 * exposes a different interface to read EDID blocks this function can be used 1322 * to get EDID data using a custom block read function. 1323 * 1324 * As in the general case the DDC bus is accessible by the kernel at the I2C 1325 * level, drivers must make all reasonable efforts to expose it as an I2C 1326 * adapter and use drm_get_edid() instead of abusing this function. 1327 * 1328 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1329 */ 1330 struct edid *drm_do_get_edid(struct drm_connector *connector, 1331 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1332 size_t len), 1333 void *data) 1334 { 1335 int i, j = 0, valid_extensions = 0; 1336 u8 *block, *new; 1337 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1338 1339 if ((block = kmalloc(EDID_LENGTH, M_DRM, M_WAITOK)) == NULL) 1340 return NULL; 1341 1342 /* base block fetch */ 1343 for (i = 0; i < 4; i++) { 1344 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1345 goto out; 1346 if (drm_edid_block_valid(block, 0, print_bad_edid, 1347 &connector->edid_corrupt)) 1348 break; 1349 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1350 connector->null_edid_counter++; 1351 goto carp; 1352 } 1353 } 1354 if (i == 4) 1355 goto carp; 1356 1357 /* if there's no extensions, we're done */ 1358 if (block[0x7e] == 0) 1359 return (struct edid *)block; 1360 1361 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1362 if (!new) 1363 goto out; 1364 block = new; 1365 1366 for (j = 1; j <= block[0x7e]; j++) { 1367 for (i = 0; i < 4; i++) { 1368 if (get_edid_block(data, 1369 block + (valid_extensions + 1) * EDID_LENGTH, 1370 j, EDID_LENGTH)) 1371 goto out; 1372 if (drm_edid_block_valid(block + (valid_extensions + 1) 1373 * EDID_LENGTH, j, 1374 print_bad_edid, 1375 NULL)) { 1376 valid_extensions++; 1377 break; 1378 } 1379 } 1380 1381 if (i == 4 && print_bad_edid) { 1382 dev_warn(connector->dev->dev, 1383 "%s: Ignoring invalid EDID block %d.\n", 1384 connector->name, j); 1385 1386 connector->bad_edid_counter++; 1387 } 1388 } 1389 1390 if (valid_extensions != block[0x7e]) { 1391 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1392 block[0x7e] = valid_extensions; 1393 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1394 if (!new) 1395 goto out; 1396 block = new; 1397 } 1398 1399 return (struct edid *)block; 1400 1401 carp: 1402 if (print_bad_edid) { 1403 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1404 connector->name, j); 1405 } 1406 connector->bad_edid_counter++; 1407 1408 out: 1409 kfree(block); 1410 return NULL; 1411 } 1412 1413 /** 1414 * drm_probe_ddc() - probe DDC presence 1415 * @adapter: I2C adapter to probe 1416 * 1417 * Return: True on success, false on failure. 1418 */ 1419 bool 1420 drm_probe_ddc(struct i2c_adapter *adapter) 1421 { 1422 unsigned char out; 1423 1424 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1425 } 1426 EXPORT_SYMBOL(drm_probe_ddc); 1427 1428 /* 1429 * Old version of drm_probe_ddc(), still using 1430 * the FreeBSD/DragonFly iic API 1431 */ 1432 static bool 1433 drm_probe_ddc_iic(device_t adapter) 1434 { 1435 unsigned char out; 1436 1437 return (drm_do_probe_ddc_edid_iic(adapter, &out, 0, 1) == 0); 1438 } 1439 1440 /** 1441 * drm_get_edid - get EDID data, if available 1442 * @connector: connector we're probing 1443 * @adapter: I2C adapter to use for DDC 1444 * 1445 * Poke the given I2C channel to grab EDID data if possible. If found, 1446 * attach it to the connector. 1447 * 1448 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1449 */ 1450 struct edid *drm_get_edid(struct drm_connector *connector, 1451 struct i2c_adapter *adapter) 1452 { 1453 if (!drm_probe_ddc(adapter)) 1454 return NULL; 1455 1456 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1457 } 1458 EXPORT_SYMBOL(drm_get_edid); 1459 1460 /* 1461 * Old version of drm_get_edid(), still using 1462 * the FreeBSD/DragonFly iic API 1463 */ 1464 struct edid *drm_get_edid_iic(struct drm_connector *connector, 1465 device_t adapter) 1466 { 1467 if (!drm_probe_ddc_iic(adapter)) 1468 return NULL; 1469 1470 return drm_do_get_edid(connector, drm_do_probe_ddc_edid_iic, adapter); 1471 } 1472 1473 /** 1474 * drm_edid_duplicate - duplicate an EDID and the extensions 1475 * @edid: EDID to duplicate 1476 * 1477 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1478 */ 1479 struct edid *drm_edid_duplicate(const struct edid *edid) 1480 { 1481 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1482 } 1483 EXPORT_SYMBOL(drm_edid_duplicate); 1484 1485 /*** EDID parsing ***/ 1486 1487 /** 1488 * edid_vendor - match a string against EDID's obfuscated vendor field 1489 * @edid: EDID to match 1490 * @vendor: vendor string 1491 * 1492 * Returns true if @vendor is in @edid, false otherwise 1493 */ 1494 static bool edid_vendor(struct edid *edid, char *vendor) 1495 { 1496 char edid_vendor[3]; 1497 1498 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1499 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1500 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1501 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1502 1503 return !strncmp(edid_vendor, vendor, 3); 1504 } 1505 1506 /** 1507 * edid_get_quirks - return quirk flags for a given EDID 1508 * @edid: EDID to process 1509 * 1510 * This tells subsequent routines what fixes they need to apply. 1511 */ 1512 static u32 edid_get_quirks(struct edid *edid) 1513 { 1514 struct edid_quirk *quirk; 1515 int i; 1516 1517 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1518 quirk = &edid_quirk_list[i]; 1519 1520 if (edid_vendor(edid, quirk->vendor) && 1521 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1522 return quirk->quirks; 1523 } 1524 1525 return 0; 1526 } 1527 1528 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1529 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1530 1531 /** 1532 * edid_fixup_preferred - set preferred modes based on quirk list 1533 * @connector: has mode list to fix up 1534 * @quirks: quirks list 1535 * 1536 * Walk the mode list for @connector, clearing the preferred status 1537 * on existing modes and setting it anew for the right mode ala @quirks. 1538 */ 1539 static void edid_fixup_preferred(struct drm_connector *connector, 1540 u32 quirks) 1541 { 1542 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1543 int target_refresh = 0; 1544 int cur_vrefresh, preferred_vrefresh; 1545 1546 if (list_empty(&connector->probed_modes)) 1547 return; 1548 1549 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1550 target_refresh = 60; 1551 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1552 target_refresh = 75; 1553 1554 preferred_mode = list_first_entry(&connector->probed_modes, 1555 struct drm_display_mode, head); 1556 1557 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1558 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1559 1560 if (cur_mode == preferred_mode) 1561 continue; 1562 1563 /* Largest mode is preferred */ 1564 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1565 preferred_mode = cur_mode; 1566 1567 cur_vrefresh = cur_mode->vrefresh ? 1568 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1569 preferred_vrefresh = preferred_mode->vrefresh ? 1570 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1571 /* At a given size, try to get closest to target refresh */ 1572 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1573 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1574 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1575 preferred_mode = cur_mode; 1576 } 1577 } 1578 1579 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1580 } 1581 1582 static bool 1583 mode_is_rb(const struct drm_display_mode *mode) 1584 { 1585 return (mode->htotal - mode->hdisplay == 160) && 1586 (mode->hsync_end - mode->hdisplay == 80) && 1587 (mode->hsync_end - mode->hsync_start == 32) && 1588 (mode->vsync_start - mode->vdisplay == 3); 1589 } 1590 1591 /* 1592 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1593 * @dev: Device to duplicate against 1594 * @hsize: Mode width 1595 * @vsize: Mode height 1596 * @fresh: Mode refresh rate 1597 * @rb: Mode reduced-blanking-ness 1598 * 1599 * Walk the DMT mode list looking for a match for the given parameters. 1600 * 1601 * Return: A newly allocated copy of the mode, or NULL if not found. 1602 */ 1603 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1604 int hsize, int vsize, int fresh, 1605 bool rb) 1606 { 1607 int i; 1608 1609 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1610 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1611 if (hsize != ptr->hdisplay) 1612 continue; 1613 if (vsize != ptr->vdisplay) 1614 continue; 1615 if (fresh != drm_mode_vrefresh(ptr)) 1616 continue; 1617 if (rb != mode_is_rb(ptr)) 1618 continue; 1619 1620 return drm_mode_duplicate(dev, ptr); 1621 } 1622 1623 return NULL; 1624 } 1625 EXPORT_SYMBOL(drm_mode_find_dmt); 1626 1627 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1628 1629 static void 1630 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1631 { 1632 int i, n = 0; 1633 u8 d = ext[0x02]; 1634 u8 *det_base = ext + d; 1635 1636 n = (127 - d) / 18; 1637 for (i = 0; i < n; i++) 1638 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1639 } 1640 1641 static void 1642 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1643 { 1644 unsigned int i, n = min((int)ext[0x02], 6); 1645 u8 *det_base = ext + 5; 1646 1647 if (ext[0x01] != 1) 1648 return; /* unknown version */ 1649 1650 for (i = 0; i < n; i++) 1651 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1652 } 1653 1654 static void 1655 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1656 { 1657 int i; 1658 struct edid *edid = (struct edid *)raw_edid; 1659 1660 if (edid == NULL) 1661 return; 1662 1663 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1664 cb(&(edid->detailed_timings[i]), closure); 1665 1666 for (i = 1; i <= raw_edid[0x7e]; i++) { 1667 u8 *ext = raw_edid + (i * EDID_LENGTH); 1668 switch (*ext) { 1669 case CEA_EXT: 1670 cea_for_each_detailed_block(ext, cb, closure); 1671 break; 1672 case VTB_EXT: 1673 vtb_for_each_detailed_block(ext, cb, closure); 1674 break; 1675 default: 1676 break; 1677 } 1678 } 1679 } 1680 1681 static void 1682 is_rb(struct detailed_timing *t, void *data) 1683 { 1684 u8 *r = (u8 *)t; 1685 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1686 if (r[15] & 0x10) 1687 *(bool *)data = true; 1688 } 1689 1690 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1691 static bool 1692 drm_monitor_supports_rb(struct edid *edid) 1693 { 1694 if (edid->revision >= 4) { 1695 bool ret = false; 1696 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1697 return ret; 1698 } 1699 1700 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1701 } 1702 1703 static void 1704 find_gtf2(struct detailed_timing *t, void *data) 1705 { 1706 u8 *r = (u8 *)t; 1707 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1708 *(u8 **)data = r; 1709 } 1710 1711 /* Secondary GTF curve kicks in above some break frequency */ 1712 static int 1713 drm_gtf2_hbreak(struct edid *edid) 1714 { 1715 u8 *r = NULL; 1716 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1717 return r ? (r[12] * 2) : 0; 1718 } 1719 1720 static int 1721 drm_gtf2_2c(struct edid *edid) 1722 { 1723 u8 *r = NULL; 1724 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1725 return r ? r[13] : 0; 1726 } 1727 1728 static int 1729 drm_gtf2_m(struct edid *edid) 1730 { 1731 u8 *r = NULL; 1732 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1733 return r ? (r[15] << 8) + r[14] : 0; 1734 } 1735 1736 static int 1737 drm_gtf2_k(struct edid *edid) 1738 { 1739 u8 *r = NULL; 1740 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1741 return r ? r[16] : 0; 1742 } 1743 1744 static int 1745 drm_gtf2_2j(struct edid *edid) 1746 { 1747 u8 *r = NULL; 1748 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1749 return r ? r[17] : 0; 1750 } 1751 1752 /** 1753 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1754 * @edid: EDID block to scan 1755 */ 1756 static int standard_timing_level(struct edid *edid) 1757 { 1758 if (edid->revision >= 2) { 1759 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1760 return LEVEL_CVT; 1761 if (drm_gtf2_hbreak(edid)) 1762 return LEVEL_GTF2; 1763 return LEVEL_GTF; 1764 } 1765 return LEVEL_DMT; 1766 } 1767 1768 /* 1769 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1770 * monitors fill with ascii space (0x20) instead. 1771 */ 1772 static int 1773 bad_std_timing(u8 a, u8 b) 1774 { 1775 return (a == 0x00 && b == 0x00) || 1776 (a == 0x01 && b == 0x01) || 1777 (a == 0x20 && b == 0x20); 1778 } 1779 1780 /** 1781 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1782 * @connector: connector of for the EDID block 1783 * @edid: EDID block to scan 1784 * @t: standard timing params 1785 * 1786 * Take the standard timing params (in this case width, aspect, and refresh) 1787 * and convert them into a real mode using CVT/GTF/DMT. 1788 */ 1789 static struct drm_display_mode * 1790 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1791 struct std_timing *t) 1792 { 1793 struct drm_device *dev = connector->dev; 1794 struct drm_display_mode *m, *mode = NULL; 1795 int hsize, vsize; 1796 int vrefresh_rate; 1797 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1798 >> EDID_TIMING_ASPECT_SHIFT; 1799 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1800 >> EDID_TIMING_VFREQ_SHIFT; 1801 int timing_level = standard_timing_level(edid); 1802 1803 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1804 return NULL; 1805 1806 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1807 hsize = t->hsize * 8 + 248; 1808 /* vrefresh_rate = vfreq + 60 */ 1809 vrefresh_rate = vfreq + 60; 1810 /* the vdisplay is calculated based on the aspect ratio */ 1811 if (aspect_ratio == 0) { 1812 if (edid->revision < 3) 1813 vsize = hsize; 1814 else 1815 vsize = (hsize * 10) / 16; 1816 } else if (aspect_ratio == 1) 1817 vsize = (hsize * 3) / 4; 1818 else if (aspect_ratio == 2) 1819 vsize = (hsize * 4) / 5; 1820 else 1821 vsize = (hsize * 9) / 16; 1822 1823 /* HDTV hack, part 1 */ 1824 if (vrefresh_rate == 60 && 1825 ((hsize == 1360 && vsize == 765) || 1826 (hsize == 1368 && vsize == 769))) { 1827 hsize = 1366; 1828 vsize = 768; 1829 } 1830 1831 /* 1832 * If this connector already has a mode for this size and refresh 1833 * rate (because it came from detailed or CVT info), use that 1834 * instead. This way we don't have to guess at interlace or 1835 * reduced blanking. 1836 */ 1837 list_for_each_entry(m, &connector->probed_modes, head) 1838 if (m->hdisplay == hsize && m->vdisplay == vsize && 1839 drm_mode_vrefresh(m) == vrefresh_rate) 1840 return NULL; 1841 1842 /* HDTV hack, part 2 */ 1843 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1844 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1845 false); 1846 mode->hdisplay = 1366; 1847 mode->hsync_start = mode->hsync_start - 1; 1848 mode->hsync_end = mode->hsync_end - 1; 1849 return mode; 1850 } 1851 1852 /* check whether it can be found in default mode table */ 1853 if (drm_monitor_supports_rb(edid)) { 1854 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1855 true); 1856 if (mode) 1857 return mode; 1858 } 1859 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1860 if (mode) 1861 return mode; 1862 1863 /* okay, generate it */ 1864 switch (timing_level) { 1865 case LEVEL_DMT: 1866 break; 1867 case LEVEL_GTF: 1868 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1869 break; 1870 case LEVEL_GTF2: 1871 /* 1872 * This is potentially wrong if there's ever a monitor with 1873 * more than one ranges section, each claiming a different 1874 * secondary GTF curve. Please don't do that. 1875 */ 1876 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1877 if (!mode) 1878 return NULL; 1879 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1880 drm_mode_destroy(dev, mode); 1881 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1882 vrefresh_rate, 0, 0, 1883 drm_gtf2_m(edid), 1884 drm_gtf2_2c(edid), 1885 drm_gtf2_k(edid), 1886 drm_gtf2_2j(edid)); 1887 } 1888 break; 1889 case LEVEL_CVT: 1890 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1891 false); 1892 break; 1893 } 1894 return mode; 1895 } 1896 1897 /* 1898 * EDID is delightfully ambiguous about how interlaced modes are to be 1899 * encoded. Our internal representation is of frame height, but some 1900 * HDTV detailed timings are encoded as field height. 1901 * 1902 * The format list here is from CEA, in frame size. Technically we 1903 * should be checking refresh rate too. Whatever. 1904 */ 1905 static void 1906 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1907 struct detailed_pixel_timing *pt) 1908 { 1909 int i; 1910 static const struct { 1911 int w, h; 1912 } cea_interlaced[] = { 1913 { 1920, 1080 }, 1914 { 720, 480 }, 1915 { 1440, 480 }, 1916 { 2880, 480 }, 1917 { 720, 576 }, 1918 { 1440, 576 }, 1919 { 2880, 576 }, 1920 }; 1921 1922 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1923 return; 1924 1925 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1926 if ((mode->hdisplay == cea_interlaced[i].w) && 1927 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1928 mode->vdisplay *= 2; 1929 mode->vsync_start *= 2; 1930 mode->vsync_end *= 2; 1931 mode->vtotal *= 2; 1932 mode->vtotal |= 1; 1933 } 1934 } 1935 1936 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1937 } 1938 1939 /** 1940 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1941 * @dev: DRM device (needed to create new mode) 1942 * @edid: EDID block 1943 * @timing: EDID detailed timing info 1944 * @quirks: quirks to apply 1945 * 1946 * An EDID detailed timing block contains enough info for us to create and 1947 * return a new struct drm_display_mode. 1948 */ 1949 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1950 struct edid *edid, 1951 struct detailed_timing *timing, 1952 u32 quirks) 1953 { 1954 struct drm_display_mode *mode; 1955 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1956 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1957 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1958 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1959 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1960 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1961 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1962 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1963 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1964 1965 /* ignore tiny modes */ 1966 if (hactive < 64 || vactive < 64) 1967 return NULL; 1968 1969 if (pt->misc & DRM_EDID_PT_STEREO) { 1970 DRM_DEBUG_KMS("stereo mode not supported\n"); 1971 return NULL; 1972 } 1973 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1974 DRM_DEBUG_KMS("composite sync not supported\n"); 1975 } 1976 1977 /* it is incorrect if hsync/vsync width is zero */ 1978 if (!hsync_pulse_width || !vsync_pulse_width) { 1979 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1980 "Wrong Hsync/Vsync pulse width\n"); 1981 return NULL; 1982 } 1983 1984 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1985 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1986 if (!mode) 1987 return NULL; 1988 1989 goto set_size; 1990 } 1991 1992 mode = drm_mode_create(dev); 1993 if (!mode) 1994 return NULL; 1995 1996 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1997 timing->pixel_clock = cpu_to_le16(1088); 1998 1999 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2000 2001 mode->hdisplay = hactive; 2002 mode->hsync_start = mode->hdisplay + hsync_offset; 2003 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2004 mode->htotal = mode->hdisplay + hblank; 2005 2006 mode->vdisplay = vactive; 2007 mode->vsync_start = mode->vdisplay + vsync_offset; 2008 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2009 mode->vtotal = mode->vdisplay + vblank; 2010 2011 /* Some EDIDs have bogus h/vtotal values */ 2012 if (mode->hsync_end > mode->htotal) 2013 mode->htotal = mode->hsync_end + 1; 2014 if (mode->vsync_end > mode->vtotal) 2015 mode->vtotal = mode->vsync_end + 1; 2016 2017 drm_mode_do_interlace_quirk(mode, pt); 2018 2019 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2020 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2021 } 2022 2023 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2024 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2025 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2026 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2027 2028 set_size: 2029 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2030 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2031 2032 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2033 mode->width_mm *= 10; 2034 mode->height_mm *= 10; 2035 } 2036 2037 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2038 mode->width_mm = edid->width_cm * 10; 2039 mode->height_mm = edid->height_cm * 10; 2040 } 2041 2042 mode->type = DRM_MODE_TYPE_DRIVER; 2043 mode->vrefresh = drm_mode_vrefresh(mode); 2044 drm_mode_set_name(mode); 2045 2046 return mode; 2047 } 2048 2049 static bool 2050 mode_in_hsync_range(const struct drm_display_mode *mode, 2051 struct edid *edid, u8 *t) 2052 { 2053 int hsync, hmin, hmax; 2054 2055 hmin = t[7]; 2056 if (edid->revision >= 4) 2057 hmin += ((t[4] & 0x04) ? 255 : 0); 2058 hmax = t[8]; 2059 if (edid->revision >= 4) 2060 hmax += ((t[4] & 0x08) ? 255 : 0); 2061 hsync = drm_mode_hsync(mode); 2062 2063 return (hsync <= hmax && hsync >= hmin); 2064 } 2065 2066 static bool 2067 mode_in_vsync_range(const struct drm_display_mode *mode, 2068 struct edid *edid, u8 *t) 2069 { 2070 int vsync, vmin, vmax; 2071 2072 vmin = t[5]; 2073 if (edid->revision >= 4) 2074 vmin += ((t[4] & 0x01) ? 255 : 0); 2075 vmax = t[6]; 2076 if (edid->revision >= 4) 2077 vmax += ((t[4] & 0x02) ? 255 : 0); 2078 vsync = drm_mode_vrefresh(mode); 2079 2080 return (vsync <= vmax && vsync >= vmin); 2081 } 2082 2083 static u32 2084 range_pixel_clock(struct edid *edid, u8 *t) 2085 { 2086 /* unspecified */ 2087 if (t[9] == 0 || t[9] == 255) 2088 return 0; 2089 2090 /* 1.4 with CVT support gives us real precision, yay */ 2091 if (edid->revision >= 4 && t[10] == 0x04) 2092 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2093 2094 /* 1.3 is pathetic, so fuzz up a bit */ 2095 return t[9] * 10000 + 5001; 2096 } 2097 2098 static bool 2099 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2100 struct detailed_timing *timing) 2101 { 2102 u32 max_clock; 2103 u8 *t = (u8 *)timing; 2104 2105 if (!mode_in_hsync_range(mode, edid, t)) 2106 return false; 2107 2108 if (!mode_in_vsync_range(mode, edid, t)) 2109 return false; 2110 2111 if ((max_clock = range_pixel_clock(edid, t))) 2112 if (mode->clock > max_clock) 2113 return false; 2114 2115 /* 1.4 max horizontal check */ 2116 if (edid->revision >= 4 && t[10] == 0x04) 2117 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2118 return false; 2119 2120 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2121 return false; 2122 2123 return true; 2124 } 2125 2126 static bool valid_inferred_mode(const struct drm_connector *connector, 2127 const struct drm_display_mode *mode) 2128 { 2129 struct drm_display_mode *m; 2130 bool ok = false; 2131 2132 list_for_each_entry(m, &connector->probed_modes, head) { 2133 if (mode->hdisplay == m->hdisplay && 2134 mode->vdisplay == m->vdisplay && 2135 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2136 return false; /* duplicated */ 2137 if (mode->hdisplay <= m->hdisplay && 2138 mode->vdisplay <= m->vdisplay) 2139 ok = true; 2140 } 2141 return ok; 2142 } 2143 2144 static int 2145 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2146 struct detailed_timing *timing) 2147 { 2148 int i, modes = 0; 2149 struct drm_display_mode *newmode; 2150 struct drm_device *dev = connector->dev; 2151 2152 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2153 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2154 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2155 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2156 if (newmode) { 2157 drm_mode_probed_add(connector, newmode); 2158 modes++; 2159 } 2160 } 2161 } 2162 2163 return modes; 2164 } 2165 2166 /* fix up 1366x768 mode from 1368x768; 2167 * GFT/CVT can't express 1366 width which isn't dividable by 8 2168 */ 2169 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2170 { 2171 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2172 mode->hdisplay = 1366; 2173 mode->hsync_start--; 2174 mode->hsync_end--; 2175 drm_mode_set_name(mode); 2176 } 2177 } 2178 2179 static int 2180 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2181 struct detailed_timing *timing) 2182 { 2183 int i, modes = 0; 2184 struct drm_display_mode *newmode; 2185 struct drm_device *dev = connector->dev; 2186 2187 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2188 const struct minimode *m = &extra_modes[i]; 2189 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2190 if (!newmode) 2191 return modes; 2192 2193 fixup_mode_1366x768(newmode); 2194 if (!mode_in_range(newmode, edid, timing) || 2195 !valid_inferred_mode(connector, newmode)) { 2196 drm_mode_destroy(dev, newmode); 2197 continue; 2198 } 2199 2200 drm_mode_probed_add(connector, newmode); 2201 modes++; 2202 } 2203 2204 return modes; 2205 } 2206 2207 static int 2208 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2209 struct detailed_timing *timing) 2210 { 2211 int i, modes = 0; 2212 struct drm_display_mode *newmode; 2213 struct drm_device *dev = connector->dev; 2214 bool rb = drm_monitor_supports_rb(edid); 2215 2216 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2217 const struct minimode *m = &extra_modes[i]; 2218 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2219 if (!newmode) 2220 return modes; 2221 2222 fixup_mode_1366x768(newmode); 2223 if (!mode_in_range(newmode, edid, timing) || 2224 !valid_inferred_mode(connector, newmode)) { 2225 drm_mode_destroy(dev, newmode); 2226 continue; 2227 } 2228 2229 drm_mode_probed_add(connector, newmode); 2230 modes++; 2231 } 2232 2233 return modes; 2234 } 2235 2236 static void 2237 do_inferred_modes(struct detailed_timing *timing, void *c) 2238 { 2239 struct detailed_mode_closure *closure = c; 2240 struct detailed_non_pixel *data = &timing->data.other_data; 2241 struct detailed_data_monitor_range *range = &data->data.range; 2242 2243 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2244 return; 2245 2246 closure->modes += drm_dmt_modes_for_range(closure->connector, 2247 closure->edid, 2248 timing); 2249 2250 if (!version_greater(closure->edid, 1, 1)) 2251 return; /* GTF not defined yet */ 2252 2253 switch (range->flags) { 2254 case 0x02: /* secondary gtf, XXX could do more */ 2255 case 0x00: /* default gtf */ 2256 closure->modes += drm_gtf_modes_for_range(closure->connector, 2257 closure->edid, 2258 timing); 2259 break; 2260 case 0x04: /* cvt, only in 1.4+ */ 2261 if (!version_greater(closure->edid, 1, 3)) 2262 break; 2263 2264 closure->modes += drm_cvt_modes_for_range(closure->connector, 2265 closure->edid, 2266 timing); 2267 break; 2268 case 0x01: /* just the ranges, no formula */ 2269 default: 2270 break; 2271 } 2272 } 2273 2274 static int 2275 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2276 { 2277 struct detailed_mode_closure closure = { 2278 .connector = connector, 2279 .edid = edid, 2280 }; 2281 2282 if (version_greater(edid, 1, 0)) 2283 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2284 &closure); 2285 2286 return closure.modes; 2287 } 2288 2289 static int 2290 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2291 { 2292 int i, j, m, modes = 0; 2293 struct drm_display_mode *mode; 2294 u8 *est = ((u8 *)timing) + 5; 2295 2296 for (i = 0; i < 6; i++) { 2297 for (j = 7; j >= 0; j--) { 2298 m = (i * 8) + (7 - j); 2299 if (m >= ARRAY_SIZE(est3_modes)) 2300 break; 2301 if (est[i] & (1 << j)) { 2302 mode = drm_mode_find_dmt(connector->dev, 2303 est3_modes[m].w, 2304 est3_modes[m].h, 2305 est3_modes[m].r, 2306 est3_modes[m].rb); 2307 if (mode) { 2308 drm_mode_probed_add(connector, mode); 2309 modes++; 2310 } 2311 } 2312 } 2313 } 2314 2315 return modes; 2316 } 2317 2318 static void 2319 do_established_modes(struct detailed_timing *timing, void *c) 2320 { 2321 struct detailed_mode_closure *closure = c; 2322 struct detailed_non_pixel *data = &timing->data.other_data; 2323 2324 if (data->type == EDID_DETAIL_EST_TIMINGS) 2325 closure->modes += drm_est3_modes(closure->connector, timing); 2326 } 2327 2328 /** 2329 * add_established_modes - get est. modes from EDID and add them 2330 * @connector: connector to add mode(s) to 2331 * @edid: EDID block to scan 2332 * 2333 * Each EDID block contains a bitmap of the supported "established modes" list 2334 * (defined above). Tease them out and add them to the global modes list. 2335 */ 2336 static int 2337 add_established_modes(struct drm_connector *connector, struct edid *edid) 2338 { 2339 struct drm_device *dev = connector->dev; 2340 unsigned long est_bits = edid->established_timings.t1 | 2341 (edid->established_timings.t2 << 8) | 2342 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2343 int i, modes = 0; 2344 struct detailed_mode_closure closure = { 2345 .connector = connector, 2346 .edid = edid, 2347 }; 2348 2349 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2350 if (est_bits & (1<<i)) { 2351 struct drm_display_mode *newmode; 2352 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2353 if (newmode) { 2354 drm_mode_probed_add(connector, newmode); 2355 modes++; 2356 } 2357 } 2358 } 2359 2360 if (version_greater(edid, 1, 0)) 2361 drm_for_each_detailed_block((u8 *)edid, 2362 do_established_modes, &closure); 2363 2364 return modes + closure.modes; 2365 } 2366 2367 static void 2368 do_standard_modes(struct detailed_timing *timing, void *c) 2369 { 2370 struct detailed_mode_closure *closure = c; 2371 struct detailed_non_pixel *data = &timing->data.other_data; 2372 struct drm_connector *connector = closure->connector; 2373 struct edid *edid = closure->edid; 2374 2375 if (data->type == EDID_DETAIL_STD_MODES) { 2376 int i; 2377 for (i = 0; i < 6; i++) { 2378 struct std_timing *std; 2379 struct drm_display_mode *newmode; 2380 2381 std = &data->data.timings[i]; 2382 newmode = drm_mode_std(connector, edid, std); 2383 if (newmode) { 2384 drm_mode_probed_add(connector, newmode); 2385 closure->modes++; 2386 } 2387 } 2388 } 2389 } 2390 2391 /** 2392 * add_standard_modes - get std. modes from EDID and add them 2393 * @connector: connector to add mode(s) to 2394 * @edid: EDID block to scan 2395 * 2396 * Standard modes can be calculated using the appropriate standard (DMT, 2397 * GTF or CVT. Grab them from @edid and add them to the list. 2398 */ 2399 static int 2400 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2401 { 2402 int i, modes = 0; 2403 struct detailed_mode_closure closure = { 2404 .connector = connector, 2405 .edid = edid, 2406 }; 2407 2408 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2409 struct drm_display_mode *newmode; 2410 2411 newmode = drm_mode_std(connector, edid, 2412 &edid->standard_timings[i]); 2413 if (newmode) { 2414 drm_mode_probed_add(connector, newmode); 2415 modes++; 2416 } 2417 } 2418 2419 if (version_greater(edid, 1, 0)) 2420 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2421 &closure); 2422 2423 /* XXX should also look for standard codes in VTB blocks */ 2424 2425 return modes + closure.modes; 2426 } 2427 2428 static int drm_cvt_modes(struct drm_connector *connector, 2429 struct detailed_timing *timing) 2430 { 2431 int i, j, modes = 0; 2432 struct drm_display_mode *newmode; 2433 struct drm_device *dev = connector->dev; 2434 struct cvt_timing *cvt; 2435 const int rates[] = { 60, 85, 75, 60, 50 }; 2436 const u8 empty[3] = { 0, 0, 0 }; 2437 2438 for (i = 0; i < 4; i++) { 2439 int width = 0, height; 2440 cvt = &(timing->data.other_data.data.cvt[i]); 2441 2442 if (!memcmp(cvt->code, empty, 3)) 2443 continue; 2444 2445 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2446 switch (cvt->code[1] & 0x0c) { 2447 case 0x00: 2448 width = height * 4 / 3; 2449 break; 2450 case 0x04: 2451 width = height * 16 / 9; 2452 break; 2453 case 0x08: 2454 width = height * 16 / 10; 2455 break; 2456 case 0x0c: 2457 width = height * 15 / 9; 2458 break; 2459 } 2460 2461 for (j = 1; j < 5; j++) { 2462 if (cvt->code[2] & (1 << j)) { 2463 newmode = drm_cvt_mode(dev, width, height, 2464 rates[j], j == 0, 2465 false, false); 2466 if (newmode) { 2467 drm_mode_probed_add(connector, newmode); 2468 modes++; 2469 } 2470 } 2471 } 2472 } 2473 2474 return modes; 2475 } 2476 2477 static void 2478 do_cvt_mode(struct detailed_timing *timing, void *c) 2479 { 2480 struct detailed_mode_closure *closure = c; 2481 struct detailed_non_pixel *data = &timing->data.other_data; 2482 2483 if (data->type == EDID_DETAIL_CVT_3BYTE) 2484 closure->modes += drm_cvt_modes(closure->connector, timing); 2485 } 2486 2487 static int 2488 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2489 { 2490 struct detailed_mode_closure closure = { 2491 .connector = connector, 2492 .edid = edid, 2493 }; 2494 2495 if (version_greater(edid, 1, 2)) 2496 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2497 2498 /* XXX should also look for CVT codes in VTB blocks */ 2499 2500 return closure.modes; 2501 } 2502 2503 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2504 2505 static void 2506 do_detailed_mode(struct detailed_timing *timing, void *c) 2507 { 2508 struct detailed_mode_closure *closure = c; 2509 struct drm_display_mode *newmode; 2510 2511 if (timing->pixel_clock) { 2512 newmode = drm_mode_detailed(closure->connector->dev, 2513 closure->edid, timing, 2514 closure->quirks); 2515 if (!newmode) 2516 return; 2517 2518 if (closure->preferred) 2519 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2520 2521 /* 2522 * Detailed modes are limited to 10kHz pixel clock resolution, 2523 * so fix up anything that looks like CEA/HDMI mode, but the clock 2524 * is just slightly off. 2525 */ 2526 fixup_detailed_cea_mode_clock(newmode); 2527 2528 drm_mode_probed_add(closure->connector, newmode); 2529 closure->modes++; 2530 closure->preferred = 0; 2531 } 2532 } 2533 2534 /* 2535 * add_detailed_modes - Add modes from detailed timings 2536 * @connector: attached connector 2537 * @edid: EDID block to scan 2538 * @quirks: quirks to apply 2539 */ 2540 static int 2541 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2542 u32 quirks) 2543 { 2544 struct detailed_mode_closure closure = { 2545 .connector = connector, 2546 .edid = edid, 2547 .preferred = 1, 2548 .quirks = quirks, 2549 }; 2550 2551 if (closure.preferred && !version_greater(edid, 1, 3)) 2552 closure.preferred = 2553 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2554 2555 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2556 2557 return closure.modes; 2558 } 2559 2560 #define AUDIO_BLOCK 0x01 2561 #define VIDEO_BLOCK 0x02 2562 #define VENDOR_BLOCK 0x03 2563 #define SPEAKER_BLOCK 0x04 2564 #define VIDEO_CAPABILITY_BLOCK 0x07 2565 #define EDID_BASIC_AUDIO (1 << 6) 2566 #define EDID_CEA_YCRCB444 (1 << 5) 2567 #define EDID_CEA_YCRCB422 (1 << 4) 2568 #define EDID_CEA_VCDB_QS (1 << 6) 2569 2570 /* 2571 * Search EDID for CEA extension block. 2572 */ 2573 static u8 *drm_find_cea_extension(struct edid *edid) 2574 { 2575 u8 *edid_ext = NULL; 2576 int i; 2577 2578 /* No EDID or EDID extensions */ 2579 if (edid == NULL || edid->extensions == 0) 2580 return NULL; 2581 2582 /* Find CEA extension */ 2583 for (i = 0; i < edid->extensions; i++) { 2584 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2585 if (edid_ext[0] == CEA_EXT) 2586 break; 2587 } 2588 2589 if (i == edid->extensions) 2590 return NULL; 2591 2592 return edid_ext; 2593 } 2594 2595 /* 2596 * Calculate the alternate clock for the CEA mode 2597 * (60Hz vs. 59.94Hz etc.) 2598 */ 2599 static unsigned int 2600 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2601 { 2602 unsigned int clock = cea_mode->clock; 2603 2604 if (cea_mode->vrefresh % 6 != 0) 2605 return clock; 2606 2607 /* 2608 * edid_cea_modes contains the 59.94Hz 2609 * variant for 240 and 480 line modes, 2610 * and the 60Hz variant otherwise. 2611 */ 2612 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2613 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2614 else 2615 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2616 2617 return clock; 2618 } 2619 2620 /** 2621 * drm_match_cea_mode - look for a CEA mode matching given mode 2622 * @to_match: display mode 2623 * 2624 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2625 * mode. 2626 */ 2627 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2628 { 2629 u8 mode; 2630 2631 if (!to_match->clock) 2632 return 0; 2633 2634 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2635 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2636 unsigned int clock1, clock2; 2637 2638 /* Check both 60Hz and 59.94Hz */ 2639 clock1 = cea_mode->clock; 2640 clock2 = cea_mode_alternate_clock(cea_mode); 2641 2642 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2643 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2644 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2645 return mode + 1; 2646 } 2647 return 0; 2648 } 2649 EXPORT_SYMBOL(drm_match_cea_mode); 2650 2651 /** 2652 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2653 * the input VIC from the CEA mode list 2654 * @video_code: ID given to each of the CEA modes 2655 * 2656 * Returns picture aspect ratio 2657 */ 2658 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2659 { 2660 /* return picture aspect ratio for video_code - 1 to access the 2661 * right array element 2662 */ 2663 return edid_cea_modes[video_code-1].picture_aspect_ratio; 2664 } 2665 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2666 2667 /* 2668 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2669 * specific block). 2670 * 2671 * It's almost like cea_mode_alternate_clock(), we just need to add an 2672 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2673 * one. 2674 */ 2675 static unsigned int 2676 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2677 { 2678 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2679 return hdmi_mode->clock; 2680 2681 return cea_mode_alternate_clock(hdmi_mode); 2682 } 2683 2684 /* 2685 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2686 * @to_match: display mode 2687 * 2688 * An HDMI mode is one defined in the HDMI vendor specific block. 2689 * 2690 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2691 */ 2692 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2693 { 2694 u8 mode; 2695 2696 if (!to_match->clock) 2697 return 0; 2698 2699 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2700 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2701 unsigned int clock1, clock2; 2702 2703 /* Make sure to also match alternate clocks */ 2704 clock1 = hdmi_mode->clock; 2705 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2706 2707 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2708 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2709 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2710 return mode + 1; 2711 } 2712 return 0; 2713 } 2714 2715 static int 2716 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2717 { 2718 struct drm_device *dev = connector->dev; 2719 struct drm_display_mode *mode, *tmp; 2720 LINUX_LIST_HEAD(list); 2721 int modes = 0; 2722 2723 /* Don't add CEA modes if the CEA extension block is missing */ 2724 if (!drm_find_cea_extension(edid)) 2725 return 0; 2726 2727 /* 2728 * Go through all probed modes and create a new mode 2729 * with the alternate clock for certain CEA modes. 2730 */ 2731 list_for_each_entry(mode, &connector->probed_modes, head) { 2732 const struct drm_display_mode *cea_mode = NULL; 2733 struct drm_display_mode *newmode; 2734 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2735 unsigned int clock1, clock2; 2736 2737 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2738 cea_mode = &edid_cea_modes[mode_idx]; 2739 clock2 = cea_mode_alternate_clock(cea_mode); 2740 } else { 2741 mode_idx = drm_match_hdmi_mode(mode) - 1; 2742 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2743 cea_mode = &edid_4k_modes[mode_idx]; 2744 clock2 = hdmi_mode_alternate_clock(cea_mode); 2745 } 2746 } 2747 2748 if (!cea_mode) 2749 continue; 2750 2751 clock1 = cea_mode->clock; 2752 2753 if (clock1 == clock2) 2754 continue; 2755 2756 if (mode->clock != clock1 && mode->clock != clock2) 2757 continue; 2758 2759 newmode = drm_mode_duplicate(dev, cea_mode); 2760 if (!newmode) 2761 continue; 2762 2763 /* Carry over the stereo flags */ 2764 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2765 2766 /* 2767 * The current mode could be either variant. Make 2768 * sure to pick the "other" clock for the new mode. 2769 */ 2770 if (mode->clock != clock1) 2771 newmode->clock = clock1; 2772 else 2773 newmode->clock = clock2; 2774 2775 list_add_tail(&newmode->head, &list); 2776 } 2777 2778 list_for_each_entry_safe(mode, tmp, &list, head) { 2779 list_del(&mode->head); 2780 drm_mode_probed_add(connector, mode); 2781 modes++; 2782 } 2783 2784 return modes; 2785 } 2786 2787 static struct drm_display_mode * 2788 drm_display_mode_from_vic_index(struct drm_connector *connector, 2789 const u8 *video_db, u8 video_len, 2790 u8 video_index) 2791 { 2792 struct drm_device *dev = connector->dev; 2793 struct drm_display_mode *newmode; 2794 u8 cea_mode; 2795 2796 if (video_db == NULL || video_index >= video_len) 2797 return NULL; 2798 2799 /* CEA modes are numbered 1..127 */ 2800 cea_mode = (video_db[video_index] & 127) - 1; 2801 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2802 return NULL; 2803 2804 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2805 if (!newmode) 2806 return NULL; 2807 2808 newmode->vrefresh = 0; 2809 2810 return newmode; 2811 } 2812 2813 static int 2814 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2815 { 2816 int i, modes = 0; 2817 2818 for (i = 0; i < len; i++) { 2819 struct drm_display_mode *mode; 2820 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2821 if (mode) { 2822 drm_mode_probed_add(connector, mode); 2823 modes++; 2824 } 2825 } 2826 2827 return modes; 2828 } 2829 2830 struct stereo_mandatory_mode { 2831 int width, height, vrefresh; 2832 unsigned int flags; 2833 }; 2834 2835 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2836 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2837 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2838 { 1920, 1080, 50, 2839 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2840 { 1920, 1080, 60, 2841 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2842 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2843 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2844 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2845 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2846 }; 2847 2848 static bool 2849 stereo_match_mandatory(const struct drm_display_mode *mode, 2850 const struct stereo_mandatory_mode *stereo_mode) 2851 { 2852 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2853 2854 return mode->hdisplay == stereo_mode->width && 2855 mode->vdisplay == stereo_mode->height && 2856 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2857 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2858 } 2859 2860 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2861 { 2862 struct drm_device *dev = connector->dev; 2863 struct drm_display_mode *mode; 2864 struct list_head stereo_modes; 2865 int modes = 0, i; 2866 2867 INIT_LIST_HEAD(&stereo_modes); 2868 2869 list_for_each_entry(mode, &connector->probed_modes, head) { 2870 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2871 const struct stereo_mandatory_mode *mandatory; 2872 struct drm_display_mode *new_mode; 2873 2874 if (!stereo_match_mandatory(mode, 2875 &stereo_mandatory_modes[i])) 2876 continue; 2877 2878 mandatory = &stereo_mandatory_modes[i]; 2879 new_mode = drm_mode_duplicate(dev, mode); 2880 if (!new_mode) 2881 continue; 2882 2883 new_mode->flags |= mandatory->flags; 2884 list_add_tail(&new_mode->head, &stereo_modes); 2885 modes++; 2886 } 2887 } 2888 2889 list_splice_tail(&stereo_modes, &connector->probed_modes); 2890 2891 return modes; 2892 } 2893 2894 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2895 { 2896 struct drm_device *dev = connector->dev; 2897 struct drm_display_mode *newmode; 2898 2899 vic--; /* VICs start at 1 */ 2900 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2901 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2902 return 0; 2903 } 2904 2905 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2906 if (!newmode) 2907 return 0; 2908 2909 drm_mode_probed_add(connector, newmode); 2910 2911 return 1; 2912 } 2913 2914 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2915 const u8 *video_db, u8 video_len, u8 video_index) 2916 { 2917 struct drm_display_mode *newmode; 2918 int modes = 0; 2919 2920 if (structure & (1 << 0)) { 2921 newmode = drm_display_mode_from_vic_index(connector, video_db, 2922 video_len, 2923 video_index); 2924 if (newmode) { 2925 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2926 drm_mode_probed_add(connector, newmode); 2927 modes++; 2928 } 2929 } 2930 if (structure & (1 << 6)) { 2931 newmode = drm_display_mode_from_vic_index(connector, video_db, 2932 video_len, 2933 video_index); 2934 if (newmode) { 2935 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2936 drm_mode_probed_add(connector, newmode); 2937 modes++; 2938 } 2939 } 2940 if (structure & (1 << 8)) { 2941 newmode = drm_display_mode_from_vic_index(connector, video_db, 2942 video_len, 2943 video_index); 2944 if (newmode) { 2945 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2946 drm_mode_probed_add(connector, newmode); 2947 modes++; 2948 } 2949 } 2950 2951 return modes; 2952 } 2953 2954 /* 2955 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2956 * @connector: connector corresponding to the HDMI sink 2957 * @db: start of the CEA vendor specific block 2958 * @len: length of the CEA block payload, ie. one can access up to db[len] 2959 * 2960 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2961 * also adds the stereo 3d modes when applicable. 2962 */ 2963 static int 2964 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2965 const u8 *video_db, u8 video_len) 2966 { 2967 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2968 u8 vic_len, hdmi_3d_len = 0; 2969 u16 mask; 2970 u16 structure_all; 2971 2972 if (len < 8) 2973 goto out; 2974 2975 /* no HDMI_Video_Present */ 2976 if (!(db[8] & (1 << 5))) 2977 goto out; 2978 2979 /* Latency_Fields_Present */ 2980 if (db[8] & (1 << 7)) 2981 offset += 2; 2982 2983 /* I_Latency_Fields_Present */ 2984 if (db[8] & (1 << 6)) 2985 offset += 2; 2986 2987 /* the declared length is not long enough for the 2 first bytes 2988 * of additional video format capabilities */ 2989 if (len < (8 + offset + 2)) 2990 goto out; 2991 2992 /* 3D_Present */ 2993 offset++; 2994 if (db[8 + offset] & (1 << 7)) { 2995 modes += add_hdmi_mandatory_stereo_modes(connector); 2996 2997 /* 3D_Multi_present */ 2998 multi_present = (db[8 + offset] & 0x60) >> 5; 2999 } 3000 3001 offset++; 3002 vic_len = db[8 + offset] >> 5; 3003 hdmi_3d_len = db[8 + offset] & 0x1f; 3004 3005 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3006 u8 vic; 3007 3008 vic = db[9 + offset + i]; 3009 modes += add_hdmi_mode(connector, vic); 3010 } 3011 offset += 1 + vic_len; 3012 3013 if (multi_present == 1) 3014 multi_len = 2; 3015 else if (multi_present == 2) 3016 multi_len = 4; 3017 else 3018 multi_len = 0; 3019 3020 if (len < (8 + offset + hdmi_3d_len - 1)) 3021 goto out; 3022 3023 if (hdmi_3d_len < multi_len) 3024 goto out; 3025 3026 if (multi_present == 1 || multi_present == 2) { 3027 /* 3D_Structure_ALL */ 3028 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3029 3030 /* check if 3D_MASK is present */ 3031 if (multi_present == 2) 3032 mask = (db[10 + offset] << 8) | db[11 + offset]; 3033 else 3034 mask = 0xffff; 3035 3036 for (i = 0; i < 16; i++) { 3037 if (mask & (1 << i)) 3038 modes += add_3d_struct_modes(connector, 3039 structure_all, 3040 video_db, 3041 video_len, i); 3042 } 3043 } 3044 3045 offset += multi_len; 3046 3047 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3048 int vic_index; 3049 struct drm_display_mode *newmode = NULL; 3050 unsigned int newflag = 0; 3051 bool detail_present; 3052 3053 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3054 3055 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3056 break; 3057 3058 /* 2D_VIC_order_X */ 3059 vic_index = db[8 + offset + i] >> 4; 3060 3061 /* 3D_Structure_X */ 3062 switch (db[8 + offset + i] & 0x0f) { 3063 case 0: 3064 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3065 break; 3066 case 6: 3067 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3068 break; 3069 case 8: 3070 /* 3D_Detail_X */ 3071 if ((db[9 + offset + i] >> 4) == 1) 3072 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3073 break; 3074 } 3075 3076 if (newflag != 0) { 3077 newmode = drm_display_mode_from_vic_index(connector, 3078 video_db, 3079 video_len, 3080 vic_index); 3081 3082 if (newmode) { 3083 newmode->flags |= newflag; 3084 drm_mode_probed_add(connector, newmode); 3085 modes++; 3086 } 3087 } 3088 3089 if (detail_present) 3090 i++; 3091 } 3092 3093 out: 3094 return modes; 3095 } 3096 3097 static int 3098 cea_db_payload_len(const u8 *db) 3099 { 3100 return db[0] & 0x1f; 3101 } 3102 3103 static int 3104 cea_db_tag(const u8 *db) 3105 { 3106 return db[0] >> 5; 3107 } 3108 3109 static int 3110 cea_revision(const u8 *cea) 3111 { 3112 return cea[1]; 3113 } 3114 3115 static int 3116 cea_db_offsets(const u8 *cea, int *start, int *end) 3117 { 3118 /* Data block offset in CEA extension block */ 3119 *start = 4; 3120 *end = cea[2]; 3121 if (*end == 0) 3122 *end = 127; 3123 if (*end < 4 || *end > 127) 3124 return -ERANGE; 3125 return 0; 3126 } 3127 3128 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3129 { 3130 int hdmi_id; 3131 3132 if (cea_db_tag(db) != VENDOR_BLOCK) 3133 return false; 3134 3135 if (cea_db_payload_len(db) < 5) 3136 return false; 3137 3138 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3139 3140 return hdmi_id == HDMI_IEEE_OUI; 3141 } 3142 3143 #define for_each_cea_db(cea, i, start, end) \ 3144 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3145 3146 static int 3147 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3148 { 3149 const u8 *cea = drm_find_cea_extension(edid); 3150 const u8 *db, *hdmi = NULL, *video = NULL; 3151 u8 dbl, hdmi_len, video_len = 0; 3152 int modes = 0; 3153 3154 if (cea && cea_revision(cea) >= 3) { 3155 int i, start, end; 3156 3157 if (cea_db_offsets(cea, &start, &end)) 3158 return 0; 3159 3160 for_each_cea_db(cea, i, start, end) { 3161 db = &cea[i]; 3162 dbl = cea_db_payload_len(db); 3163 3164 if (cea_db_tag(db) == VIDEO_BLOCK) { 3165 video = db + 1; 3166 video_len = dbl; 3167 modes += do_cea_modes(connector, video, dbl); 3168 } 3169 else if (cea_db_is_hdmi_vsdb(db)) { 3170 hdmi = db; 3171 hdmi_len = dbl; 3172 } 3173 } 3174 } 3175 3176 /* 3177 * We parse the HDMI VSDB after having added the cea modes as we will 3178 * be patching their flags when the sink supports stereo 3D. 3179 */ 3180 if (hdmi) 3181 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3182 video_len); 3183 3184 return modes; 3185 } 3186 3187 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3188 { 3189 const struct drm_display_mode *cea_mode; 3190 int clock1, clock2, clock; 3191 u8 mode_idx; 3192 const char *type; 3193 3194 mode_idx = drm_match_cea_mode(mode) - 1; 3195 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 3196 type = "CEA"; 3197 cea_mode = &edid_cea_modes[mode_idx]; 3198 clock1 = cea_mode->clock; 3199 clock2 = cea_mode_alternate_clock(cea_mode); 3200 } else { 3201 mode_idx = drm_match_hdmi_mode(mode) - 1; 3202 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 3203 type = "HDMI"; 3204 cea_mode = &edid_4k_modes[mode_idx]; 3205 clock1 = cea_mode->clock; 3206 clock2 = hdmi_mode_alternate_clock(cea_mode); 3207 } else { 3208 return; 3209 } 3210 } 3211 3212 /* pick whichever is closest */ 3213 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3214 clock = clock1; 3215 else 3216 clock = clock2; 3217 3218 if (mode->clock == clock) 3219 return; 3220 3221 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3222 type, mode_idx + 1, mode->clock, clock); 3223 mode->clock = clock; 3224 } 3225 3226 static void 3227 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3228 { 3229 u8 len = cea_db_payload_len(db); 3230 3231 if (len >= 6) { 3232 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3233 connector->dvi_dual = db[6] & 1; 3234 } 3235 if (len >= 7) 3236 connector->max_tmds_clock = db[7] * 5; 3237 if (len >= 8) { 3238 connector->latency_present[0] = db[8] >> 7; 3239 connector->latency_present[1] = (db[8] >> 6) & 1; 3240 } 3241 if (len >= 9) 3242 connector->video_latency[0] = db[9]; 3243 if (len >= 10) 3244 connector->audio_latency[0] = db[10]; 3245 if (len >= 11) 3246 connector->video_latency[1] = db[11]; 3247 if (len >= 12) 3248 connector->audio_latency[1] = db[12]; 3249 3250 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3251 "max TMDS clock %d, " 3252 "latency present %d %d, " 3253 "video latency %d %d, " 3254 "audio latency %d %d\n", 3255 connector->dvi_dual, 3256 connector->max_tmds_clock, 3257 (int) connector->latency_present[0], 3258 (int) connector->latency_present[1], 3259 connector->video_latency[0], 3260 connector->video_latency[1], 3261 connector->audio_latency[0], 3262 connector->audio_latency[1]); 3263 } 3264 3265 static void 3266 monitor_name(struct detailed_timing *t, void *data) 3267 { 3268 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3269 *(u8 **)data = t->data.other_data.data.str.str; 3270 } 3271 3272 /** 3273 * drm_edid_to_eld - build ELD from EDID 3274 * @connector: connector corresponding to the HDMI/DP sink 3275 * @edid: EDID to parse 3276 * 3277 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3278 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3279 * fill in. 3280 */ 3281 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3282 { 3283 uint8_t *eld = connector->eld; 3284 u8 *cea; 3285 u8 *name; 3286 u8 *db; 3287 int sad_count = 0; 3288 int mnl; 3289 int dbl; 3290 3291 memset(eld, 0, sizeof(connector->eld)); 3292 3293 cea = drm_find_cea_extension(edid); 3294 if (!cea) { 3295 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3296 return; 3297 } 3298 3299 name = NULL; 3300 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3301 for (mnl = 0; name && mnl < 13; mnl++) { 3302 if (name[mnl] == 0x0a) 3303 break; 3304 eld[20 + mnl] = name[mnl]; 3305 } 3306 eld[4] = (cea[1] << 5) | mnl; 3307 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3308 3309 eld[0] = 2 << 3; /* ELD version: 2 */ 3310 3311 eld[16] = edid->mfg_id[0]; 3312 eld[17] = edid->mfg_id[1]; 3313 eld[18] = edid->prod_code[0]; 3314 eld[19] = edid->prod_code[1]; 3315 3316 if (cea_revision(cea) >= 3) { 3317 int i, start, end; 3318 3319 if (cea_db_offsets(cea, &start, &end)) { 3320 start = 0; 3321 end = 0; 3322 } 3323 3324 for_each_cea_db(cea, i, start, end) { 3325 db = &cea[i]; 3326 dbl = cea_db_payload_len(db); 3327 3328 switch (cea_db_tag(db)) { 3329 case AUDIO_BLOCK: 3330 /* Audio Data Block, contains SADs */ 3331 sad_count = dbl / 3; 3332 if (dbl >= 1) 3333 memcpy(eld + 20 + mnl, &db[1], dbl); 3334 break; 3335 case SPEAKER_BLOCK: 3336 /* Speaker Allocation Data Block */ 3337 if (dbl >= 1) 3338 eld[7] = db[1]; 3339 break; 3340 case VENDOR_BLOCK: 3341 /* HDMI Vendor-Specific Data Block */ 3342 if (cea_db_is_hdmi_vsdb(db)) 3343 parse_hdmi_vsdb(connector, db); 3344 break; 3345 default: 3346 break; 3347 } 3348 } 3349 } 3350 eld[5] |= sad_count << 4; 3351 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; 3352 3353 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); 3354 } 3355 EXPORT_SYMBOL(drm_edid_to_eld); 3356 3357 /** 3358 * drm_edid_to_sad - extracts SADs from EDID 3359 * @edid: EDID to parse 3360 * @sads: pointer that will be set to the extracted SADs 3361 * 3362 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3363 * 3364 * Note: The returned pointer needs to be freed using kfree(). 3365 * 3366 * Return: The number of found SADs or negative number on error. 3367 */ 3368 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3369 { 3370 int count = 0; 3371 int i, start, end, dbl; 3372 u8 *cea; 3373 3374 cea = drm_find_cea_extension(edid); 3375 if (!cea) { 3376 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3377 return -ENOENT; 3378 } 3379 3380 if (cea_revision(cea) < 3) { 3381 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3382 return -EOPNOTSUPP; 3383 } 3384 3385 if (cea_db_offsets(cea, &start, &end)) { 3386 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3387 return -EPROTO; 3388 } 3389 3390 for_each_cea_db(cea, i, start, end) { 3391 u8 *db = &cea[i]; 3392 3393 if (cea_db_tag(db) == AUDIO_BLOCK) { 3394 int j; 3395 dbl = cea_db_payload_len(db); 3396 3397 count = dbl / 3; /* SAD is 3B */ 3398 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3399 if (!*sads) 3400 return -ENOMEM; 3401 for (j = 0; j < count; j++) { 3402 u8 *sad = &db[1 + j * 3]; 3403 3404 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3405 (*sads)[j].channels = sad[0] & 0x7; 3406 (*sads)[j].freq = sad[1] & 0x7F; 3407 (*sads)[j].byte2 = sad[2]; 3408 } 3409 break; 3410 } 3411 } 3412 3413 return count; 3414 } 3415 EXPORT_SYMBOL(drm_edid_to_sad); 3416 3417 /** 3418 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3419 * @edid: EDID to parse 3420 * @sadb: pointer to the speaker block 3421 * 3422 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3423 * 3424 * Note: The returned pointer needs to be freed using kfree(). 3425 * 3426 * Return: The number of found Speaker Allocation Blocks or negative number on 3427 * error. 3428 */ 3429 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3430 { 3431 int count = 0; 3432 int i, start, end, dbl; 3433 const u8 *cea; 3434 3435 cea = drm_find_cea_extension(edid); 3436 if (!cea) { 3437 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3438 return -ENOENT; 3439 } 3440 3441 if (cea_revision(cea) < 3) { 3442 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3443 return -ENOTSUPP; 3444 } 3445 3446 if (cea_db_offsets(cea, &start, &end)) { 3447 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3448 return -EPROTO; 3449 } 3450 3451 for_each_cea_db(cea, i, start, end) { 3452 const u8 *db = &cea[i]; 3453 3454 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3455 dbl = cea_db_payload_len(db); 3456 3457 /* Speaker Allocation Data Block */ 3458 if (dbl == 3) { 3459 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3460 if (!*sadb) 3461 return -ENOMEM; 3462 count = dbl; 3463 break; 3464 } 3465 } 3466 } 3467 3468 return count; 3469 } 3470 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3471 3472 /** 3473 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3474 * @connector: connector associated with the HDMI/DP sink 3475 * @mode: the display mode 3476 * 3477 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3478 * the sink doesn't support audio or video. 3479 */ 3480 int drm_av_sync_delay(struct drm_connector *connector, 3481 const struct drm_display_mode *mode) 3482 { 3483 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3484 int a, v; 3485 3486 if (!connector->latency_present[0]) 3487 return 0; 3488 if (!connector->latency_present[1]) 3489 i = 0; 3490 3491 a = connector->audio_latency[i]; 3492 v = connector->video_latency[i]; 3493 3494 /* 3495 * HDMI/DP sink doesn't support audio or video? 3496 */ 3497 if (a == 255 || v == 255) 3498 return 0; 3499 3500 /* 3501 * Convert raw EDID values to millisecond. 3502 * Treat unknown latency as 0ms. 3503 */ 3504 if (a) 3505 a = min(2 * (a - 1), 500); 3506 if (v) 3507 v = min(2 * (v - 1), 500); 3508 3509 return max(v - a, 0); 3510 } 3511 EXPORT_SYMBOL(drm_av_sync_delay); 3512 3513 /** 3514 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3515 * @encoder: the encoder just changed display mode 3516 * 3517 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3518 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3519 * 3520 * Return: The connector associated with the first HDMI/DP sink that has ELD 3521 * attached to it. 3522 */ 3523 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3524 { 3525 struct drm_connector *connector; 3526 struct drm_device *dev = encoder->dev; 3527 3528 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3529 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3530 3531 drm_for_each_connector(connector, dev) 3532 if (connector->encoder == encoder && connector->eld[0]) 3533 return connector; 3534 3535 return NULL; 3536 } 3537 EXPORT_SYMBOL(drm_select_eld); 3538 3539 /** 3540 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3541 * @edid: monitor EDID information 3542 * 3543 * Parse the CEA extension according to CEA-861-B. 3544 * 3545 * Return: True if the monitor is HDMI, false if not or unknown. 3546 */ 3547 bool drm_detect_hdmi_monitor(struct edid *edid) 3548 { 3549 u8 *edid_ext; 3550 int i; 3551 int start_offset, end_offset; 3552 3553 edid_ext = drm_find_cea_extension(edid); 3554 if (!edid_ext) 3555 return false; 3556 3557 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3558 return false; 3559 3560 /* 3561 * Because HDMI identifier is in Vendor Specific Block, 3562 * search it from all data blocks of CEA extension. 3563 */ 3564 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3565 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3566 return true; 3567 } 3568 3569 return false; 3570 } 3571 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3572 3573 /** 3574 * drm_detect_monitor_audio - check monitor audio capability 3575 * @edid: EDID block to scan 3576 * 3577 * Monitor should have CEA extension block. 3578 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3579 * audio' only. If there is any audio extension block and supported 3580 * audio format, assume at least 'basic audio' support, even if 'basic 3581 * audio' is not defined in EDID. 3582 * 3583 * Return: True if the monitor supports audio, false otherwise. 3584 */ 3585 bool drm_detect_monitor_audio(struct edid *edid) 3586 { 3587 u8 *edid_ext; 3588 int i, j; 3589 bool has_audio = false; 3590 int start_offset, end_offset; 3591 3592 edid_ext = drm_find_cea_extension(edid); 3593 if (!edid_ext) 3594 goto end; 3595 3596 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3597 3598 if (has_audio) { 3599 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3600 goto end; 3601 } 3602 3603 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3604 goto end; 3605 3606 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3607 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3608 has_audio = true; 3609 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3610 DRM_DEBUG_KMS("CEA audio format %d\n", 3611 (edid_ext[i + j] >> 3) & 0xf); 3612 goto end; 3613 } 3614 } 3615 end: 3616 return has_audio; 3617 } 3618 EXPORT_SYMBOL(drm_detect_monitor_audio); 3619 3620 /** 3621 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3622 * @edid: EDID block to scan 3623 * 3624 * Check whether the monitor reports the RGB quantization range selection 3625 * as supported. The AVI infoframe can then be used to inform the monitor 3626 * which quantization range (full or limited) is used. 3627 * 3628 * Return: True if the RGB quantization range is selectable, false otherwise. 3629 */ 3630 bool drm_rgb_quant_range_selectable(struct edid *edid) 3631 { 3632 u8 *edid_ext; 3633 int i, start, end; 3634 3635 edid_ext = drm_find_cea_extension(edid); 3636 if (!edid_ext) 3637 return false; 3638 3639 if (cea_db_offsets(edid_ext, &start, &end)) 3640 return false; 3641 3642 for_each_cea_db(edid_ext, i, start, end) { 3643 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3644 cea_db_payload_len(&edid_ext[i]) == 2) { 3645 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3646 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3647 } 3648 } 3649 3650 return false; 3651 } 3652 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3653 3654 /** 3655 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3656 * hdmi deep color modes and update drm_display_info if so. 3657 * @edid: monitor EDID information 3658 * @info: Updated with maximum supported deep color bpc and color format 3659 * if deep color supported. 3660 * @connector: DRM connector, used only for debug output 3661 * 3662 * Parse the CEA extension according to CEA-861-B. 3663 * Return true if HDMI deep color supported, false if not or unknown. 3664 */ 3665 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3666 struct drm_display_info *info, 3667 struct drm_connector *connector) 3668 { 3669 u8 *edid_ext, *hdmi; 3670 int i; 3671 int start_offset, end_offset; 3672 unsigned int dc_bpc = 0; 3673 3674 edid_ext = drm_find_cea_extension(edid); 3675 if (!edid_ext) 3676 return false; 3677 3678 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3679 return false; 3680 3681 /* 3682 * Because HDMI identifier is in Vendor Specific Block, 3683 * search it from all data blocks of CEA extension. 3684 */ 3685 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3686 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3687 /* HDMI supports at least 8 bpc */ 3688 info->bpc = 8; 3689 3690 hdmi = &edid_ext[i]; 3691 if (cea_db_payload_len(hdmi) < 6) 3692 return false; 3693 3694 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3695 dc_bpc = 10; 3696 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3697 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3698 connector->name); 3699 } 3700 3701 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3702 dc_bpc = 12; 3703 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3704 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3705 connector->name); 3706 } 3707 3708 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3709 dc_bpc = 16; 3710 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3711 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3712 connector->name); 3713 } 3714 3715 if (dc_bpc > 0) { 3716 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3717 connector->name, dc_bpc); 3718 info->bpc = dc_bpc; 3719 3720 /* 3721 * Deep color support mandates RGB444 support for all video 3722 * modes and forbids YCRCB422 support for all video modes per 3723 * HDMI 1.3 spec. 3724 */ 3725 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3726 3727 /* YCRCB444 is optional according to spec. */ 3728 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3729 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3730 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3731 connector->name); 3732 } 3733 3734 /* 3735 * Spec says that if any deep color mode is supported at all, 3736 * then deep color 36 bit must be supported. 3737 */ 3738 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3739 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3740 connector->name); 3741 } 3742 3743 return true; 3744 } 3745 else { 3746 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3747 connector->name); 3748 } 3749 } 3750 } 3751 3752 return false; 3753 } 3754 3755 /** 3756 * drm_add_display_info - pull display info out if present 3757 * @edid: EDID data 3758 * @info: display info (attached to connector) 3759 * @connector: connector whose edid is used to build display info 3760 * 3761 * Grab any available display info and stuff it into the drm_display_info 3762 * structure that's part of the connector. Useful for tracking bpp and 3763 * color spaces. 3764 */ 3765 static void drm_add_display_info(struct edid *edid, 3766 struct drm_display_info *info, 3767 struct drm_connector *connector) 3768 { 3769 u8 *edid_ext; 3770 3771 info->width_mm = edid->width_cm * 10; 3772 info->height_mm = edid->height_cm * 10; 3773 3774 /* driver figures it out in this case */ 3775 info->bpc = 0; 3776 info->color_formats = 0; 3777 3778 if (edid->revision < 3) 3779 return; 3780 3781 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3782 return; 3783 3784 /* Get data from CEA blocks if present */ 3785 edid_ext = drm_find_cea_extension(edid); 3786 if (edid_ext) { 3787 info->cea_rev = edid_ext[1]; 3788 3789 /* The existence of a CEA block should imply RGB support */ 3790 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3791 if (edid_ext[3] & EDID_CEA_YCRCB444) 3792 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3793 if (edid_ext[3] & EDID_CEA_YCRCB422) 3794 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3795 } 3796 3797 /* HDMI deep color modes supported? Assign to info, if so */ 3798 drm_assign_hdmi_deep_color_info(edid, info, connector); 3799 3800 /* Only defined for 1.4 with digital displays */ 3801 if (edid->revision < 4) 3802 return; 3803 3804 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3805 case DRM_EDID_DIGITAL_DEPTH_6: 3806 info->bpc = 6; 3807 break; 3808 case DRM_EDID_DIGITAL_DEPTH_8: 3809 info->bpc = 8; 3810 break; 3811 case DRM_EDID_DIGITAL_DEPTH_10: 3812 info->bpc = 10; 3813 break; 3814 case DRM_EDID_DIGITAL_DEPTH_12: 3815 info->bpc = 12; 3816 break; 3817 case DRM_EDID_DIGITAL_DEPTH_14: 3818 info->bpc = 14; 3819 break; 3820 case DRM_EDID_DIGITAL_DEPTH_16: 3821 info->bpc = 16; 3822 break; 3823 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3824 default: 3825 info->bpc = 0; 3826 break; 3827 } 3828 3829 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3830 connector->name, info->bpc); 3831 3832 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3833 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3834 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3835 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3836 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3837 } 3838 3839 /** 3840 * drm_add_edid_modes - add modes from EDID data, if available 3841 * @connector: connector we're probing 3842 * @edid: EDID data 3843 * 3844 * Add the specified modes to the connector's mode list. 3845 * 3846 * Return: The number of modes added or 0 if we couldn't find any. 3847 */ 3848 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3849 { 3850 int num_modes = 0; 3851 u32 quirks; 3852 3853 if (edid == NULL) { 3854 return 0; 3855 } 3856 if (!drm_edid_is_valid(edid)) { 3857 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3858 connector->name); 3859 return 0; 3860 } 3861 3862 quirks = edid_get_quirks(edid); 3863 3864 /* 3865 * EDID spec says modes should be preferred in this order: 3866 * - preferred detailed mode 3867 * - other detailed modes from base block 3868 * - detailed modes from extension blocks 3869 * - CVT 3-byte code modes 3870 * - standard timing codes 3871 * - established timing codes 3872 * - modes inferred from GTF or CVT range information 3873 * 3874 * We get this pretty much right. 3875 * 3876 * XXX order for additional mode types in extension blocks? 3877 */ 3878 num_modes += add_detailed_modes(connector, edid, quirks); 3879 num_modes += add_cvt_modes(connector, edid); 3880 num_modes += add_standard_modes(connector, edid); 3881 num_modes += add_established_modes(connector, edid); 3882 num_modes += add_cea_modes(connector, edid); 3883 num_modes += add_alternate_cea_modes(connector, edid); 3884 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3885 num_modes += add_inferred_modes(connector, edid); 3886 3887 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3888 edid_fixup_preferred(connector, quirks); 3889 3890 drm_add_display_info(edid, &connector->display_info, connector); 3891 3892 if (quirks & EDID_QUIRK_FORCE_8BPC) 3893 connector->display_info.bpc = 8; 3894 3895 if (quirks & EDID_QUIRK_FORCE_12BPC) 3896 connector->display_info.bpc = 12; 3897 3898 return num_modes; 3899 } 3900 EXPORT_SYMBOL(drm_add_edid_modes); 3901 3902 /** 3903 * drm_add_modes_noedid - add modes for the connectors without EDID 3904 * @connector: connector we're probing 3905 * @hdisplay: the horizontal display limit 3906 * @vdisplay: the vertical display limit 3907 * 3908 * Add the specified modes to the connector's mode list. Only when the 3909 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3910 * 3911 * Return: The number of modes added or 0 if we couldn't find any. 3912 */ 3913 int drm_add_modes_noedid(struct drm_connector *connector, 3914 int hdisplay, int vdisplay) 3915 { 3916 int i, count, num_modes = 0; 3917 struct drm_display_mode *mode; 3918 struct drm_device *dev = connector->dev; 3919 3920 count = ARRAY_SIZE(drm_dmt_modes); 3921 if (hdisplay < 0) 3922 hdisplay = 0; 3923 if (vdisplay < 0) 3924 vdisplay = 0; 3925 3926 for (i = 0; i < count; i++) { 3927 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3928 if (hdisplay && vdisplay) { 3929 /* 3930 * Only when two are valid, they will be used to check 3931 * whether the mode should be added to the mode list of 3932 * the connector. 3933 */ 3934 if (ptr->hdisplay > hdisplay || 3935 ptr->vdisplay > vdisplay) 3936 continue; 3937 } 3938 if (drm_mode_vrefresh(ptr) > 61) 3939 continue; 3940 mode = drm_mode_duplicate(dev, ptr); 3941 if (mode) { 3942 drm_mode_probed_add(connector, mode); 3943 num_modes++; 3944 } 3945 } 3946 return num_modes; 3947 } 3948 EXPORT_SYMBOL(drm_add_modes_noedid); 3949 3950 /** 3951 * drm_set_preferred_mode - Sets the preferred mode of a connector 3952 * @connector: connector whose mode list should be processed 3953 * @hpref: horizontal resolution of preferred mode 3954 * @vpref: vertical resolution of preferred mode 3955 * 3956 * Marks a mode as preferred if it matches the resolution specified by @hpref 3957 * and @vpref. 3958 */ 3959 void drm_set_preferred_mode(struct drm_connector *connector, 3960 int hpref, int vpref) 3961 { 3962 struct drm_display_mode *mode; 3963 3964 list_for_each_entry(mode, &connector->probed_modes, head) { 3965 if (mode->hdisplay == hpref && 3966 mode->vdisplay == vpref) 3967 mode->type |= DRM_MODE_TYPE_PREFERRED; 3968 } 3969 } 3970 EXPORT_SYMBOL(drm_set_preferred_mode); 3971 3972 /** 3973 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3974 * data from a DRM display mode 3975 * @frame: HDMI AVI infoframe 3976 * @mode: DRM display mode 3977 * 3978 * Return: 0 on success or a negative error code on failure. 3979 */ 3980 int 3981 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3982 const struct drm_display_mode *mode) 3983 { 3984 int err; 3985 3986 if (!frame || !mode) 3987 return -EINVAL; 3988 3989 err = hdmi_avi_infoframe_init(frame); 3990 if (err < 0) 3991 return err; 3992 3993 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3994 frame->pixel_repeat = 1; 3995 3996 frame->video_code = drm_match_cea_mode(mode); 3997 3998 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3999 4000 /* 4001 * Populate picture aspect ratio from either 4002 * user input (if specified) or from the CEA mode list. 4003 */ 4004 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4005 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4006 frame->picture_aspect = mode->picture_aspect_ratio; 4007 else if (frame->video_code > 0) 4008 frame->picture_aspect = drm_get_cea_aspect_ratio( 4009 frame->video_code); 4010 4011 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4012 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4013 4014 return 0; 4015 } 4016 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4017 4018 static enum hdmi_3d_structure 4019 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4020 { 4021 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4022 4023 switch (layout) { 4024 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4025 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4026 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4027 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4028 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4029 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4030 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4031 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4032 case DRM_MODE_FLAG_3D_L_DEPTH: 4033 return HDMI_3D_STRUCTURE_L_DEPTH; 4034 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4035 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4036 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4037 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4038 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4039 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4040 default: 4041 return HDMI_3D_STRUCTURE_INVALID; 4042 } 4043 } 4044 4045 /** 4046 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4047 * data from a DRM display mode 4048 * @frame: HDMI vendor infoframe 4049 * @mode: DRM display mode 4050 * 4051 * Note that there's is a need to send HDMI vendor infoframes only when using a 4052 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4053 * function will return -EINVAL, error that can be safely ignored. 4054 * 4055 * Return: 0 on success or a negative error code on failure. 4056 */ 4057 int 4058 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4059 const struct drm_display_mode *mode) 4060 { 4061 int err; 4062 u32 s3d_flags; 4063 u8 vic; 4064 4065 if (!frame || !mode) 4066 return -EINVAL; 4067 4068 vic = drm_match_hdmi_mode(mode); 4069 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4070 4071 if (!vic && !s3d_flags) 4072 return -EINVAL; 4073 4074 if (vic && s3d_flags) 4075 return -EINVAL; 4076 4077 err = hdmi_vendor_infoframe_init(frame); 4078 if (err < 0) 4079 return err; 4080 4081 if (vic) 4082 frame->vic = vic; 4083 else 4084 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4085 4086 return 0; 4087 } 4088 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4089