1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/hdmi.h> 32 #include <linux/i2c.h> 33 #include <linux/module.h> 34 #include <drm/drmP.h> 35 #include <drm/drm_edid.h> 36 #include <linux/string.h> 37 38 #include <bus/iicbus/iic.h> 39 #include <bus/iicbus/iiconf.h> 40 #include "iicbus_if.h" 41 42 #define version_greater(edid, maj, min) \ 43 (((edid)->version > (maj)) || \ 44 ((edid)->version == (maj) && (edid)->revision > (min))) 45 46 #define EDID_EST_TIMINGS 16 47 #define EDID_STD_TIMINGS 8 48 #define EDID_DETAILED_TIMINGS 4 49 50 /* 51 * EDID blocks out in the wild have a variety of bugs, try to collect 52 * them here (note that userspace may work around broken monitors first, 53 * but fixes should make their way here so that the kernel "just works" 54 * on as many displays as possible). 55 */ 56 57 /* First detailed mode wrong, use largest 60Hz mode */ 58 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 59 /* Reported 135MHz pixel clock is too high, needs adjustment */ 60 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 61 /* Prefer the largest mode at 75 Hz */ 62 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 63 /* Detail timing is in cm not mm */ 64 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 65 /* Detailed timing descriptors have bogus size values, so just take the 66 * maximum size and use that. 67 */ 68 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 69 /* Monitor forgot to set the first detailed is preferred bit. */ 70 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 71 /* use +hsync +vsync for detailed mode */ 72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 73 /* Force reduced-blanking timings for detailed modes */ 74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 75 /* Force 8bpc */ 76 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 77 /* Force 12bpc */ 78 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 79 80 struct detailed_mode_closure { 81 struct drm_connector *connector; 82 struct edid *edid; 83 bool preferred; 84 u32 quirks; 85 int modes; 86 }; 87 88 #define LEVEL_DMT 0 89 #define LEVEL_GTF 1 90 #define LEVEL_GTF2 2 91 #define LEVEL_CVT 3 92 93 static struct edid_quirk { 94 char vendor[4]; 95 int product_id; 96 u32 quirks; 97 } edid_quirk_list[] = { 98 /* Acer AL1706 */ 99 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 100 /* Acer F51 */ 101 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 102 /* Unknown Acer */ 103 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 104 105 /* Belinea 10 15 55 */ 106 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 107 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 108 109 /* Envision Peripherals, Inc. EN-7100e */ 110 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 111 /* Envision EN2028 */ 112 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 113 114 /* Funai Electronics PM36B */ 115 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 116 EDID_QUIRK_DETAILED_IN_CM }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 }; 146 147 /* 148 * Autogenerated from the DMT spec. 149 * This table is copied from xfree86/modes/xf86EdidModes.c. 150 */ 151 static const struct drm_display_mode drm_dmt_modes[] = { 152 /* 0x01 - 640x350@85Hz */ 153 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 154 736, 832, 0, 350, 382, 385, 445, 0, 155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 156 /* 0x02 - 640x400@85Hz */ 157 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 158 736, 832, 0, 400, 401, 404, 445, 0, 159 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 160 /* 0x03 - 720x400@85Hz */ 161 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 162 828, 936, 0, 400, 401, 404, 446, 0, 163 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 164 /* 0x04 - 640x480@60Hz */ 165 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 166 752, 800, 0, 480, 490, 492, 525, 0, 167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 168 /* 0x05 - 640x480@72Hz */ 169 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 170 704, 832, 0, 480, 489, 492, 520, 0, 171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 172 /* 0x06 - 640x480@75Hz */ 173 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 174 720, 840, 0, 480, 481, 484, 500, 0, 175 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 176 /* 0x07 - 640x480@85Hz */ 177 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 178 752, 832, 0, 480, 481, 484, 509, 0, 179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 180 /* 0x08 - 800x600@56Hz */ 181 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 182 896, 1024, 0, 600, 601, 603, 625, 0, 183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 184 /* 0x09 - 800x600@60Hz */ 185 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 186 968, 1056, 0, 600, 601, 605, 628, 0, 187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 188 /* 0x0a - 800x600@72Hz */ 189 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 190 976, 1040, 0, 600, 637, 643, 666, 0, 191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 192 /* 0x0b - 800x600@75Hz */ 193 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 194 896, 1056, 0, 600, 601, 604, 625, 0, 195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 196 /* 0x0c - 800x600@85Hz */ 197 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 198 896, 1048, 0, 600, 601, 604, 631, 0, 199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 200 /* 0x0d - 800x600@120Hz RB */ 201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 202 880, 960, 0, 600, 603, 607, 636, 0, 203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 204 /* 0x0e - 848x480@60Hz */ 205 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 206 976, 1088, 0, 480, 486, 494, 517, 0, 207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 208 /* 0x0f - 1024x768@43Hz, interlace */ 209 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 210 1208, 1264, 0, 768, 768, 772, 817, 0, 211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 212 DRM_MODE_FLAG_INTERLACE) }, 213 /* 0x10 - 1024x768@60Hz */ 214 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 215 1184, 1344, 0, 768, 771, 777, 806, 0, 216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 217 /* 0x11 - 1024x768@70Hz */ 218 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 219 1184, 1328, 0, 768, 771, 777, 806, 0, 220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 221 /* 0x12 - 1024x768@75Hz */ 222 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 223 1136, 1312, 0, 768, 769, 772, 800, 0, 224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 225 /* 0x13 - 1024x768@85Hz */ 226 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 227 1168, 1376, 0, 768, 769, 772, 808, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 229 /* 0x14 - 1024x768@120Hz RB */ 230 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 231 1104, 1184, 0, 768, 771, 775, 813, 0, 232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 233 /* 0x15 - 1152x864@75Hz */ 234 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 235 1344, 1600, 0, 864, 865, 868, 900, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 237 /* 0x55 - 1280x720@60Hz */ 238 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 239 1430, 1650, 0, 720, 725, 730, 750, 0, 240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 241 /* 0x16 - 1280x768@60Hz RB */ 242 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 243 1360, 1440, 0, 768, 771, 778, 790, 0, 244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 245 /* 0x17 - 1280x768@60Hz */ 246 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 247 1472, 1664, 0, 768, 771, 778, 798, 0, 248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 249 /* 0x18 - 1280x768@75Hz */ 250 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 251 1488, 1696, 0, 768, 771, 778, 805, 0, 252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 253 /* 0x19 - 1280x768@85Hz */ 254 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 255 1496, 1712, 0, 768, 771, 778, 809, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 257 /* 0x1a - 1280x768@120Hz RB */ 258 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 259 1360, 1440, 0, 768, 771, 778, 813, 0, 260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 261 /* 0x1b - 1280x800@60Hz RB */ 262 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 263 1360, 1440, 0, 800, 803, 809, 823, 0, 264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 265 /* 0x1c - 1280x800@60Hz */ 266 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 267 1480, 1680, 0, 800, 803, 809, 831, 0, 268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 269 /* 0x1d - 1280x800@75Hz */ 270 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 271 1488, 1696, 0, 800, 803, 809, 838, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 273 /* 0x1e - 1280x800@85Hz */ 274 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 275 1496, 1712, 0, 800, 803, 809, 843, 0, 276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 277 /* 0x1f - 1280x800@120Hz RB */ 278 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 279 1360, 1440, 0, 800, 803, 809, 847, 0, 280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 281 /* 0x20 - 1280x960@60Hz */ 282 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 283 1488, 1800, 0, 960, 961, 964, 1000, 0, 284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 285 /* 0x21 - 1280x960@85Hz */ 286 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 287 1504, 1728, 0, 960, 961, 964, 1011, 0, 288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 289 /* 0x22 - 1280x960@120Hz RB */ 290 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 291 1360, 1440, 0, 960, 963, 967, 1017, 0, 292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 293 /* 0x23 - 1280x1024@60Hz */ 294 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 295 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 297 /* 0x24 - 1280x1024@75Hz */ 298 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 299 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 301 /* 0x25 - 1280x1024@85Hz */ 302 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 303 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 0x26 - 1280x1024@120Hz RB */ 306 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 307 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 309 /* 0x27 - 1360x768@60Hz */ 310 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 311 1536, 1792, 0, 768, 771, 777, 795, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 313 /* 0x28 - 1360x768@120Hz RB */ 314 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 315 1440, 1520, 0, 768, 771, 776, 813, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 317 /* 0x51 - 1366x768@60Hz */ 318 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 319 1579, 1792, 0, 768, 771, 774, 798, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x56 - 1366x768@60Hz */ 322 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 323 1436, 1500, 0, 768, 769, 772, 800, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 325 /* 0x29 - 1400x1050@60Hz RB */ 326 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 327 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 329 /* 0x2a - 1400x1050@60Hz */ 330 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 331 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 332 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x2b - 1400x1050@75Hz */ 334 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 335 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 337 /* 0x2c - 1400x1050@85Hz */ 338 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 339 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x2d - 1400x1050@120Hz RB */ 342 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 343 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 345 /* 0x2e - 1440x900@60Hz RB */ 346 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 347 1520, 1600, 0, 900, 903, 909, 926, 0, 348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 349 /* 0x2f - 1440x900@60Hz */ 350 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 351 1672, 1904, 0, 900, 903, 909, 934, 0, 352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 353 /* 0x30 - 1440x900@75Hz */ 354 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 355 1688, 1936, 0, 900, 903, 909, 942, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x31 - 1440x900@85Hz */ 358 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 359 1696, 1952, 0, 900, 903, 909, 948, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x32 - 1440x900@120Hz RB */ 362 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 363 1520, 1600, 0, 900, 903, 909, 953, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 365 /* 0x53 - 1600x900@60Hz */ 366 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 367 1704, 1800, 0, 900, 901, 904, 1000, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x33 - 1600x1200@60Hz */ 370 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 371 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x34 - 1600x1200@65Hz */ 374 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 375 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x35 - 1600x1200@70Hz */ 378 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 379 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x36 - 1600x1200@75Hz */ 382 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 383 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x37 - 1600x1200@85Hz */ 386 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 387 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x38 - 1600x1200@120Hz RB */ 390 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 391 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 393 /* 0x39 - 1680x1050@60Hz RB */ 394 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 395 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 397 /* 0x3a - 1680x1050@60Hz */ 398 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 399 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 400 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 0x3b - 1680x1050@75Hz */ 402 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 403 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x3c - 1680x1050@85Hz */ 406 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 407 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x3d - 1680x1050@120Hz RB */ 410 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 411 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 413 /* 0x3e - 1792x1344@60Hz */ 414 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 415 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x3f - 1792x1344@75Hz */ 418 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 419 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 421 /* 0x40 - 1792x1344@120Hz RB */ 422 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 423 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 425 /* 0x41 - 1856x1392@60Hz */ 426 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 427 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x42 - 1856x1392@75Hz */ 430 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 431 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x43 - 1856x1392@120Hz RB */ 434 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 435 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 437 /* 0x52 - 1920x1080@60Hz */ 438 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 439 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 441 /* 0x44 - 1920x1200@60Hz RB */ 442 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 443 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 445 /* 0x45 - 1920x1200@60Hz */ 446 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 447 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x46 - 1920x1200@75Hz */ 450 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 451 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x47 - 1920x1200@85Hz */ 454 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 455 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x48 - 1920x1200@120Hz RB */ 458 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 459 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 461 /* 0x49 - 1920x1440@60Hz */ 462 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 463 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x4a - 1920x1440@75Hz */ 466 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 467 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 0x4b - 1920x1440@120Hz RB */ 470 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 471 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 473 /* 0x54 - 2048x1152@60Hz */ 474 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 475 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x4c - 2560x1600@60Hz RB */ 478 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 479 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 481 /* 0x4d - 2560x1600@60Hz */ 482 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 483 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 485 /* 0x4e - 2560x1600@75Hz */ 486 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 487 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x4f - 2560x1600@85Hz */ 490 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 491 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x50 - 2560x1600@120Hz RB */ 494 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 495 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 497 /* 0x57 - 4096x2160@60Hz RB */ 498 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 499 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 501 /* 0x58 - 4096x2160@59.94Hz RB */ 502 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 503 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 505 }; 506 507 /* 508 * These more or less come from the DMT spec. The 720x400 modes are 509 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 510 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 511 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 512 * mode. 513 * 514 * The DMT modes have been fact-checked; the rest are mild guesses. 515 */ 516 static const struct drm_display_mode edid_est_modes[] = { 517 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 518 968, 1056, 0, 600, 601, 605, 628, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 520 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 521 896, 1024, 0, 600, 601, 603, 625, 0, 522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 523 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 524 720, 840, 0, 480, 481, 484, 500, 0, 525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 526 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 527 704, 832, 0, 480, 489, 491, 520, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 529 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 530 768, 864, 0, 480, 483, 486, 525, 0, 531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 533 752, 800, 0, 480, 490, 492, 525, 0, 534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 535 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 536 846, 900, 0, 400, 421, 423, 449, 0, 537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 538 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 539 846, 900, 0, 400, 412, 414, 449, 0, 540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 541 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 542 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 544 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 545 1136, 1312, 0, 768, 769, 772, 800, 0, 546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 547 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 548 1184, 1328, 0, 768, 771, 777, 806, 0, 549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 550 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 551 1184, 1344, 0, 768, 771, 777, 806, 0, 552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 553 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 554 1208, 1264, 0, 768, 768, 776, 817, 0, 555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 556 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 557 928, 1152, 0, 624, 625, 628, 667, 0, 558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 559 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 560 896, 1056, 0, 600, 601, 604, 625, 0, 561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 562 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 563 976, 1040, 0, 600, 637, 643, 666, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 565 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 566 1344, 1600, 0, 864, 865, 868, 900, 0, 567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 568 }; 569 570 struct minimode { 571 short w; 572 short h; 573 short r; 574 short rb; 575 }; 576 577 static const struct minimode est3_modes[] = { 578 /* byte 6 */ 579 { 640, 350, 85, 0 }, 580 { 640, 400, 85, 0 }, 581 { 720, 400, 85, 0 }, 582 { 640, 480, 85, 0 }, 583 { 848, 480, 60, 0 }, 584 { 800, 600, 85, 0 }, 585 { 1024, 768, 85, 0 }, 586 { 1152, 864, 75, 0 }, 587 /* byte 7 */ 588 { 1280, 768, 60, 1 }, 589 { 1280, 768, 60, 0 }, 590 { 1280, 768, 75, 0 }, 591 { 1280, 768, 85, 0 }, 592 { 1280, 960, 60, 0 }, 593 { 1280, 960, 85, 0 }, 594 { 1280, 1024, 60, 0 }, 595 { 1280, 1024, 85, 0 }, 596 /* byte 8 */ 597 { 1360, 768, 60, 0 }, 598 { 1440, 900, 60, 1 }, 599 { 1440, 900, 60, 0 }, 600 { 1440, 900, 75, 0 }, 601 { 1440, 900, 85, 0 }, 602 { 1400, 1050, 60, 1 }, 603 { 1400, 1050, 60, 0 }, 604 { 1400, 1050, 75, 0 }, 605 /* byte 9 */ 606 { 1400, 1050, 85, 0 }, 607 { 1680, 1050, 60, 1 }, 608 { 1680, 1050, 60, 0 }, 609 { 1680, 1050, 75, 0 }, 610 { 1680, 1050, 85, 0 }, 611 { 1600, 1200, 60, 0 }, 612 { 1600, 1200, 65, 0 }, 613 { 1600, 1200, 70, 0 }, 614 /* byte 10 */ 615 { 1600, 1200, 75, 0 }, 616 { 1600, 1200, 85, 0 }, 617 { 1792, 1344, 60, 0 }, 618 { 1792, 1344, 75, 0 }, 619 { 1856, 1392, 60, 0 }, 620 { 1856, 1392, 75, 0 }, 621 { 1920, 1200, 60, 1 }, 622 { 1920, 1200, 60, 0 }, 623 /* byte 11 */ 624 { 1920, 1200, 75, 0 }, 625 { 1920, 1200, 85, 0 }, 626 { 1920, 1440, 60, 0 }, 627 { 1920, 1440, 75, 0 }, 628 }; 629 630 static const struct minimode extra_modes[] = { 631 { 1024, 576, 60, 0 }, 632 { 1366, 768, 60, 0 }, 633 { 1600, 900, 60, 0 }, 634 { 1680, 945, 60, 0 }, 635 { 1920, 1080, 60, 0 }, 636 { 2048, 1152, 60, 0 }, 637 { 2048, 1536, 60, 0 }, 638 }; 639 640 /* 641 * Probably taken from CEA-861 spec. 642 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 643 * 644 * Index using the VIC. 645 */ 646 static const struct drm_display_mode edid_cea_modes[] = { 647 /* 0 - dummy, VICs start at 1 */ 648 { }, 649 /* 1 - 640x480@60Hz */ 650 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 651 752, 800, 0, 480, 490, 492, 525, 0, 652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 653 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 654 /* 2 - 720x480@60Hz */ 655 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 656 798, 858, 0, 480, 489, 495, 525, 0, 657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 658 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 659 /* 3 - 720x480@60Hz */ 660 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 661 798, 858, 0, 480, 489, 495, 525, 0, 662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 663 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 664 /* 4 - 1280x720@60Hz */ 665 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 666 1430, 1650, 0, 720, 725, 730, 750, 0, 667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 669 /* 5 - 1920x1080i@60Hz */ 670 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 671 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 673 DRM_MODE_FLAG_INTERLACE), 674 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 675 /* 6 - 720(1440)x480i@60Hz */ 676 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 677 801, 858, 0, 480, 488, 494, 525, 0, 678 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 679 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 681 /* 7 - 720(1440)x480i@60Hz */ 682 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 683 801, 858, 0, 480, 488, 494, 525, 0, 684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 685 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 687 /* 8 - 720(1440)x240@60Hz */ 688 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 689 801, 858, 0, 240, 244, 247, 262, 0, 690 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 691 DRM_MODE_FLAG_DBLCLK), 692 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 693 /* 9 - 720(1440)x240@60Hz */ 694 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 695 801, 858, 0, 240, 244, 247, 262, 0, 696 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 697 DRM_MODE_FLAG_DBLCLK), 698 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 699 /* 10 - 2880x480i@60Hz */ 700 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 701 3204, 3432, 0, 480, 488, 494, 525, 0, 702 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 703 DRM_MODE_FLAG_INTERLACE), 704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 705 /* 11 - 2880x480i@60Hz */ 706 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 707 3204, 3432, 0, 480, 488, 494, 525, 0, 708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 709 DRM_MODE_FLAG_INTERLACE), 710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 711 /* 12 - 2880x240@60Hz */ 712 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 713 3204, 3432, 0, 240, 244, 247, 262, 0, 714 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 716 /* 13 - 2880x240@60Hz */ 717 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 718 3204, 3432, 0, 240, 244, 247, 262, 0, 719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 721 /* 14 - 1440x480@60Hz */ 722 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 723 1596, 1716, 0, 480, 489, 495, 525, 0, 724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 726 /* 15 - 1440x480@60Hz */ 727 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 728 1596, 1716, 0, 480, 489, 495, 525, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 731 /* 16 - 1920x1080@60Hz */ 732 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 733 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 734 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 736 /* 17 - 720x576@50Hz */ 737 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 738 796, 864, 0, 576, 581, 586, 625, 0, 739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 740 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 741 /* 18 - 720x576@50Hz */ 742 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 743 796, 864, 0, 576, 581, 586, 625, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 745 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 746 /* 19 - 1280x720@50Hz */ 747 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 748 1760, 1980, 0, 720, 725, 730, 750, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 751 /* 20 - 1920x1080i@50Hz */ 752 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 753 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 755 DRM_MODE_FLAG_INTERLACE), 756 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 21 - 720(1440)x576i@50Hz */ 758 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 759 795, 864, 0, 576, 580, 586, 625, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 761 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 763 /* 22 - 720(1440)x576i@50Hz */ 764 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 765 795, 864, 0, 576, 580, 586, 625, 0, 766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 767 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 23 - 720(1440)x288@50Hz */ 770 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 771 795, 864, 0, 288, 290, 293, 312, 0, 772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 773 DRM_MODE_FLAG_DBLCLK), 774 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 775 /* 24 - 720(1440)x288@50Hz */ 776 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 777 795, 864, 0, 288, 290, 293, 312, 0, 778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 779 DRM_MODE_FLAG_DBLCLK), 780 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 781 /* 25 - 2880x576i@50Hz */ 782 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 783 3180, 3456, 0, 576, 580, 586, 625, 0, 784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 785 DRM_MODE_FLAG_INTERLACE), 786 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 787 /* 26 - 2880x576i@50Hz */ 788 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 789 3180, 3456, 0, 576, 580, 586, 625, 0, 790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 791 DRM_MODE_FLAG_INTERLACE), 792 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 793 /* 27 - 2880x288@50Hz */ 794 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 795 3180, 3456, 0, 288, 290, 293, 312, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 798 /* 28 - 2880x288@50Hz */ 799 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 800 3180, 3456, 0, 288, 290, 293, 312, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 803 /* 29 - 1440x576@50Hz */ 804 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 805 1592, 1728, 0, 576, 581, 586, 625, 0, 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 808 /* 30 - 1440x576@50Hz */ 809 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 810 1592, 1728, 0, 576, 581, 586, 625, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 813 /* 31 - 1920x1080@50Hz */ 814 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 815 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 818 /* 32 - 1920x1080@24Hz */ 819 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 820 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 822 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 33 - 1920x1080@25Hz */ 824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 825 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 827 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 34 - 1920x1080@30Hz */ 829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 830 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 832 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 35 - 2880x480@60Hz */ 834 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 835 3192, 3432, 0, 480, 489, 495, 525, 0, 836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 837 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 838 /* 36 - 2880x480@60Hz */ 839 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 840 3192, 3432, 0, 480, 489, 495, 525, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 842 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 843 /* 37 - 2880x576@50Hz */ 844 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 845 3184, 3456, 0, 576, 581, 586, 625, 0, 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 847 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 848 /* 38 - 2880x576@50Hz */ 849 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 850 3184, 3456, 0, 576, 581, 586, 625, 0, 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 853 /* 39 - 1920x1080i@50Hz */ 854 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 855 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 857 DRM_MODE_FLAG_INTERLACE), 858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 40 - 1920x1080i@100Hz */ 860 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 861 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 863 DRM_MODE_FLAG_INTERLACE), 864 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 865 /* 41 - 1280x720@100Hz */ 866 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 867 1760, 1980, 0, 720, 725, 730, 750, 0, 868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 869 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 42 - 720x576@100Hz */ 871 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 872 796, 864, 0, 576, 581, 586, 625, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 874 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 875 /* 43 - 720x576@100Hz */ 876 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 877 796, 864, 0, 576, 581, 586, 625, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 880 /* 44 - 720(1440)x576i@100Hz */ 881 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 882 795, 864, 0, 576, 580, 586, 625, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 884 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 885 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 886 /* 45 - 720(1440)x576i@100Hz */ 887 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 888 795, 864, 0, 576, 580, 586, 625, 0, 889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 890 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 891 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 892 /* 46 - 1920x1080i@120Hz */ 893 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 894 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 896 DRM_MODE_FLAG_INTERLACE), 897 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 898 /* 47 - 1280x720@120Hz */ 899 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 900 1430, 1650, 0, 720, 725, 730, 750, 0, 901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 902 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 48 - 720x480@120Hz */ 904 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 905 798, 858, 0, 480, 489, 495, 525, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 907 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 908 /* 49 - 720x480@120Hz */ 909 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 910 798, 858, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 50 - 720(1440)x480i@120Hz */ 914 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 915 801, 858, 0, 480, 488, 494, 525, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 917 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 918 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 919 /* 51 - 720(1440)x480i@120Hz */ 920 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 921 801, 858, 0, 480, 488, 494, 525, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 923 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 924 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 925 /* 52 - 720x576@200Hz */ 926 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 927 796, 864, 0, 576, 581, 586, 625, 0, 928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 929 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 930 /* 53 - 720x576@200Hz */ 931 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 932 796, 864, 0, 576, 581, 586, 625, 0, 933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 934 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 935 /* 54 - 720(1440)x576i@200Hz */ 936 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 937 795, 864, 0, 576, 580, 586, 625, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 939 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 940 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 941 /* 55 - 720(1440)x576i@200Hz */ 942 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 943 795, 864, 0, 576, 580, 586, 625, 0, 944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 945 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 946 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 947 /* 56 - 720x480@240Hz */ 948 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 949 798, 858, 0, 480, 489, 495, 525, 0, 950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 951 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 952 /* 57 - 720x480@240Hz */ 953 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 954 798, 858, 0, 480, 489, 495, 525, 0, 955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 956 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 957 /* 58 - 720(1440)x480i@240 */ 958 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 959 801, 858, 0, 480, 488, 494, 525, 0, 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 961 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 962 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 963 /* 59 - 720(1440)x480i@240 */ 964 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 965 801, 858, 0, 480, 488, 494, 525, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 968 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 969 /* 60 - 1280x720@24Hz */ 970 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 971 3080, 3300, 0, 720, 725, 730, 750, 0, 972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 973 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 974 /* 61 - 1280x720@25Hz */ 975 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 976 3740, 3960, 0, 720, 725, 730, 750, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 978 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 979 /* 62 - 1280x720@30Hz */ 980 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 981 3080, 3300, 0, 720, 725, 730, 750, 0, 982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 983 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 63 - 1920x1080@120Hz */ 985 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 986 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 988 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 64 - 1920x1080@100Hz */ 990 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 991 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 993 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 }; 995 996 /* 997 * HDMI 1.4 4k modes. Index using the VIC. 998 */ 999 static const struct drm_display_mode edid_4k_modes[] = { 1000 /* 0 - dummy, VICs start at 1 */ 1001 { }, 1002 /* 1 - 3840x2160@30Hz */ 1003 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1004 3840, 4016, 4104, 4400, 0, 1005 2160, 2168, 2178, 2250, 0, 1006 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1007 .vrefresh = 30, }, 1008 /* 2 - 3840x2160@25Hz */ 1009 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1010 3840, 4896, 4984, 5280, 0, 1011 2160, 2168, 2178, 2250, 0, 1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1013 .vrefresh = 25, }, 1014 /* 3 - 3840x2160@24Hz */ 1015 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1016 3840, 5116, 5204, 5500, 0, 1017 2160, 2168, 2178, 2250, 0, 1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1019 .vrefresh = 24, }, 1020 /* 4 - 4096x2160@24Hz (SMPTE) */ 1021 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1022 4096, 5116, 5204, 5500, 0, 1023 2160, 2168, 2178, 2250, 0, 1024 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1025 .vrefresh = 24, }, 1026 }; 1027 1028 /*** DDC fetch and block validation ***/ 1029 1030 static const u8 edid_header[] = { 1031 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1032 }; 1033 1034 /** 1035 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1036 * @raw_edid: pointer to raw base EDID block 1037 * 1038 * Sanity check the header of the base EDID block. 1039 * 1040 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1041 */ 1042 int drm_edid_header_is_valid(const u8 *raw_edid) 1043 { 1044 int i, score = 0; 1045 1046 for (i = 0; i < sizeof(edid_header); i++) 1047 if (raw_edid[i] == edid_header[i]) 1048 score++; 1049 1050 return score; 1051 } 1052 EXPORT_SYMBOL(drm_edid_header_is_valid); 1053 1054 static int edid_fixup __read_mostly = 6; 1055 module_param_named(edid_fixup, edid_fixup, int, 0400); 1056 MODULE_PARM_DESC(edid_fixup, 1057 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1058 1059 static int drm_edid_block_checksum(const u8 *raw_edid) 1060 { 1061 int i; 1062 u8 csum = 0; 1063 for (i = 0; i < EDID_LENGTH; i++) 1064 csum += raw_edid[i]; 1065 1066 return csum; 1067 } 1068 1069 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1070 { 1071 if (memchr_inv(in_edid, 0, length)) 1072 return false; 1073 1074 return true; 1075 } 1076 1077 /** 1078 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1079 * @raw_edid: pointer to raw EDID block 1080 * @block: type of block to validate (0 for base, extension otherwise) 1081 * @print_bad_edid: if true, dump bad EDID blocks to the console 1082 * @edid_corrupt: if true, the header or checksum is invalid 1083 * 1084 * Validate a base or extension EDID block and optionally dump bad blocks to 1085 * the console. 1086 * 1087 * Return: True if the block is valid, false otherwise. 1088 */ 1089 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1090 bool *edid_corrupt) 1091 { 1092 int i; 1093 u8 csum; 1094 struct edid *edid = (struct edid *)raw_edid; 1095 1096 if (WARN_ON(!raw_edid)) 1097 return false; 1098 1099 if (edid_fixup > 8 || edid_fixup < 0) 1100 edid_fixup = 6; 1101 1102 if (block == 0) { 1103 int score = drm_edid_header_is_valid(raw_edid); 1104 if (score == 8) { 1105 if (edid_corrupt) 1106 *edid_corrupt = false; 1107 } else if (score >= edid_fixup) { 1108 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1109 * The corrupt flag needs to be set here otherwise, the 1110 * fix-up code here will correct the problem, the 1111 * checksum is correct and the test fails 1112 */ 1113 if (edid_corrupt) 1114 *edid_corrupt = true; 1115 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1116 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1117 } else { 1118 if (edid_corrupt) 1119 *edid_corrupt = true; 1120 goto bad; 1121 } 1122 } 1123 1124 csum = drm_edid_block_checksum(raw_edid); 1125 if (csum) { 1126 if (print_bad_edid) { 1127 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1128 } 1129 1130 if (edid_corrupt) 1131 *edid_corrupt = true; 1132 1133 /* allow CEA to slide through, switches mangle this */ 1134 if (raw_edid[0] != 0x02) 1135 goto bad; 1136 } 1137 1138 /* per-block-type checks */ 1139 switch (raw_edid[0]) { 1140 case 0: /* base */ 1141 if (edid->version != 1) { 1142 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1143 goto bad; 1144 } 1145 1146 if (edid->revision > 4) 1147 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1148 break; 1149 1150 default: 1151 break; 1152 } 1153 1154 return true; 1155 1156 bad: 1157 if (print_bad_edid) { 1158 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1159 printk(KERN_ERR "EDID block is all zeroes\n"); 1160 } else { 1161 printk(KERN_ERR "Raw EDID:\n"); 1162 for (i = 0; i < EDID_LENGTH; ) { 1163 kprintf("%02x", raw_edid[i]); 1164 i++; 1165 if (i % 16 == 0 || i == EDID_LENGTH) 1166 kprintf("\n"); 1167 else if (i % 8 == 0) 1168 kprintf(" "); 1169 else 1170 kprintf(" "); 1171 } 1172 } 1173 } 1174 return false; 1175 } 1176 EXPORT_SYMBOL(drm_edid_block_valid); 1177 1178 /** 1179 * drm_edid_is_valid - sanity check EDID data 1180 * @edid: EDID data 1181 * 1182 * Sanity-check an entire EDID record (including extensions) 1183 * 1184 * Return: True if the EDID data is valid, false otherwise. 1185 */ 1186 bool drm_edid_is_valid(struct edid *edid) 1187 { 1188 int i; 1189 u8 *raw = (u8 *)edid; 1190 1191 if (!edid) 1192 return false; 1193 1194 for (i = 0; i <= edid->extensions; i++) 1195 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1196 return false; 1197 1198 return true; 1199 } 1200 EXPORT_SYMBOL(drm_edid_is_valid); 1201 1202 #define DDC_SEGMENT_ADDR 0x30 1203 /** 1204 * drm_do_probe_ddc_edid() - get EDID information via I2C 1205 * @data: I2C device adapter 1206 * @buf: EDID data buffer to be filled 1207 * @block: 128 byte EDID block to start fetching from 1208 * @len: EDID data buffer length to fetch 1209 * 1210 * Try to fetch EDID information by calling I2C driver functions. 1211 * 1212 * Return: 0 on success or -1 on failure. 1213 */ 1214 static int 1215 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1216 { 1217 struct i2c_adapter *adapter = data; 1218 unsigned char start = block * EDID_LENGTH; 1219 unsigned char segment = block >> 1; 1220 unsigned char xfers = segment ? 3 : 2; 1221 int ret, retries = 5; 1222 1223 /* 1224 * The core I2C driver will automatically retry the transfer if the 1225 * adapter reports EAGAIN. However, we find that bit-banging transfers 1226 * are susceptible to errors under a heavily loaded machine and 1227 * generate spurious NAKs and timeouts. Retrying the transfer 1228 * of the individual block a few times seems to overcome this. 1229 */ 1230 do { 1231 struct i2c_msg msgs[] = { 1232 { 1233 .addr = DDC_SEGMENT_ADDR, 1234 .flags = 0, 1235 .len = 1, 1236 .buf = &segment, 1237 }, { 1238 .addr = DDC_ADDR, 1239 .flags = 0, 1240 .len = 1, 1241 .buf = &start, 1242 }, { 1243 .addr = DDC_ADDR, 1244 .flags = I2C_M_RD, 1245 .len = len, 1246 .buf = buf, 1247 } 1248 }; 1249 1250 /* 1251 * Avoid sending the segment addr to not upset non-compliant 1252 * DDC monitors. 1253 */ 1254 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1255 1256 if (ret == -ENXIO) { 1257 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1258 adapter->name); 1259 break; 1260 } 1261 } while (ret != xfers && --retries); 1262 1263 return ret == xfers ? 0 : -1; 1264 } 1265 1266 /* 1267 * Old version of drm_do_probe_ddc_edid, still using 1268 * the FreeBSD/DragonFly iic API 1269 */ 1270 static int 1271 drm_do_probe_ddc_edid_iic(void *data, u8 *buf, unsigned int block, size_t len) 1272 { 1273 device_t adapter = data; 1274 unsigned char start = block * EDID_LENGTH; 1275 unsigned char segment = block >> 1; 1276 unsigned char xfers = segment ? 3 : 2; 1277 int ret, retries = 5; 1278 1279 /* 1280 * The core I2C driver will automatically retry the transfer if the 1281 * adapter reports EAGAIN. However, we find that bit-banging transfers 1282 * are susceptible to errors under a heavily loaded machine and 1283 * generate spurious NAKs and timeouts. Retrying the transfer 1284 * of the individual block a few times seems to overcome this. 1285 */ 1286 do { 1287 struct iic_msg msgs[] = { 1288 { 1289 .slave = DDC_SEGMENT_ADDR << 1, 1290 .flags = 0, 1291 .len = 1, 1292 .buf = &segment, 1293 }, { 1294 .slave = DDC_ADDR << 1, 1295 .flags = 0, 1296 .len = 1, 1297 .buf = &start, 1298 }, { 1299 .slave = DDC_ADDR << 1, 1300 .flags = I2C_M_RD, 1301 .len = len, 1302 .buf = buf, 1303 } 1304 }; 1305 1306 /* 1307 * Avoid sending the segment addr to not upset non-compliant 1308 * DDC monitors. 1309 */ 1310 ret = iicbus_transfer(adapter, &msgs[3 - xfers], xfers); 1311 1312 if (ret != 0) 1313 DRM_DEBUG_KMS("iicbus_transfer countdown %d error %d\n", 1314 retries, ret); 1315 } while (ret != 0 && --retries); 1316 1317 return (ret == 0 ? 0 : -1); 1318 } 1319 1320 /** 1321 * drm_do_get_edid - get EDID data using a custom EDID block read function 1322 * @connector: connector we're probing 1323 * @get_edid_block: EDID block read function 1324 * @data: private data passed to the block read function 1325 * 1326 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1327 * exposes a different interface to read EDID blocks this function can be used 1328 * to get EDID data using a custom block read function. 1329 * 1330 * As in the general case the DDC bus is accessible by the kernel at the I2C 1331 * level, drivers must make all reasonable efforts to expose it as an I2C 1332 * adapter and use drm_get_edid() instead of abusing this function. 1333 * 1334 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1335 */ 1336 struct edid *drm_do_get_edid(struct drm_connector *connector, 1337 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1338 size_t len), 1339 void *data) 1340 { 1341 int i, j = 0, valid_extensions = 0; 1342 u8 *block, *new; 1343 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1344 1345 if ((block = kmalloc(EDID_LENGTH, M_DRM, M_WAITOK)) == NULL) 1346 return NULL; 1347 1348 /* base block fetch */ 1349 for (i = 0; i < 4; i++) { 1350 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1351 goto out; 1352 if (drm_edid_block_valid(block, 0, print_bad_edid, 1353 &connector->edid_corrupt)) 1354 break; 1355 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1356 connector->null_edid_counter++; 1357 goto carp; 1358 } 1359 } 1360 if (i == 4) 1361 goto carp; 1362 1363 /* if there's no extensions, we're done */ 1364 if (block[0x7e] == 0) 1365 return (struct edid *)block; 1366 1367 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1368 if (!new) 1369 goto out; 1370 block = new; 1371 1372 for (j = 1; j <= block[0x7e]; j++) { 1373 for (i = 0; i < 4; i++) { 1374 if (get_edid_block(data, 1375 block + (valid_extensions + 1) * EDID_LENGTH, 1376 j, EDID_LENGTH)) 1377 goto out; 1378 if (drm_edid_block_valid(block + (valid_extensions + 1) 1379 * EDID_LENGTH, j, 1380 print_bad_edid, 1381 NULL)) { 1382 valid_extensions++; 1383 break; 1384 } 1385 } 1386 1387 if (i == 4 && print_bad_edid) { 1388 dev_warn(connector->dev->dev, 1389 "%s: Ignoring invalid EDID block %d.\n", 1390 connector->name, j); 1391 1392 connector->bad_edid_counter++; 1393 } 1394 } 1395 1396 if (valid_extensions != block[0x7e]) { 1397 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1398 block[0x7e] = valid_extensions; 1399 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1400 if (!new) 1401 goto out; 1402 block = new; 1403 } 1404 1405 return (struct edid *)block; 1406 1407 carp: 1408 if (print_bad_edid) { 1409 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1410 connector->name, j); 1411 } 1412 connector->bad_edid_counter++; 1413 1414 out: 1415 kfree(block); 1416 return NULL; 1417 } 1418 1419 /** 1420 * drm_probe_ddc() - probe DDC presence 1421 * @adapter: I2C adapter to probe 1422 * 1423 * Return: True on success, false on failure. 1424 */ 1425 bool 1426 drm_probe_ddc(struct i2c_adapter *adapter) 1427 { 1428 unsigned char out; 1429 1430 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1431 } 1432 EXPORT_SYMBOL(drm_probe_ddc); 1433 1434 /* 1435 * Old version of drm_probe_ddc(), still using 1436 * the FreeBSD/DragonFly iic API 1437 */ 1438 static bool 1439 drm_probe_ddc_iic(device_t adapter) 1440 { 1441 unsigned char out; 1442 1443 return (drm_do_probe_ddc_edid_iic(adapter, &out, 0, 1) == 0); 1444 } 1445 1446 /** 1447 * drm_get_edid - get EDID data, if available 1448 * @connector: connector we're probing 1449 * @adapter: I2C adapter to use for DDC 1450 * 1451 * Poke the given I2C channel to grab EDID data if possible. If found, 1452 * attach it to the connector. 1453 * 1454 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1455 */ 1456 struct edid *drm_get_edid(struct drm_connector *connector, 1457 struct i2c_adapter *adapter) 1458 { 1459 if (!drm_probe_ddc(adapter)) 1460 return NULL; 1461 1462 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1463 } 1464 EXPORT_SYMBOL(drm_get_edid); 1465 1466 /* 1467 * Old version of drm_get_edid(), still using 1468 * the FreeBSD/DragonFly iic API 1469 */ 1470 struct edid *drm_get_edid_iic(struct drm_connector *connector, 1471 device_t adapter) 1472 { 1473 if (!drm_probe_ddc_iic(adapter)) 1474 return NULL; 1475 1476 return drm_do_get_edid(connector, drm_do_probe_ddc_edid_iic, adapter); 1477 } 1478 1479 /** 1480 * drm_edid_duplicate - duplicate an EDID and the extensions 1481 * @edid: EDID to duplicate 1482 * 1483 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1484 */ 1485 struct edid *drm_edid_duplicate(const struct edid *edid) 1486 { 1487 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1488 } 1489 EXPORT_SYMBOL(drm_edid_duplicate); 1490 1491 /*** EDID parsing ***/ 1492 1493 /** 1494 * edid_vendor - match a string against EDID's obfuscated vendor field 1495 * @edid: EDID to match 1496 * @vendor: vendor string 1497 * 1498 * Returns true if @vendor is in @edid, false otherwise 1499 */ 1500 static bool edid_vendor(struct edid *edid, char *vendor) 1501 { 1502 char edid_vendor[3]; 1503 1504 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1505 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1506 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1507 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1508 1509 return !strncmp(edid_vendor, vendor, 3); 1510 } 1511 1512 /** 1513 * edid_get_quirks - return quirk flags for a given EDID 1514 * @edid: EDID to process 1515 * 1516 * This tells subsequent routines what fixes they need to apply. 1517 */ 1518 static u32 edid_get_quirks(struct edid *edid) 1519 { 1520 struct edid_quirk *quirk; 1521 int i; 1522 1523 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1524 quirk = &edid_quirk_list[i]; 1525 1526 if (edid_vendor(edid, quirk->vendor) && 1527 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1528 return quirk->quirks; 1529 } 1530 1531 return 0; 1532 } 1533 1534 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1535 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1536 1537 /** 1538 * edid_fixup_preferred - set preferred modes based on quirk list 1539 * @connector: has mode list to fix up 1540 * @quirks: quirks list 1541 * 1542 * Walk the mode list for @connector, clearing the preferred status 1543 * on existing modes and setting it anew for the right mode ala @quirks. 1544 */ 1545 static void edid_fixup_preferred(struct drm_connector *connector, 1546 u32 quirks) 1547 { 1548 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1549 int target_refresh = 0; 1550 int cur_vrefresh, preferred_vrefresh; 1551 1552 if (list_empty(&connector->probed_modes)) 1553 return; 1554 1555 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1556 target_refresh = 60; 1557 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1558 target_refresh = 75; 1559 1560 preferred_mode = list_first_entry(&connector->probed_modes, 1561 struct drm_display_mode, head); 1562 1563 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1564 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1565 1566 if (cur_mode == preferred_mode) 1567 continue; 1568 1569 /* Largest mode is preferred */ 1570 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1571 preferred_mode = cur_mode; 1572 1573 cur_vrefresh = cur_mode->vrefresh ? 1574 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1575 preferred_vrefresh = preferred_mode->vrefresh ? 1576 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1577 /* At a given size, try to get closest to target refresh */ 1578 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1579 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1580 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1581 preferred_mode = cur_mode; 1582 } 1583 } 1584 1585 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1586 } 1587 1588 static bool 1589 mode_is_rb(const struct drm_display_mode *mode) 1590 { 1591 return (mode->htotal - mode->hdisplay == 160) && 1592 (mode->hsync_end - mode->hdisplay == 80) && 1593 (mode->hsync_end - mode->hsync_start == 32) && 1594 (mode->vsync_start - mode->vdisplay == 3); 1595 } 1596 1597 /* 1598 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1599 * @dev: Device to duplicate against 1600 * @hsize: Mode width 1601 * @vsize: Mode height 1602 * @fresh: Mode refresh rate 1603 * @rb: Mode reduced-blanking-ness 1604 * 1605 * Walk the DMT mode list looking for a match for the given parameters. 1606 * 1607 * Return: A newly allocated copy of the mode, or NULL if not found. 1608 */ 1609 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1610 int hsize, int vsize, int fresh, 1611 bool rb) 1612 { 1613 int i; 1614 1615 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1616 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1617 if (hsize != ptr->hdisplay) 1618 continue; 1619 if (vsize != ptr->vdisplay) 1620 continue; 1621 if (fresh != drm_mode_vrefresh(ptr)) 1622 continue; 1623 if (rb != mode_is_rb(ptr)) 1624 continue; 1625 1626 return drm_mode_duplicate(dev, ptr); 1627 } 1628 1629 return NULL; 1630 } 1631 EXPORT_SYMBOL(drm_mode_find_dmt); 1632 1633 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1634 1635 static void 1636 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1637 { 1638 int i, n = 0; 1639 u8 d = ext[0x02]; 1640 u8 *det_base = ext + d; 1641 1642 n = (127 - d) / 18; 1643 for (i = 0; i < n; i++) 1644 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1645 } 1646 1647 static void 1648 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1649 { 1650 unsigned int i, n = min((int)ext[0x02], 6); 1651 u8 *det_base = ext + 5; 1652 1653 if (ext[0x01] != 1) 1654 return; /* unknown version */ 1655 1656 for (i = 0; i < n; i++) 1657 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1658 } 1659 1660 static void 1661 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1662 { 1663 int i; 1664 struct edid *edid = (struct edid *)raw_edid; 1665 1666 if (edid == NULL) 1667 return; 1668 1669 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1670 cb(&(edid->detailed_timings[i]), closure); 1671 1672 for (i = 1; i <= raw_edid[0x7e]; i++) { 1673 u8 *ext = raw_edid + (i * EDID_LENGTH); 1674 switch (*ext) { 1675 case CEA_EXT: 1676 cea_for_each_detailed_block(ext, cb, closure); 1677 break; 1678 case VTB_EXT: 1679 vtb_for_each_detailed_block(ext, cb, closure); 1680 break; 1681 default: 1682 break; 1683 } 1684 } 1685 } 1686 1687 static void 1688 is_rb(struct detailed_timing *t, void *data) 1689 { 1690 u8 *r = (u8 *)t; 1691 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1692 if (r[15] & 0x10) 1693 *(bool *)data = true; 1694 } 1695 1696 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1697 static bool 1698 drm_monitor_supports_rb(struct edid *edid) 1699 { 1700 if (edid->revision >= 4) { 1701 bool ret = false; 1702 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1703 return ret; 1704 } 1705 1706 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1707 } 1708 1709 static void 1710 find_gtf2(struct detailed_timing *t, void *data) 1711 { 1712 u8 *r = (u8 *)t; 1713 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1714 *(u8 **)data = r; 1715 } 1716 1717 /* Secondary GTF curve kicks in above some break frequency */ 1718 static int 1719 drm_gtf2_hbreak(struct edid *edid) 1720 { 1721 u8 *r = NULL; 1722 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1723 return r ? (r[12] * 2) : 0; 1724 } 1725 1726 static int 1727 drm_gtf2_2c(struct edid *edid) 1728 { 1729 u8 *r = NULL; 1730 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1731 return r ? r[13] : 0; 1732 } 1733 1734 static int 1735 drm_gtf2_m(struct edid *edid) 1736 { 1737 u8 *r = NULL; 1738 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1739 return r ? (r[15] << 8) + r[14] : 0; 1740 } 1741 1742 static int 1743 drm_gtf2_k(struct edid *edid) 1744 { 1745 u8 *r = NULL; 1746 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1747 return r ? r[16] : 0; 1748 } 1749 1750 static int 1751 drm_gtf2_2j(struct edid *edid) 1752 { 1753 u8 *r = NULL; 1754 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1755 return r ? r[17] : 0; 1756 } 1757 1758 /** 1759 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1760 * @edid: EDID block to scan 1761 */ 1762 static int standard_timing_level(struct edid *edid) 1763 { 1764 if (edid->revision >= 2) { 1765 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1766 return LEVEL_CVT; 1767 if (drm_gtf2_hbreak(edid)) 1768 return LEVEL_GTF2; 1769 return LEVEL_GTF; 1770 } 1771 return LEVEL_DMT; 1772 } 1773 1774 /* 1775 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1776 * monitors fill with ascii space (0x20) instead. 1777 */ 1778 static int 1779 bad_std_timing(u8 a, u8 b) 1780 { 1781 return (a == 0x00 && b == 0x00) || 1782 (a == 0x01 && b == 0x01) || 1783 (a == 0x20 && b == 0x20); 1784 } 1785 1786 /** 1787 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1788 * @connector: connector of for the EDID block 1789 * @edid: EDID block to scan 1790 * @t: standard timing params 1791 * 1792 * Take the standard timing params (in this case width, aspect, and refresh) 1793 * and convert them into a real mode using CVT/GTF/DMT. 1794 */ 1795 static struct drm_display_mode * 1796 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1797 struct std_timing *t) 1798 { 1799 struct drm_device *dev = connector->dev; 1800 struct drm_display_mode *m, *mode = NULL; 1801 int hsize, vsize; 1802 int vrefresh_rate; 1803 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1804 >> EDID_TIMING_ASPECT_SHIFT; 1805 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1806 >> EDID_TIMING_VFREQ_SHIFT; 1807 int timing_level = standard_timing_level(edid); 1808 1809 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1810 return NULL; 1811 1812 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1813 hsize = t->hsize * 8 + 248; 1814 /* vrefresh_rate = vfreq + 60 */ 1815 vrefresh_rate = vfreq + 60; 1816 /* the vdisplay is calculated based on the aspect ratio */ 1817 if (aspect_ratio == 0) { 1818 if (edid->revision < 3) 1819 vsize = hsize; 1820 else 1821 vsize = (hsize * 10) / 16; 1822 } else if (aspect_ratio == 1) 1823 vsize = (hsize * 3) / 4; 1824 else if (aspect_ratio == 2) 1825 vsize = (hsize * 4) / 5; 1826 else 1827 vsize = (hsize * 9) / 16; 1828 1829 /* HDTV hack, part 1 */ 1830 if (vrefresh_rate == 60 && 1831 ((hsize == 1360 && vsize == 765) || 1832 (hsize == 1368 && vsize == 769))) { 1833 hsize = 1366; 1834 vsize = 768; 1835 } 1836 1837 /* 1838 * If this connector already has a mode for this size and refresh 1839 * rate (because it came from detailed or CVT info), use that 1840 * instead. This way we don't have to guess at interlace or 1841 * reduced blanking. 1842 */ 1843 list_for_each_entry(m, &connector->probed_modes, head) 1844 if (m->hdisplay == hsize && m->vdisplay == vsize && 1845 drm_mode_vrefresh(m) == vrefresh_rate) 1846 return NULL; 1847 1848 /* HDTV hack, part 2 */ 1849 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1850 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1851 false); 1852 mode->hdisplay = 1366; 1853 mode->hsync_start = mode->hsync_start - 1; 1854 mode->hsync_end = mode->hsync_end - 1; 1855 return mode; 1856 } 1857 1858 /* check whether it can be found in default mode table */ 1859 if (drm_monitor_supports_rb(edid)) { 1860 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1861 true); 1862 if (mode) 1863 return mode; 1864 } 1865 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1866 if (mode) 1867 return mode; 1868 1869 /* okay, generate it */ 1870 switch (timing_level) { 1871 case LEVEL_DMT: 1872 break; 1873 case LEVEL_GTF: 1874 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1875 break; 1876 case LEVEL_GTF2: 1877 /* 1878 * This is potentially wrong if there's ever a monitor with 1879 * more than one ranges section, each claiming a different 1880 * secondary GTF curve. Please don't do that. 1881 */ 1882 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1883 if (!mode) 1884 return NULL; 1885 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1886 drm_mode_destroy(dev, mode); 1887 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1888 vrefresh_rate, 0, 0, 1889 drm_gtf2_m(edid), 1890 drm_gtf2_2c(edid), 1891 drm_gtf2_k(edid), 1892 drm_gtf2_2j(edid)); 1893 } 1894 break; 1895 case LEVEL_CVT: 1896 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1897 false); 1898 break; 1899 } 1900 return mode; 1901 } 1902 1903 /* 1904 * EDID is delightfully ambiguous about how interlaced modes are to be 1905 * encoded. Our internal representation is of frame height, but some 1906 * HDTV detailed timings are encoded as field height. 1907 * 1908 * The format list here is from CEA, in frame size. Technically we 1909 * should be checking refresh rate too. Whatever. 1910 */ 1911 static void 1912 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1913 struct detailed_pixel_timing *pt) 1914 { 1915 int i; 1916 static const struct { 1917 int w, h; 1918 } cea_interlaced[] = { 1919 { 1920, 1080 }, 1920 { 720, 480 }, 1921 { 1440, 480 }, 1922 { 2880, 480 }, 1923 { 720, 576 }, 1924 { 1440, 576 }, 1925 { 2880, 576 }, 1926 }; 1927 1928 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1929 return; 1930 1931 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1932 if ((mode->hdisplay == cea_interlaced[i].w) && 1933 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1934 mode->vdisplay *= 2; 1935 mode->vsync_start *= 2; 1936 mode->vsync_end *= 2; 1937 mode->vtotal *= 2; 1938 mode->vtotal |= 1; 1939 } 1940 } 1941 1942 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1943 } 1944 1945 /** 1946 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1947 * @dev: DRM device (needed to create new mode) 1948 * @edid: EDID block 1949 * @timing: EDID detailed timing info 1950 * @quirks: quirks to apply 1951 * 1952 * An EDID detailed timing block contains enough info for us to create and 1953 * return a new struct drm_display_mode. 1954 */ 1955 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1956 struct edid *edid, 1957 struct detailed_timing *timing, 1958 u32 quirks) 1959 { 1960 struct drm_display_mode *mode; 1961 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1962 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1963 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1964 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1965 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1966 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1967 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1968 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1969 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1970 1971 /* ignore tiny modes */ 1972 if (hactive < 64 || vactive < 64) 1973 return NULL; 1974 1975 if (pt->misc & DRM_EDID_PT_STEREO) { 1976 DRM_DEBUG_KMS("stereo mode not supported\n"); 1977 return NULL; 1978 } 1979 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1980 DRM_DEBUG_KMS("composite sync not supported\n"); 1981 } 1982 1983 /* it is incorrect if hsync/vsync width is zero */ 1984 if (!hsync_pulse_width || !vsync_pulse_width) { 1985 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1986 "Wrong Hsync/Vsync pulse width\n"); 1987 return NULL; 1988 } 1989 1990 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1991 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1992 if (!mode) 1993 return NULL; 1994 1995 goto set_size; 1996 } 1997 1998 mode = drm_mode_create(dev); 1999 if (!mode) 2000 return NULL; 2001 2002 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2003 timing->pixel_clock = cpu_to_le16(1088); 2004 2005 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2006 2007 mode->hdisplay = hactive; 2008 mode->hsync_start = mode->hdisplay + hsync_offset; 2009 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2010 mode->htotal = mode->hdisplay + hblank; 2011 2012 mode->vdisplay = vactive; 2013 mode->vsync_start = mode->vdisplay + vsync_offset; 2014 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2015 mode->vtotal = mode->vdisplay + vblank; 2016 2017 /* Some EDIDs have bogus h/vtotal values */ 2018 if (mode->hsync_end > mode->htotal) 2019 mode->htotal = mode->hsync_end + 1; 2020 if (mode->vsync_end > mode->vtotal) 2021 mode->vtotal = mode->vsync_end + 1; 2022 2023 drm_mode_do_interlace_quirk(mode, pt); 2024 2025 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2026 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2027 } 2028 2029 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2030 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2031 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2032 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2033 2034 set_size: 2035 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2036 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2037 2038 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2039 mode->width_mm *= 10; 2040 mode->height_mm *= 10; 2041 } 2042 2043 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2044 mode->width_mm = edid->width_cm * 10; 2045 mode->height_mm = edid->height_cm * 10; 2046 } 2047 2048 mode->type = DRM_MODE_TYPE_DRIVER; 2049 mode->vrefresh = drm_mode_vrefresh(mode); 2050 drm_mode_set_name(mode); 2051 2052 return mode; 2053 } 2054 2055 static bool 2056 mode_in_hsync_range(const struct drm_display_mode *mode, 2057 struct edid *edid, u8 *t) 2058 { 2059 int hsync, hmin, hmax; 2060 2061 hmin = t[7]; 2062 if (edid->revision >= 4) 2063 hmin += ((t[4] & 0x04) ? 255 : 0); 2064 hmax = t[8]; 2065 if (edid->revision >= 4) 2066 hmax += ((t[4] & 0x08) ? 255 : 0); 2067 hsync = drm_mode_hsync(mode); 2068 2069 return (hsync <= hmax && hsync >= hmin); 2070 } 2071 2072 static bool 2073 mode_in_vsync_range(const struct drm_display_mode *mode, 2074 struct edid *edid, u8 *t) 2075 { 2076 int vsync, vmin, vmax; 2077 2078 vmin = t[5]; 2079 if (edid->revision >= 4) 2080 vmin += ((t[4] & 0x01) ? 255 : 0); 2081 vmax = t[6]; 2082 if (edid->revision >= 4) 2083 vmax += ((t[4] & 0x02) ? 255 : 0); 2084 vsync = drm_mode_vrefresh(mode); 2085 2086 return (vsync <= vmax && vsync >= vmin); 2087 } 2088 2089 static u32 2090 range_pixel_clock(struct edid *edid, u8 *t) 2091 { 2092 /* unspecified */ 2093 if (t[9] == 0 || t[9] == 255) 2094 return 0; 2095 2096 /* 1.4 with CVT support gives us real precision, yay */ 2097 if (edid->revision >= 4 && t[10] == 0x04) 2098 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2099 2100 /* 1.3 is pathetic, so fuzz up a bit */ 2101 return t[9] * 10000 + 5001; 2102 } 2103 2104 static bool 2105 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2106 struct detailed_timing *timing) 2107 { 2108 u32 max_clock; 2109 u8 *t = (u8 *)timing; 2110 2111 if (!mode_in_hsync_range(mode, edid, t)) 2112 return false; 2113 2114 if (!mode_in_vsync_range(mode, edid, t)) 2115 return false; 2116 2117 if ((max_clock = range_pixel_clock(edid, t))) 2118 if (mode->clock > max_clock) 2119 return false; 2120 2121 /* 1.4 max horizontal check */ 2122 if (edid->revision >= 4 && t[10] == 0x04) 2123 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2124 return false; 2125 2126 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2127 return false; 2128 2129 return true; 2130 } 2131 2132 static bool valid_inferred_mode(const struct drm_connector *connector, 2133 const struct drm_display_mode *mode) 2134 { 2135 struct drm_display_mode *m; 2136 bool ok = false; 2137 2138 list_for_each_entry(m, &connector->probed_modes, head) { 2139 if (mode->hdisplay == m->hdisplay && 2140 mode->vdisplay == m->vdisplay && 2141 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2142 return false; /* duplicated */ 2143 if (mode->hdisplay <= m->hdisplay && 2144 mode->vdisplay <= m->vdisplay) 2145 ok = true; 2146 } 2147 return ok; 2148 } 2149 2150 static int 2151 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2152 struct detailed_timing *timing) 2153 { 2154 int i, modes = 0; 2155 struct drm_display_mode *newmode; 2156 struct drm_device *dev = connector->dev; 2157 2158 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2159 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2160 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2161 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2162 if (newmode) { 2163 drm_mode_probed_add(connector, newmode); 2164 modes++; 2165 } 2166 } 2167 } 2168 2169 return modes; 2170 } 2171 2172 /* fix up 1366x768 mode from 1368x768; 2173 * GFT/CVT can't express 1366 width which isn't dividable by 8 2174 */ 2175 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2176 { 2177 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2178 mode->hdisplay = 1366; 2179 mode->hsync_start--; 2180 mode->hsync_end--; 2181 drm_mode_set_name(mode); 2182 } 2183 } 2184 2185 static int 2186 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2187 struct detailed_timing *timing) 2188 { 2189 int i, modes = 0; 2190 struct drm_display_mode *newmode; 2191 struct drm_device *dev = connector->dev; 2192 2193 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2194 const struct minimode *m = &extra_modes[i]; 2195 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2196 if (!newmode) 2197 return modes; 2198 2199 fixup_mode_1366x768(newmode); 2200 if (!mode_in_range(newmode, edid, timing) || 2201 !valid_inferred_mode(connector, newmode)) { 2202 drm_mode_destroy(dev, newmode); 2203 continue; 2204 } 2205 2206 drm_mode_probed_add(connector, newmode); 2207 modes++; 2208 } 2209 2210 return modes; 2211 } 2212 2213 static int 2214 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2215 struct detailed_timing *timing) 2216 { 2217 int i, modes = 0; 2218 struct drm_display_mode *newmode; 2219 struct drm_device *dev = connector->dev; 2220 bool rb = drm_monitor_supports_rb(edid); 2221 2222 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2223 const struct minimode *m = &extra_modes[i]; 2224 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2225 if (!newmode) 2226 return modes; 2227 2228 fixup_mode_1366x768(newmode); 2229 if (!mode_in_range(newmode, edid, timing) || 2230 !valid_inferred_mode(connector, newmode)) { 2231 drm_mode_destroy(dev, newmode); 2232 continue; 2233 } 2234 2235 drm_mode_probed_add(connector, newmode); 2236 modes++; 2237 } 2238 2239 return modes; 2240 } 2241 2242 static void 2243 do_inferred_modes(struct detailed_timing *timing, void *c) 2244 { 2245 struct detailed_mode_closure *closure = c; 2246 struct detailed_non_pixel *data = &timing->data.other_data; 2247 struct detailed_data_monitor_range *range = &data->data.range; 2248 2249 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2250 return; 2251 2252 closure->modes += drm_dmt_modes_for_range(closure->connector, 2253 closure->edid, 2254 timing); 2255 2256 if (!version_greater(closure->edid, 1, 1)) 2257 return; /* GTF not defined yet */ 2258 2259 switch (range->flags) { 2260 case 0x02: /* secondary gtf, XXX could do more */ 2261 case 0x00: /* default gtf */ 2262 closure->modes += drm_gtf_modes_for_range(closure->connector, 2263 closure->edid, 2264 timing); 2265 break; 2266 case 0x04: /* cvt, only in 1.4+ */ 2267 if (!version_greater(closure->edid, 1, 3)) 2268 break; 2269 2270 closure->modes += drm_cvt_modes_for_range(closure->connector, 2271 closure->edid, 2272 timing); 2273 break; 2274 case 0x01: /* just the ranges, no formula */ 2275 default: 2276 break; 2277 } 2278 } 2279 2280 static int 2281 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2282 { 2283 struct detailed_mode_closure closure = { 2284 .connector = connector, 2285 .edid = edid, 2286 }; 2287 2288 if (version_greater(edid, 1, 0)) 2289 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2290 &closure); 2291 2292 return closure.modes; 2293 } 2294 2295 static int 2296 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2297 { 2298 int i, j, m, modes = 0; 2299 struct drm_display_mode *mode; 2300 u8 *est = ((u8 *)timing) + 5; 2301 2302 for (i = 0; i < 6; i++) { 2303 for (j = 7; j >= 0; j--) { 2304 m = (i * 8) + (7 - j); 2305 if (m >= ARRAY_SIZE(est3_modes)) 2306 break; 2307 if (est[i] & (1 << j)) { 2308 mode = drm_mode_find_dmt(connector->dev, 2309 est3_modes[m].w, 2310 est3_modes[m].h, 2311 est3_modes[m].r, 2312 est3_modes[m].rb); 2313 if (mode) { 2314 drm_mode_probed_add(connector, mode); 2315 modes++; 2316 } 2317 } 2318 } 2319 } 2320 2321 return modes; 2322 } 2323 2324 static void 2325 do_established_modes(struct detailed_timing *timing, void *c) 2326 { 2327 struct detailed_mode_closure *closure = c; 2328 struct detailed_non_pixel *data = &timing->data.other_data; 2329 2330 if (data->type == EDID_DETAIL_EST_TIMINGS) 2331 closure->modes += drm_est3_modes(closure->connector, timing); 2332 } 2333 2334 /** 2335 * add_established_modes - get est. modes from EDID and add them 2336 * @connector: connector to add mode(s) to 2337 * @edid: EDID block to scan 2338 * 2339 * Each EDID block contains a bitmap of the supported "established modes" list 2340 * (defined above). Tease them out and add them to the global modes list. 2341 */ 2342 static int 2343 add_established_modes(struct drm_connector *connector, struct edid *edid) 2344 { 2345 struct drm_device *dev = connector->dev; 2346 unsigned long est_bits = edid->established_timings.t1 | 2347 (edid->established_timings.t2 << 8) | 2348 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2349 int i, modes = 0; 2350 struct detailed_mode_closure closure = { 2351 .connector = connector, 2352 .edid = edid, 2353 }; 2354 2355 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2356 if (est_bits & (1<<i)) { 2357 struct drm_display_mode *newmode; 2358 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2359 if (newmode) { 2360 drm_mode_probed_add(connector, newmode); 2361 modes++; 2362 } 2363 } 2364 } 2365 2366 if (version_greater(edid, 1, 0)) 2367 drm_for_each_detailed_block((u8 *)edid, 2368 do_established_modes, &closure); 2369 2370 return modes + closure.modes; 2371 } 2372 2373 static void 2374 do_standard_modes(struct detailed_timing *timing, void *c) 2375 { 2376 struct detailed_mode_closure *closure = c; 2377 struct detailed_non_pixel *data = &timing->data.other_data; 2378 struct drm_connector *connector = closure->connector; 2379 struct edid *edid = closure->edid; 2380 2381 if (data->type == EDID_DETAIL_STD_MODES) { 2382 int i; 2383 for (i = 0; i < 6; i++) { 2384 struct std_timing *std; 2385 struct drm_display_mode *newmode; 2386 2387 std = &data->data.timings[i]; 2388 newmode = drm_mode_std(connector, edid, std); 2389 if (newmode) { 2390 drm_mode_probed_add(connector, newmode); 2391 closure->modes++; 2392 } 2393 } 2394 } 2395 } 2396 2397 /** 2398 * add_standard_modes - get std. modes from EDID and add them 2399 * @connector: connector to add mode(s) to 2400 * @edid: EDID block to scan 2401 * 2402 * Standard modes can be calculated using the appropriate standard (DMT, 2403 * GTF or CVT. Grab them from @edid and add them to the list. 2404 */ 2405 static int 2406 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2407 { 2408 int i, modes = 0; 2409 struct detailed_mode_closure closure = { 2410 .connector = connector, 2411 .edid = edid, 2412 }; 2413 2414 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2415 struct drm_display_mode *newmode; 2416 2417 newmode = drm_mode_std(connector, edid, 2418 &edid->standard_timings[i]); 2419 if (newmode) { 2420 drm_mode_probed_add(connector, newmode); 2421 modes++; 2422 } 2423 } 2424 2425 if (version_greater(edid, 1, 0)) 2426 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2427 &closure); 2428 2429 /* XXX should also look for standard codes in VTB blocks */ 2430 2431 return modes + closure.modes; 2432 } 2433 2434 static int drm_cvt_modes(struct drm_connector *connector, 2435 struct detailed_timing *timing) 2436 { 2437 int i, j, modes = 0; 2438 struct drm_display_mode *newmode; 2439 struct drm_device *dev = connector->dev; 2440 struct cvt_timing *cvt; 2441 const int rates[] = { 60, 85, 75, 60, 50 }; 2442 const u8 empty[3] = { 0, 0, 0 }; 2443 2444 for (i = 0; i < 4; i++) { 2445 int width = 0, height; 2446 cvt = &(timing->data.other_data.data.cvt[i]); 2447 2448 if (!memcmp(cvt->code, empty, 3)) 2449 continue; 2450 2451 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2452 switch (cvt->code[1] & 0x0c) { 2453 case 0x00: 2454 width = height * 4 / 3; 2455 break; 2456 case 0x04: 2457 width = height * 16 / 9; 2458 break; 2459 case 0x08: 2460 width = height * 16 / 10; 2461 break; 2462 case 0x0c: 2463 width = height * 15 / 9; 2464 break; 2465 } 2466 2467 for (j = 1; j < 5; j++) { 2468 if (cvt->code[2] & (1 << j)) { 2469 newmode = drm_cvt_mode(dev, width, height, 2470 rates[j], j == 0, 2471 false, false); 2472 if (newmode) { 2473 drm_mode_probed_add(connector, newmode); 2474 modes++; 2475 } 2476 } 2477 } 2478 } 2479 2480 return modes; 2481 } 2482 2483 static void 2484 do_cvt_mode(struct detailed_timing *timing, void *c) 2485 { 2486 struct detailed_mode_closure *closure = c; 2487 struct detailed_non_pixel *data = &timing->data.other_data; 2488 2489 if (data->type == EDID_DETAIL_CVT_3BYTE) 2490 closure->modes += drm_cvt_modes(closure->connector, timing); 2491 } 2492 2493 static int 2494 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2495 { 2496 struct detailed_mode_closure closure = { 2497 .connector = connector, 2498 .edid = edid, 2499 }; 2500 2501 if (version_greater(edid, 1, 2)) 2502 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2503 2504 /* XXX should also look for CVT codes in VTB blocks */ 2505 2506 return closure.modes; 2507 } 2508 2509 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2510 2511 static void 2512 do_detailed_mode(struct detailed_timing *timing, void *c) 2513 { 2514 struct detailed_mode_closure *closure = c; 2515 struct drm_display_mode *newmode; 2516 2517 if (timing->pixel_clock) { 2518 newmode = drm_mode_detailed(closure->connector->dev, 2519 closure->edid, timing, 2520 closure->quirks); 2521 if (!newmode) 2522 return; 2523 2524 if (closure->preferred) 2525 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2526 2527 /* 2528 * Detailed modes are limited to 10kHz pixel clock resolution, 2529 * so fix up anything that looks like CEA/HDMI mode, but the clock 2530 * is just slightly off. 2531 */ 2532 fixup_detailed_cea_mode_clock(newmode); 2533 2534 drm_mode_probed_add(closure->connector, newmode); 2535 closure->modes++; 2536 closure->preferred = 0; 2537 } 2538 } 2539 2540 /* 2541 * add_detailed_modes - Add modes from detailed timings 2542 * @connector: attached connector 2543 * @edid: EDID block to scan 2544 * @quirks: quirks to apply 2545 */ 2546 static int 2547 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2548 u32 quirks) 2549 { 2550 struct detailed_mode_closure closure = { 2551 .connector = connector, 2552 .edid = edid, 2553 .preferred = 1, 2554 .quirks = quirks, 2555 }; 2556 2557 if (closure.preferred && !version_greater(edid, 1, 3)) 2558 closure.preferred = 2559 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2560 2561 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2562 2563 return closure.modes; 2564 } 2565 2566 #define AUDIO_BLOCK 0x01 2567 #define VIDEO_BLOCK 0x02 2568 #define VENDOR_BLOCK 0x03 2569 #define SPEAKER_BLOCK 0x04 2570 #define VIDEO_CAPABILITY_BLOCK 0x07 2571 #define EDID_BASIC_AUDIO (1 << 6) 2572 #define EDID_CEA_YCRCB444 (1 << 5) 2573 #define EDID_CEA_YCRCB422 (1 << 4) 2574 #define EDID_CEA_VCDB_QS (1 << 6) 2575 2576 /* 2577 * Search EDID for CEA extension block. 2578 */ 2579 static u8 *drm_find_cea_extension(struct edid *edid) 2580 { 2581 u8 *edid_ext = NULL; 2582 int i; 2583 2584 /* No EDID or EDID extensions */ 2585 if (edid == NULL || edid->extensions == 0) 2586 return NULL; 2587 2588 /* Find CEA extension */ 2589 for (i = 0; i < edid->extensions; i++) { 2590 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2591 if (edid_ext[0] == CEA_EXT) 2592 break; 2593 } 2594 2595 if (i == edid->extensions) 2596 return NULL; 2597 2598 return edid_ext; 2599 } 2600 2601 /* 2602 * Calculate the alternate clock for the CEA mode 2603 * (60Hz vs. 59.94Hz etc.) 2604 */ 2605 static unsigned int 2606 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2607 { 2608 unsigned int clock = cea_mode->clock; 2609 2610 if (cea_mode->vrefresh % 6 != 0) 2611 return clock; 2612 2613 /* 2614 * edid_cea_modes contains the 59.94Hz 2615 * variant for 240 and 480 line modes, 2616 * and the 60Hz variant otherwise. 2617 */ 2618 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2619 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2620 else 2621 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2622 2623 return clock; 2624 } 2625 2626 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2627 unsigned int clock_tolerance) 2628 { 2629 u8 vic; 2630 2631 if (!to_match->clock) 2632 return 0; 2633 2634 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2635 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2636 unsigned int clock1, clock2; 2637 2638 /* Check both 60Hz and 59.94Hz */ 2639 clock1 = cea_mode->clock; 2640 clock2 = cea_mode_alternate_clock(cea_mode); 2641 2642 if (abs(to_match->clock - clock1) > clock_tolerance && 2643 abs(to_match->clock - clock2) > clock_tolerance) 2644 continue; 2645 2646 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 2647 return vic; 2648 } 2649 2650 return 0; 2651 } 2652 2653 /** 2654 * drm_match_cea_mode - look for a CEA mode matching given mode 2655 * @to_match: display mode 2656 * 2657 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2658 * mode. 2659 */ 2660 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2661 { 2662 u8 vic; 2663 2664 if (!to_match->clock) 2665 return 0; 2666 2667 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2668 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2669 unsigned int clock1, clock2; 2670 2671 /* Check both 60Hz and 59.94Hz */ 2672 clock1 = cea_mode->clock; 2673 clock2 = cea_mode_alternate_clock(cea_mode); 2674 2675 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2676 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2677 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2678 return vic; 2679 } 2680 return 0; 2681 } 2682 EXPORT_SYMBOL(drm_match_cea_mode); 2683 2684 static bool drm_valid_cea_vic(u8 vic) 2685 { 2686 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2687 } 2688 2689 /** 2690 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2691 * the input VIC from the CEA mode list 2692 * @video_code: ID given to each of the CEA modes 2693 * 2694 * Returns picture aspect ratio 2695 */ 2696 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2697 { 2698 return edid_cea_modes[video_code].picture_aspect_ratio; 2699 } 2700 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2701 2702 /* 2703 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2704 * specific block). 2705 * 2706 * It's almost like cea_mode_alternate_clock(), we just need to add an 2707 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2708 * one. 2709 */ 2710 static unsigned int 2711 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2712 { 2713 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2714 return hdmi_mode->clock; 2715 2716 return cea_mode_alternate_clock(hdmi_mode); 2717 } 2718 2719 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 2720 unsigned int clock_tolerance) 2721 { 2722 u8 vic; 2723 2724 if (!to_match->clock) 2725 return 0; 2726 2727 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2728 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2729 unsigned int clock1, clock2; 2730 2731 /* Make sure to also match alternate clocks */ 2732 clock1 = hdmi_mode->clock; 2733 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2734 2735 if (abs(to_match->clock - clock1) > clock_tolerance && 2736 abs(to_match->clock - clock2) > clock_tolerance) 2737 continue; 2738 2739 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 2740 return vic; 2741 } 2742 2743 return 0; 2744 } 2745 2746 /* 2747 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2748 * @to_match: display mode 2749 * 2750 * An HDMI mode is one defined in the HDMI vendor specific block. 2751 * 2752 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2753 */ 2754 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2755 { 2756 u8 vic; 2757 2758 if (!to_match->clock) 2759 return 0; 2760 2761 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2762 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2763 unsigned int clock1, clock2; 2764 2765 /* Make sure to also match alternate clocks */ 2766 clock1 = hdmi_mode->clock; 2767 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2768 2769 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2770 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2771 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2772 return vic; 2773 } 2774 return 0; 2775 } 2776 2777 static bool drm_valid_hdmi_vic(u8 vic) 2778 { 2779 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2780 } 2781 2782 static int 2783 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2784 { 2785 struct drm_device *dev = connector->dev; 2786 struct drm_display_mode *mode, *tmp; 2787 LINUX_LIST_HEAD(list); 2788 int modes = 0; 2789 2790 /* Don't add CEA modes if the CEA extension block is missing */ 2791 if (!drm_find_cea_extension(edid)) 2792 return 0; 2793 2794 /* 2795 * Go through all probed modes and create a new mode 2796 * with the alternate clock for certain CEA modes. 2797 */ 2798 list_for_each_entry(mode, &connector->probed_modes, head) { 2799 const struct drm_display_mode *cea_mode = NULL; 2800 struct drm_display_mode *newmode; 2801 u8 vic = drm_match_cea_mode(mode); 2802 unsigned int clock1, clock2; 2803 2804 if (drm_valid_cea_vic(vic)) { 2805 cea_mode = &edid_cea_modes[vic]; 2806 clock2 = cea_mode_alternate_clock(cea_mode); 2807 } else { 2808 vic = drm_match_hdmi_mode(mode); 2809 if (drm_valid_hdmi_vic(vic)) { 2810 cea_mode = &edid_4k_modes[vic]; 2811 clock2 = hdmi_mode_alternate_clock(cea_mode); 2812 } 2813 } 2814 2815 if (!cea_mode) 2816 continue; 2817 2818 clock1 = cea_mode->clock; 2819 2820 if (clock1 == clock2) 2821 continue; 2822 2823 if (mode->clock != clock1 && mode->clock != clock2) 2824 continue; 2825 2826 newmode = drm_mode_duplicate(dev, cea_mode); 2827 if (!newmode) 2828 continue; 2829 2830 /* Carry over the stereo flags */ 2831 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2832 2833 /* 2834 * The current mode could be either variant. Make 2835 * sure to pick the "other" clock for the new mode. 2836 */ 2837 if (mode->clock != clock1) 2838 newmode->clock = clock1; 2839 else 2840 newmode->clock = clock2; 2841 2842 list_add_tail(&newmode->head, &list); 2843 } 2844 2845 list_for_each_entry_safe(mode, tmp, &list, head) { 2846 list_del(&mode->head); 2847 drm_mode_probed_add(connector, mode); 2848 modes++; 2849 } 2850 2851 return modes; 2852 } 2853 2854 static struct drm_display_mode * 2855 drm_display_mode_from_vic_index(struct drm_connector *connector, 2856 const u8 *video_db, u8 video_len, 2857 u8 video_index) 2858 { 2859 struct drm_device *dev = connector->dev; 2860 struct drm_display_mode *newmode; 2861 u8 vic; 2862 2863 if (video_db == NULL || video_index >= video_len) 2864 return NULL; 2865 2866 /* CEA modes are numbered 1..127 */ 2867 vic = (video_db[video_index] & 127); 2868 if (!drm_valid_cea_vic(vic)) 2869 return NULL; 2870 2871 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 2872 if (!newmode) 2873 return NULL; 2874 2875 newmode->vrefresh = 0; 2876 2877 return newmode; 2878 } 2879 2880 static int 2881 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2882 { 2883 int i, modes = 0; 2884 2885 for (i = 0; i < len; i++) { 2886 struct drm_display_mode *mode; 2887 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2888 if (mode) { 2889 drm_mode_probed_add(connector, mode); 2890 modes++; 2891 } 2892 } 2893 2894 return modes; 2895 } 2896 2897 struct stereo_mandatory_mode { 2898 int width, height, vrefresh; 2899 unsigned int flags; 2900 }; 2901 2902 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2903 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2904 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2905 { 1920, 1080, 50, 2906 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2907 { 1920, 1080, 60, 2908 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2909 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2910 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2911 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2912 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2913 }; 2914 2915 static bool 2916 stereo_match_mandatory(const struct drm_display_mode *mode, 2917 const struct stereo_mandatory_mode *stereo_mode) 2918 { 2919 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2920 2921 return mode->hdisplay == stereo_mode->width && 2922 mode->vdisplay == stereo_mode->height && 2923 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2924 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2925 } 2926 2927 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2928 { 2929 struct drm_device *dev = connector->dev; 2930 struct drm_display_mode *mode; 2931 struct list_head stereo_modes; 2932 int modes = 0, i; 2933 2934 INIT_LIST_HEAD(&stereo_modes); 2935 2936 list_for_each_entry(mode, &connector->probed_modes, head) { 2937 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2938 const struct stereo_mandatory_mode *mandatory; 2939 struct drm_display_mode *new_mode; 2940 2941 if (!stereo_match_mandatory(mode, 2942 &stereo_mandatory_modes[i])) 2943 continue; 2944 2945 mandatory = &stereo_mandatory_modes[i]; 2946 new_mode = drm_mode_duplicate(dev, mode); 2947 if (!new_mode) 2948 continue; 2949 2950 new_mode->flags |= mandatory->flags; 2951 list_add_tail(&new_mode->head, &stereo_modes); 2952 modes++; 2953 } 2954 } 2955 2956 list_splice_tail(&stereo_modes, &connector->probed_modes); 2957 2958 return modes; 2959 } 2960 2961 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2962 { 2963 struct drm_device *dev = connector->dev; 2964 struct drm_display_mode *newmode; 2965 2966 if (!drm_valid_hdmi_vic(vic)) { 2967 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2968 return 0; 2969 } 2970 2971 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2972 if (!newmode) 2973 return 0; 2974 2975 drm_mode_probed_add(connector, newmode); 2976 2977 return 1; 2978 } 2979 2980 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2981 const u8 *video_db, u8 video_len, u8 video_index) 2982 { 2983 struct drm_display_mode *newmode; 2984 int modes = 0; 2985 2986 if (structure & (1 << 0)) { 2987 newmode = drm_display_mode_from_vic_index(connector, video_db, 2988 video_len, 2989 video_index); 2990 if (newmode) { 2991 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2992 drm_mode_probed_add(connector, newmode); 2993 modes++; 2994 } 2995 } 2996 if (structure & (1 << 6)) { 2997 newmode = drm_display_mode_from_vic_index(connector, video_db, 2998 video_len, 2999 video_index); 3000 if (newmode) { 3001 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3002 drm_mode_probed_add(connector, newmode); 3003 modes++; 3004 } 3005 } 3006 if (structure & (1 << 8)) { 3007 newmode = drm_display_mode_from_vic_index(connector, video_db, 3008 video_len, 3009 video_index); 3010 if (newmode) { 3011 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3012 drm_mode_probed_add(connector, newmode); 3013 modes++; 3014 } 3015 } 3016 3017 return modes; 3018 } 3019 3020 /* 3021 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3022 * @connector: connector corresponding to the HDMI sink 3023 * @db: start of the CEA vendor specific block 3024 * @len: length of the CEA block payload, ie. one can access up to db[len] 3025 * 3026 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3027 * also adds the stereo 3d modes when applicable. 3028 */ 3029 static int 3030 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3031 const u8 *video_db, u8 video_len) 3032 { 3033 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3034 u8 vic_len, hdmi_3d_len = 0; 3035 u16 mask; 3036 u16 structure_all; 3037 3038 if (len < 8) 3039 goto out; 3040 3041 /* no HDMI_Video_Present */ 3042 if (!(db[8] & (1 << 5))) 3043 goto out; 3044 3045 /* Latency_Fields_Present */ 3046 if (db[8] & (1 << 7)) 3047 offset += 2; 3048 3049 /* I_Latency_Fields_Present */ 3050 if (db[8] & (1 << 6)) 3051 offset += 2; 3052 3053 /* the declared length is not long enough for the 2 first bytes 3054 * of additional video format capabilities */ 3055 if (len < (8 + offset + 2)) 3056 goto out; 3057 3058 /* 3D_Present */ 3059 offset++; 3060 if (db[8 + offset] & (1 << 7)) { 3061 modes += add_hdmi_mandatory_stereo_modes(connector); 3062 3063 /* 3D_Multi_present */ 3064 multi_present = (db[8 + offset] & 0x60) >> 5; 3065 } 3066 3067 offset++; 3068 vic_len = db[8 + offset] >> 5; 3069 hdmi_3d_len = db[8 + offset] & 0x1f; 3070 3071 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3072 u8 vic; 3073 3074 vic = db[9 + offset + i]; 3075 modes += add_hdmi_mode(connector, vic); 3076 } 3077 offset += 1 + vic_len; 3078 3079 if (multi_present == 1) 3080 multi_len = 2; 3081 else if (multi_present == 2) 3082 multi_len = 4; 3083 else 3084 multi_len = 0; 3085 3086 if (len < (8 + offset + hdmi_3d_len - 1)) 3087 goto out; 3088 3089 if (hdmi_3d_len < multi_len) 3090 goto out; 3091 3092 if (multi_present == 1 || multi_present == 2) { 3093 /* 3D_Structure_ALL */ 3094 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3095 3096 /* check if 3D_MASK is present */ 3097 if (multi_present == 2) 3098 mask = (db[10 + offset] << 8) | db[11 + offset]; 3099 else 3100 mask = 0xffff; 3101 3102 for (i = 0; i < 16; i++) { 3103 if (mask & (1 << i)) 3104 modes += add_3d_struct_modes(connector, 3105 structure_all, 3106 video_db, 3107 video_len, i); 3108 } 3109 } 3110 3111 offset += multi_len; 3112 3113 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3114 int vic_index; 3115 struct drm_display_mode *newmode = NULL; 3116 unsigned int newflag = 0; 3117 bool detail_present; 3118 3119 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3120 3121 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3122 break; 3123 3124 /* 2D_VIC_order_X */ 3125 vic_index = db[8 + offset + i] >> 4; 3126 3127 /* 3D_Structure_X */ 3128 switch (db[8 + offset + i] & 0x0f) { 3129 case 0: 3130 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3131 break; 3132 case 6: 3133 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3134 break; 3135 case 8: 3136 /* 3D_Detail_X */ 3137 if ((db[9 + offset + i] >> 4) == 1) 3138 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3139 break; 3140 } 3141 3142 if (newflag != 0) { 3143 newmode = drm_display_mode_from_vic_index(connector, 3144 video_db, 3145 video_len, 3146 vic_index); 3147 3148 if (newmode) { 3149 newmode->flags |= newflag; 3150 drm_mode_probed_add(connector, newmode); 3151 modes++; 3152 } 3153 } 3154 3155 if (detail_present) 3156 i++; 3157 } 3158 3159 out: 3160 return modes; 3161 } 3162 3163 static int 3164 cea_db_payload_len(const u8 *db) 3165 { 3166 return db[0] & 0x1f; 3167 } 3168 3169 static int 3170 cea_db_tag(const u8 *db) 3171 { 3172 return db[0] >> 5; 3173 } 3174 3175 static int 3176 cea_revision(const u8 *cea) 3177 { 3178 return cea[1]; 3179 } 3180 3181 static int 3182 cea_db_offsets(const u8 *cea, int *start, int *end) 3183 { 3184 /* Data block offset in CEA extension block */ 3185 *start = 4; 3186 *end = cea[2]; 3187 if (*end == 0) 3188 *end = 127; 3189 if (*end < 4 || *end > 127) 3190 return -ERANGE; 3191 return 0; 3192 } 3193 3194 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3195 { 3196 int hdmi_id; 3197 3198 if (cea_db_tag(db) != VENDOR_BLOCK) 3199 return false; 3200 3201 if (cea_db_payload_len(db) < 5) 3202 return false; 3203 3204 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3205 3206 return hdmi_id == HDMI_IEEE_OUI; 3207 } 3208 3209 #define for_each_cea_db(cea, i, start, end) \ 3210 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3211 3212 static int 3213 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3214 { 3215 const u8 *cea = drm_find_cea_extension(edid); 3216 const u8 *db, *hdmi = NULL, *video = NULL; 3217 u8 dbl, hdmi_len, video_len = 0; 3218 int modes = 0; 3219 3220 if (cea && cea_revision(cea) >= 3) { 3221 int i, start, end; 3222 3223 if (cea_db_offsets(cea, &start, &end)) 3224 return 0; 3225 3226 for_each_cea_db(cea, i, start, end) { 3227 db = &cea[i]; 3228 dbl = cea_db_payload_len(db); 3229 3230 if (cea_db_tag(db) == VIDEO_BLOCK) { 3231 video = db + 1; 3232 video_len = dbl; 3233 modes += do_cea_modes(connector, video, dbl); 3234 } 3235 else if (cea_db_is_hdmi_vsdb(db)) { 3236 hdmi = db; 3237 hdmi_len = dbl; 3238 } 3239 } 3240 } 3241 3242 /* 3243 * We parse the HDMI VSDB after having added the cea modes as we will 3244 * be patching their flags when the sink supports stereo 3D. 3245 */ 3246 if (hdmi) 3247 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3248 video_len); 3249 3250 return modes; 3251 } 3252 3253 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3254 { 3255 const struct drm_display_mode *cea_mode; 3256 int clock1, clock2, clock; 3257 u8 vic; 3258 const char *type; 3259 3260 /* 3261 * allow 5kHz clock difference either way to account for 3262 * the 10kHz clock resolution limit of detailed timings. 3263 */ 3264 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3265 if (drm_valid_cea_vic(vic)) { 3266 type = "CEA"; 3267 cea_mode = &edid_cea_modes[vic]; 3268 clock1 = cea_mode->clock; 3269 clock2 = cea_mode_alternate_clock(cea_mode); 3270 } else { 3271 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3272 if (drm_valid_hdmi_vic(vic)) { 3273 type = "HDMI"; 3274 cea_mode = &edid_4k_modes[vic]; 3275 clock1 = cea_mode->clock; 3276 clock2 = hdmi_mode_alternate_clock(cea_mode); 3277 } else { 3278 return; 3279 } 3280 } 3281 3282 /* pick whichever is closest */ 3283 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3284 clock = clock1; 3285 else 3286 clock = clock2; 3287 3288 if (mode->clock == clock) 3289 return; 3290 3291 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3292 type, vic, mode->clock, clock); 3293 mode->clock = clock; 3294 } 3295 3296 static void 3297 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3298 { 3299 u8 len = cea_db_payload_len(db); 3300 3301 if (len >= 6) { 3302 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3303 connector->dvi_dual = db[6] & 1; 3304 } 3305 if (len >= 7) 3306 connector->max_tmds_clock = db[7] * 5; 3307 if (len >= 8) { 3308 connector->latency_present[0] = db[8] >> 7; 3309 connector->latency_present[1] = (db[8] >> 6) & 1; 3310 } 3311 if (len >= 9) 3312 connector->video_latency[0] = db[9]; 3313 if (len >= 10) 3314 connector->audio_latency[0] = db[10]; 3315 if (len >= 11) 3316 connector->video_latency[1] = db[11]; 3317 if (len >= 12) 3318 connector->audio_latency[1] = db[12]; 3319 3320 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3321 "max TMDS clock %d, " 3322 "latency present %d %d, " 3323 "video latency %d %d, " 3324 "audio latency %d %d\n", 3325 connector->dvi_dual, 3326 connector->max_tmds_clock, 3327 (int) connector->latency_present[0], 3328 (int) connector->latency_present[1], 3329 connector->video_latency[0], 3330 connector->video_latency[1], 3331 connector->audio_latency[0], 3332 connector->audio_latency[1]); 3333 } 3334 3335 static void 3336 monitor_name(struct detailed_timing *t, void *data) 3337 { 3338 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3339 *(u8 **)data = t->data.other_data.data.str.str; 3340 } 3341 3342 /** 3343 * drm_edid_to_eld - build ELD from EDID 3344 * @connector: connector corresponding to the HDMI/DP sink 3345 * @edid: EDID to parse 3346 * 3347 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3348 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3349 * fill in. 3350 */ 3351 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3352 { 3353 uint8_t *eld = connector->eld; 3354 u8 *cea; 3355 u8 *name; 3356 u8 *db; 3357 int sad_count = 0; 3358 int mnl; 3359 int dbl; 3360 3361 memset(eld, 0, sizeof(connector->eld)); 3362 3363 cea = drm_find_cea_extension(edid); 3364 if (!cea) { 3365 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3366 return; 3367 } 3368 3369 name = NULL; 3370 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3371 for (mnl = 0; name && mnl < 13; mnl++) { 3372 if (name[mnl] == 0x0a) 3373 break; 3374 eld[20 + mnl] = name[mnl]; 3375 } 3376 eld[4] = (cea[1] << 5) | mnl; 3377 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3378 3379 eld[0] = 2 << 3; /* ELD version: 2 */ 3380 3381 eld[16] = edid->mfg_id[0]; 3382 eld[17] = edid->mfg_id[1]; 3383 eld[18] = edid->prod_code[0]; 3384 eld[19] = edid->prod_code[1]; 3385 3386 if (cea_revision(cea) >= 3) { 3387 int i, start, end; 3388 3389 if (cea_db_offsets(cea, &start, &end)) { 3390 start = 0; 3391 end = 0; 3392 } 3393 3394 for_each_cea_db(cea, i, start, end) { 3395 db = &cea[i]; 3396 dbl = cea_db_payload_len(db); 3397 3398 switch (cea_db_tag(db)) { 3399 case AUDIO_BLOCK: 3400 /* Audio Data Block, contains SADs */ 3401 sad_count = dbl / 3; 3402 if (dbl >= 1) 3403 memcpy(eld + 20 + mnl, &db[1], dbl); 3404 break; 3405 case SPEAKER_BLOCK: 3406 /* Speaker Allocation Data Block */ 3407 if (dbl >= 1) 3408 eld[7] = db[1]; 3409 break; 3410 case VENDOR_BLOCK: 3411 /* HDMI Vendor-Specific Data Block */ 3412 if (cea_db_is_hdmi_vsdb(db)) 3413 parse_hdmi_vsdb(connector, db); 3414 break; 3415 default: 3416 break; 3417 } 3418 } 3419 } 3420 eld[5] |= sad_count << 4; 3421 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; 3422 3423 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); 3424 } 3425 EXPORT_SYMBOL(drm_edid_to_eld); 3426 3427 /** 3428 * drm_edid_to_sad - extracts SADs from EDID 3429 * @edid: EDID to parse 3430 * @sads: pointer that will be set to the extracted SADs 3431 * 3432 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3433 * 3434 * Note: The returned pointer needs to be freed using kfree(). 3435 * 3436 * Return: The number of found SADs or negative number on error. 3437 */ 3438 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3439 { 3440 int count = 0; 3441 int i, start, end, dbl; 3442 u8 *cea; 3443 3444 cea = drm_find_cea_extension(edid); 3445 if (!cea) { 3446 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3447 return -ENOENT; 3448 } 3449 3450 if (cea_revision(cea) < 3) { 3451 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3452 return -EOPNOTSUPP; 3453 } 3454 3455 if (cea_db_offsets(cea, &start, &end)) { 3456 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3457 return -EPROTO; 3458 } 3459 3460 for_each_cea_db(cea, i, start, end) { 3461 u8 *db = &cea[i]; 3462 3463 if (cea_db_tag(db) == AUDIO_BLOCK) { 3464 int j; 3465 dbl = cea_db_payload_len(db); 3466 3467 count = dbl / 3; /* SAD is 3B */ 3468 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3469 if (!*sads) 3470 return -ENOMEM; 3471 for (j = 0; j < count; j++) { 3472 u8 *sad = &db[1 + j * 3]; 3473 3474 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3475 (*sads)[j].channels = sad[0] & 0x7; 3476 (*sads)[j].freq = sad[1] & 0x7F; 3477 (*sads)[j].byte2 = sad[2]; 3478 } 3479 break; 3480 } 3481 } 3482 3483 return count; 3484 } 3485 EXPORT_SYMBOL(drm_edid_to_sad); 3486 3487 /** 3488 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3489 * @edid: EDID to parse 3490 * @sadb: pointer to the speaker block 3491 * 3492 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3493 * 3494 * Note: The returned pointer needs to be freed using kfree(). 3495 * 3496 * Return: The number of found Speaker Allocation Blocks or negative number on 3497 * error. 3498 */ 3499 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3500 { 3501 int count = 0; 3502 int i, start, end, dbl; 3503 const u8 *cea; 3504 3505 cea = drm_find_cea_extension(edid); 3506 if (!cea) { 3507 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3508 return -ENOENT; 3509 } 3510 3511 if (cea_revision(cea) < 3) { 3512 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3513 return -ENOTSUPP; 3514 } 3515 3516 if (cea_db_offsets(cea, &start, &end)) { 3517 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3518 return -EPROTO; 3519 } 3520 3521 for_each_cea_db(cea, i, start, end) { 3522 const u8 *db = &cea[i]; 3523 3524 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3525 dbl = cea_db_payload_len(db); 3526 3527 /* Speaker Allocation Data Block */ 3528 if (dbl == 3) { 3529 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3530 if (!*sadb) 3531 return -ENOMEM; 3532 count = dbl; 3533 break; 3534 } 3535 } 3536 } 3537 3538 return count; 3539 } 3540 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3541 3542 /** 3543 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3544 * @connector: connector associated with the HDMI/DP sink 3545 * @mode: the display mode 3546 * 3547 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3548 * the sink doesn't support audio or video. 3549 */ 3550 int drm_av_sync_delay(struct drm_connector *connector, 3551 const struct drm_display_mode *mode) 3552 { 3553 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3554 int a, v; 3555 3556 if (!connector->latency_present[0]) 3557 return 0; 3558 if (!connector->latency_present[1]) 3559 i = 0; 3560 3561 a = connector->audio_latency[i]; 3562 v = connector->video_latency[i]; 3563 3564 /* 3565 * HDMI/DP sink doesn't support audio or video? 3566 */ 3567 if (a == 255 || v == 255) 3568 return 0; 3569 3570 /* 3571 * Convert raw EDID values to millisecond. 3572 * Treat unknown latency as 0ms. 3573 */ 3574 if (a) 3575 a = min(2 * (a - 1), 500); 3576 if (v) 3577 v = min(2 * (v - 1), 500); 3578 3579 return max(v - a, 0); 3580 } 3581 EXPORT_SYMBOL(drm_av_sync_delay); 3582 3583 /** 3584 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3585 * @encoder: the encoder just changed display mode 3586 * 3587 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3588 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3589 * 3590 * Return: The connector associated with the first HDMI/DP sink that has ELD 3591 * attached to it. 3592 */ 3593 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3594 { 3595 struct drm_connector *connector; 3596 struct drm_device *dev = encoder->dev; 3597 3598 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3599 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3600 3601 drm_for_each_connector(connector, dev) 3602 if (connector->encoder == encoder && connector->eld[0]) 3603 return connector; 3604 3605 return NULL; 3606 } 3607 EXPORT_SYMBOL(drm_select_eld); 3608 3609 /** 3610 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3611 * @edid: monitor EDID information 3612 * 3613 * Parse the CEA extension according to CEA-861-B. 3614 * 3615 * Return: True if the monitor is HDMI, false if not or unknown. 3616 */ 3617 bool drm_detect_hdmi_monitor(struct edid *edid) 3618 { 3619 u8 *edid_ext; 3620 int i; 3621 int start_offset, end_offset; 3622 3623 edid_ext = drm_find_cea_extension(edid); 3624 if (!edid_ext) 3625 return false; 3626 3627 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3628 return false; 3629 3630 /* 3631 * Because HDMI identifier is in Vendor Specific Block, 3632 * search it from all data blocks of CEA extension. 3633 */ 3634 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3635 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3636 return true; 3637 } 3638 3639 return false; 3640 } 3641 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3642 3643 /** 3644 * drm_detect_monitor_audio - check monitor audio capability 3645 * @edid: EDID block to scan 3646 * 3647 * Monitor should have CEA extension block. 3648 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3649 * audio' only. If there is any audio extension block and supported 3650 * audio format, assume at least 'basic audio' support, even if 'basic 3651 * audio' is not defined in EDID. 3652 * 3653 * Return: True if the monitor supports audio, false otherwise. 3654 */ 3655 bool drm_detect_monitor_audio(struct edid *edid) 3656 { 3657 u8 *edid_ext; 3658 int i, j; 3659 bool has_audio = false; 3660 int start_offset, end_offset; 3661 3662 edid_ext = drm_find_cea_extension(edid); 3663 if (!edid_ext) 3664 goto end; 3665 3666 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3667 3668 if (has_audio) { 3669 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3670 goto end; 3671 } 3672 3673 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3674 goto end; 3675 3676 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3677 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3678 has_audio = true; 3679 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3680 DRM_DEBUG_KMS("CEA audio format %d\n", 3681 (edid_ext[i + j] >> 3) & 0xf); 3682 goto end; 3683 } 3684 } 3685 end: 3686 return has_audio; 3687 } 3688 EXPORT_SYMBOL(drm_detect_monitor_audio); 3689 3690 /** 3691 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3692 * @edid: EDID block to scan 3693 * 3694 * Check whether the monitor reports the RGB quantization range selection 3695 * as supported. The AVI infoframe can then be used to inform the monitor 3696 * which quantization range (full or limited) is used. 3697 * 3698 * Return: True if the RGB quantization range is selectable, false otherwise. 3699 */ 3700 bool drm_rgb_quant_range_selectable(struct edid *edid) 3701 { 3702 u8 *edid_ext; 3703 int i, start, end; 3704 3705 edid_ext = drm_find_cea_extension(edid); 3706 if (!edid_ext) 3707 return false; 3708 3709 if (cea_db_offsets(edid_ext, &start, &end)) 3710 return false; 3711 3712 for_each_cea_db(edid_ext, i, start, end) { 3713 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3714 cea_db_payload_len(&edid_ext[i]) == 2) { 3715 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3716 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3717 } 3718 } 3719 3720 return false; 3721 } 3722 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3723 3724 /** 3725 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3726 * hdmi deep color modes and update drm_display_info if so. 3727 * @edid: monitor EDID information 3728 * @info: Updated with maximum supported deep color bpc and color format 3729 * if deep color supported. 3730 * @connector: DRM connector, used only for debug output 3731 * 3732 * Parse the CEA extension according to CEA-861-B. 3733 * Return true if HDMI deep color supported, false if not or unknown. 3734 */ 3735 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3736 struct drm_display_info *info, 3737 struct drm_connector *connector) 3738 { 3739 u8 *edid_ext, *hdmi; 3740 int i; 3741 int start_offset, end_offset; 3742 unsigned int dc_bpc = 0; 3743 3744 edid_ext = drm_find_cea_extension(edid); 3745 if (!edid_ext) 3746 return false; 3747 3748 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3749 return false; 3750 3751 /* 3752 * Because HDMI identifier is in Vendor Specific Block, 3753 * search it from all data blocks of CEA extension. 3754 */ 3755 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3756 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3757 /* HDMI supports at least 8 bpc */ 3758 info->bpc = 8; 3759 3760 hdmi = &edid_ext[i]; 3761 if (cea_db_payload_len(hdmi) < 6) 3762 return false; 3763 3764 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3765 dc_bpc = 10; 3766 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3767 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3768 connector->name); 3769 } 3770 3771 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3772 dc_bpc = 12; 3773 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3774 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3775 connector->name); 3776 } 3777 3778 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3779 dc_bpc = 16; 3780 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3781 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3782 connector->name); 3783 } 3784 3785 if (dc_bpc > 0) { 3786 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3787 connector->name, dc_bpc); 3788 info->bpc = dc_bpc; 3789 3790 /* 3791 * Deep color support mandates RGB444 support for all video 3792 * modes and forbids YCRCB422 support for all video modes per 3793 * HDMI 1.3 spec. 3794 */ 3795 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3796 3797 /* YCRCB444 is optional according to spec. */ 3798 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3799 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3800 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3801 connector->name); 3802 } 3803 3804 /* 3805 * Spec says that if any deep color mode is supported at all, 3806 * then deep color 36 bit must be supported. 3807 */ 3808 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3809 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3810 connector->name); 3811 } 3812 3813 return true; 3814 } 3815 else { 3816 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3817 connector->name); 3818 } 3819 } 3820 } 3821 3822 return false; 3823 } 3824 3825 /** 3826 * drm_add_display_info - pull display info out if present 3827 * @edid: EDID data 3828 * @info: display info (attached to connector) 3829 * @connector: connector whose edid is used to build display info 3830 * 3831 * Grab any available display info and stuff it into the drm_display_info 3832 * structure that's part of the connector. Useful for tracking bpp and 3833 * color spaces. 3834 */ 3835 static void drm_add_display_info(struct edid *edid, 3836 struct drm_display_info *info, 3837 struct drm_connector *connector) 3838 { 3839 u8 *edid_ext; 3840 3841 info->width_mm = edid->width_cm * 10; 3842 info->height_mm = edid->height_cm * 10; 3843 3844 /* driver figures it out in this case */ 3845 info->bpc = 0; 3846 info->color_formats = 0; 3847 3848 if (edid->revision < 3) 3849 return; 3850 3851 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3852 return; 3853 3854 /* Get data from CEA blocks if present */ 3855 edid_ext = drm_find_cea_extension(edid); 3856 if (edid_ext) { 3857 info->cea_rev = edid_ext[1]; 3858 3859 /* The existence of a CEA block should imply RGB support */ 3860 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3861 if (edid_ext[3] & EDID_CEA_YCRCB444) 3862 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3863 if (edid_ext[3] & EDID_CEA_YCRCB422) 3864 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3865 } 3866 3867 /* HDMI deep color modes supported? Assign to info, if so */ 3868 drm_assign_hdmi_deep_color_info(edid, info, connector); 3869 3870 /* Only defined for 1.4 with digital displays */ 3871 if (edid->revision < 4) 3872 return; 3873 3874 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3875 case DRM_EDID_DIGITAL_DEPTH_6: 3876 info->bpc = 6; 3877 break; 3878 case DRM_EDID_DIGITAL_DEPTH_8: 3879 info->bpc = 8; 3880 break; 3881 case DRM_EDID_DIGITAL_DEPTH_10: 3882 info->bpc = 10; 3883 break; 3884 case DRM_EDID_DIGITAL_DEPTH_12: 3885 info->bpc = 12; 3886 break; 3887 case DRM_EDID_DIGITAL_DEPTH_14: 3888 info->bpc = 14; 3889 break; 3890 case DRM_EDID_DIGITAL_DEPTH_16: 3891 info->bpc = 16; 3892 break; 3893 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3894 default: 3895 info->bpc = 0; 3896 break; 3897 } 3898 3899 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3900 connector->name, info->bpc); 3901 3902 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3903 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3904 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3905 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3906 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3907 } 3908 3909 /** 3910 * drm_add_edid_modes - add modes from EDID data, if available 3911 * @connector: connector we're probing 3912 * @edid: EDID data 3913 * 3914 * Add the specified modes to the connector's mode list. 3915 * 3916 * Return: The number of modes added or 0 if we couldn't find any. 3917 */ 3918 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3919 { 3920 int num_modes = 0; 3921 u32 quirks; 3922 3923 if (edid == NULL) { 3924 return 0; 3925 } 3926 if (!drm_edid_is_valid(edid)) { 3927 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3928 connector->name); 3929 return 0; 3930 } 3931 3932 quirks = edid_get_quirks(edid); 3933 3934 /* 3935 * EDID spec says modes should be preferred in this order: 3936 * - preferred detailed mode 3937 * - other detailed modes from base block 3938 * - detailed modes from extension blocks 3939 * - CVT 3-byte code modes 3940 * - standard timing codes 3941 * - established timing codes 3942 * - modes inferred from GTF or CVT range information 3943 * 3944 * We get this pretty much right. 3945 * 3946 * XXX order for additional mode types in extension blocks? 3947 */ 3948 num_modes += add_detailed_modes(connector, edid, quirks); 3949 num_modes += add_cvt_modes(connector, edid); 3950 num_modes += add_standard_modes(connector, edid); 3951 num_modes += add_established_modes(connector, edid); 3952 num_modes += add_cea_modes(connector, edid); 3953 num_modes += add_alternate_cea_modes(connector, edid); 3954 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3955 num_modes += add_inferred_modes(connector, edid); 3956 3957 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3958 edid_fixup_preferred(connector, quirks); 3959 3960 drm_add_display_info(edid, &connector->display_info, connector); 3961 3962 if (quirks & EDID_QUIRK_FORCE_8BPC) 3963 connector->display_info.bpc = 8; 3964 3965 if (quirks & EDID_QUIRK_FORCE_12BPC) 3966 connector->display_info.bpc = 12; 3967 3968 return num_modes; 3969 } 3970 EXPORT_SYMBOL(drm_add_edid_modes); 3971 3972 /** 3973 * drm_add_modes_noedid - add modes for the connectors without EDID 3974 * @connector: connector we're probing 3975 * @hdisplay: the horizontal display limit 3976 * @vdisplay: the vertical display limit 3977 * 3978 * Add the specified modes to the connector's mode list. Only when the 3979 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3980 * 3981 * Return: The number of modes added or 0 if we couldn't find any. 3982 */ 3983 int drm_add_modes_noedid(struct drm_connector *connector, 3984 int hdisplay, int vdisplay) 3985 { 3986 int i, count, num_modes = 0; 3987 struct drm_display_mode *mode; 3988 struct drm_device *dev = connector->dev; 3989 3990 count = ARRAY_SIZE(drm_dmt_modes); 3991 if (hdisplay < 0) 3992 hdisplay = 0; 3993 if (vdisplay < 0) 3994 vdisplay = 0; 3995 3996 for (i = 0; i < count; i++) { 3997 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3998 if (hdisplay && vdisplay) { 3999 /* 4000 * Only when two are valid, they will be used to check 4001 * whether the mode should be added to the mode list of 4002 * the connector. 4003 */ 4004 if (ptr->hdisplay > hdisplay || 4005 ptr->vdisplay > vdisplay) 4006 continue; 4007 } 4008 if (drm_mode_vrefresh(ptr) > 61) 4009 continue; 4010 mode = drm_mode_duplicate(dev, ptr); 4011 if (mode) { 4012 drm_mode_probed_add(connector, mode); 4013 num_modes++; 4014 } 4015 } 4016 return num_modes; 4017 } 4018 EXPORT_SYMBOL(drm_add_modes_noedid); 4019 4020 /** 4021 * drm_set_preferred_mode - Sets the preferred mode of a connector 4022 * @connector: connector whose mode list should be processed 4023 * @hpref: horizontal resolution of preferred mode 4024 * @vpref: vertical resolution of preferred mode 4025 * 4026 * Marks a mode as preferred if it matches the resolution specified by @hpref 4027 * and @vpref. 4028 */ 4029 void drm_set_preferred_mode(struct drm_connector *connector, 4030 int hpref, int vpref) 4031 { 4032 struct drm_display_mode *mode; 4033 4034 list_for_each_entry(mode, &connector->probed_modes, head) { 4035 if (mode->hdisplay == hpref && 4036 mode->vdisplay == vpref) 4037 mode->type |= DRM_MODE_TYPE_PREFERRED; 4038 } 4039 } 4040 EXPORT_SYMBOL(drm_set_preferred_mode); 4041 4042 /** 4043 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4044 * data from a DRM display mode 4045 * @frame: HDMI AVI infoframe 4046 * @mode: DRM display mode 4047 * 4048 * Return: 0 on success or a negative error code on failure. 4049 */ 4050 int 4051 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4052 const struct drm_display_mode *mode) 4053 { 4054 int err; 4055 4056 if (!frame || !mode) 4057 return -EINVAL; 4058 4059 err = hdmi_avi_infoframe_init(frame); 4060 if (err < 0) 4061 return err; 4062 4063 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4064 frame->pixel_repeat = 1; 4065 4066 frame->video_code = drm_match_cea_mode(mode); 4067 4068 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4069 4070 /* 4071 * Populate picture aspect ratio from either 4072 * user input (if specified) or from the CEA mode list. 4073 */ 4074 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4075 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4076 frame->picture_aspect = mode->picture_aspect_ratio; 4077 else if (frame->video_code > 0) 4078 frame->picture_aspect = drm_get_cea_aspect_ratio( 4079 frame->video_code); 4080 4081 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4082 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4083 4084 return 0; 4085 } 4086 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4087 4088 static enum hdmi_3d_structure 4089 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4090 { 4091 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4092 4093 switch (layout) { 4094 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4095 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4096 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4097 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4098 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4099 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4100 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4101 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4102 case DRM_MODE_FLAG_3D_L_DEPTH: 4103 return HDMI_3D_STRUCTURE_L_DEPTH; 4104 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4105 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4106 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4107 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4108 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4109 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4110 default: 4111 return HDMI_3D_STRUCTURE_INVALID; 4112 } 4113 } 4114 4115 /** 4116 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4117 * data from a DRM display mode 4118 * @frame: HDMI vendor infoframe 4119 * @mode: DRM display mode 4120 * 4121 * Note that there's is a need to send HDMI vendor infoframes only when using a 4122 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4123 * function will return -EINVAL, error that can be safely ignored. 4124 * 4125 * Return: 0 on success or a negative error code on failure. 4126 */ 4127 int 4128 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4129 const struct drm_display_mode *mode) 4130 { 4131 int err; 4132 u32 s3d_flags; 4133 u8 vic; 4134 4135 if (!frame || !mode) 4136 return -EINVAL; 4137 4138 vic = drm_match_hdmi_mode(mode); 4139 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4140 4141 if (!vic && !s3d_flags) 4142 return -EINVAL; 4143 4144 if (vic && s3d_flags) 4145 return -EINVAL; 4146 4147 err = hdmi_vendor_infoframe_init(frame); 4148 if (err < 0) 4149 return err; 4150 4151 if (vic) 4152 frame->vic = vic; 4153 else 4154 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4155 4156 return 0; 4157 } 4158 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4159