1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #ifdef __DragonFly__ 32 #include "opt_drm.h" 33 #endif 34 35 #include <linux/kernel.h> 36 #include <linux/slab.h> 37 #include <linux/hdmi.h> 38 #include <linux/i2c.h> 39 #include <linux/module.h> 40 #include <linux/vga_switcheroo.h> 41 #include <drm/drmP.h> 42 #include <drm/drm_edid.h> 43 #include <drm/drm_encoder.h> 44 #include <drm/drm_displayid.h> 45 #include <drm/drm_scdc_helper.h> 46 47 #include "drm_crtc_internal.h" 48 49 #define version_greater(edid, maj, min) \ 50 (((edid)->version > (maj)) || \ 51 ((edid)->version == (maj) && (edid)->revision > (min))) 52 53 #define EDID_EST_TIMINGS 16 54 #define EDID_STD_TIMINGS 8 55 #define EDID_DETAILED_TIMINGS 4 56 57 /* 58 * EDID blocks out in the wild have a variety of bugs, try to collect 59 * them here (note that userspace may work around broken monitors first, 60 * but fixes should make their way here so that the kernel "just works" 61 * on as many displays as possible). 62 */ 63 64 /* First detailed mode wrong, use largest 60Hz mode */ 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 66 /* Reported 135MHz pixel clock is too high, needs adjustment */ 67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 68 /* Prefer the largest mode at 75 Hz */ 69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 70 /* Detail timing is in cm not mm */ 71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 72 /* Detailed timing descriptors have bogus size values, so just take the 73 * maximum size and use that. 74 */ 75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 76 /* Monitor forgot to set the first detailed is preferred bit. */ 77 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 78 /* use +hsync +vsync for detailed mode */ 79 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 80 /* Force reduced-blanking timings for detailed modes */ 81 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 82 /* Force 8bpc */ 83 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 84 /* Force 12bpc */ 85 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 86 /* Force 6bpc */ 87 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 88 /* Force 10bpc */ 89 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 90 91 struct detailed_mode_closure { 92 struct drm_connector *connector; 93 struct edid *edid; 94 bool preferred; 95 u32 quirks; 96 int modes; 97 }; 98 99 #define LEVEL_DMT 0 100 #define LEVEL_GTF 1 101 #define LEVEL_GTF2 2 102 #define LEVEL_CVT 3 103 104 static const struct edid_quirk { 105 char vendor[4]; 106 int product_id; 107 u32 quirks; 108 } edid_quirk_list[] = { 109 /* Acer AL1706 */ 110 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 111 /* Acer F51 */ 112 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 113 /* Unknown Acer */ 114 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 115 116 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 117 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 118 119 /* Belinea 10 15 55 */ 120 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 121 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 122 123 /* Envision Peripherals, Inc. EN-7100e */ 124 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 125 /* Envision EN2028 */ 126 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 127 128 /* Funai Electronics PM36B */ 129 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 130 EDID_QUIRK_DETAILED_IN_CM }, 131 132 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 133 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 134 135 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 136 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 137 138 /* LG Philips LCD LP154W01-A5 */ 139 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 140 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 141 142 /* Philips 107p5 CRT */ 143 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 144 145 /* Proview AY765C */ 146 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 147 148 /* Samsung SyncMaster 205BW. Note: irony */ 149 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 150 /* Samsung SyncMaster 22[5-6]BW */ 151 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 152 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 153 154 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 155 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 156 157 /* ViewSonic VA2026w */ 158 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 159 160 /* Medion MD 30217 PG */ 161 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 162 163 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 164 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 165 166 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 167 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 168 }; 169 170 /* 171 * Autogenerated from the DMT spec. 172 * This table is copied from xfree86/modes/xf86EdidModes.c. 173 */ 174 static const struct drm_display_mode drm_dmt_modes[] = { 175 /* 0x01 - 640x350@85Hz */ 176 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 177 736, 832, 0, 350, 382, 385, 445, 0, 178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 179 /* 0x02 - 640x400@85Hz */ 180 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 181 736, 832, 0, 400, 401, 404, 445, 0, 182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 183 /* 0x03 - 720x400@85Hz */ 184 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 185 828, 936, 0, 400, 401, 404, 446, 0, 186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 187 /* 0x04 - 640x480@60Hz */ 188 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 189 752, 800, 0, 480, 490, 492, 525, 0, 190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 191 /* 0x05 - 640x480@72Hz */ 192 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 193 704, 832, 0, 480, 489, 492, 520, 0, 194 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 195 /* 0x06 - 640x480@75Hz */ 196 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 197 720, 840, 0, 480, 481, 484, 500, 0, 198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 199 /* 0x07 - 640x480@85Hz */ 200 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 201 752, 832, 0, 480, 481, 484, 509, 0, 202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 203 /* 0x08 - 800x600@56Hz */ 204 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 205 896, 1024, 0, 600, 601, 603, 625, 0, 206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 207 /* 0x09 - 800x600@60Hz */ 208 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 209 968, 1056, 0, 600, 601, 605, 628, 0, 210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 211 /* 0x0a - 800x600@72Hz */ 212 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 213 976, 1040, 0, 600, 637, 643, 666, 0, 214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 215 /* 0x0b - 800x600@75Hz */ 216 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 217 896, 1056, 0, 600, 601, 604, 625, 0, 218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 219 /* 0x0c - 800x600@85Hz */ 220 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 221 896, 1048, 0, 600, 601, 604, 631, 0, 222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 223 /* 0x0d - 800x600@120Hz RB */ 224 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 225 880, 960, 0, 600, 603, 607, 636, 0, 226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 227 /* 0x0e - 848x480@60Hz */ 228 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 229 976, 1088, 0, 480, 486, 494, 517, 0, 230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 231 /* 0x0f - 1024x768@43Hz, interlace */ 232 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 233 1208, 1264, 0, 768, 768, 776, 817, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 235 DRM_MODE_FLAG_INTERLACE) }, 236 /* 0x10 - 1024x768@60Hz */ 237 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 238 1184, 1344, 0, 768, 771, 777, 806, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 240 /* 0x11 - 1024x768@70Hz */ 241 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 242 1184, 1328, 0, 768, 771, 777, 806, 0, 243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 244 /* 0x12 - 1024x768@75Hz */ 245 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 246 1136, 1312, 0, 768, 769, 772, 800, 0, 247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 248 /* 0x13 - 1024x768@85Hz */ 249 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 250 1168, 1376, 0, 768, 769, 772, 808, 0, 251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 252 /* 0x14 - 1024x768@120Hz RB */ 253 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 254 1104, 1184, 0, 768, 771, 775, 813, 0, 255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 256 /* 0x15 - 1152x864@75Hz */ 257 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 258 1344, 1600, 0, 864, 865, 868, 900, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 260 /* 0x55 - 1280x720@60Hz */ 261 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 262 1430, 1650, 0, 720, 725, 730, 750, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x16 - 1280x768@60Hz RB */ 265 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 266 1360, 1440, 0, 768, 771, 778, 790, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 268 /* 0x17 - 1280x768@60Hz */ 269 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 270 1472, 1664, 0, 768, 771, 778, 798, 0, 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x18 - 1280x768@75Hz */ 273 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 274 1488, 1696, 0, 768, 771, 778, 805, 0, 275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x19 - 1280x768@85Hz */ 277 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 278 1496, 1712, 0, 768, 771, 778, 809, 0, 279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x1a - 1280x768@120Hz RB */ 281 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 282 1360, 1440, 0, 768, 771, 778, 813, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 284 /* 0x1b - 1280x800@60Hz RB */ 285 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 286 1360, 1440, 0, 800, 803, 809, 823, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 288 /* 0x1c - 1280x800@60Hz */ 289 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 290 1480, 1680, 0, 800, 803, 809, 831, 0, 291 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 0x1d - 1280x800@75Hz */ 293 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 294 1488, 1696, 0, 800, 803, 809, 838, 0, 295 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 296 /* 0x1e - 1280x800@85Hz */ 297 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 298 1496, 1712, 0, 800, 803, 809, 843, 0, 299 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x1f - 1280x800@120Hz RB */ 301 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 302 1360, 1440, 0, 800, 803, 809, 847, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 304 /* 0x20 - 1280x960@60Hz */ 305 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 306 1488, 1800, 0, 960, 961, 964, 1000, 0, 307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 308 /* 0x21 - 1280x960@85Hz */ 309 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 310 1504, 1728, 0, 960, 961, 964, 1011, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 312 /* 0x22 - 1280x960@120Hz RB */ 313 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 314 1360, 1440, 0, 960, 963, 967, 1017, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 316 /* 0x23 - 1280x1024@60Hz */ 317 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 318 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 320 /* 0x24 - 1280x1024@75Hz */ 321 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 322 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 324 /* 0x25 - 1280x1024@85Hz */ 325 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 326 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 328 /* 0x26 - 1280x1024@120Hz RB */ 329 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 330 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 332 /* 0x27 - 1360x768@60Hz */ 333 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 334 1536, 1792, 0, 768, 771, 777, 795, 0, 335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 336 /* 0x28 - 1360x768@120Hz RB */ 337 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 338 1440, 1520, 0, 768, 771, 776, 813, 0, 339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 340 /* 0x51 - 1366x768@60Hz */ 341 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 342 1579, 1792, 0, 768, 771, 774, 798, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 344 /* 0x56 - 1366x768@60Hz */ 345 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 346 1436, 1500, 0, 768, 769, 772, 800, 0, 347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 348 /* 0x29 - 1400x1050@60Hz RB */ 349 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 350 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 351 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 352 /* 0x2a - 1400x1050@60Hz */ 353 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 354 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 355 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 356 /* 0x2b - 1400x1050@75Hz */ 357 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 358 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 359 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 360 /* 0x2c - 1400x1050@85Hz */ 361 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 362 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 364 /* 0x2d - 1400x1050@120Hz RB */ 365 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 366 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 368 /* 0x2e - 1440x900@60Hz RB */ 369 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 370 1520, 1600, 0, 900, 903, 909, 926, 0, 371 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 372 /* 0x2f - 1440x900@60Hz */ 373 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 374 1672, 1904, 0, 900, 903, 909, 934, 0, 375 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 376 /* 0x30 - 1440x900@75Hz */ 377 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 378 1688, 1936, 0, 900, 903, 909, 942, 0, 379 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 380 /* 0x31 - 1440x900@85Hz */ 381 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 382 1696, 1952, 0, 900, 903, 909, 948, 0, 383 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 384 /* 0x32 - 1440x900@120Hz RB */ 385 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 386 1520, 1600, 0, 900, 903, 909, 953, 0, 387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 388 /* 0x53 - 1600x900@60Hz */ 389 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 390 1704, 1800, 0, 900, 901, 904, 1000, 0, 391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 392 /* 0x33 - 1600x1200@60Hz */ 393 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 394 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 396 /* 0x34 - 1600x1200@65Hz */ 397 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 398 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 400 /* 0x35 - 1600x1200@70Hz */ 401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 402 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 404 /* 0x36 - 1600x1200@75Hz */ 405 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 406 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 408 /* 0x37 - 1600x1200@85Hz */ 409 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 410 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 412 /* 0x38 - 1600x1200@120Hz RB */ 413 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 414 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 416 /* 0x39 - 1680x1050@60Hz RB */ 417 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 418 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 420 /* 0x3a - 1680x1050@60Hz */ 421 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 422 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 424 /* 0x3b - 1680x1050@75Hz */ 425 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 426 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 428 /* 0x3c - 1680x1050@85Hz */ 429 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 430 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 432 /* 0x3d - 1680x1050@120Hz RB */ 433 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 434 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 436 /* 0x3e - 1792x1344@60Hz */ 437 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 438 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 440 /* 0x3f - 1792x1344@75Hz */ 441 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 442 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 444 /* 0x40 - 1792x1344@120Hz RB */ 445 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 446 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 448 /* 0x41 - 1856x1392@60Hz */ 449 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 450 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 452 /* 0x42 - 1856x1392@75Hz */ 453 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 454 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 456 /* 0x43 - 1856x1392@120Hz RB */ 457 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 458 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 460 /* 0x52 - 1920x1080@60Hz */ 461 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 462 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 464 /* 0x44 - 1920x1200@60Hz RB */ 465 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 466 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 468 /* 0x45 - 1920x1200@60Hz */ 469 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 470 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 471 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 472 /* 0x46 - 1920x1200@75Hz */ 473 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 474 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 475 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 476 /* 0x47 - 1920x1200@85Hz */ 477 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 478 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 480 /* 0x48 - 1920x1200@120Hz RB */ 481 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 482 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 484 /* 0x49 - 1920x1440@60Hz */ 485 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 486 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 487 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 488 /* 0x4a - 1920x1440@75Hz */ 489 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 490 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 492 /* 0x4b - 1920x1440@120Hz RB */ 493 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 494 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 496 /* 0x54 - 2048x1152@60Hz */ 497 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 498 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 500 /* 0x4c - 2560x1600@60Hz RB */ 501 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 502 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 503 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 504 /* 0x4d - 2560x1600@60Hz */ 505 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 506 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 507 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 508 /* 0x4e - 2560x1600@75Hz */ 509 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 510 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 512 /* 0x4f - 2560x1600@85Hz */ 513 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 514 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 516 /* 0x50 - 2560x1600@120Hz RB */ 517 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 518 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 520 /* 0x57 - 4096x2160@60Hz RB */ 521 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 522 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 523 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 524 /* 0x58 - 4096x2160@59.94Hz RB */ 525 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 526 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 528 }; 529 530 /* 531 * These more or less come from the DMT spec. The 720x400 modes are 532 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 533 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 534 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 535 * mode. 536 * 537 * The DMT modes have been fact-checked; the rest are mild guesses. 538 */ 539 static const struct drm_display_mode edid_est_modes[] = { 540 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 541 968, 1056, 0, 600, 601, 605, 628, 0, 542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 543 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 544 896, 1024, 0, 600, 601, 603, 625, 0, 545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 546 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 547 720, 840, 0, 480, 481, 484, 500, 0, 548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 549 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 550 704, 832, 0, 480, 489, 492, 520, 0, 551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 552 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 553 768, 864, 0, 480, 483, 486, 525, 0, 554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 555 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 556 752, 800, 0, 480, 490, 492, 525, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 558 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 559 846, 900, 0, 400, 421, 423, 449, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 561 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 562 846, 900, 0, 400, 412, 414, 449, 0, 563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 564 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 565 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 567 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 568 1136, 1312, 0, 768, 769, 772, 800, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 570 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 571 1184, 1328, 0, 768, 771, 777, 806, 0, 572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 573 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 574 1184, 1344, 0, 768, 771, 777, 806, 0, 575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 576 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 577 1208, 1264, 0, 768, 768, 776, 817, 0, 578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 579 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 580 928, 1152, 0, 624, 625, 628, 667, 0, 581 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 582 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 583 896, 1056, 0, 600, 601, 604, 625, 0, 584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 585 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 586 976, 1040, 0, 600, 637, 643, 666, 0, 587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 588 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 589 1344, 1600, 0, 864, 865, 868, 900, 0, 590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 591 }; 592 593 struct minimode { 594 short w; 595 short h; 596 short r; 597 short rb; 598 }; 599 600 static const struct minimode est3_modes[] = { 601 /* byte 6 */ 602 { 640, 350, 85, 0 }, 603 { 640, 400, 85, 0 }, 604 { 720, 400, 85, 0 }, 605 { 640, 480, 85, 0 }, 606 { 848, 480, 60, 0 }, 607 { 800, 600, 85, 0 }, 608 { 1024, 768, 85, 0 }, 609 { 1152, 864, 75, 0 }, 610 /* byte 7 */ 611 { 1280, 768, 60, 1 }, 612 { 1280, 768, 60, 0 }, 613 { 1280, 768, 75, 0 }, 614 { 1280, 768, 85, 0 }, 615 { 1280, 960, 60, 0 }, 616 { 1280, 960, 85, 0 }, 617 { 1280, 1024, 60, 0 }, 618 { 1280, 1024, 85, 0 }, 619 /* byte 8 */ 620 { 1360, 768, 60, 0 }, 621 { 1440, 900, 60, 1 }, 622 { 1440, 900, 60, 0 }, 623 { 1440, 900, 75, 0 }, 624 { 1440, 900, 85, 0 }, 625 { 1400, 1050, 60, 1 }, 626 { 1400, 1050, 60, 0 }, 627 { 1400, 1050, 75, 0 }, 628 /* byte 9 */ 629 { 1400, 1050, 85, 0 }, 630 { 1680, 1050, 60, 1 }, 631 { 1680, 1050, 60, 0 }, 632 { 1680, 1050, 75, 0 }, 633 { 1680, 1050, 85, 0 }, 634 { 1600, 1200, 60, 0 }, 635 { 1600, 1200, 65, 0 }, 636 { 1600, 1200, 70, 0 }, 637 /* byte 10 */ 638 { 1600, 1200, 75, 0 }, 639 { 1600, 1200, 85, 0 }, 640 { 1792, 1344, 60, 0 }, 641 { 1792, 1344, 75, 0 }, 642 { 1856, 1392, 60, 0 }, 643 { 1856, 1392, 75, 0 }, 644 { 1920, 1200, 60, 1 }, 645 { 1920, 1200, 60, 0 }, 646 /* byte 11 */ 647 { 1920, 1200, 75, 0 }, 648 { 1920, 1200, 85, 0 }, 649 { 1920, 1440, 60, 0 }, 650 { 1920, 1440, 75, 0 }, 651 }; 652 653 static const struct minimode extra_modes[] = { 654 { 1024, 576, 60, 0 }, 655 { 1366, 768, 60, 0 }, 656 { 1600, 900, 60, 0 }, 657 { 1680, 945, 60, 0 }, 658 { 1920, 1080, 60, 0 }, 659 { 2048, 1152, 60, 0 }, 660 { 2048, 1536, 60, 0 }, 661 }; 662 663 /* 664 * Probably taken from CEA-861 spec. 665 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 666 * 667 * Index using the VIC. 668 */ 669 static const struct drm_display_mode edid_cea_modes[] = { 670 /* 0 - dummy, VICs start at 1 */ 671 { }, 672 /* 1 - 640x480@60Hz */ 673 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 674 752, 800, 0, 480, 490, 492, 525, 0, 675 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 676 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 677 /* 2 - 720x480@60Hz */ 678 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 679 798, 858, 0, 480, 489, 495, 525, 0, 680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 681 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 682 /* 3 - 720x480@60Hz */ 683 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 684 798, 858, 0, 480, 489, 495, 525, 0, 685 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 687 /* 4 - 1280x720@60Hz */ 688 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 689 1430, 1650, 0, 720, 725, 730, 750, 0, 690 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 692 /* 5 - 1920x1080i@60Hz */ 693 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 694 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 696 DRM_MODE_FLAG_INTERLACE), 697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 698 /* 6 - 720(1440)x480i@60Hz */ 699 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 700 801, 858, 0, 480, 488, 494, 525, 0, 701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 702 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 704 /* 7 - 720(1440)x480i@60Hz */ 705 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 706 801, 858, 0, 480, 488, 494, 525, 0, 707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 708 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 710 /* 8 - 720(1440)x240@60Hz */ 711 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 712 801, 858, 0, 240, 244, 247, 262, 0, 713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 714 DRM_MODE_FLAG_DBLCLK), 715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 716 /* 9 - 720(1440)x240@60Hz */ 717 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 718 801, 858, 0, 240, 244, 247, 262, 0, 719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 720 DRM_MODE_FLAG_DBLCLK), 721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 722 /* 10 - 2880x480i@60Hz */ 723 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 724 3204, 3432, 0, 480, 488, 494, 525, 0, 725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 726 DRM_MODE_FLAG_INTERLACE), 727 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 728 /* 11 - 2880x480i@60Hz */ 729 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 730 3204, 3432, 0, 480, 488, 494, 525, 0, 731 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 732 DRM_MODE_FLAG_INTERLACE), 733 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 734 /* 12 - 2880x240@60Hz */ 735 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 736 3204, 3432, 0, 240, 244, 247, 262, 0, 737 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 739 /* 13 - 2880x240@60Hz */ 740 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 741 3204, 3432, 0, 240, 244, 247, 262, 0, 742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 744 /* 14 - 1440x480@60Hz */ 745 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 746 1596, 1716, 0, 480, 489, 495, 525, 0, 747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 748 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 749 /* 15 - 1440x480@60Hz */ 750 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 751 1596, 1716, 0, 480, 489, 495, 525, 0, 752 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 753 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 754 /* 16 - 1920x1080@60Hz */ 755 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 756 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 759 /* 17 - 720x576@50Hz */ 760 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 761 796, 864, 0, 576, 581, 586, 625, 0, 762 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 763 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 764 /* 18 - 720x576@50Hz */ 765 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 766 796, 864, 0, 576, 581, 586, 625, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 769 /* 19 - 1280x720@50Hz */ 770 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 771 1760, 1980, 0, 720, 725, 730, 750, 0, 772 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 774 /* 20 - 1920x1080i@50Hz */ 775 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 776 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 777 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 778 DRM_MODE_FLAG_INTERLACE), 779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 780 /* 21 - 720(1440)x576i@50Hz */ 781 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 782 795, 864, 0, 576, 580, 586, 625, 0, 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 784 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 786 /* 22 - 720(1440)x576i@50Hz */ 787 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 788 795, 864, 0, 576, 580, 586, 625, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 790 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 792 /* 23 - 720(1440)x288@50Hz */ 793 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 794 795, 864, 0, 288, 290, 293, 312, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 796 DRM_MODE_FLAG_DBLCLK), 797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 798 /* 24 - 720(1440)x288@50Hz */ 799 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 800 795, 864, 0, 288, 290, 293, 312, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 802 DRM_MODE_FLAG_DBLCLK), 803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 804 /* 25 - 2880x576i@50Hz */ 805 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 806 3180, 3456, 0, 576, 580, 586, 625, 0, 807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 808 DRM_MODE_FLAG_INTERLACE), 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 810 /* 26 - 2880x576i@50Hz */ 811 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 812 3180, 3456, 0, 576, 580, 586, 625, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 814 DRM_MODE_FLAG_INTERLACE), 815 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 816 /* 27 - 2880x288@50Hz */ 817 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 818 3180, 3456, 0, 288, 290, 293, 312, 0, 819 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 821 /* 28 - 2880x288@50Hz */ 822 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 823 3180, 3456, 0, 288, 290, 293, 312, 0, 824 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 826 /* 29 - 1440x576@50Hz */ 827 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 828 1592, 1728, 0, 576, 581, 586, 625, 0, 829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 830 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 831 /* 30 - 1440x576@50Hz */ 832 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 833 1592, 1728, 0, 576, 581, 586, 625, 0, 834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 835 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 836 /* 31 - 1920x1080@50Hz */ 837 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 838 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 841 /* 32 - 1920x1080@24Hz */ 842 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 843 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 845 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 846 /* 33 - 1920x1080@25Hz */ 847 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 848 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 850 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 851 /* 34 - 1920x1080@30Hz */ 852 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 853 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 855 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 856 /* 35 - 2880x480@60Hz */ 857 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 858 3192, 3432, 0, 480, 489, 495, 525, 0, 859 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 860 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 861 /* 36 - 2880x480@60Hz */ 862 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 863 3192, 3432, 0, 480, 489, 495, 525, 0, 864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 865 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 866 /* 37 - 2880x576@50Hz */ 867 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 868 3184, 3456, 0, 576, 581, 586, 625, 0, 869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 870 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 871 /* 38 - 2880x576@50Hz */ 872 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 873 3184, 3456, 0, 576, 581, 586, 625, 0, 874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 875 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 876 /* 39 - 1920x1080i@50Hz */ 877 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 878 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 880 DRM_MODE_FLAG_INTERLACE), 881 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 40 - 1920x1080i@100Hz */ 883 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 884 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 885 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 886 DRM_MODE_FLAG_INTERLACE), 887 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 888 /* 41 - 1280x720@100Hz */ 889 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 890 1760, 1980, 0, 720, 725, 730, 750, 0, 891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 892 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 893 /* 42 - 720x576@100Hz */ 894 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 895 796, 864, 0, 576, 581, 586, 625, 0, 896 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 897 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 898 /* 43 - 720x576@100Hz */ 899 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 900 796, 864, 0, 576, 581, 586, 625, 0, 901 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 902 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 44 - 720(1440)x576i@100Hz */ 904 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 905 795, 864, 0, 576, 580, 586, 625, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 907 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 908 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 909 /* 45 - 720(1440)x576i@100Hz */ 910 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 911 795, 864, 0, 576, 580, 586, 625, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 913 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 914 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 915 /* 46 - 1920x1080i@120Hz */ 916 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 917 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 919 DRM_MODE_FLAG_INTERLACE), 920 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 921 /* 47 - 1280x720@120Hz */ 922 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 923 1430, 1650, 0, 720, 725, 730, 750, 0, 924 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 925 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 926 /* 48 - 720x480@120Hz */ 927 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 928 798, 858, 0, 480, 489, 495, 525, 0, 929 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 930 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 931 /* 49 - 720x480@120Hz */ 932 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 933 798, 858, 0, 480, 489, 495, 525, 0, 934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 935 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 936 /* 50 - 720(1440)x480i@120Hz */ 937 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 938 801, 858, 0, 480, 488, 494, 525, 0, 939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 940 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 941 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 942 /* 51 - 720(1440)x480i@120Hz */ 943 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 944 801, 858, 0, 480, 488, 494, 525, 0, 945 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 946 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 947 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 948 /* 52 - 720x576@200Hz */ 949 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 950 796, 864, 0, 576, 581, 586, 625, 0, 951 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 952 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 953 /* 53 - 720x576@200Hz */ 954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 955 796, 864, 0, 576, 581, 586, 625, 0, 956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 957 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 958 /* 54 - 720(1440)x576i@200Hz */ 959 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 960 795, 864, 0, 576, 580, 586, 625, 0, 961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 962 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 963 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 964 /* 55 - 720(1440)x576i@200Hz */ 965 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 966 795, 864, 0, 576, 580, 586, 625, 0, 967 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 969 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 970 /* 56 - 720x480@240Hz */ 971 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 972 798, 858, 0, 480, 489, 495, 525, 0, 973 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 974 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 975 /* 57 - 720x480@240Hz */ 976 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 977 798, 858, 0, 480, 489, 495, 525, 0, 978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 979 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 980 /* 58 - 720(1440)x480i@240Hz */ 981 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 982 801, 858, 0, 480, 488, 494, 525, 0, 983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 984 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 985 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 986 /* 59 - 720(1440)x480i@240Hz */ 987 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 988 801, 858, 0, 480, 488, 494, 525, 0, 989 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 990 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 991 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 992 /* 60 - 1280x720@24Hz */ 993 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 994 3080, 3300, 0, 720, 725, 730, 750, 0, 995 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 996 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 997 /* 61 - 1280x720@25Hz */ 998 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 999 3740, 3960, 0, 720, 725, 730, 750, 0, 1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1001 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1002 /* 62 - 1280x720@30Hz */ 1003 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1004 3080, 3300, 0, 720, 725, 730, 750, 0, 1005 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1006 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1007 /* 63 - 1920x1080@120Hz */ 1008 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1009 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1010 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1011 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1012 /* 64 - 1920x1080@100Hz */ 1013 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1014 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1016 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1017 }; 1018 1019 /* 1020 * HDMI 1.4 4k modes. Index using the VIC. 1021 */ 1022 static const struct drm_display_mode edid_4k_modes[] = { 1023 /* 0 - dummy, VICs start at 1 */ 1024 { }, 1025 /* 1 - 3840x2160@30Hz */ 1026 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1027 3840, 4016, 4104, 4400, 0, 1028 2160, 2168, 2178, 2250, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1030 .vrefresh = 30, }, 1031 /* 2 - 3840x2160@25Hz */ 1032 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1033 3840, 4896, 4984, 5280, 0, 1034 2160, 2168, 2178, 2250, 0, 1035 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1036 .vrefresh = 25, }, 1037 /* 3 - 3840x2160@24Hz */ 1038 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1039 3840, 5116, 5204, 5500, 0, 1040 2160, 2168, 2178, 2250, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1042 .vrefresh = 24, }, 1043 /* 4 - 4096x2160@24Hz (SMPTE) */ 1044 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1045 4096, 5116, 5204, 5500, 0, 1046 2160, 2168, 2178, 2250, 0, 1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1048 .vrefresh = 24, }, 1049 }; 1050 1051 /*** DDC fetch and block validation ***/ 1052 1053 static const u8 edid_header[] = { 1054 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1055 }; 1056 1057 /** 1058 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1059 * @raw_edid: pointer to raw base EDID block 1060 * 1061 * Sanity check the header of the base EDID block. 1062 * 1063 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1064 */ 1065 int drm_edid_header_is_valid(const u8 *raw_edid) 1066 { 1067 int i, score = 0; 1068 1069 for (i = 0; i < sizeof(edid_header); i++) 1070 if (raw_edid[i] == edid_header[i]) 1071 score++; 1072 1073 return score; 1074 } 1075 EXPORT_SYMBOL(drm_edid_header_is_valid); 1076 1077 static int edid_fixup __read_mostly = 6; 1078 module_param_named(edid_fixup, edid_fixup, int, 0400); 1079 MODULE_PARM_DESC(edid_fixup, 1080 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1081 1082 static void drm_get_displayid(struct drm_connector *connector, 1083 struct edid *edid); 1084 1085 static int drm_edid_block_checksum(const u8 *raw_edid) 1086 { 1087 int i; 1088 u8 csum = 0; 1089 for (i = 0; i < EDID_LENGTH; i++) 1090 csum += raw_edid[i]; 1091 1092 return csum; 1093 } 1094 1095 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1096 { 1097 if (memchr_inv(in_edid, 0, length)) 1098 return false; 1099 1100 return true; 1101 } 1102 1103 /** 1104 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1105 * @raw_edid: pointer to raw EDID block 1106 * @block: type of block to validate (0 for base, extension otherwise) 1107 * @print_bad_edid: if true, dump bad EDID blocks to the console 1108 * @edid_corrupt: if true, the header or checksum is invalid 1109 * 1110 * Validate a base or extension EDID block and optionally dump bad blocks to 1111 * the console. 1112 * 1113 * Return: True if the block is valid, false otherwise. 1114 */ 1115 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1116 bool *edid_corrupt) 1117 { 1118 u8 csum; 1119 struct edid *edid = (struct edid *)raw_edid; 1120 1121 if (WARN_ON(!raw_edid)) 1122 return false; 1123 1124 if (edid_fixup > 8 || edid_fixup < 0) 1125 edid_fixup = 6; 1126 1127 if (block == 0) { 1128 int score = drm_edid_header_is_valid(raw_edid); 1129 if (score == 8) { 1130 if (edid_corrupt) 1131 *edid_corrupt = false; 1132 } else if (score >= edid_fixup) { 1133 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1134 * The corrupt flag needs to be set here otherwise, the 1135 * fix-up code here will correct the problem, the 1136 * checksum is correct and the test fails 1137 */ 1138 if (edid_corrupt) 1139 *edid_corrupt = true; 1140 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1141 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1142 } else { 1143 if (edid_corrupt) 1144 *edid_corrupt = true; 1145 goto bad; 1146 } 1147 } 1148 1149 csum = drm_edid_block_checksum(raw_edid); 1150 if (csum) { 1151 if (edid_corrupt) 1152 *edid_corrupt = true; 1153 1154 /* allow CEA to slide through, switches mangle this */ 1155 if (raw_edid[0] == CEA_EXT) { 1156 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1157 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1158 } else { 1159 if (print_bad_edid) 1160 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1161 1162 goto bad; 1163 } 1164 } 1165 1166 /* per-block-type checks */ 1167 switch (raw_edid[0]) { 1168 case 0: /* base */ 1169 if (edid->version != 1) { 1170 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1171 goto bad; 1172 } 1173 1174 if (edid->revision > 4) 1175 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1176 break; 1177 1178 default: 1179 break; 1180 } 1181 1182 return true; 1183 1184 bad: 1185 if (print_bad_edid) { 1186 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1187 pr_notice("EDID block is all zeroes\n"); 1188 } else { 1189 pr_notice("Raw EDID:\n"); 1190 print_hex_dump(KERN_NOTICE, 1191 " \t", DUMP_PREFIX_NONE, 16, 1, 1192 raw_edid, EDID_LENGTH, false); 1193 } 1194 } 1195 return false; 1196 } 1197 EXPORT_SYMBOL(drm_edid_block_valid); 1198 1199 /** 1200 * drm_edid_is_valid - sanity check EDID data 1201 * @edid: EDID data 1202 * 1203 * Sanity-check an entire EDID record (including extensions) 1204 * 1205 * Return: True if the EDID data is valid, false otherwise. 1206 */ 1207 bool drm_edid_is_valid(struct edid *edid) 1208 { 1209 int i; 1210 u8 *raw = (u8 *)edid; 1211 1212 if (!edid) 1213 return false; 1214 1215 for (i = 0; i <= edid->extensions; i++) 1216 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1217 return false; 1218 1219 return true; 1220 } 1221 EXPORT_SYMBOL(drm_edid_is_valid); 1222 1223 #define DDC_SEGMENT_ADDR 0x30 1224 /** 1225 * drm_do_probe_ddc_edid() - get EDID information via I2C 1226 * @data: I2C device adapter 1227 * @buf: EDID data buffer to be filled 1228 * @block: 128 byte EDID block to start fetching from 1229 * @len: EDID data buffer length to fetch 1230 * 1231 * Try to fetch EDID information by calling I2C driver functions. 1232 * 1233 * Return: 0 on success or -1 on failure. 1234 */ 1235 static int 1236 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1237 { 1238 struct i2c_adapter *adapter = data; 1239 unsigned char start = block * EDID_LENGTH; 1240 unsigned char segment = block >> 1; 1241 unsigned char xfers = segment ? 3 : 2; 1242 int ret, retries = 5; 1243 1244 /* 1245 * The core I2C driver will automatically retry the transfer if the 1246 * adapter reports EAGAIN. However, we find that bit-banging transfers 1247 * are susceptible to errors under a heavily loaded machine and 1248 * generate spurious NAKs and timeouts. Retrying the transfer 1249 * of the individual block a few times seems to overcome this. 1250 */ 1251 do { 1252 struct i2c_msg msgs[] = { 1253 { 1254 .addr = DDC_SEGMENT_ADDR, 1255 .flags = 0, 1256 .len = 1, 1257 .buf = &segment, 1258 }, { 1259 .addr = DDC_ADDR, 1260 .flags = 0, 1261 .len = 1, 1262 .buf = &start, 1263 }, { 1264 .addr = DDC_ADDR, 1265 .flags = I2C_M_RD, 1266 .len = len, 1267 .buf = buf, 1268 } 1269 }; 1270 1271 /* 1272 * Avoid sending the segment addr to not upset non-compliant 1273 * DDC monitors. 1274 */ 1275 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1276 1277 if (ret == -ENXIO) { 1278 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1279 adapter->name); 1280 break; 1281 } 1282 } while (ret != xfers && --retries); 1283 1284 return ret == xfers ? 0 : -1; 1285 } 1286 1287 static void connector_bad_edid(struct drm_connector *connector, 1288 u8 *edid, int num_blocks) 1289 { 1290 int i; 1291 1292 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS)) 1293 return; 1294 1295 dev_warn(connector->dev->dev, 1296 "%s: EDID is invalid:\n", 1297 connector->name); 1298 for (i = 0; i < num_blocks; i++) { 1299 u8 *block = edid + i * EDID_LENGTH; 1300 char prefix[20]; 1301 1302 if (drm_edid_is_zero(block, EDID_LENGTH)) 1303 ksprintf(prefix, "\t[%02x] ZERO ", i); 1304 else if (!drm_edid_block_valid(block, i, false, NULL)) 1305 ksprintf(prefix, "\t[%02x] BAD ", i); 1306 else 1307 ksprintf(prefix, "\t[%02x] GOOD ", i); 1308 1309 print_hex_dump(KERN_WARNING, 1310 prefix, DUMP_PREFIX_NONE, 16, 1, 1311 block, EDID_LENGTH, false); 1312 } 1313 } 1314 1315 /** 1316 * drm_do_get_edid - get EDID data using a custom EDID block read function 1317 * @connector: connector we're probing 1318 * @get_edid_block: EDID block read function 1319 * @data: private data passed to the block read function 1320 * 1321 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1322 * exposes a different interface to read EDID blocks this function can be used 1323 * to get EDID data using a custom block read function. 1324 * 1325 * As in the general case the DDC bus is accessible by the kernel at the I2C 1326 * level, drivers must make all reasonable efforts to expose it as an I2C 1327 * adapter and use drm_get_edid() instead of abusing this function. 1328 * 1329 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1330 */ 1331 struct edid *drm_do_get_edid(struct drm_connector *connector, 1332 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1333 size_t len), 1334 void *data) 1335 { 1336 int i, j = 0, valid_extensions = 0; 1337 u8 *edid, *new; 1338 1339 if ((edid = kmalloc(EDID_LENGTH, M_DRM, GFP_KERNEL)) == NULL) 1340 return NULL; 1341 1342 /* base block fetch */ 1343 for (i = 0; i < 4; i++) { 1344 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1345 goto out; 1346 if (drm_edid_block_valid(edid, 0, false, 1347 &connector->edid_corrupt)) 1348 break; 1349 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1350 connector->null_edid_counter++; 1351 goto carp; 1352 } 1353 } 1354 if (i == 4) 1355 goto carp; 1356 1357 /* if there's no extensions, we're done */ 1358 valid_extensions = edid[0x7e]; 1359 if (valid_extensions == 0) 1360 return (struct edid *)edid; 1361 1362 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, M_DRM, 1363 GFP_KERNEL); 1364 if (!new) 1365 goto out; 1366 edid = new; 1367 1368 for (j = 1; j <= edid[0x7e]; j++) { 1369 u8 *block = edid + j * EDID_LENGTH; 1370 1371 for (i = 0; i < 4; i++) { 1372 if (get_edid_block(data, block, j, EDID_LENGTH)) 1373 goto out; 1374 if (drm_edid_block_valid(block, j, false, NULL)) 1375 break; 1376 } 1377 1378 if (i == 4) 1379 valid_extensions--; 1380 } 1381 1382 if (valid_extensions != edid[0x7e]) { 1383 u8 *base; 1384 1385 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1386 1387 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1388 edid[0x7e] = valid_extensions; 1389 1390 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, M_DRM, 1391 GFP_KERNEL); 1392 if (!new) 1393 goto out; 1394 1395 base = new; 1396 for (i = 0; i <= edid[0x7e]; i++) { 1397 u8 *block = edid + i * EDID_LENGTH; 1398 1399 if (!drm_edid_block_valid(block, i, false, NULL)) 1400 continue; 1401 1402 memcpy(base, block, EDID_LENGTH); 1403 base += EDID_LENGTH; 1404 } 1405 1406 kfree(edid); 1407 edid = new; 1408 } 1409 1410 return (struct edid *)edid; 1411 1412 carp: 1413 connector_bad_edid(connector, edid, 1); 1414 out: 1415 kfree(edid); 1416 return NULL; 1417 } 1418 1419 /** 1420 * drm_probe_ddc() - probe DDC presence 1421 * @adapter: I2C adapter to probe 1422 * 1423 * Return: True on success, false on failure. 1424 */ 1425 bool 1426 drm_probe_ddc(struct i2c_adapter *adapter) 1427 { 1428 unsigned char out; 1429 1430 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1431 } 1432 EXPORT_SYMBOL(drm_probe_ddc); 1433 1434 /** 1435 * drm_get_edid - get EDID data, if available 1436 * @connector: connector we're probing 1437 * @adapter: I2C adapter to use for DDC 1438 * 1439 * Poke the given I2C channel to grab EDID data if possible. If found, 1440 * attach it to the connector. 1441 * 1442 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1443 */ 1444 struct edid *drm_get_edid(struct drm_connector *connector, 1445 struct i2c_adapter *adapter) 1446 { 1447 struct edid *edid; 1448 1449 if (connector->force == DRM_FORCE_OFF) 1450 return NULL; 1451 1452 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 1453 return NULL; 1454 1455 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1456 if (edid) 1457 drm_get_displayid(connector, edid); 1458 return edid; 1459 } 1460 EXPORT_SYMBOL(drm_get_edid); 1461 1462 /** 1463 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1464 * @connector: connector we're probing 1465 * @adapter: I2C adapter to use for DDC 1466 * 1467 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1468 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1469 * switch DDC to the GPU which is retrieving EDID. 1470 * 1471 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1472 */ 1473 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1474 struct i2c_adapter *adapter) 1475 { 1476 struct pci_dev *pdev = connector->dev->pdev; 1477 struct edid *edid; 1478 1479 vga_switcheroo_lock_ddc(pdev); 1480 edid = drm_get_edid(connector, adapter); 1481 vga_switcheroo_unlock_ddc(pdev); 1482 1483 return edid; 1484 } 1485 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1486 1487 /** 1488 * drm_edid_duplicate - duplicate an EDID and the extensions 1489 * @edid: EDID to duplicate 1490 * 1491 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1492 */ 1493 struct edid *drm_edid_duplicate(const struct edid *edid) 1494 { 1495 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1496 } 1497 EXPORT_SYMBOL(drm_edid_duplicate); 1498 1499 /*** EDID parsing ***/ 1500 1501 /** 1502 * edid_vendor - match a string against EDID's obfuscated vendor field 1503 * @edid: EDID to match 1504 * @vendor: vendor string 1505 * 1506 * Returns true if @vendor is in @edid, false otherwise 1507 */ 1508 static bool edid_vendor(struct edid *edid, const char *vendor) 1509 { 1510 char edid_vendor[3]; 1511 1512 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1513 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1514 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1515 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1516 1517 return !strncmp(edid_vendor, vendor, 3); 1518 } 1519 1520 /** 1521 * edid_get_quirks - return quirk flags for a given EDID 1522 * @edid: EDID to process 1523 * 1524 * This tells subsequent routines what fixes they need to apply. 1525 */ 1526 static u32 edid_get_quirks(struct edid *edid) 1527 { 1528 const struct edid_quirk *quirk; 1529 int i; 1530 1531 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1532 quirk = &edid_quirk_list[i]; 1533 1534 if (edid_vendor(edid, quirk->vendor) && 1535 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1536 return quirk->quirks; 1537 } 1538 1539 return 0; 1540 } 1541 1542 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1543 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1544 1545 /** 1546 * edid_fixup_preferred - set preferred modes based on quirk list 1547 * @connector: has mode list to fix up 1548 * @quirks: quirks list 1549 * 1550 * Walk the mode list for @connector, clearing the preferred status 1551 * on existing modes and setting it anew for the right mode ala @quirks. 1552 */ 1553 static void edid_fixup_preferred(struct drm_connector *connector, 1554 u32 quirks) 1555 { 1556 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1557 int target_refresh = 0; 1558 int cur_vrefresh, preferred_vrefresh; 1559 1560 if (list_empty(&connector->probed_modes)) 1561 return; 1562 1563 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1564 target_refresh = 60; 1565 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1566 target_refresh = 75; 1567 1568 preferred_mode = list_first_entry(&connector->probed_modes, 1569 struct drm_display_mode, head); 1570 1571 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1572 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1573 1574 if (cur_mode == preferred_mode) 1575 continue; 1576 1577 /* Largest mode is preferred */ 1578 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1579 preferred_mode = cur_mode; 1580 1581 cur_vrefresh = cur_mode->vrefresh ? 1582 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1583 preferred_vrefresh = preferred_mode->vrefresh ? 1584 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1585 /* At a given size, try to get closest to target refresh */ 1586 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1587 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1588 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1589 preferred_mode = cur_mode; 1590 } 1591 } 1592 1593 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1594 } 1595 1596 static bool 1597 mode_is_rb(const struct drm_display_mode *mode) 1598 { 1599 return (mode->htotal - mode->hdisplay == 160) && 1600 (mode->hsync_end - mode->hdisplay == 80) && 1601 (mode->hsync_end - mode->hsync_start == 32) && 1602 (mode->vsync_start - mode->vdisplay == 3); 1603 } 1604 1605 /* 1606 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1607 * @dev: Device to duplicate against 1608 * @hsize: Mode width 1609 * @vsize: Mode height 1610 * @fresh: Mode refresh rate 1611 * @rb: Mode reduced-blanking-ness 1612 * 1613 * Walk the DMT mode list looking for a match for the given parameters. 1614 * 1615 * Return: A newly allocated copy of the mode, or NULL if not found. 1616 */ 1617 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1618 int hsize, int vsize, int fresh, 1619 bool rb) 1620 { 1621 int i; 1622 1623 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1624 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1625 if (hsize != ptr->hdisplay) 1626 continue; 1627 if (vsize != ptr->vdisplay) 1628 continue; 1629 if (fresh != drm_mode_vrefresh(ptr)) 1630 continue; 1631 if (rb != mode_is_rb(ptr)) 1632 continue; 1633 1634 return drm_mode_duplicate(dev, ptr); 1635 } 1636 1637 return NULL; 1638 } 1639 EXPORT_SYMBOL(drm_mode_find_dmt); 1640 1641 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1642 1643 static void 1644 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1645 { 1646 int i, n = 0; 1647 u8 d = ext[0x02]; 1648 u8 *det_base = ext + d; 1649 1650 n = (127 - d) / 18; 1651 for (i = 0; i < n; i++) 1652 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1653 } 1654 1655 static void 1656 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1657 { 1658 unsigned int i, n = min((int)ext[0x02], 6); 1659 u8 *det_base = ext + 5; 1660 1661 if (ext[0x01] != 1) 1662 return; /* unknown version */ 1663 1664 for (i = 0; i < n; i++) 1665 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1666 } 1667 1668 static void 1669 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1670 { 1671 int i; 1672 struct edid *edid = (struct edid *)raw_edid; 1673 1674 if (edid == NULL) 1675 return; 1676 1677 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1678 cb(&(edid->detailed_timings[i]), closure); 1679 1680 for (i = 1; i <= raw_edid[0x7e]; i++) { 1681 u8 *ext = raw_edid + (i * EDID_LENGTH); 1682 switch (*ext) { 1683 case CEA_EXT: 1684 cea_for_each_detailed_block(ext, cb, closure); 1685 break; 1686 case VTB_EXT: 1687 vtb_for_each_detailed_block(ext, cb, closure); 1688 break; 1689 default: 1690 break; 1691 } 1692 } 1693 } 1694 1695 static void 1696 is_rb(struct detailed_timing *t, void *data) 1697 { 1698 u8 *r = (u8 *)t; 1699 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1700 if (r[15] & 0x10) 1701 *(bool *)data = true; 1702 } 1703 1704 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1705 static bool 1706 drm_monitor_supports_rb(struct edid *edid) 1707 { 1708 if (edid->revision >= 4) { 1709 bool ret = false; 1710 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1711 return ret; 1712 } 1713 1714 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1715 } 1716 1717 static void 1718 find_gtf2(struct detailed_timing *t, void *data) 1719 { 1720 u8 *r = (u8 *)t; 1721 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1722 *(u8 **)data = r; 1723 } 1724 1725 /* Secondary GTF curve kicks in above some break frequency */ 1726 static int 1727 drm_gtf2_hbreak(struct edid *edid) 1728 { 1729 u8 *r = NULL; 1730 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1731 return r ? (r[12] * 2) : 0; 1732 } 1733 1734 static int 1735 drm_gtf2_2c(struct edid *edid) 1736 { 1737 u8 *r = NULL; 1738 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1739 return r ? r[13] : 0; 1740 } 1741 1742 static int 1743 drm_gtf2_m(struct edid *edid) 1744 { 1745 u8 *r = NULL; 1746 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1747 return r ? (r[15] << 8) + r[14] : 0; 1748 } 1749 1750 static int 1751 drm_gtf2_k(struct edid *edid) 1752 { 1753 u8 *r = NULL; 1754 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1755 return r ? r[16] : 0; 1756 } 1757 1758 static int 1759 drm_gtf2_2j(struct edid *edid) 1760 { 1761 u8 *r = NULL; 1762 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1763 return r ? r[17] : 0; 1764 } 1765 1766 /** 1767 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1768 * @edid: EDID block to scan 1769 */ 1770 static int standard_timing_level(struct edid *edid) 1771 { 1772 if (edid->revision >= 2) { 1773 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1774 return LEVEL_CVT; 1775 if (drm_gtf2_hbreak(edid)) 1776 return LEVEL_GTF2; 1777 return LEVEL_GTF; 1778 } 1779 return LEVEL_DMT; 1780 } 1781 1782 /* 1783 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1784 * monitors fill with ascii space (0x20) instead. 1785 */ 1786 static int 1787 bad_std_timing(u8 a, u8 b) 1788 { 1789 return (a == 0x00 && b == 0x00) || 1790 (a == 0x01 && b == 0x01) || 1791 (a == 0x20 && b == 0x20); 1792 } 1793 1794 /** 1795 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1796 * @connector: connector of for the EDID block 1797 * @edid: EDID block to scan 1798 * @t: standard timing params 1799 * 1800 * Take the standard timing params (in this case width, aspect, and refresh) 1801 * and convert them into a real mode using CVT/GTF/DMT. 1802 */ 1803 static struct drm_display_mode * 1804 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1805 struct std_timing *t) 1806 { 1807 struct drm_device *dev = connector->dev; 1808 struct drm_display_mode *m, *mode = NULL; 1809 int hsize, vsize; 1810 int vrefresh_rate; 1811 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1812 >> EDID_TIMING_ASPECT_SHIFT; 1813 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1814 >> EDID_TIMING_VFREQ_SHIFT; 1815 int timing_level = standard_timing_level(edid); 1816 1817 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1818 return NULL; 1819 1820 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1821 hsize = t->hsize * 8 + 248; 1822 /* vrefresh_rate = vfreq + 60 */ 1823 vrefresh_rate = vfreq + 60; 1824 /* the vdisplay is calculated based on the aspect ratio */ 1825 if (aspect_ratio == 0) { 1826 if (edid->revision < 3) 1827 vsize = hsize; 1828 else 1829 vsize = (hsize * 10) / 16; 1830 } else if (aspect_ratio == 1) 1831 vsize = (hsize * 3) / 4; 1832 else if (aspect_ratio == 2) 1833 vsize = (hsize * 4) / 5; 1834 else 1835 vsize = (hsize * 9) / 16; 1836 1837 /* HDTV hack, part 1 */ 1838 if (vrefresh_rate == 60 && 1839 ((hsize == 1360 && vsize == 765) || 1840 (hsize == 1368 && vsize == 769))) { 1841 hsize = 1366; 1842 vsize = 768; 1843 } 1844 1845 /* 1846 * If this connector already has a mode for this size and refresh 1847 * rate (because it came from detailed or CVT info), use that 1848 * instead. This way we don't have to guess at interlace or 1849 * reduced blanking. 1850 */ 1851 list_for_each_entry(m, &connector->probed_modes, head) 1852 if (m->hdisplay == hsize && m->vdisplay == vsize && 1853 drm_mode_vrefresh(m) == vrefresh_rate) 1854 return NULL; 1855 1856 /* HDTV hack, part 2 */ 1857 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1858 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1859 false); 1860 mode->hdisplay = 1366; 1861 mode->hsync_start = mode->hsync_start - 1; 1862 mode->hsync_end = mode->hsync_end - 1; 1863 return mode; 1864 } 1865 1866 /* check whether it can be found in default mode table */ 1867 if (drm_monitor_supports_rb(edid)) { 1868 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1869 true); 1870 if (mode) 1871 return mode; 1872 } 1873 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1874 if (mode) 1875 return mode; 1876 1877 /* okay, generate it */ 1878 switch (timing_level) { 1879 case LEVEL_DMT: 1880 break; 1881 case LEVEL_GTF: 1882 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1883 break; 1884 case LEVEL_GTF2: 1885 /* 1886 * This is potentially wrong if there's ever a monitor with 1887 * more than one ranges section, each claiming a different 1888 * secondary GTF curve. Please don't do that. 1889 */ 1890 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1891 if (!mode) 1892 return NULL; 1893 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1894 drm_mode_destroy(dev, mode); 1895 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1896 vrefresh_rate, 0, 0, 1897 drm_gtf2_m(edid), 1898 drm_gtf2_2c(edid), 1899 drm_gtf2_k(edid), 1900 drm_gtf2_2j(edid)); 1901 } 1902 break; 1903 case LEVEL_CVT: 1904 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1905 false); 1906 break; 1907 } 1908 return mode; 1909 } 1910 1911 /* 1912 * EDID is delightfully ambiguous about how interlaced modes are to be 1913 * encoded. Our internal representation is of frame height, but some 1914 * HDTV detailed timings are encoded as field height. 1915 * 1916 * The format list here is from CEA, in frame size. Technically we 1917 * should be checking refresh rate too. Whatever. 1918 */ 1919 static void 1920 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1921 struct detailed_pixel_timing *pt) 1922 { 1923 int i; 1924 static const struct { 1925 int w, h; 1926 } cea_interlaced[] = { 1927 { 1920, 1080 }, 1928 { 720, 480 }, 1929 { 1440, 480 }, 1930 { 2880, 480 }, 1931 { 720, 576 }, 1932 { 1440, 576 }, 1933 { 2880, 576 }, 1934 }; 1935 1936 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1937 return; 1938 1939 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1940 if ((mode->hdisplay == cea_interlaced[i].w) && 1941 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1942 mode->vdisplay *= 2; 1943 mode->vsync_start *= 2; 1944 mode->vsync_end *= 2; 1945 mode->vtotal *= 2; 1946 mode->vtotal |= 1; 1947 } 1948 } 1949 1950 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1951 } 1952 1953 /** 1954 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1955 * @dev: DRM device (needed to create new mode) 1956 * @edid: EDID block 1957 * @timing: EDID detailed timing info 1958 * @quirks: quirks to apply 1959 * 1960 * An EDID detailed timing block contains enough info for us to create and 1961 * return a new struct drm_display_mode. 1962 */ 1963 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1964 struct edid *edid, 1965 struct detailed_timing *timing, 1966 u32 quirks) 1967 { 1968 struct drm_display_mode *mode; 1969 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1970 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1971 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1972 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1973 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1974 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1975 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1976 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1977 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1978 1979 /* ignore tiny modes */ 1980 if (hactive < 64 || vactive < 64) 1981 return NULL; 1982 1983 if (pt->misc & DRM_EDID_PT_STEREO) { 1984 DRM_DEBUG_KMS("stereo mode not supported\n"); 1985 return NULL; 1986 } 1987 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1988 DRM_DEBUG_KMS("composite sync not supported\n"); 1989 } 1990 1991 /* it is incorrect if hsync/vsync width is zero */ 1992 if (!hsync_pulse_width || !vsync_pulse_width) { 1993 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1994 "Wrong Hsync/Vsync pulse width\n"); 1995 return NULL; 1996 } 1997 1998 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1999 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2000 if (!mode) 2001 return NULL; 2002 2003 goto set_size; 2004 } 2005 2006 mode = drm_mode_create(dev); 2007 if (!mode) 2008 return NULL; 2009 2010 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2011 timing->pixel_clock = cpu_to_le16(1088); 2012 2013 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2014 2015 mode->hdisplay = hactive; 2016 mode->hsync_start = mode->hdisplay + hsync_offset; 2017 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2018 mode->htotal = mode->hdisplay + hblank; 2019 2020 mode->vdisplay = vactive; 2021 mode->vsync_start = mode->vdisplay + vsync_offset; 2022 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2023 mode->vtotal = mode->vdisplay + vblank; 2024 2025 /* Some EDIDs have bogus h/vtotal values */ 2026 if (mode->hsync_end > mode->htotal) 2027 mode->htotal = mode->hsync_end + 1; 2028 if (mode->vsync_end > mode->vtotal) 2029 mode->vtotal = mode->vsync_end + 1; 2030 2031 drm_mode_do_interlace_quirk(mode, pt); 2032 2033 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2034 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2035 } 2036 2037 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2038 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2039 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2040 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2041 2042 set_size: 2043 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2044 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2045 2046 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2047 mode->width_mm *= 10; 2048 mode->height_mm *= 10; 2049 } 2050 2051 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2052 mode->width_mm = edid->width_cm * 10; 2053 mode->height_mm = edid->height_cm * 10; 2054 } 2055 2056 mode->type = DRM_MODE_TYPE_DRIVER; 2057 mode->vrefresh = drm_mode_vrefresh(mode); 2058 drm_mode_set_name(mode); 2059 2060 return mode; 2061 } 2062 2063 static bool 2064 mode_in_hsync_range(const struct drm_display_mode *mode, 2065 struct edid *edid, u8 *t) 2066 { 2067 int hsync, hmin, hmax; 2068 2069 hmin = t[7]; 2070 if (edid->revision >= 4) 2071 hmin += ((t[4] & 0x04) ? 255 : 0); 2072 hmax = t[8]; 2073 if (edid->revision >= 4) 2074 hmax += ((t[4] & 0x08) ? 255 : 0); 2075 hsync = drm_mode_hsync(mode); 2076 2077 return (hsync <= hmax && hsync >= hmin); 2078 } 2079 2080 static bool 2081 mode_in_vsync_range(const struct drm_display_mode *mode, 2082 struct edid *edid, u8 *t) 2083 { 2084 int vsync, vmin, vmax; 2085 2086 vmin = t[5]; 2087 if (edid->revision >= 4) 2088 vmin += ((t[4] & 0x01) ? 255 : 0); 2089 vmax = t[6]; 2090 if (edid->revision >= 4) 2091 vmax += ((t[4] & 0x02) ? 255 : 0); 2092 vsync = drm_mode_vrefresh(mode); 2093 2094 return (vsync <= vmax && vsync >= vmin); 2095 } 2096 2097 static u32 2098 range_pixel_clock(struct edid *edid, u8 *t) 2099 { 2100 /* unspecified */ 2101 if (t[9] == 0 || t[9] == 255) 2102 return 0; 2103 2104 /* 1.4 with CVT support gives us real precision, yay */ 2105 if (edid->revision >= 4 && t[10] == 0x04) 2106 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2107 2108 /* 1.3 is pathetic, so fuzz up a bit */ 2109 return t[9] * 10000 + 5001; 2110 } 2111 2112 static bool 2113 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2114 struct detailed_timing *timing) 2115 { 2116 u32 max_clock; 2117 u8 *t = (u8 *)timing; 2118 2119 if (!mode_in_hsync_range(mode, edid, t)) 2120 return false; 2121 2122 if (!mode_in_vsync_range(mode, edid, t)) 2123 return false; 2124 2125 if ((max_clock = range_pixel_clock(edid, t))) 2126 if (mode->clock > max_clock) 2127 return false; 2128 2129 /* 1.4 max horizontal check */ 2130 if (edid->revision >= 4 && t[10] == 0x04) 2131 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2132 return false; 2133 2134 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2135 return false; 2136 2137 return true; 2138 } 2139 2140 static bool valid_inferred_mode(const struct drm_connector *connector, 2141 const struct drm_display_mode *mode) 2142 { 2143 const struct drm_display_mode *m; 2144 bool ok = false; 2145 2146 list_for_each_entry(m, &connector->probed_modes, head) { 2147 if (mode->hdisplay == m->hdisplay && 2148 mode->vdisplay == m->vdisplay && 2149 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2150 return false; /* duplicated */ 2151 if (mode->hdisplay <= m->hdisplay && 2152 mode->vdisplay <= m->vdisplay) 2153 ok = true; 2154 } 2155 return ok; 2156 } 2157 2158 static int 2159 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2160 struct detailed_timing *timing) 2161 { 2162 int i, modes = 0; 2163 struct drm_display_mode *newmode; 2164 struct drm_device *dev = connector->dev; 2165 2166 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2167 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2168 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2169 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2170 if (newmode) { 2171 drm_mode_probed_add(connector, newmode); 2172 modes++; 2173 } 2174 } 2175 } 2176 2177 return modes; 2178 } 2179 2180 /* fix up 1366x768 mode from 1368x768; 2181 * GFT/CVT can't express 1366 width which isn't dividable by 8 2182 */ 2183 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2184 { 2185 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2186 mode->hdisplay = 1366; 2187 mode->hsync_start--; 2188 mode->hsync_end--; 2189 drm_mode_set_name(mode); 2190 } 2191 } 2192 2193 static int 2194 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2195 struct detailed_timing *timing) 2196 { 2197 int i, modes = 0; 2198 struct drm_display_mode *newmode; 2199 struct drm_device *dev = connector->dev; 2200 2201 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2202 const struct minimode *m = &extra_modes[i]; 2203 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2204 if (!newmode) 2205 return modes; 2206 2207 drm_mode_fixup_1366x768(newmode); 2208 if (!mode_in_range(newmode, edid, timing) || 2209 !valid_inferred_mode(connector, newmode)) { 2210 drm_mode_destroy(dev, newmode); 2211 continue; 2212 } 2213 2214 drm_mode_probed_add(connector, newmode); 2215 modes++; 2216 } 2217 2218 return modes; 2219 } 2220 2221 static int 2222 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2223 struct detailed_timing *timing) 2224 { 2225 int i, modes = 0; 2226 struct drm_display_mode *newmode; 2227 struct drm_device *dev = connector->dev; 2228 bool rb = drm_monitor_supports_rb(edid); 2229 2230 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2231 const struct minimode *m = &extra_modes[i]; 2232 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2233 if (!newmode) 2234 return modes; 2235 2236 drm_mode_fixup_1366x768(newmode); 2237 if (!mode_in_range(newmode, edid, timing) || 2238 !valid_inferred_mode(connector, newmode)) { 2239 drm_mode_destroy(dev, newmode); 2240 continue; 2241 } 2242 2243 drm_mode_probed_add(connector, newmode); 2244 modes++; 2245 } 2246 2247 return modes; 2248 } 2249 2250 static void 2251 do_inferred_modes(struct detailed_timing *timing, void *c) 2252 { 2253 struct detailed_mode_closure *closure = c; 2254 struct detailed_non_pixel *data = &timing->data.other_data; 2255 struct detailed_data_monitor_range *range = &data->data.range; 2256 2257 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2258 return; 2259 2260 closure->modes += drm_dmt_modes_for_range(closure->connector, 2261 closure->edid, 2262 timing); 2263 2264 if (!version_greater(closure->edid, 1, 1)) 2265 return; /* GTF not defined yet */ 2266 2267 switch (range->flags) { 2268 case 0x02: /* secondary gtf, XXX could do more */ 2269 case 0x00: /* default gtf */ 2270 closure->modes += drm_gtf_modes_for_range(closure->connector, 2271 closure->edid, 2272 timing); 2273 break; 2274 case 0x04: /* cvt, only in 1.4+ */ 2275 if (!version_greater(closure->edid, 1, 3)) 2276 break; 2277 2278 closure->modes += drm_cvt_modes_for_range(closure->connector, 2279 closure->edid, 2280 timing); 2281 break; 2282 case 0x01: /* just the ranges, no formula */ 2283 default: 2284 break; 2285 } 2286 } 2287 2288 static int 2289 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2290 { 2291 struct detailed_mode_closure closure = { 2292 .connector = connector, 2293 .edid = edid, 2294 }; 2295 2296 if (version_greater(edid, 1, 0)) 2297 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2298 &closure); 2299 2300 return closure.modes; 2301 } 2302 2303 static int 2304 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2305 { 2306 int i, j, m, modes = 0; 2307 struct drm_display_mode *mode; 2308 u8 *est = ((u8 *)timing) + 6; 2309 2310 for (i = 0; i < 6; i++) { 2311 for (j = 7; j >= 0; j--) { 2312 m = (i * 8) + (7 - j); 2313 if (m >= ARRAY_SIZE(est3_modes)) 2314 break; 2315 if (est[i] & (1 << j)) { 2316 mode = drm_mode_find_dmt(connector->dev, 2317 est3_modes[m].w, 2318 est3_modes[m].h, 2319 est3_modes[m].r, 2320 est3_modes[m].rb); 2321 if (mode) { 2322 drm_mode_probed_add(connector, mode); 2323 modes++; 2324 } 2325 } 2326 } 2327 } 2328 2329 return modes; 2330 } 2331 2332 static void 2333 do_established_modes(struct detailed_timing *timing, void *c) 2334 { 2335 struct detailed_mode_closure *closure = c; 2336 struct detailed_non_pixel *data = &timing->data.other_data; 2337 2338 if (data->type == EDID_DETAIL_EST_TIMINGS) 2339 closure->modes += drm_est3_modes(closure->connector, timing); 2340 } 2341 2342 /** 2343 * add_established_modes - get est. modes from EDID and add them 2344 * @connector: connector to add mode(s) to 2345 * @edid: EDID block to scan 2346 * 2347 * Each EDID block contains a bitmap of the supported "established modes" list 2348 * (defined above). Tease them out and add them to the global modes list. 2349 */ 2350 static int 2351 add_established_modes(struct drm_connector *connector, struct edid *edid) 2352 { 2353 struct drm_device *dev = connector->dev; 2354 unsigned long est_bits = edid->established_timings.t1 | 2355 (edid->established_timings.t2 << 8) | 2356 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2357 int i, modes = 0; 2358 struct detailed_mode_closure closure = { 2359 .connector = connector, 2360 .edid = edid, 2361 }; 2362 2363 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2364 if (est_bits & (1<<i)) { 2365 struct drm_display_mode *newmode; 2366 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2367 if (newmode) { 2368 drm_mode_probed_add(connector, newmode); 2369 modes++; 2370 } 2371 } 2372 } 2373 2374 if (version_greater(edid, 1, 0)) 2375 drm_for_each_detailed_block((u8 *)edid, 2376 do_established_modes, &closure); 2377 2378 return modes + closure.modes; 2379 } 2380 2381 static void 2382 do_standard_modes(struct detailed_timing *timing, void *c) 2383 { 2384 struct detailed_mode_closure *closure = c; 2385 struct detailed_non_pixel *data = &timing->data.other_data; 2386 struct drm_connector *connector = closure->connector; 2387 struct edid *edid = closure->edid; 2388 2389 if (data->type == EDID_DETAIL_STD_MODES) { 2390 int i; 2391 for (i = 0; i < 6; i++) { 2392 struct std_timing *std; 2393 struct drm_display_mode *newmode; 2394 2395 std = &data->data.timings[i]; 2396 newmode = drm_mode_std(connector, edid, std); 2397 if (newmode) { 2398 drm_mode_probed_add(connector, newmode); 2399 closure->modes++; 2400 } 2401 } 2402 } 2403 } 2404 2405 /** 2406 * add_standard_modes - get std. modes from EDID and add them 2407 * @connector: connector to add mode(s) to 2408 * @edid: EDID block to scan 2409 * 2410 * Standard modes can be calculated using the appropriate standard (DMT, 2411 * GTF or CVT. Grab them from @edid and add them to the list. 2412 */ 2413 static int 2414 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2415 { 2416 int i, modes = 0; 2417 struct detailed_mode_closure closure = { 2418 .connector = connector, 2419 .edid = edid, 2420 }; 2421 2422 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2423 struct drm_display_mode *newmode; 2424 2425 newmode = drm_mode_std(connector, edid, 2426 &edid->standard_timings[i]); 2427 if (newmode) { 2428 drm_mode_probed_add(connector, newmode); 2429 modes++; 2430 } 2431 } 2432 2433 if (version_greater(edid, 1, 0)) 2434 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2435 &closure); 2436 2437 /* XXX should also look for standard codes in VTB blocks */ 2438 2439 return modes + closure.modes; 2440 } 2441 2442 static int drm_cvt_modes(struct drm_connector *connector, 2443 struct detailed_timing *timing) 2444 { 2445 int i, j, modes = 0; 2446 struct drm_display_mode *newmode; 2447 struct drm_device *dev = connector->dev; 2448 struct cvt_timing *cvt; 2449 const int rates[] = { 60, 85, 75, 60, 50 }; 2450 const u8 empty[3] = { 0, 0, 0 }; 2451 2452 for (i = 0; i < 4; i++) { 2453 int width = 0, height; 2454 cvt = &(timing->data.other_data.data.cvt[i]); 2455 2456 if (!memcmp(cvt->code, empty, 3)) 2457 continue; 2458 2459 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2460 switch (cvt->code[1] & 0x0c) { 2461 case 0x00: 2462 width = height * 4 / 3; 2463 break; 2464 case 0x04: 2465 width = height * 16 / 9; 2466 break; 2467 case 0x08: 2468 width = height * 16 / 10; 2469 break; 2470 case 0x0c: 2471 width = height * 15 / 9; 2472 break; 2473 } 2474 2475 for (j = 1; j < 5; j++) { 2476 if (cvt->code[2] & (1 << j)) { 2477 newmode = drm_cvt_mode(dev, width, height, 2478 rates[j], j == 0, 2479 false, false); 2480 if (newmode) { 2481 drm_mode_probed_add(connector, newmode); 2482 modes++; 2483 } 2484 } 2485 } 2486 } 2487 2488 return modes; 2489 } 2490 2491 static void 2492 do_cvt_mode(struct detailed_timing *timing, void *c) 2493 { 2494 struct detailed_mode_closure *closure = c; 2495 struct detailed_non_pixel *data = &timing->data.other_data; 2496 2497 if (data->type == EDID_DETAIL_CVT_3BYTE) 2498 closure->modes += drm_cvt_modes(closure->connector, timing); 2499 } 2500 2501 static int 2502 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2503 { 2504 struct detailed_mode_closure closure = { 2505 .connector = connector, 2506 .edid = edid, 2507 }; 2508 2509 if (version_greater(edid, 1, 2)) 2510 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2511 2512 /* XXX should also look for CVT codes in VTB blocks */ 2513 2514 return closure.modes; 2515 } 2516 2517 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2518 2519 static void 2520 do_detailed_mode(struct detailed_timing *timing, void *c) 2521 { 2522 struct detailed_mode_closure *closure = c; 2523 struct drm_display_mode *newmode; 2524 2525 if (timing->pixel_clock) { 2526 newmode = drm_mode_detailed(closure->connector->dev, 2527 closure->edid, timing, 2528 closure->quirks); 2529 if (!newmode) 2530 return; 2531 2532 if (closure->preferred) 2533 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2534 2535 /* 2536 * Detailed modes are limited to 10kHz pixel clock resolution, 2537 * so fix up anything that looks like CEA/HDMI mode, but the clock 2538 * is just slightly off. 2539 */ 2540 fixup_detailed_cea_mode_clock(newmode); 2541 2542 drm_mode_probed_add(closure->connector, newmode); 2543 closure->modes++; 2544 closure->preferred = 0; 2545 } 2546 } 2547 2548 /* 2549 * add_detailed_modes - Add modes from detailed timings 2550 * @connector: attached connector 2551 * @edid: EDID block to scan 2552 * @quirks: quirks to apply 2553 */ 2554 static int 2555 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2556 u32 quirks) 2557 { 2558 struct detailed_mode_closure closure = { 2559 .connector = connector, 2560 .edid = edid, 2561 .preferred = 1, 2562 .quirks = quirks, 2563 }; 2564 2565 if (closure.preferred && !version_greater(edid, 1, 3)) 2566 closure.preferred = 2567 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2568 2569 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2570 2571 return closure.modes; 2572 } 2573 2574 #define AUDIO_BLOCK 0x01 2575 #define VIDEO_BLOCK 0x02 2576 #define VENDOR_BLOCK 0x03 2577 #define SPEAKER_BLOCK 0x04 2578 #define VIDEO_CAPABILITY_BLOCK 0x07 2579 #define EDID_BASIC_AUDIO (1 << 6) 2580 #define EDID_CEA_YCRCB444 (1 << 5) 2581 #define EDID_CEA_YCRCB422 (1 << 4) 2582 #define EDID_CEA_VCDB_QS (1 << 6) 2583 2584 /* 2585 * Search EDID for CEA extension block. 2586 */ 2587 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2588 { 2589 u8 *edid_ext = NULL; 2590 int i; 2591 2592 /* No EDID or EDID extensions */ 2593 if (edid == NULL || edid->extensions == 0) 2594 return NULL; 2595 2596 /* Find CEA extension */ 2597 for (i = 0; i < edid->extensions; i++) { 2598 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2599 if (edid_ext[0] == ext_id) 2600 break; 2601 } 2602 2603 if (i == edid->extensions) 2604 return NULL; 2605 2606 return edid_ext; 2607 } 2608 2609 static u8 *drm_find_cea_extension(struct edid *edid) 2610 { 2611 return drm_find_edid_extension(edid, CEA_EXT); 2612 } 2613 2614 static u8 *drm_find_displayid_extension(struct edid *edid) 2615 { 2616 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2617 } 2618 2619 /* 2620 * Calculate the alternate clock for the CEA mode 2621 * (60Hz vs. 59.94Hz etc.) 2622 */ 2623 static unsigned int 2624 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2625 { 2626 unsigned int clock = cea_mode->clock; 2627 2628 if (cea_mode->vrefresh % 6 != 0) 2629 return clock; 2630 2631 /* 2632 * edid_cea_modes contains the 59.94Hz 2633 * variant for 240 and 480 line modes, 2634 * and the 60Hz variant otherwise. 2635 */ 2636 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2637 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2638 else 2639 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2640 2641 return clock; 2642 } 2643 2644 static bool 2645 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 2646 { 2647 /* 2648 * For certain VICs the spec allows the vertical 2649 * front porch to vary by one or two lines. 2650 * 2651 * cea_modes[] stores the variant with the shortest 2652 * vertical front porch. We can adjust the mode to 2653 * get the other variants by simply increasing the 2654 * vertical front porch length. 2655 */ 2656 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 || 2657 edid_cea_modes[9].vtotal != 262 || 2658 edid_cea_modes[12].vtotal != 262 || 2659 edid_cea_modes[13].vtotal != 262 || 2660 edid_cea_modes[23].vtotal != 312 || 2661 edid_cea_modes[24].vtotal != 312 || 2662 edid_cea_modes[27].vtotal != 312 || 2663 edid_cea_modes[28].vtotal != 312); 2664 2665 if (((vic == 8 || vic == 9 || 2666 vic == 12 || vic == 13) && mode->vtotal < 263) || 2667 ((vic == 23 || vic == 24 || 2668 vic == 27 || vic == 28) && mode->vtotal < 314)) { 2669 mode->vsync_start++; 2670 mode->vsync_end++; 2671 mode->vtotal++; 2672 2673 return true; 2674 } 2675 2676 return false; 2677 } 2678 2679 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2680 unsigned int clock_tolerance) 2681 { 2682 u8 vic; 2683 2684 if (!to_match->clock) 2685 return 0; 2686 2687 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2688 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2689 unsigned int clock1, clock2; 2690 2691 /* Check both 60Hz and 59.94Hz */ 2692 clock1 = cea_mode.clock; 2693 clock2 = cea_mode_alternate_clock(&cea_mode); 2694 2695 if (abs(to_match->clock - clock1) > clock_tolerance && 2696 abs(to_match->clock - clock2) > clock_tolerance) 2697 continue; 2698 2699 do { 2700 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode)) 2701 return vic; 2702 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2703 } 2704 2705 return 0; 2706 } 2707 2708 /** 2709 * drm_match_cea_mode - look for a CEA mode matching given mode 2710 * @to_match: display mode 2711 * 2712 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2713 * mode. 2714 */ 2715 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2716 { 2717 u8 vic; 2718 2719 if (!to_match->clock) 2720 return 0; 2721 2722 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2723 struct drm_display_mode cea_mode = edid_cea_modes[vic]; 2724 unsigned int clock1, clock2; 2725 2726 /* Check both 60Hz and 59.94Hz */ 2727 clock1 = cea_mode.clock; 2728 clock2 = cea_mode_alternate_clock(&cea_mode); 2729 2730 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 2731 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 2732 continue; 2733 2734 do { 2735 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode)) 2736 return vic; 2737 } while (cea_mode_alternate_timings(vic, &cea_mode)); 2738 } 2739 2740 return 0; 2741 } 2742 EXPORT_SYMBOL(drm_match_cea_mode); 2743 2744 static bool drm_valid_cea_vic(u8 vic) 2745 { 2746 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2747 } 2748 2749 /** 2750 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2751 * the input VIC from the CEA mode list 2752 * @video_code: ID given to each of the CEA modes 2753 * 2754 * Returns picture aspect ratio 2755 */ 2756 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2757 { 2758 return edid_cea_modes[video_code].picture_aspect_ratio; 2759 } 2760 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2761 2762 /* 2763 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2764 * specific block). 2765 * 2766 * It's almost like cea_mode_alternate_clock(), we just need to add an 2767 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2768 * one. 2769 */ 2770 static unsigned int 2771 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2772 { 2773 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2774 return hdmi_mode->clock; 2775 2776 return cea_mode_alternate_clock(hdmi_mode); 2777 } 2778 2779 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 2780 unsigned int clock_tolerance) 2781 { 2782 u8 vic; 2783 2784 if (!to_match->clock) 2785 return 0; 2786 2787 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2788 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2789 unsigned int clock1, clock2; 2790 2791 /* Make sure to also match alternate clocks */ 2792 clock1 = hdmi_mode->clock; 2793 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2794 2795 if (abs(to_match->clock - clock1) > clock_tolerance && 2796 abs(to_match->clock - clock2) > clock_tolerance) 2797 continue; 2798 2799 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 2800 return vic; 2801 } 2802 2803 return 0; 2804 } 2805 2806 /* 2807 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2808 * @to_match: display mode 2809 * 2810 * An HDMI mode is one defined in the HDMI vendor specific block. 2811 * 2812 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2813 */ 2814 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2815 { 2816 u8 vic; 2817 2818 if (!to_match->clock) 2819 return 0; 2820 2821 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2822 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2823 unsigned int clock1, clock2; 2824 2825 /* Make sure to also match alternate clocks */ 2826 clock1 = hdmi_mode->clock; 2827 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2828 2829 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2830 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2831 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2832 return vic; 2833 } 2834 return 0; 2835 } 2836 2837 static bool drm_valid_hdmi_vic(u8 vic) 2838 { 2839 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2840 } 2841 2842 static int 2843 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2844 { 2845 struct drm_device *dev = connector->dev; 2846 struct drm_display_mode *mode, *tmp; 2847 LINUX_LIST_HEAD(list); 2848 int modes = 0; 2849 2850 /* Don't add CEA modes if the CEA extension block is missing */ 2851 if (!drm_find_cea_extension(edid)) 2852 return 0; 2853 2854 /* 2855 * Go through all probed modes and create a new mode 2856 * with the alternate clock for certain CEA modes. 2857 */ 2858 list_for_each_entry(mode, &connector->probed_modes, head) { 2859 const struct drm_display_mode *cea_mode = NULL; 2860 struct drm_display_mode *newmode; 2861 u8 vic = drm_match_cea_mode(mode); 2862 unsigned int clock1, clock2; 2863 2864 if (drm_valid_cea_vic(vic)) { 2865 cea_mode = &edid_cea_modes[vic]; 2866 clock2 = cea_mode_alternate_clock(cea_mode); 2867 } else { 2868 vic = drm_match_hdmi_mode(mode); 2869 if (drm_valid_hdmi_vic(vic)) { 2870 cea_mode = &edid_4k_modes[vic]; 2871 clock2 = hdmi_mode_alternate_clock(cea_mode); 2872 } 2873 } 2874 2875 if (!cea_mode) 2876 continue; 2877 2878 clock1 = cea_mode->clock; 2879 2880 if (clock1 == clock2) 2881 continue; 2882 2883 if (mode->clock != clock1 && mode->clock != clock2) 2884 continue; 2885 2886 newmode = drm_mode_duplicate(dev, cea_mode); 2887 if (!newmode) 2888 continue; 2889 2890 /* Carry over the stereo flags */ 2891 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2892 2893 /* 2894 * The current mode could be either variant. Make 2895 * sure to pick the "other" clock for the new mode. 2896 */ 2897 if (mode->clock != clock1) 2898 newmode->clock = clock1; 2899 else 2900 newmode->clock = clock2; 2901 2902 list_add_tail(&newmode->head, &list); 2903 } 2904 2905 list_for_each_entry_safe(mode, tmp, &list, head) { 2906 list_del(&mode->head); 2907 drm_mode_probed_add(connector, mode); 2908 modes++; 2909 } 2910 2911 return modes; 2912 } 2913 2914 static struct drm_display_mode * 2915 drm_display_mode_from_vic_index(struct drm_connector *connector, 2916 const u8 *video_db, u8 video_len, 2917 u8 video_index) 2918 { 2919 struct drm_device *dev = connector->dev; 2920 struct drm_display_mode *newmode; 2921 u8 vic; 2922 2923 if (video_db == NULL || video_index >= video_len) 2924 return NULL; 2925 2926 /* CEA modes are numbered 1..127 */ 2927 vic = (video_db[video_index] & 127); 2928 if (!drm_valid_cea_vic(vic)) 2929 return NULL; 2930 2931 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 2932 if (!newmode) 2933 return NULL; 2934 2935 newmode->vrefresh = 0; 2936 2937 return newmode; 2938 } 2939 2940 static int 2941 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2942 { 2943 int i, modes = 0; 2944 2945 for (i = 0; i < len; i++) { 2946 struct drm_display_mode *mode; 2947 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2948 if (mode) { 2949 drm_mode_probed_add(connector, mode); 2950 modes++; 2951 } 2952 } 2953 2954 return modes; 2955 } 2956 2957 struct stereo_mandatory_mode { 2958 int width, height, vrefresh; 2959 unsigned int flags; 2960 }; 2961 2962 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2963 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2964 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2965 { 1920, 1080, 50, 2966 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2967 { 1920, 1080, 60, 2968 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2969 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2970 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2971 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2972 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2973 }; 2974 2975 static bool 2976 stereo_match_mandatory(const struct drm_display_mode *mode, 2977 const struct stereo_mandatory_mode *stereo_mode) 2978 { 2979 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2980 2981 return mode->hdisplay == stereo_mode->width && 2982 mode->vdisplay == stereo_mode->height && 2983 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2984 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2985 } 2986 2987 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2988 { 2989 struct drm_device *dev = connector->dev; 2990 const struct drm_display_mode *mode; 2991 struct list_head stereo_modes; 2992 int modes = 0, i; 2993 2994 INIT_LIST_HEAD(&stereo_modes); 2995 2996 list_for_each_entry(mode, &connector->probed_modes, head) { 2997 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2998 const struct stereo_mandatory_mode *mandatory; 2999 struct drm_display_mode *new_mode; 3000 3001 if (!stereo_match_mandatory(mode, 3002 &stereo_mandatory_modes[i])) 3003 continue; 3004 3005 mandatory = &stereo_mandatory_modes[i]; 3006 new_mode = drm_mode_duplicate(dev, mode); 3007 if (!new_mode) 3008 continue; 3009 3010 new_mode->flags |= mandatory->flags; 3011 list_add_tail(&new_mode->head, &stereo_modes); 3012 modes++; 3013 } 3014 } 3015 3016 list_splice_tail(&stereo_modes, &connector->probed_modes); 3017 3018 return modes; 3019 } 3020 3021 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3022 { 3023 struct drm_device *dev = connector->dev; 3024 struct drm_display_mode *newmode; 3025 3026 if (!drm_valid_hdmi_vic(vic)) { 3027 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3028 return 0; 3029 } 3030 3031 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3032 if (!newmode) 3033 return 0; 3034 3035 drm_mode_probed_add(connector, newmode); 3036 3037 return 1; 3038 } 3039 3040 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3041 const u8 *video_db, u8 video_len, u8 video_index) 3042 { 3043 struct drm_display_mode *newmode; 3044 int modes = 0; 3045 3046 if (structure & (1 << 0)) { 3047 newmode = drm_display_mode_from_vic_index(connector, video_db, 3048 video_len, 3049 video_index); 3050 if (newmode) { 3051 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3052 drm_mode_probed_add(connector, newmode); 3053 modes++; 3054 } 3055 } 3056 if (structure & (1 << 6)) { 3057 newmode = drm_display_mode_from_vic_index(connector, video_db, 3058 video_len, 3059 video_index); 3060 if (newmode) { 3061 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3062 drm_mode_probed_add(connector, newmode); 3063 modes++; 3064 } 3065 } 3066 if (structure & (1 << 8)) { 3067 newmode = drm_display_mode_from_vic_index(connector, video_db, 3068 video_len, 3069 video_index); 3070 if (newmode) { 3071 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3072 drm_mode_probed_add(connector, newmode); 3073 modes++; 3074 } 3075 } 3076 3077 return modes; 3078 } 3079 3080 /* 3081 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3082 * @connector: connector corresponding to the HDMI sink 3083 * @db: start of the CEA vendor specific block 3084 * @len: length of the CEA block payload, ie. one can access up to db[len] 3085 * 3086 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3087 * also adds the stereo 3d modes when applicable. 3088 */ 3089 static int 3090 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3091 const u8 *video_db, u8 video_len) 3092 { 3093 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3094 u8 vic_len, hdmi_3d_len = 0; 3095 u16 mask; 3096 u16 structure_all; 3097 3098 if (len < 8) 3099 goto out; 3100 3101 /* no HDMI_Video_Present */ 3102 if (!(db[8] & (1 << 5))) 3103 goto out; 3104 3105 /* Latency_Fields_Present */ 3106 if (db[8] & (1 << 7)) 3107 offset += 2; 3108 3109 /* I_Latency_Fields_Present */ 3110 if (db[8] & (1 << 6)) 3111 offset += 2; 3112 3113 /* the declared length is not long enough for the 2 first bytes 3114 * of additional video format capabilities */ 3115 if (len < (8 + offset + 2)) 3116 goto out; 3117 3118 /* 3D_Present */ 3119 offset++; 3120 if (db[8 + offset] & (1 << 7)) { 3121 modes += add_hdmi_mandatory_stereo_modes(connector); 3122 3123 /* 3D_Multi_present */ 3124 multi_present = (db[8 + offset] & 0x60) >> 5; 3125 } 3126 3127 offset++; 3128 vic_len = db[8 + offset] >> 5; 3129 hdmi_3d_len = db[8 + offset] & 0x1f; 3130 3131 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3132 u8 vic; 3133 3134 vic = db[9 + offset + i]; 3135 modes += add_hdmi_mode(connector, vic); 3136 } 3137 offset += 1 + vic_len; 3138 3139 if (multi_present == 1) 3140 multi_len = 2; 3141 else if (multi_present == 2) 3142 multi_len = 4; 3143 else 3144 multi_len = 0; 3145 3146 if (len < (8 + offset + hdmi_3d_len - 1)) 3147 goto out; 3148 3149 if (hdmi_3d_len < multi_len) 3150 goto out; 3151 3152 if (multi_present == 1 || multi_present == 2) { 3153 /* 3D_Structure_ALL */ 3154 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3155 3156 /* check if 3D_MASK is present */ 3157 if (multi_present == 2) 3158 mask = (db[10 + offset] << 8) | db[11 + offset]; 3159 else 3160 mask = 0xffff; 3161 3162 for (i = 0; i < 16; i++) { 3163 if (mask & (1 << i)) 3164 modes += add_3d_struct_modes(connector, 3165 structure_all, 3166 video_db, 3167 video_len, i); 3168 } 3169 } 3170 3171 offset += multi_len; 3172 3173 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3174 int vic_index; 3175 struct drm_display_mode *newmode = NULL; 3176 unsigned int newflag = 0; 3177 bool detail_present; 3178 3179 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3180 3181 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3182 break; 3183 3184 /* 2D_VIC_order_X */ 3185 vic_index = db[8 + offset + i] >> 4; 3186 3187 /* 3D_Structure_X */ 3188 switch (db[8 + offset + i] & 0x0f) { 3189 case 0: 3190 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3191 break; 3192 case 6: 3193 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3194 break; 3195 case 8: 3196 /* 3D_Detail_X */ 3197 if ((db[9 + offset + i] >> 4) == 1) 3198 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3199 break; 3200 } 3201 3202 if (newflag != 0) { 3203 newmode = drm_display_mode_from_vic_index(connector, 3204 video_db, 3205 video_len, 3206 vic_index); 3207 3208 if (newmode) { 3209 newmode->flags |= newflag; 3210 drm_mode_probed_add(connector, newmode); 3211 modes++; 3212 } 3213 } 3214 3215 if (detail_present) 3216 i++; 3217 } 3218 3219 out: 3220 return modes; 3221 } 3222 3223 static int 3224 cea_db_payload_len(const u8 *db) 3225 { 3226 return db[0] & 0x1f; 3227 } 3228 3229 static int 3230 cea_db_tag(const u8 *db) 3231 { 3232 return db[0] >> 5; 3233 } 3234 3235 static int 3236 cea_revision(const u8 *cea) 3237 { 3238 return cea[1]; 3239 } 3240 3241 static int 3242 cea_db_offsets(const u8 *cea, int *start, int *end) 3243 { 3244 /* Data block offset in CEA extension block */ 3245 *start = 4; 3246 *end = cea[2]; 3247 if (*end == 0) 3248 *end = 127; 3249 if (*end < 4 || *end > 127) 3250 return -ERANGE; 3251 return 0; 3252 } 3253 3254 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3255 { 3256 int hdmi_id; 3257 3258 if (cea_db_tag(db) != VENDOR_BLOCK) 3259 return false; 3260 3261 if (cea_db_payload_len(db) < 5) 3262 return false; 3263 3264 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3265 3266 return hdmi_id == HDMI_IEEE_OUI; 3267 } 3268 3269 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 3270 { 3271 unsigned int oui; 3272 3273 if (cea_db_tag(db) != VENDOR_BLOCK) 3274 return false; 3275 3276 if (cea_db_payload_len(db) < 7) 3277 return false; 3278 3279 oui = db[3] << 16 | db[2] << 8 | db[1]; 3280 3281 return oui == HDMI_FORUM_IEEE_OUI; 3282 } 3283 3284 #define for_each_cea_db(cea, i, start, end) \ 3285 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3286 3287 static int 3288 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3289 { 3290 const u8 *cea = drm_find_cea_extension(edid); 3291 const u8 *db, *hdmi = NULL, *video = NULL; 3292 u8 dbl, hdmi_len, video_len = 0; 3293 int modes = 0; 3294 3295 if (cea && cea_revision(cea) >= 3) { 3296 int i, start, end; 3297 3298 if (cea_db_offsets(cea, &start, &end)) 3299 return 0; 3300 3301 for_each_cea_db(cea, i, start, end) { 3302 db = &cea[i]; 3303 dbl = cea_db_payload_len(db); 3304 3305 if (cea_db_tag(db) == VIDEO_BLOCK) { 3306 video = db + 1; 3307 video_len = dbl; 3308 modes += do_cea_modes(connector, video, dbl); 3309 } 3310 else if (cea_db_is_hdmi_vsdb(db)) { 3311 hdmi = db; 3312 hdmi_len = dbl; 3313 } 3314 } 3315 } 3316 3317 /* 3318 * We parse the HDMI VSDB after having added the cea modes as we will 3319 * be patching their flags when the sink supports stereo 3D. 3320 */ 3321 if (hdmi) 3322 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3323 video_len); 3324 3325 return modes; 3326 } 3327 3328 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3329 { 3330 const struct drm_display_mode *cea_mode; 3331 int clock1, clock2, clock; 3332 u8 vic; 3333 const char *type; 3334 3335 /* 3336 * allow 5kHz clock difference either way to account for 3337 * the 10kHz clock resolution limit of detailed timings. 3338 */ 3339 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3340 if (drm_valid_cea_vic(vic)) { 3341 type = "CEA"; 3342 cea_mode = &edid_cea_modes[vic]; 3343 clock1 = cea_mode->clock; 3344 clock2 = cea_mode_alternate_clock(cea_mode); 3345 } else { 3346 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3347 if (drm_valid_hdmi_vic(vic)) { 3348 type = "HDMI"; 3349 cea_mode = &edid_4k_modes[vic]; 3350 clock1 = cea_mode->clock; 3351 clock2 = hdmi_mode_alternate_clock(cea_mode); 3352 } else { 3353 return; 3354 } 3355 } 3356 3357 /* pick whichever is closest */ 3358 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3359 clock = clock1; 3360 else 3361 clock = clock2; 3362 3363 if (mode->clock == clock) 3364 return; 3365 3366 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3367 type, vic, mode->clock, clock); 3368 mode->clock = clock; 3369 } 3370 3371 static void 3372 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 3373 { 3374 u8 len = cea_db_payload_len(db); 3375 3376 if (len >= 6) 3377 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3378 if (len >= 8) { 3379 connector->latency_present[0] = db[8] >> 7; 3380 connector->latency_present[1] = (db[8] >> 6) & 1; 3381 } 3382 if (len >= 9) 3383 connector->video_latency[0] = db[9]; 3384 if (len >= 10) 3385 connector->audio_latency[0] = db[10]; 3386 if (len >= 11) 3387 connector->video_latency[1] = db[11]; 3388 if (len >= 12) 3389 connector->audio_latency[1] = db[12]; 3390 3391 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 3392 "video latency %d %d, " 3393 "audio latency %d %d\n", 3394 connector->latency_present[0], 3395 connector->latency_present[1], 3396 connector->video_latency[0], 3397 connector->video_latency[1], 3398 connector->audio_latency[0], 3399 connector->audio_latency[1]); 3400 } 3401 3402 static void 3403 monitor_name(struct detailed_timing *t, void *data) 3404 { 3405 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3406 *(u8 **)data = t->data.other_data.data.str.str; 3407 } 3408 3409 static int get_monitor_name(struct edid *edid, char name[13]) 3410 { 3411 char *edid_name = NULL; 3412 int mnl; 3413 3414 if (!edid || !name) 3415 return 0; 3416 3417 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3418 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3419 if (edid_name[mnl] == 0x0a) 3420 break; 3421 3422 name[mnl] = edid_name[mnl]; 3423 } 3424 3425 return mnl; 3426 } 3427 3428 /** 3429 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3430 * @edid: monitor EDID information 3431 * @name: pointer to a character array to hold the name of the monitor 3432 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3433 * 3434 */ 3435 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3436 { 3437 int name_length; 3438 char buf[13]; 3439 3440 if (bufsize <= 0) 3441 return; 3442 3443 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3444 memcpy(name, buf, name_length); 3445 name[name_length] = '\0'; 3446 } 3447 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3448 3449 /** 3450 * drm_edid_to_eld - build ELD from EDID 3451 * @connector: connector corresponding to the HDMI/DP sink 3452 * @edid: EDID to parse 3453 * 3454 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3455 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3456 * fill in. 3457 */ 3458 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3459 { 3460 uint8_t *eld = connector->eld; 3461 u8 *cea; 3462 u8 *db; 3463 int total_sad_count = 0; 3464 int mnl; 3465 int dbl; 3466 3467 memset(eld, 0, sizeof(connector->eld)); 3468 3469 connector->latency_present[0] = false; 3470 connector->latency_present[1] = false; 3471 connector->video_latency[0] = 0; 3472 connector->audio_latency[0] = 0; 3473 connector->video_latency[1] = 0; 3474 connector->audio_latency[1] = 0; 3475 3476 if (!edid) 3477 return; 3478 3479 cea = drm_find_cea_extension(edid); 3480 if (!cea) { 3481 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3482 return; 3483 } 3484 3485 mnl = get_monitor_name(edid, eld + 20); 3486 3487 eld[4] = (cea[1] << 5) | mnl; 3488 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3489 3490 eld[0] = 2 << 3; /* ELD version: 2 */ 3491 3492 eld[16] = edid->mfg_id[0]; 3493 eld[17] = edid->mfg_id[1]; 3494 eld[18] = edid->prod_code[0]; 3495 eld[19] = edid->prod_code[1]; 3496 3497 if (cea_revision(cea) >= 3) { 3498 int i, start, end; 3499 3500 if (cea_db_offsets(cea, &start, &end)) { 3501 start = 0; 3502 end = 0; 3503 } 3504 3505 for_each_cea_db(cea, i, start, end) { 3506 db = &cea[i]; 3507 dbl = cea_db_payload_len(db); 3508 3509 switch (cea_db_tag(db)) { 3510 int sad_count; 3511 3512 case AUDIO_BLOCK: 3513 /* Audio Data Block, contains SADs */ 3514 sad_count = min(dbl / 3, 15 - total_sad_count); 3515 if (sad_count >= 1) 3516 memcpy(eld + 20 + mnl + total_sad_count * 3, 3517 &db[1], sad_count * 3); 3518 total_sad_count += sad_count; 3519 break; 3520 case SPEAKER_BLOCK: 3521 /* Speaker Allocation Data Block */ 3522 if (dbl >= 1) 3523 eld[7] = db[1]; 3524 break; 3525 case VENDOR_BLOCK: 3526 /* HDMI Vendor-Specific Data Block */ 3527 if (cea_db_is_hdmi_vsdb(db)) 3528 drm_parse_hdmi_vsdb_audio(connector, db); 3529 break; 3530 default: 3531 break; 3532 } 3533 } 3534 } 3535 eld[5] |= total_sad_count << 4; 3536 3537 eld[DRM_ELD_BASELINE_ELD_LEN] = 3538 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3539 3540 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3541 drm_eld_size(eld), total_sad_count); 3542 } 3543 EXPORT_SYMBOL(drm_edid_to_eld); 3544 3545 /** 3546 * drm_edid_to_sad - extracts SADs from EDID 3547 * @edid: EDID to parse 3548 * @sads: pointer that will be set to the extracted SADs 3549 * 3550 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3551 * 3552 * Note: The returned pointer needs to be freed using kfree(). 3553 * 3554 * Return: The number of found SADs or negative number on error. 3555 */ 3556 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3557 { 3558 int count = 0; 3559 int i, start, end, dbl; 3560 u8 *cea; 3561 3562 cea = drm_find_cea_extension(edid); 3563 if (!cea) { 3564 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3565 return -ENOENT; 3566 } 3567 3568 if (cea_revision(cea) < 3) { 3569 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3570 return -ENOTSUPP; 3571 } 3572 3573 if (cea_db_offsets(cea, &start, &end)) { 3574 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3575 return -EPROTO; 3576 } 3577 3578 for_each_cea_db(cea, i, start, end) { 3579 u8 *db = &cea[i]; 3580 3581 if (cea_db_tag(db) == AUDIO_BLOCK) { 3582 int j; 3583 dbl = cea_db_payload_len(db); 3584 3585 count = dbl / 3; /* SAD is 3B */ 3586 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3587 if (!*sads) 3588 return -ENOMEM; 3589 for (j = 0; j < count; j++) { 3590 u8 *sad = &db[1 + j * 3]; 3591 3592 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3593 (*sads)[j].channels = sad[0] & 0x7; 3594 (*sads)[j].freq = sad[1] & 0x7F; 3595 (*sads)[j].byte2 = sad[2]; 3596 } 3597 break; 3598 } 3599 } 3600 3601 return count; 3602 } 3603 EXPORT_SYMBOL(drm_edid_to_sad); 3604 3605 /** 3606 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3607 * @edid: EDID to parse 3608 * @sadb: pointer to the speaker block 3609 * 3610 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3611 * 3612 * Note: The returned pointer needs to be freed using kfree(). 3613 * 3614 * Return: The number of found Speaker Allocation Blocks or negative number on 3615 * error. 3616 */ 3617 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3618 { 3619 int count = 0; 3620 int i, start, end, dbl; 3621 const u8 *cea; 3622 3623 cea = drm_find_cea_extension(edid); 3624 if (!cea) { 3625 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3626 return -ENOENT; 3627 } 3628 3629 if (cea_revision(cea) < 3) { 3630 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3631 return -ENOTSUPP; 3632 } 3633 3634 if (cea_db_offsets(cea, &start, &end)) { 3635 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3636 return -EPROTO; 3637 } 3638 3639 for_each_cea_db(cea, i, start, end) { 3640 const u8 *db = &cea[i]; 3641 3642 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3643 dbl = cea_db_payload_len(db); 3644 3645 /* Speaker Allocation Data Block */ 3646 if (dbl == 3) { 3647 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3648 if (!*sadb) 3649 return -ENOMEM; 3650 count = dbl; 3651 break; 3652 } 3653 } 3654 } 3655 3656 return count; 3657 } 3658 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3659 3660 /** 3661 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3662 * @connector: connector associated with the HDMI/DP sink 3663 * @mode: the display mode 3664 * 3665 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3666 * the sink doesn't support audio or video. 3667 */ 3668 int drm_av_sync_delay(struct drm_connector *connector, 3669 const struct drm_display_mode *mode) 3670 { 3671 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3672 int a, v; 3673 3674 if (!connector->latency_present[0]) 3675 return 0; 3676 if (!connector->latency_present[1]) 3677 i = 0; 3678 3679 a = connector->audio_latency[i]; 3680 v = connector->video_latency[i]; 3681 3682 /* 3683 * HDMI/DP sink doesn't support audio or video? 3684 */ 3685 if (a == 255 || v == 255) 3686 return 0; 3687 3688 /* 3689 * Convert raw EDID values to millisecond. 3690 * Treat unknown latency as 0ms. 3691 */ 3692 if (a) 3693 a = min(2 * (a - 1), 500); 3694 if (v) 3695 v = min(2 * (v - 1), 500); 3696 3697 return max(v - a, 0); 3698 } 3699 EXPORT_SYMBOL(drm_av_sync_delay); 3700 3701 /** 3702 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3703 * @edid: monitor EDID information 3704 * 3705 * Parse the CEA extension according to CEA-861-B. 3706 * 3707 * Return: True if the monitor is HDMI, false if not or unknown. 3708 */ 3709 bool drm_detect_hdmi_monitor(struct edid *edid) 3710 { 3711 u8 *edid_ext; 3712 int i; 3713 int start_offset, end_offset; 3714 3715 edid_ext = drm_find_cea_extension(edid); 3716 if (!edid_ext) 3717 return false; 3718 3719 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3720 return false; 3721 3722 /* 3723 * Because HDMI identifier is in Vendor Specific Block, 3724 * search it from all data blocks of CEA extension. 3725 */ 3726 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3727 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3728 return true; 3729 } 3730 3731 return false; 3732 } 3733 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3734 3735 /** 3736 * drm_detect_monitor_audio - check monitor audio capability 3737 * @edid: EDID block to scan 3738 * 3739 * Monitor should have CEA extension block. 3740 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3741 * audio' only. If there is any audio extension block and supported 3742 * audio format, assume at least 'basic audio' support, even if 'basic 3743 * audio' is not defined in EDID. 3744 * 3745 * Return: True if the monitor supports audio, false otherwise. 3746 */ 3747 bool drm_detect_monitor_audio(struct edid *edid) 3748 { 3749 u8 *edid_ext; 3750 int i, j; 3751 bool has_audio = false; 3752 int start_offset, end_offset; 3753 3754 edid_ext = drm_find_cea_extension(edid); 3755 if (!edid_ext) 3756 goto end; 3757 3758 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3759 3760 if (has_audio) { 3761 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3762 goto end; 3763 } 3764 3765 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3766 goto end; 3767 3768 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3769 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3770 has_audio = true; 3771 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3772 DRM_DEBUG_KMS("CEA audio format %d\n", 3773 (edid_ext[i + j] >> 3) & 0xf); 3774 goto end; 3775 } 3776 } 3777 end: 3778 return has_audio; 3779 } 3780 EXPORT_SYMBOL(drm_detect_monitor_audio); 3781 3782 /** 3783 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3784 * @edid: EDID block to scan 3785 * 3786 * Check whether the monitor reports the RGB quantization range selection 3787 * as supported. The AVI infoframe can then be used to inform the monitor 3788 * which quantization range (full or limited) is used. 3789 * 3790 * Return: True if the RGB quantization range is selectable, false otherwise. 3791 */ 3792 bool drm_rgb_quant_range_selectable(struct edid *edid) 3793 { 3794 u8 *edid_ext; 3795 int i, start, end; 3796 3797 edid_ext = drm_find_cea_extension(edid); 3798 if (!edid_ext) 3799 return false; 3800 3801 if (cea_db_offsets(edid_ext, &start, &end)) 3802 return false; 3803 3804 for_each_cea_db(edid_ext, i, start, end) { 3805 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3806 cea_db_payload_len(&edid_ext[i]) == 2) { 3807 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3808 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3809 } 3810 } 3811 3812 return false; 3813 } 3814 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3815 3816 /** 3817 * drm_default_rgb_quant_range - default RGB quantization range 3818 * @mode: display mode 3819 * 3820 * Determine the default RGB quantization range for the mode, 3821 * as specified in CEA-861. 3822 * 3823 * Return: The default RGB quantization range for the mode 3824 */ 3825 enum hdmi_quantization_range 3826 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 3827 { 3828 /* All CEA modes other than VIC 1 use limited quantization range. */ 3829 return drm_match_cea_mode(mode) > 1 ? 3830 HDMI_QUANTIZATION_RANGE_LIMITED : 3831 HDMI_QUANTIZATION_RANGE_FULL; 3832 } 3833 EXPORT_SYMBOL(drm_default_rgb_quant_range); 3834 3835 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 3836 const u8 *hf_vsdb) 3837 { 3838 struct drm_display_info *display = &connector->display_info; 3839 struct drm_hdmi_info *hdmi = &display->hdmi; 3840 3841 if (hf_vsdb[6] & 0x80) { 3842 hdmi->scdc.supported = true; 3843 if (hf_vsdb[6] & 0x40) 3844 hdmi->scdc.read_request = true; 3845 } 3846 3847 /* 3848 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 3849 * And as per the spec, three factors confirm this: 3850 * * Availability of a HF-VSDB block in EDID (check) 3851 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 3852 * * SCDC support available (let's check) 3853 * Lets check it out. 3854 */ 3855 3856 if (hf_vsdb[5]) { 3857 /* max clock is 5000 KHz times block value */ 3858 u32 max_tmds_clock = hf_vsdb[5] * 5000; 3859 struct drm_scdc *scdc = &hdmi->scdc; 3860 3861 if (max_tmds_clock > 340000) { 3862 display->max_tmds_clock = max_tmds_clock; 3863 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 3864 display->max_tmds_clock); 3865 } 3866 3867 if (scdc->supported) { 3868 scdc->scrambling.supported = true; 3869 3870 /* Few sinks support scrambling for cloks < 340M */ 3871 if ((hf_vsdb[6] & 0x8)) 3872 scdc->scrambling.low_rates = true; 3873 } 3874 } 3875 } 3876 3877 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 3878 const u8 *hdmi) 3879 { 3880 struct drm_display_info *info = &connector->display_info; 3881 unsigned int dc_bpc = 0; 3882 3883 /* HDMI supports at least 8 bpc */ 3884 info->bpc = 8; 3885 3886 if (cea_db_payload_len(hdmi) < 6) 3887 return; 3888 3889 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3890 dc_bpc = 10; 3891 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3892 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3893 connector->name); 3894 } 3895 3896 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3897 dc_bpc = 12; 3898 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3899 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3900 connector->name); 3901 } 3902 3903 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3904 dc_bpc = 16; 3905 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3906 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3907 connector->name); 3908 } 3909 3910 if (dc_bpc == 0) { 3911 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3912 connector->name); 3913 return; 3914 } 3915 3916 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3917 connector->name, dc_bpc); 3918 info->bpc = dc_bpc; 3919 3920 /* 3921 * Deep color support mandates RGB444 support for all video 3922 * modes and forbids YCRCB422 support for all video modes per 3923 * HDMI 1.3 spec. 3924 */ 3925 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3926 3927 /* YCRCB444 is optional according to spec. */ 3928 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3929 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3930 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3931 connector->name); 3932 } 3933 3934 /* 3935 * Spec says that if any deep color mode is supported at all, 3936 * then deep color 36 bit must be supported. 3937 */ 3938 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3939 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3940 connector->name); 3941 } 3942 } 3943 3944 static void 3945 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 3946 { 3947 struct drm_display_info *info = &connector->display_info; 3948 u8 len = cea_db_payload_len(db); 3949 3950 if (len >= 6) 3951 info->dvi_dual = db[6] & 1; 3952 if (len >= 7) 3953 info->max_tmds_clock = db[7] * 5000; 3954 3955 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3956 "max TMDS clock %d kHz\n", 3957 info->dvi_dual, 3958 info->max_tmds_clock); 3959 3960 drm_parse_hdmi_deep_color_info(connector, db); 3961 } 3962 3963 static void drm_parse_cea_ext(struct drm_connector *connector, 3964 struct edid *edid) 3965 { 3966 struct drm_display_info *info = &connector->display_info; 3967 const u8 *edid_ext; 3968 int i, start, end; 3969 3970 edid_ext = drm_find_cea_extension(edid); 3971 if (!edid_ext) 3972 return; 3973 3974 info->cea_rev = edid_ext[1]; 3975 3976 /* The existence of a CEA block should imply RGB support */ 3977 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3978 if (edid_ext[3] & EDID_CEA_YCRCB444) 3979 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3980 if (edid_ext[3] & EDID_CEA_YCRCB422) 3981 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3982 3983 if (cea_db_offsets(edid_ext, &start, &end)) 3984 return; 3985 3986 for_each_cea_db(edid_ext, i, start, end) { 3987 const u8 *db = &edid_ext[i]; 3988 3989 if (cea_db_is_hdmi_vsdb(db)) 3990 drm_parse_hdmi_vsdb_video(connector, db); 3991 if (cea_db_is_hdmi_forum_vsdb(db)) 3992 drm_parse_hdmi_forum_vsdb(connector, db); 3993 } 3994 } 3995 3996 static void drm_add_display_info(struct drm_connector *connector, 3997 struct edid *edid) 3998 { 3999 struct drm_display_info *info = &connector->display_info; 4000 4001 info->width_mm = edid->width_cm * 10; 4002 info->height_mm = edid->height_cm * 10; 4003 4004 /* driver figures it out in this case */ 4005 info->bpc = 0; 4006 info->color_formats = 0; 4007 info->cea_rev = 0; 4008 info->max_tmds_clock = 0; 4009 info->dvi_dual = false; 4010 4011 if (edid->revision < 3) 4012 return; 4013 4014 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4015 return; 4016 4017 drm_parse_cea_ext(connector, edid); 4018 4019 /* 4020 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4021 * 4022 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4023 * tells us to assume 8 bpc color depth if the EDID doesn't have 4024 * extensions which tell otherwise. 4025 */ 4026 if ((info->bpc == 0) && (edid->revision < 4) && 4027 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 4028 info->bpc = 8; 4029 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4030 connector->name, info->bpc); 4031 } 4032 4033 /* Only defined for 1.4 with digital displays */ 4034 if (edid->revision < 4) 4035 return; 4036 4037 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4038 case DRM_EDID_DIGITAL_DEPTH_6: 4039 info->bpc = 6; 4040 break; 4041 case DRM_EDID_DIGITAL_DEPTH_8: 4042 info->bpc = 8; 4043 break; 4044 case DRM_EDID_DIGITAL_DEPTH_10: 4045 info->bpc = 10; 4046 break; 4047 case DRM_EDID_DIGITAL_DEPTH_12: 4048 info->bpc = 12; 4049 break; 4050 case DRM_EDID_DIGITAL_DEPTH_14: 4051 info->bpc = 14; 4052 break; 4053 case DRM_EDID_DIGITAL_DEPTH_16: 4054 info->bpc = 16; 4055 break; 4056 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4057 default: 4058 info->bpc = 0; 4059 break; 4060 } 4061 4062 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4063 connector->name, info->bpc); 4064 4065 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4066 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4067 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4068 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4069 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4070 } 4071 4072 static int validate_displayid(u8 *displayid, int length, int idx) 4073 { 4074 int i; 4075 u8 csum = 0; 4076 struct displayid_hdr *base; 4077 4078 base = (struct displayid_hdr *)&displayid[idx]; 4079 4080 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4081 base->rev, base->bytes, base->prod_id, base->ext_count); 4082 4083 if (base->bytes + 5 > length - idx) 4084 return -EINVAL; 4085 for (i = idx; i <= base->bytes + 5; i++) { 4086 csum += displayid[i]; 4087 } 4088 if (csum) { 4089 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 4090 return -EINVAL; 4091 } 4092 return 0; 4093 } 4094 4095 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 4096 struct displayid_detailed_timings_1 *timings) 4097 { 4098 struct drm_display_mode *mode; 4099 unsigned pixel_clock = (timings->pixel_clock[0] | 4100 (timings->pixel_clock[1] << 8) | 4101 (timings->pixel_clock[2] << 16)); 4102 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4103 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4104 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 4105 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4106 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 4107 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4108 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 4109 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4110 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4111 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4112 mode = drm_mode_create(dev); 4113 if (!mode) 4114 return NULL; 4115 4116 mode->clock = pixel_clock * 10; 4117 mode->hdisplay = hactive; 4118 mode->hsync_start = mode->hdisplay + hsync; 4119 mode->hsync_end = mode->hsync_start + hsync_width; 4120 mode->htotal = mode->hdisplay + hblank; 4121 4122 mode->vdisplay = vactive; 4123 mode->vsync_start = mode->vdisplay + vsync; 4124 mode->vsync_end = mode->vsync_start + vsync_width; 4125 mode->vtotal = mode->vdisplay + vblank; 4126 4127 mode->flags = 0; 4128 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4129 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4130 mode->type = DRM_MODE_TYPE_DRIVER; 4131 4132 if (timings->flags & 0x80) 4133 mode->type |= DRM_MODE_TYPE_PREFERRED; 4134 mode->vrefresh = drm_mode_vrefresh(mode); 4135 drm_mode_set_name(mode); 4136 4137 return mode; 4138 } 4139 4140 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 4141 struct displayid_block *block) 4142 { 4143 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 4144 int i; 4145 int num_timings; 4146 struct drm_display_mode *newmode; 4147 int num_modes = 0; 4148 /* blocks must be multiple of 20 bytes length */ 4149 if (block->num_bytes % 20) 4150 return 0; 4151 4152 num_timings = block->num_bytes / 20; 4153 for (i = 0; i < num_timings; i++) { 4154 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4155 4156 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4157 if (!newmode) 4158 continue; 4159 4160 drm_mode_probed_add(connector, newmode); 4161 num_modes++; 4162 } 4163 return num_modes; 4164 } 4165 4166 static int add_displayid_detailed_modes(struct drm_connector *connector, 4167 struct edid *edid) 4168 { 4169 u8 *displayid; 4170 int ret; 4171 int idx = 1; 4172 int length = EDID_LENGTH; 4173 struct displayid_block *block; 4174 int num_modes = 0; 4175 4176 displayid = drm_find_displayid_extension(edid); 4177 if (!displayid) 4178 return 0; 4179 4180 ret = validate_displayid(displayid, length, idx); 4181 if (ret) 4182 return 0; 4183 4184 idx += sizeof(struct displayid_hdr); 4185 while (block = (struct displayid_block *)&displayid[idx], 4186 idx + sizeof(struct displayid_block) <= length && 4187 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4188 block->num_bytes > 0) { 4189 idx += block->num_bytes + sizeof(struct displayid_block); 4190 switch (block->tag) { 4191 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4192 num_modes += add_displayid_detailed_1_modes(connector, block); 4193 break; 4194 } 4195 } 4196 return num_modes; 4197 } 4198 4199 /** 4200 * drm_add_edid_modes - add modes from EDID data, if available 4201 * @connector: connector we're probing 4202 * @edid: EDID data 4203 * 4204 * Add the specified modes to the connector's mode list. Also fills out the 4205 * &drm_display_info structure in @connector with any information which can be 4206 * derived from the edid. 4207 * 4208 * Return: The number of modes added or 0 if we couldn't find any. 4209 */ 4210 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4211 { 4212 int num_modes = 0; 4213 u32 quirks; 4214 4215 if (edid == NULL) { 4216 return 0; 4217 } 4218 if (!drm_edid_is_valid(edid)) { 4219 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4220 connector->name); 4221 return 0; 4222 } 4223 4224 quirks = edid_get_quirks(edid); 4225 4226 /* 4227 * EDID spec says modes should be preferred in this order: 4228 * - preferred detailed mode 4229 * - other detailed modes from base block 4230 * - detailed modes from extension blocks 4231 * - CVT 3-byte code modes 4232 * - standard timing codes 4233 * - established timing codes 4234 * - modes inferred from GTF or CVT range information 4235 * 4236 * We get this pretty much right. 4237 * 4238 * XXX order for additional mode types in extension blocks? 4239 */ 4240 num_modes += add_detailed_modes(connector, edid, quirks); 4241 num_modes += add_cvt_modes(connector, edid); 4242 num_modes += add_standard_modes(connector, edid); 4243 num_modes += add_established_modes(connector, edid); 4244 num_modes += add_cea_modes(connector, edid); 4245 num_modes += add_alternate_cea_modes(connector, edid); 4246 num_modes += add_displayid_detailed_modes(connector, edid); 4247 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4248 num_modes += add_inferred_modes(connector, edid); 4249 4250 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4251 edid_fixup_preferred(connector, quirks); 4252 4253 drm_add_display_info(connector, edid); 4254 4255 if (quirks & EDID_QUIRK_FORCE_6BPC) 4256 connector->display_info.bpc = 6; 4257 4258 if (quirks & EDID_QUIRK_FORCE_8BPC) 4259 connector->display_info.bpc = 8; 4260 4261 if (quirks & EDID_QUIRK_FORCE_10BPC) 4262 connector->display_info.bpc = 10; 4263 4264 if (quirks & EDID_QUIRK_FORCE_10BPC) 4265 connector->display_info.bpc = 10; 4266 4267 if (quirks & EDID_QUIRK_FORCE_12BPC) 4268 connector->display_info.bpc = 12; 4269 4270 return num_modes; 4271 } 4272 EXPORT_SYMBOL(drm_add_edid_modes); 4273 4274 /** 4275 * drm_add_modes_noedid - add modes for the connectors without EDID 4276 * @connector: connector we're probing 4277 * @hdisplay: the horizontal display limit 4278 * @vdisplay: the vertical display limit 4279 * 4280 * Add the specified modes to the connector's mode list. Only when the 4281 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4282 * 4283 * Return: The number of modes added or 0 if we couldn't find any. 4284 */ 4285 int drm_add_modes_noedid(struct drm_connector *connector, 4286 int hdisplay, int vdisplay) 4287 { 4288 int i, count, num_modes = 0; 4289 struct drm_display_mode *mode; 4290 struct drm_device *dev = connector->dev; 4291 4292 count = ARRAY_SIZE(drm_dmt_modes); 4293 if (hdisplay < 0) 4294 hdisplay = 0; 4295 if (vdisplay < 0) 4296 vdisplay = 0; 4297 4298 for (i = 0; i < count; i++) { 4299 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4300 if (hdisplay && vdisplay) { 4301 /* 4302 * Only when two are valid, they will be used to check 4303 * whether the mode should be added to the mode list of 4304 * the connector. 4305 */ 4306 if (ptr->hdisplay > hdisplay || 4307 ptr->vdisplay > vdisplay) 4308 continue; 4309 } 4310 if (drm_mode_vrefresh(ptr) > 61) 4311 continue; 4312 mode = drm_mode_duplicate(dev, ptr); 4313 if (mode) { 4314 drm_mode_probed_add(connector, mode); 4315 num_modes++; 4316 } 4317 } 4318 return num_modes; 4319 } 4320 EXPORT_SYMBOL(drm_add_modes_noedid); 4321 4322 /** 4323 * drm_set_preferred_mode - Sets the preferred mode of a connector 4324 * @connector: connector whose mode list should be processed 4325 * @hpref: horizontal resolution of preferred mode 4326 * @vpref: vertical resolution of preferred mode 4327 * 4328 * Marks a mode as preferred if it matches the resolution specified by @hpref 4329 * and @vpref. 4330 */ 4331 void drm_set_preferred_mode(struct drm_connector *connector, 4332 int hpref, int vpref) 4333 { 4334 struct drm_display_mode *mode; 4335 4336 list_for_each_entry(mode, &connector->probed_modes, head) { 4337 if (mode->hdisplay == hpref && 4338 mode->vdisplay == vpref) 4339 mode->type |= DRM_MODE_TYPE_PREFERRED; 4340 } 4341 } 4342 EXPORT_SYMBOL(drm_set_preferred_mode); 4343 4344 /** 4345 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4346 * data from a DRM display mode 4347 * @frame: HDMI AVI infoframe 4348 * @mode: DRM display mode 4349 * 4350 * Return: 0 on success or a negative error code on failure. 4351 */ 4352 int 4353 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4354 const struct drm_display_mode *mode) 4355 { 4356 int err; 4357 4358 if (!frame || !mode) 4359 return -EINVAL; 4360 4361 err = hdmi_avi_infoframe_init(frame); 4362 if (err < 0) 4363 return err; 4364 4365 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4366 frame->pixel_repeat = 1; 4367 4368 frame->video_code = drm_match_cea_mode(mode); 4369 4370 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4371 4372 /* 4373 * Populate picture aspect ratio from either 4374 * user input (if specified) or from the CEA mode list. 4375 */ 4376 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4377 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4378 frame->picture_aspect = mode->picture_aspect_ratio; 4379 else if (frame->video_code > 0) 4380 frame->picture_aspect = drm_get_cea_aspect_ratio( 4381 frame->video_code); 4382 4383 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4384 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4385 4386 return 0; 4387 } 4388 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4389 4390 /** 4391 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 4392 * quantization range information 4393 * @frame: HDMI AVI infoframe 4394 * @mode: DRM display mode 4395 * @rgb_quant_range: RGB quantization range (Q) 4396 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 4397 */ 4398 void 4399 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 4400 const struct drm_display_mode *mode, 4401 enum hdmi_quantization_range rgb_quant_range, 4402 bool rgb_quant_range_selectable) 4403 { 4404 /* 4405 * CEA-861: 4406 * "A Source shall not send a non-zero Q value that does not correspond 4407 * to the default RGB Quantization Range for the transmitted Picture 4408 * unless the Sink indicates support for the Q bit in a Video 4409 * Capabilities Data Block." 4410 * 4411 * HDMI 2.0 recommends sending non-zero Q when it does match the 4412 * default RGB quantization range for the mode, even when QS=0. 4413 */ 4414 if (rgb_quant_range_selectable || 4415 rgb_quant_range == drm_default_rgb_quant_range(mode)) 4416 frame->quantization_range = rgb_quant_range; 4417 else 4418 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 4419 4420 /* 4421 * CEA-861-F: 4422 * "When transmitting any RGB colorimetry, the Source should set the 4423 * YQ-field to match the RGB Quantization Range being transmitted 4424 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 4425 * set YQ=1) and the Sink shall ignore the YQ-field." 4426 */ 4427 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 4428 frame->ycc_quantization_range = 4429 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 4430 else 4431 frame->ycc_quantization_range = 4432 HDMI_YCC_QUANTIZATION_RANGE_FULL; 4433 } 4434 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 4435 4436 static enum hdmi_3d_structure 4437 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4438 { 4439 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4440 4441 switch (layout) { 4442 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4443 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4444 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4445 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4446 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4447 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4448 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4449 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4450 case DRM_MODE_FLAG_3D_L_DEPTH: 4451 return HDMI_3D_STRUCTURE_L_DEPTH; 4452 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4453 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4454 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4455 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4456 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4457 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4458 default: 4459 return HDMI_3D_STRUCTURE_INVALID; 4460 } 4461 } 4462 4463 /** 4464 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4465 * data from a DRM display mode 4466 * @frame: HDMI vendor infoframe 4467 * @mode: DRM display mode 4468 * 4469 * Note that there's is a need to send HDMI vendor infoframes only when using a 4470 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4471 * function will return -EINVAL, error that can be safely ignored. 4472 * 4473 * Return: 0 on success or a negative error code on failure. 4474 */ 4475 int 4476 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4477 const struct drm_display_mode *mode) 4478 { 4479 int err; 4480 u32 s3d_flags; 4481 u8 vic; 4482 4483 if (!frame || !mode) 4484 return -EINVAL; 4485 4486 vic = drm_match_hdmi_mode(mode); 4487 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4488 4489 if (!vic && !s3d_flags) 4490 return -EINVAL; 4491 4492 if (vic && s3d_flags) 4493 return -EINVAL; 4494 4495 err = hdmi_vendor_infoframe_init(frame); 4496 if (err < 0) 4497 return err; 4498 4499 if (vic) 4500 frame->vic = vic; 4501 else 4502 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4503 4504 return 0; 4505 } 4506 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4507 4508 static int drm_parse_tiled_block(struct drm_connector *connector, 4509 struct displayid_block *block) 4510 { 4511 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4512 u16 w, h; 4513 u8 tile_v_loc, tile_h_loc; 4514 u8 num_v_tile, num_h_tile; 4515 struct drm_tile_group *tg; 4516 4517 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4518 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4519 4520 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4521 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4522 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4523 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4524 4525 connector->has_tile = true; 4526 if (tile->tile_cap & 0x80) 4527 connector->tile_is_single_monitor = true; 4528 4529 connector->num_h_tile = num_h_tile + 1; 4530 connector->num_v_tile = num_v_tile + 1; 4531 connector->tile_h_loc = tile_h_loc; 4532 connector->tile_v_loc = tile_v_loc; 4533 connector->tile_h_size = w + 1; 4534 connector->tile_v_size = h + 1; 4535 4536 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4537 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4538 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4539 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4540 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4541 4542 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4543 if (!tg) { 4544 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4545 } 4546 if (!tg) 4547 return -ENOMEM; 4548 4549 if (connector->tile_group != tg) { 4550 /* if we haven't got a pointer, 4551 take the reference, drop ref to old tile group */ 4552 if (connector->tile_group) { 4553 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4554 } 4555 connector->tile_group = tg; 4556 } else 4557 /* if same tile group, then release the ref we just took. */ 4558 drm_mode_put_tile_group(connector->dev, tg); 4559 return 0; 4560 } 4561 4562 static int drm_parse_display_id(struct drm_connector *connector, 4563 u8 *displayid, int length, 4564 bool is_edid_extension) 4565 { 4566 /* if this is an EDID extension the first byte will be 0x70 */ 4567 int idx = 0; 4568 struct displayid_block *block; 4569 int ret; 4570 4571 if (is_edid_extension) 4572 idx = 1; 4573 4574 ret = validate_displayid(displayid, length, idx); 4575 if (ret) 4576 return ret; 4577 4578 idx += sizeof(struct displayid_hdr); 4579 while (block = (struct displayid_block *)&displayid[idx], 4580 idx + sizeof(struct displayid_block) <= length && 4581 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4582 block->num_bytes > 0) { 4583 idx += block->num_bytes + sizeof(struct displayid_block); 4584 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 4585 block->tag, block->rev, block->num_bytes); 4586 4587 switch (block->tag) { 4588 case DATA_BLOCK_TILED_DISPLAY: 4589 ret = drm_parse_tiled_block(connector, block); 4590 if (ret) 4591 return ret; 4592 break; 4593 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4594 /* handled in mode gathering code. */ 4595 break; 4596 default: 4597 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 4598 break; 4599 } 4600 } 4601 return 0; 4602 } 4603 4604 static void drm_get_displayid(struct drm_connector *connector, 4605 struct edid *edid) 4606 { 4607 void *displayid = NULL; 4608 int ret; 4609 connector->has_tile = false; 4610 displayid = drm_find_displayid_extension(edid); 4611 if (!displayid) { 4612 /* drop reference to any tile group we had */ 4613 goto out_drop_ref; 4614 } 4615 4616 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4617 if (ret < 0) 4618 goto out_drop_ref; 4619 if (!connector->has_tile) 4620 goto out_drop_ref; 4621 return; 4622 out_drop_ref: 4623 if (connector->tile_group) { 4624 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4625 connector->tile_group = NULL; 4626 } 4627 return; 4628 } 4629