1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include "opt_drm.h" 31 32 #include <linux/kernel.h> 33 #include <linux/hdmi.h> 34 #include <linux/i2c.h> 35 #include <linux/module.h> 36 #include <linux/vga_switcheroo.h> 37 #include <drm/drmP.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_displayid.h> 40 #include <linux/string.h> 41 42 #define version_greater(edid, maj, min) \ 43 (((edid)->version > (maj)) || \ 44 ((edid)->version == (maj) && (edid)->revision > (min))) 45 46 #define EDID_EST_TIMINGS 16 47 #define EDID_STD_TIMINGS 8 48 #define EDID_DETAILED_TIMINGS 4 49 50 /* 51 * EDID blocks out in the wild have a variety of bugs, try to collect 52 * them here (note that userspace may work around broken monitors first, 53 * but fixes should make their way here so that the kernel "just works" 54 * on as many displays as possible). 55 */ 56 57 /* First detailed mode wrong, use largest 60Hz mode */ 58 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 59 /* Reported 135MHz pixel clock is too high, needs adjustment */ 60 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 61 /* Prefer the largest mode at 75 Hz */ 62 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 63 /* Detail timing is in cm not mm */ 64 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 65 /* Detailed timing descriptors have bogus size values, so just take the 66 * maximum size and use that. 67 */ 68 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 69 /* Monitor forgot to set the first detailed is preferred bit. */ 70 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 71 /* use +hsync +vsync for detailed mode */ 72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 73 /* Force reduced-blanking timings for detailed modes */ 74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 75 /* Force 8bpc */ 76 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 77 /* Force 12bpc */ 78 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 79 /* Force 6bpc */ 80 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 81 82 struct detailed_mode_closure { 83 struct drm_connector *connector; 84 struct edid *edid; 85 bool preferred; 86 u32 quirks; 87 int modes; 88 }; 89 90 #define LEVEL_DMT 0 91 #define LEVEL_GTF 1 92 #define LEVEL_GTF2 2 93 #define LEVEL_CVT 3 94 95 static struct edid_quirk { 96 char vendor[4]; 97 int product_id; 98 u32 quirks; 99 } edid_quirk_list[] = { 100 /* Acer AL1706 */ 101 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 102 /* Acer F51 */ 103 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 104 /* Unknown Acer */ 105 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 106 107 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 108 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 109 110 /* Belinea 10 15 55 */ 111 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 112 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 113 114 /* Envision Peripherals, Inc. EN-7100e */ 115 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 116 /* Envision EN2028 */ 117 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 118 119 /* Funai Electronics PM36B */ 120 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 121 EDID_QUIRK_DETAILED_IN_CM }, 122 123 /* LG Philips LCD LP154W01-A5 */ 124 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 125 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 126 127 /* Philips 107p5 CRT */ 128 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 129 130 /* Proview AY765C */ 131 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 132 133 /* Samsung SyncMaster 205BW. Note: irony */ 134 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 135 /* Samsung SyncMaster 22[5-6]BW */ 136 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 137 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 138 139 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 140 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 141 142 /* ViewSonic VA2026w */ 143 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 144 145 /* Medion MD 30217 PG */ 146 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 147 148 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 149 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 150 }; 151 152 /* 153 * Autogenerated from the DMT spec. 154 * This table is copied from xfree86/modes/xf86EdidModes.c. 155 */ 156 static const struct drm_display_mode drm_dmt_modes[] = { 157 /* 0x01 - 640x350@85Hz */ 158 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 159 736, 832, 0, 350, 382, 385, 445, 0, 160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 161 /* 0x02 - 640x400@85Hz */ 162 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 163 736, 832, 0, 400, 401, 404, 445, 0, 164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 165 /* 0x03 - 720x400@85Hz */ 166 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 167 828, 936, 0, 400, 401, 404, 446, 0, 168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 169 /* 0x04 - 640x480@60Hz */ 170 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 171 752, 800, 0, 480, 490, 492, 525, 0, 172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 173 /* 0x05 - 640x480@72Hz */ 174 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 175 704, 832, 0, 480, 489, 492, 520, 0, 176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 177 /* 0x06 - 640x480@75Hz */ 178 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 179 720, 840, 0, 480, 481, 484, 500, 0, 180 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 181 /* 0x07 - 640x480@85Hz */ 182 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 183 752, 832, 0, 480, 481, 484, 509, 0, 184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 185 /* 0x08 - 800x600@56Hz */ 186 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 187 896, 1024, 0, 600, 601, 603, 625, 0, 188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 189 /* 0x09 - 800x600@60Hz */ 190 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 191 968, 1056, 0, 600, 601, 605, 628, 0, 192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 193 /* 0x0a - 800x600@72Hz */ 194 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 195 976, 1040, 0, 600, 637, 643, 666, 0, 196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 197 /* 0x0b - 800x600@75Hz */ 198 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 199 896, 1056, 0, 600, 601, 604, 625, 0, 200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 201 /* 0x0c - 800x600@85Hz */ 202 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 203 896, 1048, 0, 600, 601, 604, 631, 0, 204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 205 /* 0x0d - 800x600@120Hz RB */ 206 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 207 880, 960, 0, 600, 603, 607, 636, 0, 208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 209 /* 0x0e - 848x480@60Hz */ 210 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 211 976, 1088, 0, 480, 486, 494, 517, 0, 212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 213 /* 0x0f - 1024x768@43Hz, interlace */ 214 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 215 1208, 1264, 0, 768, 768, 776, 817, 0, 216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 217 DRM_MODE_FLAG_INTERLACE) }, 218 /* 0x10 - 1024x768@60Hz */ 219 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 220 1184, 1344, 0, 768, 771, 777, 806, 0, 221 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 222 /* 0x11 - 1024x768@70Hz */ 223 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 224 1184, 1328, 0, 768, 771, 777, 806, 0, 225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 226 /* 0x12 - 1024x768@75Hz */ 227 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 228 1136, 1312, 0, 768, 769, 772, 800, 0, 229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 230 /* 0x13 - 1024x768@85Hz */ 231 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 232 1168, 1376, 0, 768, 769, 772, 808, 0, 233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 234 /* 0x14 - 1024x768@120Hz RB */ 235 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 236 1104, 1184, 0, 768, 771, 775, 813, 0, 237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 238 /* 0x15 - 1152x864@75Hz */ 239 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 240 1344, 1600, 0, 864, 865, 868, 900, 0, 241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 242 /* 0x55 - 1280x720@60Hz */ 243 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 244 1430, 1650, 0, 720, 725, 730, 750, 0, 245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 246 /* 0x16 - 1280x768@60Hz RB */ 247 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 248 1360, 1440, 0, 768, 771, 778, 790, 0, 249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 250 /* 0x17 - 1280x768@60Hz */ 251 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 252 1472, 1664, 0, 768, 771, 778, 798, 0, 253 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 254 /* 0x18 - 1280x768@75Hz */ 255 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 256 1488, 1696, 0, 768, 771, 778, 805, 0, 257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 258 /* 0x19 - 1280x768@85Hz */ 259 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 260 1496, 1712, 0, 768, 771, 778, 809, 0, 261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 262 /* 0x1a - 1280x768@120Hz RB */ 263 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 264 1360, 1440, 0, 768, 771, 778, 813, 0, 265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 266 /* 0x1b - 1280x800@60Hz RB */ 267 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 268 1360, 1440, 0, 800, 803, 809, 823, 0, 269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 270 /* 0x1c - 1280x800@60Hz */ 271 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 272 1480, 1680, 0, 800, 803, 809, 831, 0, 273 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 274 /* 0x1d - 1280x800@75Hz */ 275 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 276 1488, 1696, 0, 800, 803, 809, 838, 0, 277 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 278 /* 0x1e - 1280x800@85Hz */ 279 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 280 1496, 1712, 0, 800, 803, 809, 843, 0, 281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 282 /* 0x1f - 1280x800@120Hz RB */ 283 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 284 1360, 1440, 0, 800, 803, 809, 847, 0, 285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 286 /* 0x20 - 1280x960@60Hz */ 287 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 288 1488, 1800, 0, 960, 961, 964, 1000, 0, 289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 290 /* 0x21 - 1280x960@85Hz */ 291 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 292 1504, 1728, 0, 960, 961, 964, 1011, 0, 293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 294 /* 0x22 - 1280x960@120Hz RB */ 295 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 296 1360, 1440, 0, 960, 963, 967, 1017, 0, 297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 298 /* 0x23 - 1280x1024@60Hz */ 299 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 300 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x24 - 1280x1024@75Hz */ 303 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 304 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 306 /* 0x25 - 1280x1024@85Hz */ 307 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 308 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x26 - 1280x1024@120Hz RB */ 311 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 312 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 314 /* 0x27 - 1360x768@60Hz */ 315 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 316 1536, 1792, 0, 768, 771, 777, 795, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 318 /* 0x28 - 1360x768@120Hz RB */ 319 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 320 1440, 1520, 0, 768, 771, 776, 813, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 322 /* 0x51 - 1366x768@60Hz */ 323 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 324 1579, 1792, 0, 768, 771, 774, 798, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x56 - 1366x768@60Hz */ 327 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 328 1436, 1500, 0, 768, 769, 772, 800, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x29 - 1400x1050@60Hz RB */ 331 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 332 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x2a - 1400x1050@60Hz */ 335 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 336 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 337 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x2b - 1400x1050@75Hz */ 339 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 340 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 342 /* 0x2c - 1400x1050@85Hz */ 343 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 344 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x2d - 1400x1050@120Hz RB */ 347 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 348 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 350 /* 0x2e - 1440x900@60Hz RB */ 351 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 352 1520, 1600, 0, 900, 903, 909, 926, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x2f - 1440x900@60Hz */ 355 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 356 1672, 1904, 0, 900, 903, 909, 934, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x30 - 1440x900@75Hz */ 359 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 360 1688, 1936, 0, 900, 903, 909, 942, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x31 - 1440x900@85Hz */ 363 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 364 1696, 1952, 0, 900, 903, 909, 948, 0, 365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x32 - 1440x900@120Hz RB */ 367 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 368 1520, 1600, 0, 900, 903, 909, 953, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 370 /* 0x53 - 1600x900@60Hz */ 371 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 372 1704, 1800, 0, 900, 901, 904, 1000, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 374 /* 0x33 - 1600x1200@60Hz */ 375 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 376 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x34 - 1600x1200@65Hz */ 379 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 380 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x35 - 1600x1200@70Hz */ 383 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 384 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x36 - 1600x1200@75Hz */ 387 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 388 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 390 /* 0x37 - 1600x1200@85Hz */ 391 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 392 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x38 - 1600x1200@120Hz RB */ 395 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 396 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 398 /* 0x39 - 1680x1050@60Hz RB */ 399 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 400 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 402 /* 0x3a - 1680x1050@60Hz */ 403 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 404 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x3b - 1680x1050@75Hz */ 407 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 408 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x3c - 1680x1050@85Hz */ 411 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 412 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x3d - 1680x1050@120Hz RB */ 415 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 416 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x3e - 1792x1344@60Hz */ 419 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 420 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 421 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 422 /* 0x3f - 1792x1344@75Hz */ 423 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 424 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x40 - 1792x1344@120Hz RB */ 427 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 428 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 430 /* 0x41 - 1856x1392@60Hz */ 431 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 432 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x42 - 1856x1392@75Hz */ 435 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 436 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 438 /* 0x43 - 1856x1392@120Hz RB */ 439 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 440 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 442 /* 0x52 - 1920x1080@60Hz */ 443 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 444 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 446 /* 0x44 - 1920x1200@60Hz RB */ 447 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 448 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 450 /* 0x45 - 1920x1200@60Hz */ 451 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 452 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x46 - 1920x1200@75Hz */ 455 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 456 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x47 - 1920x1200@85Hz */ 459 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 460 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 462 /* 0x48 - 1920x1200@120Hz RB */ 463 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 464 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x49 - 1920x1440@60Hz */ 467 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 468 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 469 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 470 /* 0x4a - 1920x1440@75Hz */ 471 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 472 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x4b - 1920x1440@120Hz RB */ 475 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 476 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 478 /* 0x54 - 2048x1152@60Hz */ 479 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 480 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x4c - 2560x1600@60Hz RB */ 483 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 484 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x4d - 2560x1600@60Hz */ 487 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 488 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x4e - 2560x1600@75Hz */ 491 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 492 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x4f - 2560x1600@85Hz */ 495 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 496 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 498 /* 0x50 - 2560x1600@120Hz RB */ 499 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 500 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 502 /* 0x57 - 4096x2160@60Hz RB */ 503 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 504 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 506 /* 0x58 - 4096x2160@59.94Hz RB */ 507 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 508 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 510 }; 511 512 /* 513 * These more or less come from the DMT spec. The 720x400 modes are 514 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 515 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 516 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 517 * mode. 518 * 519 * The DMT modes have been fact-checked; the rest are mild guesses. 520 */ 521 static const struct drm_display_mode edid_est_modes[] = { 522 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 523 968, 1056, 0, 600, 601, 605, 628, 0, 524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 525 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 526 896, 1024, 0, 600, 601, 603, 625, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 528 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 529 720, 840, 0, 480, 481, 484, 500, 0, 530 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 531 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 532 704, 832, 0, 480, 489, 492, 520, 0, 533 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 534 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 535 768, 864, 0, 480, 483, 486, 525, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 537 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 538 752, 800, 0, 480, 490, 492, 525, 0, 539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 540 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 541 846, 900, 0, 400, 421, 423, 449, 0, 542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 543 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 544 846, 900, 0, 400, 412, 414, 449, 0, 545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 546 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 547 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 549 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 550 1136, 1312, 0, 768, 769, 772, 800, 0, 551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 552 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 553 1184, 1328, 0, 768, 771, 777, 806, 0, 554 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 555 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 556 1184, 1344, 0, 768, 771, 777, 806, 0, 557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 558 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 559 1208, 1264, 0, 768, 768, 776, 817, 0, 560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 561 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 562 928, 1152, 0, 624, 625, 628, 667, 0, 563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 564 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 565 896, 1056, 0, 600, 601, 604, 625, 0, 566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 567 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 568 976, 1040, 0, 600, 637, 643, 666, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 570 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 571 1344, 1600, 0, 864, 865, 868, 900, 0, 572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 573 }; 574 575 struct minimode { 576 short w; 577 short h; 578 short r; 579 short rb; 580 }; 581 582 static const struct minimode est3_modes[] = { 583 /* byte 6 */ 584 { 640, 350, 85, 0 }, 585 { 640, 400, 85, 0 }, 586 { 720, 400, 85, 0 }, 587 { 640, 480, 85, 0 }, 588 { 848, 480, 60, 0 }, 589 { 800, 600, 85, 0 }, 590 { 1024, 768, 85, 0 }, 591 { 1152, 864, 75, 0 }, 592 /* byte 7 */ 593 { 1280, 768, 60, 1 }, 594 { 1280, 768, 60, 0 }, 595 { 1280, 768, 75, 0 }, 596 { 1280, 768, 85, 0 }, 597 { 1280, 960, 60, 0 }, 598 { 1280, 960, 85, 0 }, 599 { 1280, 1024, 60, 0 }, 600 { 1280, 1024, 85, 0 }, 601 /* byte 8 */ 602 { 1360, 768, 60, 0 }, 603 { 1440, 900, 60, 1 }, 604 { 1440, 900, 60, 0 }, 605 { 1440, 900, 75, 0 }, 606 { 1440, 900, 85, 0 }, 607 { 1400, 1050, 60, 1 }, 608 { 1400, 1050, 60, 0 }, 609 { 1400, 1050, 75, 0 }, 610 /* byte 9 */ 611 { 1400, 1050, 85, 0 }, 612 { 1680, 1050, 60, 1 }, 613 { 1680, 1050, 60, 0 }, 614 { 1680, 1050, 75, 0 }, 615 { 1680, 1050, 85, 0 }, 616 { 1600, 1200, 60, 0 }, 617 { 1600, 1200, 65, 0 }, 618 { 1600, 1200, 70, 0 }, 619 /* byte 10 */ 620 { 1600, 1200, 75, 0 }, 621 { 1600, 1200, 85, 0 }, 622 { 1792, 1344, 60, 0 }, 623 { 1792, 1344, 75, 0 }, 624 { 1856, 1392, 60, 0 }, 625 { 1856, 1392, 75, 0 }, 626 { 1920, 1200, 60, 1 }, 627 { 1920, 1200, 60, 0 }, 628 /* byte 11 */ 629 { 1920, 1200, 75, 0 }, 630 { 1920, 1200, 85, 0 }, 631 { 1920, 1440, 60, 0 }, 632 { 1920, 1440, 75, 0 }, 633 }; 634 635 static const struct minimode extra_modes[] = { 636 { 1024, 576, 60, 0 }, 637 { 1366, 768, 60, 0 }, 638 { 1600, 900, 60, 0 }, 639 { 1680, 945, 60, 0 }, 640 { 1920, 1080, 60, 0 }, 641 { 2048, 1152, 60, 0 }, 642 { 2048, 1536, 60, 0 }, 643 }; 644 645 /* 646 * Probably taken from CEA-861 spec. 647 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 648 * 649 * Index using the VIC. 650 */ 651 static const struct drm_display_mode edid_cea_modes[] = { 652 /* 0 - dummy, VICs start at 1 */ 653 { }, 654 /* 1 - 640x480@60Hz */ 655 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 656 752, 800, 0, 480, 490, 492, 525, 0, 657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 658 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 659 /* 2 - 720x480@60Hz */ 660 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 661 798, 858, 0, 480, 489, 495, 525, 0, 662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 663 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 664 /* 3 - 720x480@60Hz */ 665 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 666 798, 858, 0, 480, 489, 495, 525, 0, 667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 669 /* 4 - 1280x720@60Hz */ 670 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 671 1430, 1650, 0, 720, 725, 730, 750, 0, 672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 674 /* 5 - 1920x1080i@60Hz */ 675 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 676 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 678 DRM_MODE_FLAG_INTERLACE), 679 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 680 /* 6 - 720(1440)x480i@60Hz */ 681 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 682 801, 858, 0, 480, 488, 494, 525, 0, 683 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 684 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 686 /* 7 - 720(1440)x480i@60Hz */ 687 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 688 801, 858, 0, 480, 488, 494, 525, 0, 689 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 690 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 692 /* 8 - 720(1440)x240@60Hz */ 693 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 694 801, 858, 0, 240, 244, 247, 262, 0, 695 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 696 DRM_MODE_FLAG_DBLCLK), 697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 698 /* 9 - 720(1440)x240@60Hz */ 699 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 700 801, 858, 0, 240, 244, 247, 262, 0, 701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 702 DRM_MODE_FLAG_DBLCLK), 703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 704 /* 10 - 2880x480i@60Hz */ 705 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 706 3204, 3432, 0, 480, 488, 494, 525, 0, 707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 708 DRM_MODE_FLAG_INTERLACE), 709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 710 /* 11 - 2880x480i@60Hz */ 711 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 712 3204, 3432, 0, 480, 488, 494, 525, 0, 713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 714 DRM_MODE_FLAG_INTERLACE), 715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 716 /* 12 - 2880x240@60Hz */ 717 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 718 3204, 3432, 0, 240, 244, 247, 262, 0, 719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 721 /* 13 - 2880x240@60Hz */ 722 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 723 3204, 3432, 0, 240, 244, 247, 262, 0, 724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 726 /* 14 - 1440x480@60Hz */ 727 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 728 1596, 1716, 0, 480, 489, 495, 525, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 731 /* 15 - 1440x480@60Hz */ 732 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 733 1596, 1716, 0, 480, 489, 495, 525, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 736 /* 16 - 1920x1080@60Hz */ 737 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 738 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 17 - 720x576@50Hz */ 742 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 743 796, 864, 0, 576, 581, 586, 625, 0, 744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 745 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 746 /* 18 - 720x576@50Hz */ 747 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 748 796, 864, 0, 576, 581, 586, 625, 0, 749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 750 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 751 /* 19 - 1280x720@50Hz */ 752 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 753 1760, 1980, 0, 720, 725, 730, 750, 0, 754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 755 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 20 - 1920x1080i@50Hz */ 757 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 758 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 760 DRM_MODE_FLAG_INTERLACE), 761 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 762 /* 21 - 720(1440)x576i@50Hz */ 763 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 764 795, 864, 0, 576, 580, 586, 625, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 766 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 768 /* 22 - 720(1440)x576i@50Hz */ 769 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 770 795, 864, 0, 576, 580, 586, 625, 0, 771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 772 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 774 /* 23 - 720(1440)x288@50Hz */ 775 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 776 795, 864, 0, 288, 290, 293, 312, 0, 777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 778 DRM_MODE_FLAG_DBLCLK), 779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 780 /* 24 - 720(1440)x288@50Hz */ 781 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 782 795, 864, 0, 288, 290, 293, 312, 0, 783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 784 DRM_MODE_FLAG_DBLCLK), 785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 786 /* 25 - 2880x576i@50Hz */ 787 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 788 3180, 3456, 0, 576, 580, 586, 625, 0, 789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 790 DRM_MODE_FLAG_INTERLACE), 791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 792 /* 26 - 2880x576i@50Hz */ 793 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 794 3180, 3456, 0, 576, 580, 586, 625, 0, 795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 796 DRM_MODE_FLAG_INTERLACE), 797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 798 /* 27 - 2880x288@50Hz */ 799 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 800 3180, 3456, 0, 288, 290, 293, 312, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 803 /* 28 - 2880x288@50Hz */ 804 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 805 3180, 3456, 0, 288, 290, 293, 312, 0, 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 808 /* 29 - 1440x576@50Hz */ 809 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 810 1592, 1728, 0, 576, 581, 586, 625, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 813 /* 30 - 1440x576@50Hz */ 814 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 815 1592, 1728, 0, 576, 581, 586, 625, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 818 /* 31 - 1920x1080@50Hz */ 819 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 820 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 32 - 1920x1080@24Hz */ 824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 825 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 827 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 33 - 1920x1080@25Hz */ 829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 830 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 832 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 833 /* 34 - 1920x1080@30Hz */ 834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 835 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 837 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 838 /* 35 - 2880x480@60Hz */ 839 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 840 3192, 3432, 0, 480, 489, 495, 525, 0, 841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 842 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 843 /* 36 - 2880x480@60Hz */ 844 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 845 3192, 3432, 0, 480, 489, 495, 525, 0, 846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 847 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 848 /* 37 - 2880x576@50Hz */ 849 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 850 3184, 3456, 0, 576, 581, 586, 625, 0, 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 853 /* 38 - 2880x576@50Hz */ 854 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 855 3184, 3456, 0, 576, 581, 586, 625, 0, 856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 857 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 39 - 1920x1080i@50Hz */ 859 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 860 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_INTERLACE), 863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 40 - 1920x1080i@100Hz */ 865 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 866 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 868 DRM_MODE_FLAG_INTERLACE), 869 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 41 - 1280x720@100Hz */ 871 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 872 1760, 1980, 0, 720, 725, 730, 750, 0, 873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 874 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 875 /* 42 - 720x576@100Hz */ 876 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 877 796, 864, 0, 576, 581, 586, 625, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 880 /* 43 - 720x576@100Hz */ 881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 882 796, 864, 0, 576, 581, 586, 625, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 885 /* 44 - 720(1440)x576i@100Hz */ 886 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 887 795, 864, 0, 576, 580, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 889 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 890 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 891 /* 45 - 720(1440)x576i@100Hz */ 892 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 893 795, 864, 0, 576, 580, 586, 625, 0, 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 895 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 896 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 897 /* 46 - 1920x1080i@120Hz */ 898 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 899 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 900 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 901 DRM_MODE_FLAG_INTERLACE), 902 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 903 /* 47 - 1280x720@120Hz */ 904 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 905 1430, 1650, 0, 720, 725, 730, 750, 0, 906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 907 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 908 /* 48 - 720x480@120Hz */ 909 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 910 798, 858, 0, 480, 489, 495, 525, 0, 911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 913 /* 49 - 720x480@120Hz */ 914 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 915 798, 858, 0, 480, 489, 495, 525, 0, 916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 918 /* 50 - 720(1440)x480i@120Hz */ 919 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 920 801, 858, 0, 480, 488, 494, 525, 0, 921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 922 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 923 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 924 /* 51 - 720(1440)x480i@120Hz */ 925 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 926 801, 858, 0, 480, 488, 494, 525, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 928 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 929 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 930 /* 52 - 720x576@200Hz */ 931 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 932 796, 864, 0, 576, 581, 586, 625, 0, 933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 934 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 935 /* 53 - 720x576@200Hz */ 936 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 937 796, 864, 0, 576, 581, 586, 625, 0, 938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 939 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 940 /* 54 - 720(1440)x576i@200Hz */ 941 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 942 795, 864, 0, 576, 580, 586, 625, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 944 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 945 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 946 /* 55 - 720(1440)x576i@200Hz */ 947 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 948 795, 864, 0, 576, 580, 586, 625, 0, 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 950 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 951 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 952 /* 56 - 720x480@240Hz */ 953 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 954 798, 858, 0, 480, 489, 495, 525, 0, 955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 956 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 957 /* 57 - 720x480@240Hz */ 958 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 959 798, 858, 0, 480, 489, 495, 525, 0, 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 961 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 962 /* 58 - 720(1440)x480i@240 */ 963 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 964 801, 858, 0, 480, 488, 494, 525, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 966 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 967 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 968 /* 59 - 720(1440)x480i@240 */ 969 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 970 801, 858, 0, 480, 488, 494, 525, 0, 971 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 972 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 973 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 974 /* 60 - 1280x720@24Hz */ 975 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 976 3080, 3300, 0, 720, 725, 730, 750, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 978 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 979 /* 61 - 1280x720@25Hz */ 980 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 981 3740, 3960, 0, 720, 725, 730, 750, 0, 982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 983 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 984 /* 62 - 1280x720@30Hz */ 985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 986 3080, 3300, 0, 720, 725, 730, 750, 0, 987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 988 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 989 /* 63 - 1920x1080@120Hz */ 990 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 991 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 993 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 994 /* 64 - 1920x1080@100Hz */ 995 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 996 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 998 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 }; 1000 1001 /* 1002 * HDMI 1.4 4k modes. Index using the VIC. 1003 */ 1004 static const struct drm_display_mode edid_4k_modes[] = { 1005 /* 0 - dummy, VICs start at 1 */ 1006 { }, 1007 /* 1 - 3840x2160@30Hz */ 1008 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1009 3840, 4016, 4104, 4400, 0, 1010 2160, 2168, 2178, 2250, 0, 1011 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1012 .vrefresh = 30, }, 1013 /* 2 - 3840x2160@25Hz */ 1014 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1015 3840, 4896, 4984, 5280, 0, 1016 2160, 2168, 2178, 2250, 0, 1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1018 .vrefresh = 25, }, 1019 /* 3 - 3840x2160@24Hz */ 1020 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1021 3840, 5116, 5204, 5500, 0, 1022 2160, 2168, 2178, 2250, 0, 1023 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1024 .vrefresh = 24, }, 1025 /* 4 - 4096x2160@24Hz (SMPTE) */ 1026 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1027 4096, 5116, 5204, 5500, 0, 1028 2160, 2168, 2178, 2250, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1030 .vrefresh = 24, }, 1031 }; 1032 1033 /*** DDC fetch and block validation ***/ 1034 1035 static const u8 edid_header[] = { 1036 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1037 }; 1038 1039 /** 1040 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1041 * @raw_edid: pointer to raw base EDID block 1042 * 1043 * Sanity check the header of the base EDID block. 1044 * 1045 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1046 */ 1047 int drm_edid_header_is_valid(const u8 *raw_edid) 1048 { 1049 int i, score = 0; 1050 1051 for (i = 0; i < sizeof(edid_header); i++) 1052 if (raw_edid[i] == edid_header[i]) 1053 score++; 1054 1055 return score; 1056 } 1057 EXPORT_SYMBOL(drm_edid_header_is_valid); 1058 1059 static int edid_fixup __read_mostly = 6; 1060 module_param_named(edid_fixup, edid_fixup, int, 0400); 1061 MODULE_PARM_DESC(edid_fixup, 1062 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1063 1064 static void drm_get_displayid(struct drm_connector *connector, 1065 struct edid *edid); 1066 1067 static int drm_edid_block_checksum(const u8 *raw_edid) 1068 { 1069 int i; 1070 u8 csum = 0; 1071 for (i = 0; i < EDID_LENGTH; i++) 1072 csum += raw_edid[i]; 1073 1074 return csum; 1075 } 1076 1077 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1078 { 1079 if (memchr_inv(in_edid, 0, length)) 1080 return false; 1081 1082 return true; 1083 } 1084 1085 /** 1086 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1087 * @raw_edid: pointer to raw EDID block 1088 * @block: type of block to validate (0 for base, extension otherwise) 1089 * @print_bad_edid: if true, dump bad EDID blocks to the console 1090 * @edid_corrupt: if true, the header or checksum is invalid 1091 * 1092 * Validate a base or extension EDID block and optionally dump bad blocks to 1093 * the console. 1094 * 1095 * Return: True if the block is valid, false otherwise. 1096 */ 1097 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1098 bool *edid_corrupt) 1099 { 1100 u8 csum; 1101 struct edid *edid = (struct edid *)raw_edid; 1102 1103 if (WARN_ON(!raw_edid)) 1104 return false; 1105 1106 if (edid_fixup > 8 || edid_fixup < 0) 1107 edid_fixup = 6; 1108 1109 if (block == 0) { 1110 int score = drm_edid_header_is_valid(raw_edid); 1111 if (score == 8) { 1112 if (edid_corrupt) 1113 *edid_corrupt = false; 1114 } else if (score >= edid_fixup) { 1115 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1116 * The corrupt flag needs to be set here otherwise, the 1117 * fix-up code here will correct the problem, the 1118 * checksum is correct and the test fails 1119 */ 1120 if (edid_corrupt) 1121 *edid_corrupt = true; 1122 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1123 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1124 } else { 1125 if (edid_corrupt) 1126 *edid_corrupt = true; 1127 goto bad; 1128 } 1129 } 1130 1131 csum = drm_edid_block_checksum(raw_edid); 1132 if (csum) { 1133 if (print_bad_edid) { 1134 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1135 } 1136 1137 if (edid_corrupt) 1138 *edid_corrupt = true; 1139 1140 /* allow CEA to slide through, switches mangle this */ 1141 if (raw_edid[0] != 0x02) 1142 goto bad; 1143 } 1144 1145 /* per-block-type checks */ 1146 switch (raw_edid[0]) { 1147 case 0: /* base */ 1148 if (edid->version != 1) { 1149 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1150 goto bad; 1151 } 1152 1153 if (edid->revision > 4) 1154 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1155 break; 1156 1157 default: 1158 break; 1159 } 1160 1161 return true; 1162 1163 bad: 1164 if (print_bad_edid) { 1165 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1166 printk(KERN_ERR "EDID block is all zeroes\n"); 1167 } else { 1168 printk(KERN_ERR "Raw EDID:\n"); 1169 for (int i = 0; i < EDID_LENGTH; ) { 1170 kprintf("%02x", raw_edid[i]); 1171 i++; 1172 if (i % 16 == 0 || i == EDID_LENGTH) 1173 kprintf("\n"); 1174 else if (i % 8 == 0) 1175 kprintf(" "); 1176 else 1177 kprintf(" "); 1178 } 1179 } 1180 } 1181 return false; 1182 } 1183 EXPORT_SYMBOL(drm_edid_block_valid); 1184 1185 /** 1186 * drm_edid_is_valid - sanity check EDID data 1187 * @edid: EDID data 1188 * 1189 * Sanity-check an entire EDID record (including extensions) 1190 * 1191 * Return: True if the EDID data is valid, false otherwise. 1192 */ 1193 bool drm_edid_is_valid(struct edid *edid) 1194 { 1195 int i; 1196 u8 *raw = (u8 *)edid; 1197 1198 if (!edid) 1199 return false; 1200 1201 for (i = 0; i <= edid->extensions; i++) 1202 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1203 return false; 1204 1205 return true; 1206 } 1207 EXPORT_SYMBOL(drm_edid_is_valid); 1208 1209 #define DDC_SEGMENT_ADDR 0x30 1210 /** 1211 * drm_do_probe_ddc_edid() - get EDID information via I2C 1212 * @data: I2C device adapter 1213 * @buf: EDID data buffer to be filled 1214 * @block: 128 byte EDID block to start fetching from 1215 * @len: EDID data buffer length to fetch 1216 * 1217 * Try to fetch EDID information by calling I2C driver functions. 1218 * 1219 * Return: 0 on success or -1 on failure. 1220 */ 1221 static int 1222 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1223 { 1224 struct i2c_adapter *adapter = data; 1225 unsigned char start = block * EDID_LENGTH; 1226 unsigned char segment = block >> 1; 1227 unsigned char xfers = segment ? 3 : 2; 1228 int ret, retries = 5; 1229 1230 /* 1231 * The core I2C driver will automatically retry the transfer if the 1232 * adapter reports EAGAIN. However, we find that bit-banging transfers 1233 * are susceptible to errors under a heavily loaded machine and 1234 * generate spurious NAKs and timeouts. Retrying the transfer 1235 * of the individual block a few times seems to overcome this. 1236 */ 1237 do { 1238 struct i2c_msg msgs[] = { 1239 { 1240 .addr = DDC_SEGMENT_ADDR, 1241 .flags = 0, 1242 .len = 1, 1243 .buf = &segment, 1244 }, { 1245 .addr = DDC_ADDR, 1246 .flags = 0, 1247 .len = 1, 1248 .buf = &start, 1249 }, { 1250 .addr = DDC_ADDR, 1251 .flags = I2C_M_RD, 1252 .len = len, 1253 .buf = buf, 1254 } 1255 }; 1256 1257 /* 1258 * Avoid sending the segment addr to not upset non-compliant 1259 * DDC monitors. 1260 */ 1261 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1262 1263 if (ret == -ENXIO) { 1264 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1265 adapter->name); 1266 break; 1267 } 1268 } while (ret != xfers && --retries); 1269 1270 return ret == xfers ? 0 : -1; 1271 } 1272 1273 /** 1274 * drm_do_get_edid - get EDID data using a custom EDID block read function 1275 * @connector: connector we're probing 1276 * @get_edid_block: EDID block read function 1277 * @data: private data passed to the block read function 1278 * 1279 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1280 * exposes a different interface to read EDID blocks this function can be used 1281 * to get EDID data using a custom block read function. 1282 * 1283 * As in the general case the DDC bus is accessible by the kernel at the I2C 1284 * level, drivers must make all reasonable efforts to expose it as an I2C 1285 * adapter and use drm_get_edid() instead of abusing this function. 1286 * 1287 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1288 */ 1289 struct edid *drm_do_get_edid(struct drm_connector *connector, 1290 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1291 size_t len), 1292 void *data) 1293 { 1294 int i, j = 0, valid_extensions = 0; 1295 u8 *block, *new; 1296 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1297 1298 if ((block = kmalloc(EDID_LENGTH, M_DRM, M_WAITOK)) == NULL) 1299 return NULL; 1300 1301 /* base block fetch */ 1302 for (i = 0; i < 4; i++) { 1303 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1304 goto out; 1305 if (drm_edid_block_valid(block, 0, print_bad_edid, 1306 &connector->edid_corrupt)) 1307 break; 1308 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1309 connector->null_edid_counter++; 1310 goto carp; 1311 } 1312 } 1313 if (i == 4) 1314 goto carp; 1315 1316 /* if there's no extensions, we're done */ 1317 if (block[0x7e] == 0) 1318 return (struct edid *)block; 1319 1320 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1321 if (!new) 1322 goto out; 1323 block = new; 1324 1325 for (j = 1; j <= block[0x7e]; j++) { 1326 for (i = 0; i < 4; i++) { 1327 if (get_edid_block(data, 1328 block + (valid_extensions + 1) * EDID_LENGTH, 1329 j, EDID_LENGTH)) 1330 goto out; 1331 if (drm_edid_block_valid(block + (valid_extensions + 1) 1332 * EDID_LENGTH, j, 1333 print_bad_edid, 1334 NULL)) { 1335 valid_extensions++; 1336 break; 1337 } 1338 } 1339 1340 if (i == 4 && print_bad_edid) { 1341 dev_warn(connector->dev->dev, 1342 "%s: Ignoring invalid EDID block %d.\n", 1343 connector->name, j); 1344 1345 connector->bad_edid_counter++; 1346 } 1347 } 1348 1349 if (valid_extensions != block[0x7e]) { 1350 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1351 block[0x7e] = valid_extensions; 1352 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, M_DRM, M_WAITOK); 1353 if (!new) 1354 goto out; 1355 block = new; 1356 } 1357 1358 return (struct edid *)block; 1359 1360 carp: 1361 if (print_bad_edid) { 1362 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1363 connector->name, j); 1364 } 1365 connector->bad_edid_counter++; 1366 1367 out: 1368 kfree(block); 1369 return NULL; 1370 } 1371 1372 /** 1373 * drm_probe_ddc() - probe DDC presence 1374 * @adapter: I2C adapter to probe 1375 * 1376 * Return: True on success, false on failure. 1377 */ 1378 bool 1379 drm_probe_ddc(struct i2c_adapter *adapter) 1380 { 1381 unsigned char out; 1382 1383 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1384 } 1385 EXPORT_SYMBOL(drm_probe_ddc); 1386 1387 /** 1388 * drm_get_edid - get EDID data, if available 1389 * @connector: connector we're probing 1390 * @adapter: I2C adapter to use for DDC 1391 * 1392 * Poke the given I2C channel to grab EDID data if possible. If found, 1393 * attach it to the connector. 1394 * 1395 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1396 */ 1397 struct edid *drm_get_edid(struct drm_connector *connector, 1398 struct i2c_adapter *adapter) 1399 { 1400 struct edid *edid; 1401 1402 if (!drm_probe_ddc(adapter)) 1403 return NULL; 1404 1405 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1406 if (edid) 1407 drm_get_displayid(connector, edid); 1408 return edid; 1409 } 1410 EXPORT_SYMBOL(drm_get_edid); 1411 1412 /** 1413 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 1414 * @connector: connector we're probing 1415 * @adapter: I2C adapter to use for DDC 1416 * 1417 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 1418 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 1419 * switch DDC to the GPU which is retrieving EDID. 1420 * 1421 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 1422 */ 1423 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 1424 struct i2c_adapter *adapter) 1425 { 1426 struct pci_dev *pdev = connector->dev->pdev; 1427 struct edid *edid; 1428 1429 vga_switcheroo_lock_ddc(pdev); 1430 edid = drm_get_edid(connector, adapter); 1431 vga_switcheroo_unlock_ddc(pdev); 1432 1433 return edid; 1434 } 1435 EXPORT_SYMBOL(drm_get_edid_switcheroo); 1436 1437 /** 1438 * drm_edid_duplicate - duplicate an EDID and the extensions 1439 * @edid: EDID to duplicate 1440 * 1441 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1442 */ 1443 struct edid *drm_edid_duplicate(const struct edid *edid) 1444 { 1445 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1446 } 1447 EXPORT_SYMBOL(drm_edid_duplicate); 1448 1449 /*** EDID parsing ***/ 1450 1451 /** 1452 * edid_vendor - match a string against EDID's obfuscated vendor field 1453 * @edid: EDID to match 1454 * @vendor: vendor string 1455 * 1456 * Returns true if @vendor is in @edid, false otherwise 1457 */ 1458 static bool edid_vendor(struct edid *edid, char *vendor) 1459 { 1460 char edid_vendor[3]; 1461 1462 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1463 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1464 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1465 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1466 1467 return !strncmp(edid_vendor, vendor, 3); 1468 } 1469 1470 /** 1471 * edid_get_quirks - return quirk flags for a given EDID 1472 * @edid: EDID to process 1473 * 1474 * This tells subsequent routines what fixes they need to apply. 1475 */ 1476 static u32 edid_get_quirks(struct edid *edid) 1477 { 1478 struct edid_quirk *quirk; 1479 int i; 1480 1481 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1482 quirk = &edid_quirk_list[i]; 1483 1484 if (edid_vendor(edid, quirk->vendor) && 1485 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1486 return quirk->quirks; 1487 } 1488 1489 return 0; 1490 } 1491 1492 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1493 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1494 1495 /** 1496 * edid_fixup_preferred - set preferred modes based on quirk list 1497 * @connector: has mode list to fix up 1498 * @quirks: quirks list 1499 * 1500 * Walk the mode list for @connector, clearing the preferred status 1501 * on existing modes and setting it anew for the right mode ala @quirks. 1502 */ 1503 static void edid_fixup_preferred(struct drm_connector *connector, 1504 u32 quirks) 1505 { 1506 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1507 int target_refresh = 0; 1508 int cur_vrefresh, preferred_vrefresh; 1509 1510 if (list_empty(&connector->probed_modes)) 1511 return; 1512 1513 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1514 target_refresh = 60; 1515 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1516 target_refresh = 75; 1517 1518 preferred_mode = list_first_entry(&connector->probed_modes, 1519 struct drm_display_mode, head); 1520 1521 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1522 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1523 1524 if (cur_mode == preferred_mode) 1525 continue; 1526 1527 /* Largest mode is preferred */ 1528 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1529 preferred_mode = cur_mode; 1530 1531 cur_vrefresh = cur_mode->vrefresh ? 1532 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1533 preferred_vrefresh = preferred_mode->vrefresh ? 1534 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1535 /* At a given size, try to get closest to target refresh */ 1536 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1537 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1538 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1539 preferred_mode = cur_mode; 1540 } 1541 } 1542 1543 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1544 } 1545 1546 static bool 1547 mode_is_rb(const struct drm_display_mode *mode) 1548 { 1549 return (mode->htotal - mode->hdisplay == 160) && 1550 (mode->hsync_end - mode->hdisplay == 80) && 1551 (mode->hsync_end - mode->hsync_start == 32) && 1552 (mode->vsync_start - mode->vdisplay == 3); 1553 } 1554 1555 /* 1556 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1557 * @dev: Device to duplicate against 1558 * @hsize: Mode width 1559 * @vsize: Mode height 1560 * @fresh: Mode refresh rate 1561 * @rb: Mode reduced-blanking-ness 1562 * 1563 * Walk the DMT mode list looking for a match for the given parameters. 1564 * 1565 * Return: A newly allocated copy of the mode, or NULL if not found. 1566 */ 1567 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1568 int hsize, int vsize, int fresh, 1569 bool rb) 1570 { 1571 int i; 1572 1573 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1574 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1575 if (hsize != ptr->hdisplay) 1576 continue; 1577 if (vsize != ptr->vdisplay) 1578 continue; 1579 if (fresh != drm_mode_vrefresh(ptr)) 1580 continue; 1581 if (rb != mode_is_rb(ptr)) 1582 continue; 1583 1584 return drm_mode_duplicate(dev, ptr); 1585 } 1586 1587 return NULL; 1588 } 1589 EXPORT_SYMBOL(drm_mode_find_dmt); 1590 1591 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1592 1593 static void 1594 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1595 { 1596 int i, n = 0; 1597 u8 d = ext[0x02]; 1598 u8 *det_base = ext + d; 1599 1600 n = (127 - d) / 18; 1601 for (i = 0; i < n; i++) 1602 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1603 } 1604 1605 static void 1606 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1607 { 1608 unsigned int i, n = min((int)ext[0x02], 6); 1609 u8 *det_base = ext + 5; 1610 1611 if (ext[0x01] != 1) 1612 return; /* unknown version */ 1613 1614 for (i = 0; i < n; i++) 1615 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1616 } 1617 1618 static void 1619 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1620 { 1621 int i; 1622 struct edid *edid = (struct edid *)raw_edid; 1623 1624 if (edid == NULL) 1625 return; 1626 1627 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1628 cb(&(edid->detailed_timings[i]), closure); 1629 1630 for (i = 1; i <= raw_edid[0x7e]; i++) { 1631 u8 *ext = raw_edid + (i * EDID_LENGTH); 1632 switch (*ext) { 1633 case CEA_EXT: 1634 cea_for_each_detailed_block(ext, cb, closure); 1635 break; 1636 case VTB_EXT: 1637 vtb_for_each_detailed_block(ext, cb, closure); 1638 break; 1639 default: 1640 break; 1641 } 1642 } 1643 } 1644 1645 static void 1646 is_rb(struct detailed_timing *t, void *data) 1647 { 1648 u8 *r = (u8 *)t; 1649 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1650 if (r[15] & 0x10) 1651 *(bool *)data = true; 1652 } 1653 1654 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1655 static bool 1656 drm_monitor_supports_rb(struct edid *edid) 1657 { 1658 if (edid->revision >= 4) { 1659 bool ret = false; 1660 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1661 return ret; 1662 } 1663 1664 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1665 } 1666 1667 static void 1668 find_gtf2(struct detailed_timing *t, void *data) 1669 { 1670 u8 *r = (u8 *)t; 1671 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1672 *(u8 **)data = r; 1673 } 1674 1675 /* Secondary GTF curve kicks in above some break frequency */ 1676 static int 1677 drm_gtf2_hbreak(struct edid *edid) 1678 { 1679 u8 *r = NULL; 1680 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1681 return r ? (r[12] * 2) : 0; 1682 } 1683 1684 static int 1685 drm_gtf2_2c(struct edid *edid) 1686 { 1687 u8 *r = NULL; 1688 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1689 return r ? r[13] : 0; 1690 } 1691 1692 static int 1693 drm_gtf2_m(struct edid *edid) 1694 { 1695 u8 *r = NULL; 1696 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1697 return r ? (r[15] << 8) + r[14] : 0; 1698 } 1699 1700 static int 1701 drm_gtf2_k(struct edid *edid) 1702 { 1703 u8 *r = NULL; 1704 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1705 return r ? r[16] : 0; 1706 } 1707 1708 static int 1709 drm_gtf2_2j(struct edid *edid) 1710 { 1711 u8 *r = NULL; 1712 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1713 return r ? r[17] : 0; 1714 } 1715 1716 /** 1717 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1718 * @edid: EDID block to scan 1719 */ 1720 static int standard_timing_level(struct edid *edid) 1721 { 1722 if (edid->revision >= 2) { 1723 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1724 return LEVEL_CVT; 1725 if (drm_gtf2_hbreak(edid)) 1726 return LEVEL_GTF2; 1727 return LEVEL_GTF; 1728 } 1729 return LEVEL_DMT; 1730 } 1731 1732 /* 1733 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1734 * monitors fill with ascii space (0x20) instead. 1735 */ 1736 static int 1737 bad_std_timing(u8 a, u8 b) 1738 { 1739 return (a == 0x00 && b == 0x00) || 1740 (a == 0x01 && b == 0x01) || 1741 (a == 0x20 && b == 0x20); 1742 } 1743 1744 /** 1745 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1746 * @connector: connector of for the EDID block 1747 * @edid: EDID block to scan 1748 * @t: standard timing params 1749 * 1750 * Take the standard timing params (in this case width, aspect, and refresh) 1751 * and convert them into a real mode using CVT/GTF/DMT. 1752 */ 1753 static struct drm_display_mode * 1754 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1755 struct std_timing *t) 1756 { 1757 struct drm_device *dev = connector->dev; 1758 struct drm_display_mode *m, *mode = NULL; 1759 int hsize, vsize; 1760 int vrefresh_rate; 1761 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1762 >> EDID_TIMING_ASPECT_SHIFT; 1763 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1764 >> EDID_TIMING_VFREQ_SHIFT; 1765 int timing_level = standard_timing_level(edid); 1766 1767 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1768 return NULL; 1769 1770 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1771 hsize = t->hsize * 8 + 248; 1772 /* vrefresh_rate = vfreq + 60 */ 1773 vrefresh_rate = vfreq + 60; 1774 /* the vdisplay is calculated based on the aspect ratio */ 1775 if (aspect_ratio == 0) { 1776 if (edid->revision < 3) 1777 vsize = hsize; 1778 else 1779 vsize = (hsize * 10) / 16; 1780 } else if (aspect_ratio == 1) 1781 vsize = (hsize * 3) / 4; 1782 else if (aspect_ratio == 2) 1783 vsize = (hsize * 4) / 5; 1784 else 1785 vsize = (hsize * 9) / 16; 1786 1787 /* HDTV hack, part 1 */ 1788 if (vrefresh_rate == 60 && 1789 ((hsize == 1360 && vsize == 765) || 1790 (hsize == 1368 && vsize == 769))) { 1791 hsize = 1366; 1792 vsize = 768; 1793 } 1794 1795 /* 1796 * If this connector already has a mode for this size and refresh 1797 * rate (because it came from detailed or CVT info), use that 1798 * instead. This way we don't have to guess at interlace or 1799 * reduced blanking. 1800 */ 1801 list_for_each_entry(m, &connector->probed_modes, head) 1802 if (m->hdisplay == hsize && m->vdisplay == vsize && 1803 drm_mode_vrefresh(m) == vrefresh_rate) 1804 return NULL; 1805 1806 /* HDTV hack, part 2 */ 1807 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1808 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1809 false); 1810 mode->hdisplay = 1366; 1811 mode->hsync_start = mode->hsync_start - 1; 1812 mode->hsync_end = mode->hsync_end - 1; 1813 return mode; 1814 } 1815 1816 /* check whether it can be found in default mode table */ 1817 if (drm_monitor_supports_rb(edid)) { 1818 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1819 true); 1820 if (mode) 1821 return mode; 1822 } 1823 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1824 if (mode) 1825 return mode; 1826 1827 /* okay, generate it */ 1828 switch (timing_level) { 1829 case LEVEL_DMT: 1830 break; 1831 case LEVEL_GTF: 1832 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1833 break; 1834 case LEVEL_GTF2: 1835 /* 1836 * This is potentially wrong if there's ever a monitor with 1837 * more than one ranges section, each claiming a different 1838 * secondary GTF curve. Please don't do that. 1839 */ 1840 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1841 if (!mode) 1842 return NULL; 1843 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1844 drm_mode_destroy(dev, mode); 1845 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1846 vrefresh_rate, 0, 0, 1847 drm_gtf2_m(edid), 1848 drm_gtf2_2c(edid), 1849 drm_gtf2_k(edid), 1850 drm_gtf2_2j(edid)); 1851 } 1852 break; 1853 case LEVEL_CVT: 1854 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1855 false); 1856 break; 1857 } 1858 return mode; 1859 } 1860 1861 /* 1862 * EDID is delightfully ambiguous about how interlaced modes are to be 1863 * encoded. Our internal representation is of frame height, but some 1864 * HDTV detailed timings are encoded as field height. 1865 * 1866 * The format list here is from CEA, in frame size. Technically we 1867 * should be checking refresh rate too. Whatever. 1868 */ 1869 static void 1870 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1871 struct detailed_pixel_timing *pt) 1872 { 1873 int i; 1874 static const struct { 1875 int w, h; 1876 } cea_interlaced[] = { 1877 { 1920, 1080 }, 1878 { 720, 480 }, 1879 { 1440, 480 }, 1880 { 2880, 480 }, 1881 { 720, 576 }, 1882 { 1440, 576 }, 1883 { 2880, 576 }, 1884 }; 1885 1886 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1887 return; 1888 1889 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1890 if ((mode->hdisplay == cea_interlaced[i].w) && 1891 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1892 mode->vdisplay *= 2; 1893 mode->vsync_start *= 2; 1894 mode->vsync_end *= 2; 1895 mode->vtotal *= 2; 1896 mode->vtotal |= 1; 1897 } 1898 } 1899 1900 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1901 } 1902 1903 /** 1904 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1905 * @dev: DRM device (needed to create new mode) 1906 * @edid: EDID block 1907 * @timing: EDID detailed timing info 1908 * @quirks: quirks to apply 1909 * 1910 * An EDID detailed timing block contains enough info for us to create and 1911 * return a new struct drm_display_mode. 1912 */ 1913 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1914 struct edid *edid, 1915 struct detailed_timing *timing, 1916 u32 quirks) 1917 { 1918 struct drm_display_mode *mode; 1919 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1920 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1921 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1922 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1923 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1924 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1925 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1926 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1927 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1928 1929 /* ignore tiny modes */ 1930 if (hactive < 64 || vactive < 64) 1931 return NULL; 1932 1933 if (pt->misc & DRM_EDID_PT_STEREO) { 1934 DRM_DEBUG_KMS("stereo mode not supported\n"); 1935 return NULL; 1936 } 1937 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1938 DRM_DEBUG_KMS("composite sync not supported\n"); 1939 } 1940 1941 /* it is incorrect if hsync/vsync width is zero */ 1942 if (!hsync_pulse_width || !vsync_pulse_width) { 1943 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1944 "Wrong Hsync/Vsync pulse width\n"); 1945 return NULL; 1946 } 1947 1948 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1949 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1950 if (!mode) 1951 return NULL; 1952 1953 goto set_size; 1954 } 1955 1956 mode = drm_mode_create(dev); 1957 if (!mode) 1958 return NULL; 1959 1960 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1961 timing->pixel_clock = cpu_to_le16(1088); 1962 1963 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1964 1965 mode->hdisplay = hactive; 1966 mode->hsync_start = mode->hdisplay + hsync_offset; 1967 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1968 mode->htotal = mode->hdisplay + hblank; 1969 1970 mode->vdisplay = vactive; 1971 mode->vsync_start = mode->vdisplay + vsync_offset; 1972 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1973 mode->vtotal = mode->vdisplay + vblank; 1974 1975 /* Some EDIDs have bogus h/vtotal values */ 1976 if (mode->hsync_end > mode->htotal) 1977 mode->htotal = mode->hsync_end + 1; 1978 if (mode->vsync_end > mode->vtotal) 1979 mode->vtotal = mode->vsync_end + 1; 1980 1981 drm_mode_do_interlace_quirk(mode, pt); 1982 1983 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1984 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1985 } 1986 1987 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1988 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1989 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1990 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1991 1992 set_size: 1993 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1994 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1995 1996 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1997 mode->width_mm *= 10; 1998 mode->height_mm *= 10; 1999 } 2000 2001 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2002 mode->width_mm = edid->width_cm * 10; 2003 mode->height_mm = edid->height_cm * 10; 2004 } 2005 2006 mode->type = DRM_MODE_TYPE_DRIVER; 2007 mode->vrefresh = drm_mode_vrefresh(mode); 2008 drm_mode_set_name(mode); 2009 2010 return mode; 2011 } 2012 2013 static bool 2014 mode_in_hsync_range(const struct drm_display_mode *mode, 2015 struct edid *edid, u8 *t) 2016 { 2017 int hsync, hmin, hmax; 2018 2019 hmin = t[7]; 2020 if (edid->revision >= 4) 2021 hmin += ((t[4] & 0x04) ? 255 : 0); 2022 hmax = t[8]; 2023 if (edid->revision >= 4) 2024 hmax += ((t[4] & 0x08) ? 255 : 0); 2025 hsync = drm_mode_hsync(mode); 2026 2027 return (hsync <= hmax && hsync >= hmin); 2028 } 2029 2030 static bool 2031 mode_in_vsync_range(const struct drm_display_mode *mode, 2032 struct edid *edid, u8 *t) 2033 { 2034 int vsync, vmin, vmax; 2035 2036 vmin = t[5]; 2037 if (edid->revision >= 4) 2038 vmin += ((t[4] & 0x01) ? 255 : 0); 2039 vmax = t[6]; 2040 if (edid->revision >= 4) 2041 vmax += ((t[4] & 0x02) ? 255 : 0); 2042 vsync = drm_mode_vrefresh(mode); 2043 2044 return (vsync <= vmax && vsync >= vmin); 2045 } 2046 2047 static u32 2048 range_pixel_clock(struct edid *edid, u8 *t) 2049 { 2050 /* unspecified */ 2051 if (t[9] == 0 || t[9] == 255) 2052 return 0; 2053 2054 /* 1.4 with CVT support gives us real precision, yay */ 2055 if (edid->revision >= 4 && t[10] == 0x04) 2056 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2057 2058 /* 1.3 is pathetic, so fuzz up a bit */ 2059 return t[9] * 10000 + 5001; 2060 } 2061 2062 static bool 2063 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2064 struct detailed_timing *timing) 2065 { 2066 u32 max_clock; 2067 u8 *t = (u8 *)timing; 2068 2069 if (!mode_in_hsync_range(mode, edid, t)) 2070 return false; 2071 2072 if (!mode_in_vsync_range(mode, edid, t)) 2073 return false; 2074 2075 if ((max_clock = range_pixel_clock(edid, t))) 2076 if (mode->clock > max_clock) 2077 return false; 2078 2079 /* 1.4 max horizontal check */ 2080 if (edid->revision >= 4 && t[10] == 0x04) 2081 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2082 return false; 2083 2084 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2085 return false; 2086 2087 return true; 2088 } 2089 2090 static bool valid_inferred_mode(const struct drm_connector *connector, 2091 const struct drm_display_mode *mode) 2092 { 2093 struct drm_display_mode *m; 2094 bool ok = false; 2095 2096 list_for_each_entry(m, &connector->probed_modes, head) { 2097 if (mode->hdisplay == m->hdisplay && 2098 mode->vdisplay == m->vdisplay && 2099 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2100 return false; /* duplicated */ 2101 if (mode->hdisplay <= m->hdisplay && 2102 mode->vdisplay <= m->vdisplay) 2103 ok = true; 2104 } 2105 return ok; 2106 } 2107 2108 static int 2109 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2110 struct detailed_timing *timing) 2111 { 2112 int i, modes = 0; 2113 struct drm_display_mode *newmode; 2114 struct drm_device *dev = connector->dev; 2115 2116 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2117 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2118 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2119 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2120 if (newmode) { 2121 drm_mode_probed_add(connector, newmode); 2122 modes++; 2123 } 2124 } 2125 } 2126 2127 return modes; 2128 } 2129 2130 /* fix up 1366x768 mode from 1368x768; 2131 * GFT/CVT can't express 1366 width which isn't dividable by 8 2132 */ 2133 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2134 { 2135 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2136 mode->hdisplay = 1366; 2137 mode->hsync_start--; 2138 mode->hsync_end--; 2139 drm_mode_set_name(mode); 2140 } 2141 } 2142 2143 static int 2144 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2145 struct detailed_timing *timing) 2146 { 2147 int i, modes = 0; 2148 struct drm_display_mode *newmode; 2149 struct drm_device *dev = connector->dev; 2150 2151 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2152 const struct minimode *m = &extra_modes[i]; 2153 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2154 if (!newmode) 2155 return modes; 2156 2157 fixup_mode_1366x768(newmode); 2158 if (!mode_in_range(newmode, edid, timing) || 2159 !valid_inferred_mode(connector, newmode)) { 2160 drm_mode_destroy(dev, newmode); 2161 continue; 2162 } 2163 2164 drm_mode_probed_add(connector, newmode); 2165 modes++; 2166 } 2167 2168 return modes; 2169 } 2170 2171 static int 2172 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2173 struct detailed_timing *timing) 2174 { 2175 int i, modes = 0; 2176 struct drm_display_mode *newmode; 2177 struct drm_device *dev = connector->dev; 2178 bool rb = drm_monitor_supports_rb(edid); 2179 2180 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2181 const struct minimode *m = &extra_modes[i]; 2182 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2183 if (!newmode) 2184 return modes; 2185 2186 fixup_mode_1366x768(newmode); 2187 if (!mode_in_range(newmode, edid, timing) || 2188 !valid_inferred_mode(connector, newmode)) { 2189 drm_mode_destroy(dev, newmode); 2190 continue; 2191 } 2192 2193 drm_mode_probed_add(connector, newmode); 2194 modes++; 2195 } 2196 2197 return modes; 2198 } 2199 2200 static void 2201 do_inferred_modes(struct detailed_timing *timing, void *c) 2202 { 2203 struct detailed_mode_closure *closure = c; 2204 struct detailed_non_pixel *data = &timing->data.other_data; 2205 struct detailed_data_monitor_range *range = &data->data.range; 2206 2207 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2208 return; 2209 2210 closure->modes += drm_dmt_modes_for_range(closure->connector, 2211 closure->edid, 2212 timing); 2213 2214 if (!version_greater(closure->edid, 1, 1)) 2215 return; /* GTF not defined yet */ 2216 2217 switch (range->flags) { 2218 case 0x02: /* secondary gtf, XXX could do more */ 2219 case 0x00: /* default gtf */ 2220 closure->modes += drm_gtf_modes_for_range(closure->connector, 2221 closure->edid, 2222 timing); 2223 break; 2224 case 0x04: /* cvt, only in 1.4+ */ 2225 if (!version_greater(closure->edid, 1, 3)) 2226 break; 2227 2228 closure->modes += drm_cvt_modes_for_range(closure->connector, 2229 closure->edid, 2230 timing); 2231 break; 2232 case 0x01: /* just the ranges, no formula */ 2233 default: 2234 break; 2235 } 2236 } 2237 2238 static int 2239 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2240 { 2241 struct detailed_mode_closure closure = { 2242 .connector = connector, 2243 .edid = edid, 2244 }; 2245 2246 if (version_greater(edid, 1, 0)) 2247 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2248 &closure); 2249 2250 return closure.modes; 2251 } 2252 2253 static int 2254 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2255 { 2256 int i, j, m, modes = 0; 2257 struct drm_display_mode *mode; 2258 u8 *est = ((u8 *)timing) + 6; 2259 2260 for (i = 0; i < 6; i++) { 2261 for (j = 7; j >= 0; j--) { 2262 m = (i * 8) + (7 - j); 2263 if (m >= ARRAY_SIZE(est3_modes)) 2264 break; 2265 if (est[i] & (1 << j)) { 2266 mode = drm_mode_find_dmt(connector->dev, 2267 est3_modes[m].w, 2268 est3_modes[m].h, 2269 est3_modes[m].r, 2270 est3_modes[m].rb); 2271 if (mode) { 2272 drm_mode_probed_add(connector, mode); 2273 modes++; 2274 } 2275 } 2276 } 2277 } 2278 2279 return modes; 2280 } 2281 2282 static void 2283 do_established_modes(struct detailed_timing *timing, void *c) 2284 { 2285 struct detailed_mode_closure *closure = c; 2286 struct detailed_non_pixel *data = &timing->data.other_data; 2287 2288 if (data->type == EDID_DETAIL_EST_TIMINGS) 2289 closure->modes += drm_est3_modes(closure->connector, timing); 2290 } 2291 2292 /** 2293 * add_established_modes - get est. modes from EDID and add them 2294 * @connector: connector to add mode(s) to 2295 * @edid: EDID block to scan 2296 * 2297 * Each EDID block contains a bitmap of the supported "established modes" list 2298 * (defined above). Tease them out and add them to the global modes list. 2299 */ 2300 static int 2301 add_established_modes(struct drm_connector *connector, struct edid *edid) 2302 { 2303 struct drm_device *dev = connector->dev; 2304 unsigned long est_bits = edid->established_timings.t1 | 2305 (edid->established_timings.t2 << 8) | 2306 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2307 int i, modes = 0; 2308 struct detailed_mode_closure closure = { 2309 .connector = connector, 2310 .edid = edid, 2311 }; 2312 2313 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2314 if (est_bits & (1<<i)) { 2315 struct drm_display_mode *newmode; 2316 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2317 if (newmode) { 2318 drm_mode_probed_add(connector, newmode); 2319 modes++; 2320 } 2321 } 2322 } 2323 2324 if (version_greater(edid, 1, 0)) 2325 drm_for_each_detailed_block((u8 *)edid, 2326 do_established_modes, &closure); 2327 2328 return modes + closure.modes; 2329 } 2330 2331 static void 2332 do_standard_modes(struct detailed_timing *timing, void *c) 2333 { 2334 struct detailed_mode_closure *closure = c; 2335 struct detailed_non_pixel *data = &timing->data.other_data; 2336 struct drm_connector *connector = closure->connector; 2337 struct edid *edid = closure->edid; 2338 2339 if (data->type == EDID_DETAIL_STD_MODES) { 2340 int i; 2341 for (i = 0; i < 6; i++) { 2342 struct std_timing *std; 2343 struct drm_display_mode *newmode; 2344 2345 std = &data->data.timings[i]; 2346 newmode = drm_mode_std(connector, edid, std); 2347 if (newmode) { 2348 drm_mode_probed_add(connector, newmode); 2349 closure->modes++; 2350 } 2351 } 2352 } 2353 } 2354 2355 /** 2356 * add_standard_modes - get std. modes from EDID and add them 2357 * @connector: connector to add mode(s) to 2358 * @edid: EDID block to scan 2359 * 2360 * Standard modes can be calculated using the appropriate standard (DMT, 2361 * GTF or CVT. Grab them from @edid and add them to the list. 2362 */ 2363 static int 2364 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2365 { 2366 int i, modes = 0; 2367 struct detailed_mode_closure closure = { 2368 .connector = connector, 2369 .edid = edid, 2370 }; 2371 2372 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2373 struct drm_display_mode *newmode; 2374 2375 newmode = drm_mode_std(connector, edid, 2376 &edid->standard_timings[i]); 2377 if (newmode) { 2378 drm_mode_probed_add(connector, newmode); 2379 modes++; 2380 } 2381 } 2382 2383 if (version_greater(edid, 1, 0)) 2384 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2385 &closure); 2386 2387 /* XXX should also look for standard codes in VTB blocks */ 2388 2389 return modes + closure.modes; 2390 } 2391 2392 static int drm_cvt_modes(struct drm_connector *connector, 2393 struct detailed_timing *timing) 2394 { 2395 int i, j, modes = 0; 2396 struct drm_display_mode *newmode; 2397 struct drm_device *dev = connector->dev; 2398 struct cvt_timing *cvt; 2399 const int rates[] = { 60, 85, 75, 60, 50 }; 2400 const u8 empty[3] = { 0, 0, 0 }; 2401 2402 for (i = 0; i < 4; i++) { 2403 int width = 0, height; 2404 cvt = &(timing->data.other_data.data.cvt[i]); 2405 2406 if (!memcmp(cvt->code, empty, 3)) 2407 continue; 2408 2409 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2410 switch (cvt->code[1] & 0x0c) { 2411 case 0x00: 2412 width = height * 4 / 3; 2413 break; 2414 case 0x04: 2415 width = height * 16 / 9; 2416 break; 2417 case 0x08: 2418 width = height * 16 / 10; 2419 break; 2420 case 0x0c: 2421 width = height * 15 / 9; 2422 break; 2423 } 2424 2425 for (j = 1; j < 5; j++) { 2426 if (cvt->code[2] & (1 << j)) { 2427 newmode = drm_cvt_mode(dev, width, height, 2428 rates[j], j == 0, 2429 false, false); 2430 if (newmode) { 2431 drm_mode_probed_add(connector, newmode); 2432 modes++; 2433 } 2434 } 2435 } 2436 } 2437 2438 return modes; 2439 } 2440 2441 static void 2442 do_cvt_mode(struct detailed_timing *timing, void *c) 2443 { 2444 struct detailed_mode_closure *closure = c; 2445 struct detailed_non_pixel *data = &timing->data.other_data; 2446 2447 if (data->type == EDID_DETAIL_CVT_3BYTE) 2448 closure->modes += drm_cvt_modes(closure->connector, timing); 2449 } 2450 2451 static int 2452 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2453 { 2454 struct detailed_mode_closure closure = { 2455 .connector = connector, 2456 .edid = edid, 2457 }; 2458 2459 if (version_greater(edid, 1, 2)) 2460 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2461 2462 /* XXX should also look for CVT codes in VTB blocks */ 2463 2464 return closure.modes; 2465 } 2466 2467 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2468 2469 static void 2470 do_detailed_mode(struct detailed_timing *timing, void *c) 2471 { 2472 struct detailed_mode_closure *closure = c; 2473 struct drm_display_mode *newmode; 2474 2475 if (timing->pixel_clock) { 2476 newmode = drm_mode_detailed(closure->connector->dev, 2477 closure->edid, timing, 2478 closure->quirks); 2479 if (!newmode) 2480 return; 2481 2482 if (closure->preferred) 2483 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2484 2485 /* 2486 * Detailed modes are limited to 10kHz pixel clock resolution, 2487 * so fix up anything that looks like CEA/HDMI mode, but the clock 2488 * is just slightly off. 2489 */ 2490 fixup_detailed_cea_mode_clock(newmode); 2491 2492 drm_mode_probed_add(closure->connector, newmode); 2493 closure->modes++; 2494 closure->preferred = 0; 2495 } 2496 } 2497 2498 /* 2499 * add_detailed_modes - Add modes from detailed timings 2500 * @connector: attached connector 2501 * @edid: EDID block to scan 2502 * @quirks: quirks to apply 2503 */ 2504 static int 2505 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2506 u32 quirks) 2507 { 2508 struct detailed_mode_closure closure = { 2509 .connector = connector, 2510 .edid = edid, 2511 .preferred = 1, 2512 .quirks = quirks, 2513 }; 2514 2515 if (closure.preferred && !version_greater(edid, 1, 3)) 2516 closure.preferred = 2517 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2518 2519 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2520 2521 return closure.modes; 2522 } 2523 2524 #define AUDIO_BLOCK 0x01 2525 #define VIDEO_BLOCK 0x02 2526 #define VENDOR_BLOCK 0x03 2527 #define SPEAKER_BLOCK 0x04 2528 #define VIDEO_CAPABILITY_BLOCK 0x07 2529 #define EDID_BASIC_AUDIO (1 << 6) 2530 #define EDID_CEA_YCRCB444 (1 << 5) 2531 #define EDID_CEA_YCRCB422 (1 << 4) 2532 #define EDID_CEA_VCDB_QS (1 << 6) 2533 2534 /* 2535 * Search EDID for CEA extension block. 2536 */ 2537 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2538 { 2539 u8 *edid_ext = NULL; 2540 int i; 2541 2542 /* No EDID or EDID extensions */ 2543 if (edid == NULL || edid->extensions == 0) 2544 return NULL; 2545 2546 /* Find CEA extension */ 2547 for (i = 0; i < edid->extensions; i++) { 2548 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2549 if (edid_ext[0] == ext_id) 2550 break; 2551 } 2552 2553 if (i == edid->extensions) 2554 return NULL; 2555 2556 return edid_ext; 2557 } 2558 2559 static u8 *drm_find_cea_extension(struct edid *edid) 2560 { 2561 return drm_find_edid_extension(edid, CEA_EXT); 2562 } 2563 2564 static u8 *drm_find_displayid_extension(struct edid *edid) 2565 { 2566 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2567 } 2568 2569 /* 2570 * Calculate the alternate clock for the CEA mode 2571 * (60Hz vs. 59.94Hz etc.) 2572 */ 2573 static unsigned int 2574 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2575 { 2576 unsigned int clock = cea_mode->clock; 2577 2578 if (cea_mode->vrefresh % 6 != 0) 2579 return clock; 2580 2581 /* 2582 * edid_cea_modes contains the 59.94Hz 2583 * variant for 240 and 480 line modes, 2584 * and the 60Hz variant otherwise. 2585 */ 2586 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2587 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2588 else 2589 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2590 2591 return clock; 2592 } 2593 2594 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 2595 unsigned int clock_tolerance) 2596 { 2597 u8 vic; 2598 2599 if (!to_match->clock) 2600 return 0; 2601 2602 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2603 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2604 unsigned int clock1, clock2; 2605 2606 /* Check both 60Hz and 59.94Hz */ 2607 clock1 = cea_mode->clock; 2608 clock2 = cea_mode_alternate_clock(cea_mode); 2609 2610 if (abs(to_match->clock - clock1) > clock_tolerance && 2611 abs(to_match->clock - clock2) > clock_tolerance) 2612 continue; 2613 2614 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 2615 return vic; 2616 } 2617 2618 return 0; 2619 } 2620 2621 /** 2622 * drm_match_cea_mode - look for a CEA mode matching given mode 2623 * @to_match: display mode 2624 * 2625 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2626 * mode. 2627 */ 2628 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2629 { 2630 u8 vic; 2631 2632 if (!to_match->clock) 2633 return 0; 2634 2635 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) { 2636 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic]; 2637 unsigned int clock1, clock2; 2638 2639 /* Check both 60Hz and 59.94Hz */ 2640 clock1 = cea_mode->clock; 2641 clock2 = cea_mode_alternate_clock(cea_mode); 2642 2643 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2644 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2645 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2646 return vic; 2647 } 2648 return 0; 2649 } 2650 EXPORT_SYMBOL(drm_match_cea_mode); 2651 2652 static bool drm_valid_cea_vic(u8 vic) 2653 { 2654 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes); 2655 } 2656 2657 /** 2658 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2659 * the input VIC from the CEA mode list 2660 * @video_code: ID given to each of the CEA modes 2661 * 2662 * Returns picture aspect ratio 2663 */ 2664 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2665 { 2666 return edid_cea_modes[video_code].picture_aspect_ratio; 2667 } 2668 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2669 2670 /* 2671 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2672 * specific block). 2673 * 2674 * It's almost like cea_mode_alternate_clock(), we just need to add an 2675 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2676 * one. 2677 */ 2678 static unsigned int 2679 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2680 { 2681 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2682 return hdmi_mode->clock; 2683 2684 return cea_mode_alternate_clock(hdmi_mode); 2685 } 2686 2687 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 2688 unsigned int clock_tolerance) 2689 { 2690 u8 vic; 2691 2692 if (!to_match->clock) 2693 return 0; 2694 2695 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2696 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2697 unsigned int clock1, clock2; 2698 2699 /* Make sure to also match alternate clocks */ 2700 clock1 = hdmi_mode->clock; 2701 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2702 2703 if (abs(to_match->clock - clock1) > clock_tolerance && 2704 abs(to_match->clock - clock2) > clock_tolerance) 2705 continue; 2706 2707 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 2708 return vic; 2709 } 2710 2711 return 0; 2712 } 2713 2714 /* 2715 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2716 * @to_match: display mode 2717 * 2718 * An HDMI mode is one defined in the HDMI vendor specific block. 2719 * 2720 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2721 */ 2722 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2723 { 2724 u8 vic; 2725 2726 if (!to_match->clock) 2727 return 0; 2728 2729 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 2730 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 2731 unsigned int clock1, clock2; 2732 2733 /* Make sure to also match alternate clocks */ 2734 clock1 = hdmi_mode->clock; 2735 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2736 2737 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2738 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2739 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2740 return vic; 2741 } 2742 return 0; 2743 } 2744 2745 static bool drm_valid_hdmi_vic(u8 vic) 2746 { 2747 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2748 } 2749 2750 static int 2751 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2752 { 2753 struct drm_device *dev = connector->dev; 2754 struct drm_display_mode *mode, *tmp; 2755 LINUX_LIST_HEAD(list); 2756 int modes = 0; 2757 2758 /* Don't add CEA modes if the CEA extension block is missing */ 2759 if (!drm_find_cea_extension(edid)) 2760 return 0; 2761 2762 /* 2763 * Go through all probed modes and create a new mode 2764 * with the alternate clock for certain CEA modes. 2765 */ 2766 list_for_each_entry(mode, &connector->probed_modes, head) { 2767 const struct drm_display_mode *cea_mode = NULL; 2768 struct drm_display_mode *newmode; 2769 u8 vic = drm_match_cea_mode(mode); 2770 unsigned int clock1, clock2; 2771 2772 if (drm_valid_cea_vic(vic)) { 2773 cea_mode = &edid_cea_modes[vic]; 2774 clock2 = cea_mode_alternate_clock(cea_mode); 2775 } else { 2776 vic = drm_match_hdmi_mode(mode); 2777 if (drm_valid_hdmi_vic(vic)) { 2778 cea_mode = &edid_4k_modes[vic]; 2779 clock2 = hdmi_mode_alternate_clock(cea_mode); 2780 } 2781 } 2782 2783 if (!cea_mode) 2784 continue; 2785 2786 clock1 = cea_mode->clock; 2787 2788 if (clock1 == clock2) 2789 continue; 2790 2791 if (mode->clock != clock1 && mode->clock != clock2) 2792 continue; 2793 2794 newmode = drm_mode_duplicate(dev, cea_mode); 2795 if (!newmode) 2796 continue; 2797 2798 /* Carry over the stereo flags */ 2799 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2800 2801 /* 2802 * The current mode could be either variant. Make 2803 * sure to pick the "other" clock for the new mode. 2804 */ 2805 if (mode->clock != clock1) 2806 newmode->clock = clock1; 2807 else 2808 newmode->clock = clock2; 2809 2810 list_add_tail(&newmode->head, &list); 2811 } 2812 2813 list_for_each_entry_safe(mode, tmp, &list, head) { 2814 list_del(&mode->head); 2815 drm_mode_probed_add(connector, mode); 2816 modes++; 2817 } 2818 2819 return modes; 2820 } 2821 2822 static struct drm_display_mode * 2823 drm_display_mode_from_vic_index(struct drm_connector *connector, 2824 const u8 *video_db, u8 video_len, 2825 u8 video_index) 2826 { 2827 struct drm_device *dev = connector->dev; 2828 struct drm_display_mode *newmode; 2829 u8 vic; 2830 2831 if (video_db == NULL || video_index >= video_len) 2832 return NULL; 2833 2834 /* CEA modes are numbered 1..127 */ 2835 vic = (video_db[video_index] & 127); 2836 if (!drm_valid_cea_vic(vic)) 2837 return NULL; 2838 2839 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]); 2840 if (!newmode) 2841 return NULL; 2842 2843 newmode->vrefresh = 0; 2844 2845 return newmode; 2846 } 2847 2848 static int 2849 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2850 { 2851 int i, modes = 0; 2852 2853 for (i = 0; i < len; i++) { 2854 struct drm_display_mode *mode; 2855 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2856 if (mode) { 2857 drm_mode_probed_add(connector, mode); 2858 modes++; 2859 } 2860 } 2861 2862 return modes; 2863 } 2864 2865 struct stereo_mandatory_mode { 2866 int width, height, vrefresh; 2867 unsigned int flags; 2868 }; 2869 2870 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2871 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2872 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2873 { 1920, 1080, 50, 2874 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2875 { 1920, 1080, 60, 2876 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2877 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2878 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2879 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2880 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2881 }; 2882 2883 static bool 2884 stereo_match_mandatory(const struct drm_display_mode *mode, 2885 const struct stereo_mandatory_mode *stereo_mode) 2886 { 2887 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2888 2889 return mode->hdisplay == stereo_mode->width && 2890 mode->vdisplay == stereo_mode->height && 2891 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2892 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2893 } 2894 2895 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2896 { 2897 struct drm_device *dev = connector->dev; 2898 struct drm_display_mode *mode; 2899 struct list_head stereo_modes; 2900 int modes = 0, i; 2901 2902 INIT_LIST_HEAD(&stereo_modes); 2903 2904 list_for_each_entry(mode, &connector->probed_modes, head) { 2905 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2906 const struct stereo_mandatory_mode *mandatory; 2907 struct drm_display_mode *new_mode; 2908 2909 if (!stereo_match_mandatory(mode, 2910 &stereo_mandatory_modes[i])) 2911 continue; 2912 2913 mandatory = &stereo_mandatory_modes[i]; 2914 new_mode = drm_mode_duplicate(dev, mode); 2915 if (!new_mode) 2916 continue; 2917 2918 new_mode->flags |= mandatory->flags; 2919 list_add_tail(&new_mode->head, &stereo_modes); 2920 modes++; 2921 } 2922 } 2923 2924 list_splice_tail(&stereo_modes, &connector->probed_modes); 2925 2926 return modes; 2927 } 2928 2929 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2930 { 2931 struct drm_device *dev = connector->dev; 2932 struct drm_display_mode *newmode; 2933 2934 if (!drm_valid_hdmi_vic(vic)) { 2935 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2936 return 0; 2937 } 2938 2939 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2940 if (!newmode) 2941 return 0; 2942 2943 drm_mode_probed_add(connector, newmode); 2944 2945 return 1; 2946 } 2947 2948 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2949 const u8 *video_db, u8 video_len, u8 video_index) 2950 { 2951 struct drm_display_mode *newmode; 2952 int modes = 0; 2953 2954 if (structure & (1 << 0)) { 2955 newmode = drm_display_mode_from_vic_index(connector, video_db, 2956 video_len, 2957 video_index); 2958 if (newmode) { 2959 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2960 drm_mode_probed_add(connector, newmode); 2961 modes++; 2962 } 2963 } 2964 if (structure & (1 << 6)) { 2965 newmode = drm_display_mode_from_vic_index(connector, video_db, 2966 video_len, 2967 video_index); 2968 if (newmode) { 2969 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2970 drm_mode_probed_add(connector, newmode); 2971 modes++; 2972 } 2973 } 2974 if (structure & (1 << 8)) { 2975 newmode = drm_display_mode_from_vic_index(connector, video_db, 2976 video_len, 2977 video_index); 2978 if (newmode) { 2979 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2980 drm_mode_probed_add(connector, newmode); 2981 modes++; 2982 } 2983 } 2984 2985 return modes; 2986 } 2987 2988 /* 2989 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2990 * @connector: connector corresponding to the HDMI sink 2991 * @db: start of the CEA vendor specific block 2992 * @len: length of the CEA block payload, ie. one can access up to db[len] 2993 * 2994 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2995 * also adds the stereo 3d modes when applicable. 2996 */ 2997 static int 2998 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2999 const u8 *video_db, u8 video_len) 3000 { 3001 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3002 u8 vic_len, hdmi_3d_len = 0; 3003 u16 mask; 3004 u16 structure_all; 3005 3006 if (len < 8) 3007 goto out; 3008 3009 /* no HDMI_Video_Present */ 3010 if (!(db[8] & (1 << 5))) 3011 goto out; 3012 3013 /* Latency_Fields_Present */ 3014 if (db[8] & (1 << 7)) 3015 offset += 2; 3016 3017 /* I_Latency_Fields_Present */ 3018 if (db[8] & (1 << 6)) 3019 offset += 2; 3020 3021 /* the declared length is not long enough for the 2 first bytes 3022 * of additional video format capabilities */ 3023 if (len < (8 + offset + 2)) 3024 goto out; 3025 3026 /* 3D_Present */ 3027 offset++; 3028 if (db[8 + offset] & (1 << 7)) { 3029 modes += add_hdmi_mandatory_stereo_modes(connector); 3030 3031 /* 3D_Multi_present */ 3032 multi_present = (db[8 + offset] & 0x60) >> 5; 3033 } 3034 3035 offset++; 3036 vic_len = db[8 + offset] >> 5; 3037 hdmi_3d_len = db[8 + offset] & 0x1f; 3038 3039 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3040 u8 vic; 3041 3042 vic = db[9 + offset + i]; 3043 modes += add_hdmi_mode(connector, vic); 3044 } 3045 offset += 1 + vic_len; 3046 3047 if (multi_present == 1) 3048 multi_len = 2; 3049 else if (multi_present == 2) 3050 multi_len = 4; 3051 else 3052 multi_len = 0; 3053 3054 if (len < (8 + offset + hdmi_3d_len - 1)) 3055 goto out; 3056 3057 if (hdmi_3d_len < multi_len) 3058 goto out; 3059 3060 if (multi_present == 1 || multi_present == 2) { 3061 /* 3D_Structure_ALL */ 3062 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3063 3064 /* check if 3D_MASK is present */ 3065 if (multi_present == 2) 3066 mask = (db[10 + offset] << 8) | db[11 + offset]; 3067 else 3068 mask = 0xffff; 3069 3070 for (i = 0; i < 16; i++) { 3071 if (mask & (1 << i)) 3072 modes += add_3d_struct_modes(connector, 3073 structure_all, 3074 video_db, 3075 video_len, i); 3076 } 3077 } 3078 3079 offset += multi_len; 3080 3081 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3082 int vic_index; 3083 struct drm_display_mode *newmode = NULL; 3084 unsigned int newflag = 0; 3085 bool detail_present; 3086 3087 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3088 3089 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3090 break; 3091 3092 /* 2D_VIC_order_X */ 3093 vic_index = db[8 + offset + i] >> 4; 3094 3095 /* 3D_Structure_X */ 3096 switch (db[8 + offset + i] & 0x0f) { 3097 case 0: 3098 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3099 break; 3100 case 6: 3101 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3102 break; 3103 case 8: 3104 /* 3D_Detail_X */ 3105 if ((db[9 + offset + i] >> 4) == 1) 3106 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3107 break; 3108 } 3109 3110 if (newflag != 0) { 3111 newmode = drm_display_mode_from_vic_index(connector, 3112 video_db, 3113 video_len, 3114 vic_index); 3115 3116 if (newmode) { 3117 newmode->flags |= newflag; 3118 drm_mode_probed_add(connector, newmode); 3119 modes++; 3120 } 3121 } 3122 3123 if (detail_present) 3124 i++; 3125 } 3126 3127 out: 3128 return modes; 3129 } 3130 3131 static int 3132 cea_db_payload_len(const u8 *db) 3133 { 3134 return db[0] & 0x1f; 3135 } 3136 3137 static int 3138 cea_db_tag(const u8 *db) 3139 { 3140 return db[0] >> 5; 3141 } 3142 3143 static int 3144 cea_revision(const u8 *cea) 3145 { 3146 return cea[1]; 3147 } 3148 3149 static int 3150 cea_db_offsets(const u8 *cea, int *start, int *end) 3151 { 3152 /* Data block offset in CEA extension block */ 3153 *start = 4; 3154 *end = cea[2]; 3155 if (*end == 0) 3156 *end = 127; 3157 if (*end < 4 || *end > 127) 3158 return -ERANGE; 3159 return 0; 3160 } 3161 3162 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3163 { 3164 int hdmi_id; 3165 3166 if (cea_db_tag(db) != VENDOR_BLOCK) 3167 return false; 3168 3169 if (cea_db_payload_len(db) < 5) 3170 return false; 3171 3172 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3173 3174 return hdmi_id == HDMI_IEEE_OUI; 3175 } 3176 3177 #define for_each_cea_db(cea, i, start, end) \ 3178 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3179 3180 static int 3181 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3182 { 3183 const u8 *cea = drm_find_cea_extension(edid); 3184 const u8 *db, *hdmi = NULL, *video = NULL; 3185 u8 dbl, hdmi_len, video_len = 0; 3186 int modes = 0; 3187 3188 if (cea && cea_revision(cea) >= 3) { 3189 int i, start, end; 3190 3191 if (cea_db_offsets(cea, &start, &end)) 3192 return 0; 3193 3194 for_each_cea_db(cea, i, start, end) { 3195 db = &cea[i]; 3196 dbl = cea_db_payload_len(db); 3197 3198 if (cea_db_tag(db) == VIDEO_BLOCK) { 3199 video = db + 1; 3200 video_len = dbl; 3201 modes += do_cea_modes(connector, video, dbl); 3202 } 3203 else if (cea_db_is_hdmi_vsdb(db)) { 3204 hdmi = db; 3205 hdmi_len = dbl; 3206 } 3207 } 3208 } 3209 3210 /* 3211 * We parse the HDMI VSDB after having added the cea modes as we will 3212 * be patching their flags when the sink supports stereo 3D. 3213 */ 3214 if (hdmi) 3215 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3216 video_len); 3217 3218 return modes; 3219 } 3220 3221 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3222 { 3223 const struct drm_display_mode *cea_mode; 3224 int clock1, clock2, clock; 3225 u8 vic; 3226 const char *type; 3227 3228 /* 3229 * allow 5kHz clock difference either way to account for 3230 * the 10kHz clock resolution limit of detailed timings. 3231 */ 3232 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3233 if (drm_valid_cea_vic(vic)) { 3234 type = "CEA"; 3235 cea_mode = &edid_cea_modes[vic]; 3236 clock1 = cea_mode->clock; 3237 clock2 = cea_mode_alternate_clock(cea_mode); 3238 } else { 3239 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3240 if (drm_valid_hdmi_vic(vic)) { 3241 type = "HDMI"; 3242 cea_mode = &edid_4k_modes[vic]; 3243 clock1 = cea_mode->clock; 3244 clock2 = hdmi_mode_alternate_clock(cea_mode); 3245 } else { 3246 return; 3247 } 3248 } 3249 3250 /* pick whichever is closest */ 3251 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3252 clock = clock1; 3253 else 3254 clock = clock2; 3255 3256 if (mode->clock == clock) 3257 return; 3258 3259 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3260 type, vic, mode->clock, clock); 3261 mode->clock = clock; 3262 } 3263 3264 static void 3265 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3266 { 3267 u8 len = cea_db_payload_len(db); 3268 3269 if (len >= 6) { 3270 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3271 connector->dvi_dual = db[6] & 1; 3272 } 3273 if (len >= 7) 3274 connector->max_tmds_clock = db[7] * 5; 3275 if (len >= 8) { 3276 connector->latency_present[0] = db[8] >> 7; 3277 connector->latency_present[1] = (db[8] >> 6) & 1; 3278 } 3279 if (len >= 9) 3280 connector->video_latency[0] = db[9]; 3281 if (len >= 10) 3282 connector->audio_latency[0] = db[10]; 3283 if (len >= 11) 3284 connector->video_latency[1] = db[11]; 3285 if (len >= 12) 3286 connector->audio_latency[1] = db[12]; 3287 3288 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3289 "max TMDS clock %d, " 3290 "latency present %d %d, " 3291 "video latency %d %d, " 3292 "audio latency %d %d\n", 3293 connector->dvi_dual, 3294 connector->max_tmds_clock, 3295 (int) connector->latency_present[0], 3296 (int) connector->latency_present[1], 3297 connector->video_latency[0], 3298 connector->video_latency[1], 3299 connector->audio_latency[0], 3300 connector->audio_latency[1]); 3301 } 3302 3303 static void 3304 monitor_name(struct detailed_timing *t, void *data) 3305 { 3306 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3307 *(u8 **)data = t->data.other_data.data.str.str; 3308 } 3309 3310 static int get_monitor_name(struct edid *edid, char name[13]) 3311 { 3312 char *edid_name = NULL; 3313 int mnl; 3314 3315 if (!edid || !name) 3316 return 0; 3317 3318 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 3319 for (mnl = 0; edid_name && mnl < 13; mnl++) { 3320 if (edid_name[mnl] == 0x0a) 3321 break; 3322 3323 name[mnl] = edid_name[mnl]; 3324 } 3325 3326 return mnl; 3327 } 3328 3329 /** 3330 * drm_edid_get_monitor_name - fetch the monitor name from the edid 3331 * @edid: monitor EDID information 3332 * @name: pointer to a character array to hold the name of the monitor 3333 * @bufsize: The size of the name buffer (should be at least 14 chars.) 3334 * 3335 */ 3336 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 3337 { 3338 int name_length; 3339 char buf[13]; 3340 3341 if (bufsize <= 0) 3342 return; 3343 3344 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 3345 memcpy(name, buf, name_length); 3346 name[name_length] = '\0'; 3347 } 3348 EXPORT_SYMBOL(drm_edid_get_monitor_name); 3349 3350 /** 3351 * drm_edid_to_eld - build ELD from EDID 3352 * @connector: connector corresponding to the HDMI/DP sink 3353 * @edid: EDID to parse 3354 * 3355 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3356 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to 3357 * fill in. 3358 */ 3359 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3360 { 3361 uint8_t *eld = connector->eld; 3362 u8 *cea; 3363 u8 *db; 3364 int total_sad_count = 0; 3365 int mnl; 3366 int dbl; 3367 3368 memset(eld, 0, sizeof(connector->eld)); 3369 3370 cea = drm_find_cea_extension(edid); 3371 if (!cea) { 3372 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3373 return; 3374 } 3375 3376 mnl = get_monitor_name(edid, eld + 20); 3377 3378 eld[4] = (cea[1] << 5) | mnl; 3379 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3380 3381 eld[0] = 2 << 3; /* ELD version: 2 */ 3382 3383 eld[16] = edid->mfg_id[0]; 3384 eld[17] = edid->mfg_id[1]; 3385 eld[18] = edid->prod_code[0]; 3386 eld[19] = edid->prod_code[1]; 3387 3388 if (cea_revision(cea) >= 3) { 3389 int i, start, end; 3390 3391 if (cea_db_offsets(cea, &start, &end)) { 3392 start = 0; 3393 end = 0; 3394 } 3395 3396 for_each_cea_db(cea, i, start, end) { 3397 db = &cea[i]; 3398 dbl = cea_db_payload_len(db); 3399 3400 switch (cea_db_tag(db)) { 3401 int sad_count; 3402 3403 case AUDIO_BLOCK: 3404 /* Audio Data Block, contains SADs */ 3405 sad_count = min(dbl / 3, 15 - total_sad_count); 3406 if (sad_count >= 1) 3407 memcpy(eld + 20 + mnl + total_sad_count * 3, 3408 &db[1], sad_count * 3); 3409 total_sad_count += sad_count; 3410 break; 3411 case SPEAKER_BLOCK: 3412 /* Speaker Allocation Data Block */ 3413 if (dbl >= 1) 3414 eld[7] = db[1]; 3415 break; 3416 case VENDOR_BLOCK: 3417 /* HDMI Vendor-Specific Data Block */ 3418 if (cea_db_is_hdmi_vsdb(db)) 3419 parse_hdmi_vsdb(connector, db); 3420 break; 3421 default: 3422 break; 3423 } 3424 } 3425 } 3426 eld[5] |= total_sad_count << 4; 3427 3428 eld[DRM_ELD_BASELINE_ELD_LEN] = 3429 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3430 3431 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3432 drm_eld_size(eld), total_sad_count); 3433 } 3434 EXPORT_SYMBOL(drm_edid_to_eld); 3435 3436 /** 3437 * drm_edid_to_sad - extracts SADs from EDID 3438 * @edid: EDID to parse 3439 * @sads: pointer that will be set to the extracted SADs 3440 * 3441 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3442 * 3443 * Note: The returned pointer needs to be freed using kfree(). 3444 * 3445 * Return: The number of found SADs or negative number on error. 3446 */ 3447 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3448 { 3449 int count = 0; 3450 int i, start, end, dbl; 3451 u8 *cea; 3452 3453 cea = drm_find_cea_extension(edid); 3454 if (!cea) { 3455 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3456 return -ENOENT; 3457 } 3458 3459 if (cea_revision(cea) < 3) { 3460 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3461 return -EOPNOTSUPP; 3462 } 3463 3464 if (cea_db_offsets(cea, &start, &end)) { 3465 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3466 return -EPROTO; 3467 } 3468 3469 for_each_cea_db(cea, i, start, end) { 3470 u8 *db = &cea[i]; 3471 3472 if (cea_db_tag(db) == AUDIO_BLOCK) { 3473 int j; 3474 dbl = cea_db_payload_len(db); 3475 3476 count = dbl / 3; /* SAD is 3B */ 3477 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3478 if (!*sads) 3479 return -ENOMEM; 3480 for (j = 0; j < count; j++) { 3481 u8 *sad = &db[1 + j * 3]; 3482 3483 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3484 (*sads)[j].channels = sad[0] & 0x7; 3485 (*sads)[j].freq = sad[1] & 0x7F; 3486 (*sads)[j].byte2 = sad[2]; 3487 } 3488 break; 3489 } 3490 } 3491 3492 return count; 3493 } 3494 EXPORT_SYMBOL(drm_edid_to_sad); 3495 3496 /** 3497 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3498 * @edid: EDID to parse 3499 * @sadb: pointer to the speaker block 3500 * 3501 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3502 * 3503 * Note: The returned pointer needs to be freed using kfree(). 3504 * 3505 * Return: The number of found Speaker Allocation Blocks or negative number on 3506 * error. 3507 */ 3508 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3509 { 3510 int count = 0; 3511 int i, start, end, dbl; 3512 const u8 *cea; 3513 3514 cea = drm_find_cea_extension(edid); 3515 if (!cea) { 3516 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3517 return -ENOENT; 3518 } 3519 3520 if (cea_revision(cea) < 3) { 3521 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3522 return -ENOTSUPP; 3523 } 3524 3525 if (cea_db_offsets(cea, &start, &end)) { 3526 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3527 return -EPROTO; 3528 } 3529 3530 for_each_cea_db(cea, i, start, end) { 3531 const u8 *db = &cea[i]; 3532 3533 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3534 dbl = cea_db_payload_len(db); 3535 3536 /* Speaker Allocation Data Block */ 3537 if (dbl == 3) { 3538 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3539 if (!*sadb) 3540 return -ENOMEM; 3541 count = dbl; 3542 break; 3543 } 3544 } 3545 } 3546 3547 return count; 3548 } 3549 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3550 3551 /** 3552 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3553 * @connector: connector associated with the HDMI/DP sink 3554 * @mode: the display mode 3555 * 3556 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3557 * the sink doesn't support audio or video. 3558 */ 3559 int drm_av_sync_delay(struct drm_connector *connector, 3560 const struct drm_display_mode *mode) 3561 { 3562 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3563 int a, v; 3564 3565 if (!connector->latency_present[0]) 3566 return 0; 3567 if (!connector->latency_present[1]) 3568 i = 0; 3569 3570 a = connector->audio_latency[i]; 3571 v = connector->video_latency[i]; 3572 3573 /* 3574 * HDMI/DP sink doesn't support audio or video? 3575 */ 3576 if (a == 255 || v == 255) 3577 return 0; 3578 3579 /* 3580 * Convert raw EDID values to millisecond. 3581 * Treat unknown latency as 0ms. 3582 */ 3583 if (a) 3584 a = min(2 * (a - 1), 500); 3585 if (v) 3586 v = min(2 * (v - 1), 500); 3587 3588 return max(v - a, 0); 3589 } 3590 EXPORT_SYMBOL(drm_av_sync_delay); 3591 3592 /** 3593 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3594 * @encoder: the encoder just changed display mode 3595 * 3596 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3597 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3598 * 3599 * Return: The connector associated with the first HDMI/DP sink that has ELD 3600 * attached to it. 3601 */ 3602 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3603 { 3604 struct drm_connector *connector; 3605 struct drm_device *dev = encoder->dev; 3606 3607 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3608 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3609 3610 drm_for_each_connector(connector, dev) 3611 if (connector->encoder == encoder && connector->eld[0]) 3612 return connector; 3613 3614 return NULL; 3615 } 3616 EXPORT_SYMBOL(drm_select_eld); 3617 3618 /** 3619 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3620 * @edid: monitor EDID information 3621 * 3622 * Parse the CEA extension according to CEA-861-B. 3623 * 3624 * Return: True if the monitor is HDMI, false if not or unknown. 3625 */ 3626 bool drm_detect_hdmi_monitor(struct edid *edid) 3627 { 3628 u8 *edid_ext; 3629 int i; 3630 int start_offset, end_offset; 3631 3632 edid_ext = drm_find_cea_extension(edid); 3633 if (!edid_ext) 3634 return false; 3635 3636 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3637 return false; 3638 3639 /* 3640 * Because HDMI identifier is in Vendor Specific Block, 3641 * search it from all data blocks of CEA extension. 3642 */ 3643 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3644 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3645 return true; 3646 } 3647 3648 return false; 3649 } 3650 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3651 3652 /** 3653 * drm_detect_monitor_audio - check monitor audio capability 3654 * @edid: EDID block to scan 3655 * 3656 * Monitor should have CEA extension block. 3657 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3658 * audio' only. If there is any audio extension block and supported 3659 * audio format, assume at least 'basic audio' support, even if 'basic 3660 * audio' is not defined in EDID. 3661 * 3662 * Return: True if the monitor supports audio, false otherwise. 3663 */ 3664 bool drm_detect_monitor_audio(struct edid *edid) 3665 { 3666 u8 *edid_ext; 3667 int i, j; 3668 bool has_audio = false; 3669 int start_offset, end_offset; 3670 3671 edid_ext = drm_find_cea_extension(edid); 3672 if (!edid_ext) 3673 goto end; 3674 3675 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3676 3677 if (has_audio) { 3678 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3679 goto end; 3680 } 3681 3682 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3683 goto end; 3684 3685 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3686 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3687 has_audio = true; 3688 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3689 DRM_DEBUG_KMS("CEA audio format %d\n", 3690 (edid_ext[i + j] >> 3) & 0xf); 3691 goto end; 3692 } 3693 } 3694 end: 3695 return has_audio; 3696 } 3697 EXPORT_SYMBOL(drm_detect_monitor_audio); 3698 3699 /** 3700 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3701 * @edid: EDID block to scan 3702 * 3703 * Check whether the monitor reports the RGB quantization range selection 3704 * as supported. The AVI infoframe can then be used to inform the monitor 3705 * which quantization range (full or limited) is used. 3706 * 3707 * Return: True if the RGB quantization range is selectable, false otherwise. 3708 */ 3709 bool drm_rgb_quant_range_selectable(struct edid *edid) 3710 { 3711 u8 *edid_ext; 3712 int i, start, end; 3713 3714 edid_ext = drm_find_cea_extension(edid); 3715 if (!edid_ext) 3716 return false; 3717 3718 if (cea_db_offsets(edid_ext, &start, &end)) 3719 return false; 3720 3721 for_each_cea_db(edid_ext, i, start, end) { 3722 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3723 cea_db_payload_len(&edid_ext[i]) == 2) { 3724 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3725 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3726 } 3727 } 3728 3729 return false; 3730 } 3731 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3732 3733 /** 3734 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3735 * hdmi deep color modes and update drm_display_info if so. 3736 * @edid: monitor EDID information 3737 * @info: Updated with maximum supported deep color bpc and color format 3738 * if deep color supported. 3739 * @connector: DRM connector, used only for debug output 3740 * 3741 * Parse the CEA extension according to CEA-861-B. 3742 * Return true if HDMI deep color supported, false if not or unknown. 3743 */ 3744 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3745 struct drm_display_info *info, 3746 struct drm_connector *connector) 3747 { 3748 u8 *edid_ext, *hdmi; 3749 int i; 3750 int start_offset, end_offset; 3751 unsigned int dc_bpc = 0; 3752 3753 edid_ext = drm_find_cea_extension(edid); 3754 if (!edid_ext) 3755 return false; 3756 3757 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3758 return false; 3759 3760 /* 3761 * Because HDMI identifier is in Vendor Specific Block, 3762 * search it from all data blocks of CEA extension. 3763 */ 3764 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3765 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3766 /* HDMI supports at least 8 bpc */ 3767 info->bpc = 8; 3768 3769 hdmi = &edid_ext[i]; 3770 if (cea_db_payload_len(hdmi) < 6) 3771 return false; 3772 3773 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3774 dc_bpc = 10; 3775 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3776 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3777 connector->name); 3778 } 3779 3780 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3781 dc_bpc = 12; 3782 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3783 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3784 connector->name); 3785 } 3786 3787 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3788 dc_bpc = 16; 3789 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3790 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3791 connector->name); 3792 } 3793 3794 if (dc_bpc > 0) { 3795 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3796 connector->name, dc_bpc); 3797 info->bpc = dc_bpc; 3798 3799 /* 3800 * Deep color support mandates RGB444 support for all video 3801 * modes and forbids YCRCB422 support for all video modes per 3802 * HDMI 1.3 spec. 3803 */ 3804 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3805 3806 /* YCRCB444 is optional according to spec. */ 3807 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3808 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3809 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3810 connector->name); 3811 } 3812 3813 /* 3814 * Spec says that if any deep color mode is supported at all, 3815 * then deep color 36 bit must be supported. 3816 */ 3817 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3818 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3819 connector->name); 3820 } 3821 3822 return true; 3823 } 3824 else { 3825 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3826 connector->name); 3827 } 3828 } 3829 } 3830 3831 return false; 3832 } 3833 3834 /** 3835 * drm_add_display_info - pull display info out if present 3836 * @edid: EDID data 3837 * @info: display info (attached to connector) 3838 * @connector: connector whose edid is used to build display info 3839 * 3840 * Grab any available display info and stuff it into the drm_display_info 3841 * structure that's part of the connector. Useful for tracking bpp and 3842 * color spaces. 3843 */ 3844 static void drm_add_display_info(struct edid *edid, 3845 struct drm_display_info *info, 3846 struct drm_connector *connector) 3847 { 3848 u8 *edid_ext; 3849 3850 info->width_mm = edid->width_cm * 10; 3851 info->height_mm = edid->height_cm * 10; 3852 3853 /* driver figures it out in this case */ 3854 info->bpc = 0; 3855 info->color_formats = 0; 3856 3857 if (edid->revision < 3) 3858 return; 3859 3860 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3861 return; 3862 3863 /* Get data from CEA blocks if present */ 3864 edid_ext = drm_find_cea_extension(edid); 3865 if (edid_ext) { 3866 info->cea_rev = edid_ext[1]; 3867 3868 /* The existence of a CEA block should imply RGB support */ 3869 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3870 if (edid_ext[3] & EDID_CEA_YCRCB444) 3871 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3872 if (edid_ext[3] & EDID_CEA_YCRCB422) 3873 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3874 } 3875 3876 /* HDMI deep color modes supported? Assign to info, if so */ 3877 drm_assign_hdmi_deep_color_info(edid, info, connector); 3878 3879 /* Only defined for 1.4 with digital displays */ 3880 if (edid->revision < 4) 3881 return; 3882 3883 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3884 case DRM_EDID_DIGITAL_DEPTH_6: 3885 info->bpc = 6; 3886 break; 3887 case DRM_EDID_DIGITAL_DEPTH_8: 3888 info->bpc = 8; 3889 break; 3890 case DRM_EDID_DIGITAL_DEPTH_10: 3891 info->bpc = 10; 3892 break; 3893 case DRM_EDID_DIGITAL_DEPTH_12: 3894 info->bpc = 12; 3895 break; 3896 case DRM_EDID_DIGITAL_DEPTH_14: 3897 info->bpc = 14; 3898 break; 3899 case DRM_EDID_DIGITAL_DEPTH_16: 3900 info->bpc = 16; 3901 break; 3902 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3903 default: 3904 info->bpc = 0; 3905 break; 3906 } 3907 3908 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3909 connector->name, info->bpc); 3910 3911 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3912 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3913 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3914 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3915 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3916 } 3917 3918 static int validate_displayid(u8 *displayid, int length, int idx) 3919 { 3920 int i; 3921 u8 csum = 0; 3922 struct displayid_hdr *base; 3923 3924 base = (struct displayid_hdr *)&displayid[idx]; 3925 3926 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 3927 base->rev, base->bytes, base->prod_id, base->ext_count); 3928 3929 if (base->bytes + 5 > length - idx) 3930 return -EINVAL; 3931 for (i = idx; i <= base->bytes + 5; i++) { 3932 csum += displayid[i]; 3933 } 3934 if (csum) { 3935 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); 3936 return -EINVAL; 3937 } 3938 return 0; 3939 } 3940 3941 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 3942 struct displayid_detailed_timings_1 *timings) 3943 { 3944 struct drm_display_mode *mode; 3945 unsigned pixel_clock = (timings->pixel_clock[0] | 3946 (timings->pixel_clock[1] << 8) | 3947 (timings->pixel_clock[2] << 16)); 3948 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 3949 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 3950 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 3951 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 3952 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 3953 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 3954 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 3955 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 3956 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 3957 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 3958 mode = drm_mode_create(dev); 3959 if (!mode) 3960 return NULL; 3961 3962 mode->clock = pixel_clock * 10; 3963 mode->hdisplay = hactive; 3964 mode->hsync_start = mode->hdisplay + hsync; 3965 mode->hsync_end = mode->hsync_start + hsync_width; 3966 mode->htotal = mode->hdisplay + hblank; 3967 3968 mode->vdisplay = vactive; 3969 mode->vsync_start = mode->vdisplay + vsync; 3970 mode->vsync_end = mode->vsync_start + vsync_width; 3971 mode->vtotal = mode->vdisplay + vblank; 3972 3973 mode->flags = 0; 3974 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3975 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3976 mode->type = DRM_MODE_TYPE_DRIVER; 3977 3978 if (timings->flags & 0x80) 3979 mode->type |= DRM_MODE_TYPE_PREFERRED; 3980 mode->vrefresh = drm_mode_vrefresh(mode); 3981 drm_mode_set_name(mode); 3982 3983 return mode; 3984 } 3985 3986 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 3987 struct displayid_block *block) 3988 { 3989 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 3990 int i; 3991 int num_timings; 3992 struct drm_display_mode *newmode; 3993 int num_modes = 0; 3994 /* blocks must be multiple of 20 bytes length */ 3995 if (block->num_bytes % 20) 3996 return 0; 3997 3998 num_timings = block->num_bytes / 20; 3999 for (i = 0; i < num_timings; i++) { 4000 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 4001 4002 newmode = drm_mode_displayid_detailed(connector->dev, timings); 4003 if (!newmode) 4004 continue; 4005 4006 drm_mode_probed_add(connector, newmode); 4007 num_modes++; 4008 } 4009 return num_modes; 4010 } 4011 4012 static int add_displayid_detailed_modes(struct drm_connector *connector, 4013 struct edid *edid) 4014 { 4015 u8 *displayid; 4016 int ret; 4017 int idx = 1; 4018 int length = EDID_LENGTH; 4019 struct displayid_block *block; 4020 int num_modes = 0; 4021 4022 displayid = drm_find_displayid_extension(edid); 4023 if (!displayid) 4024 return 0; 4025 4026 ret = validate_displayid(displayid, length, idx); 4027 if (ret) 4028 return 0; 4029 4030 idx += sizeof(struct displayid_hdr); 4031 while (block = (struct displayid_block *)&displayid[idx], 4032 idx + sizeof(struct displayid_block) <= length && 4033 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4034 block->num_bytes > 0) { 4035 idx += block->num_bytes + sizeof(struct displayid_block); 4036 switch (block->tag) { 4037 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4038 num_modes += add_displayid_detailed_1_modes(connector, block); 4039 break; 4040 } 4041 } 4042 return num_modes; 4043 } 4044 4045 /** 4046 * drm_add_edid_modes - add modes from EDID data, if available 4047 * @connector: connector we're probing 4048 * @edid: EDID data 4049 * 4050 * Add the specified modes to the connector's mode list. 4051 * 4052 * Return: The number of modes added or 0 if we couldn't find any. 4053 */ 4054 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 4055 { 4056 int num_modes = 0; 4057 u32 quirks; 4058 4059 if (edid == NULL) { 4060 return 0; 4061 } 4062 if (!drm_edid_is_valid(edid)) { 4063 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 4064 connector->name); 4065 return 0; 4066 } 4067 4068 quirks = edid_get_quirks(edid); 4069 4070 /* 4071 * EDID spec says modes should be preferred in this order: 4072 * - preferred detailed mode 4073 * - other detailed modes from base block 4074 * - detailed modes from extension blocks 4075 * - CVT 3-byte code modes 4076 * - standard timing codes 4077 * - established timing codes 4078 * - modes inferred from GTF or CVT range information 4079 * 4080 * We get this pretty much right. 4081 * 4082 * XXX order for additional mode types in extension blocks? 4083 */ 4084 num_modes += add_detailed_modes(connector, edid, quirks); 4085 num_modes += add_cvt_modes(connector, edid); 4086 num_modes += add_standard_modes(connector, edid); 4087 num_modes += add_established_modes(connector, edid); 4088 num_modes += add_cea_modes(connector, edid); 4089 num_modes += add_alternate_cea_modes(connector, edid); 4090 num_modes += add_displayid_detailed_modes(connector, edid); 4091 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 4092 num_modes += add_inferred_modes(connector, edid); 4093 4094 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 4095 edid_fixup_preferred(connector, quirks); 4096 4097 drm_add_display_info(edid, &connector->display_info, connector); 4098 4099 if (quirks & EDID_QUIRK_FORCE_6BPC) 4100 connector->display_info.bpc = 6; 4101 4102 if (quirks & EDID_QUIRK_FORCE_8BPC) 4103 connector->display_info.bpc = 8; 4104 4105 if (quirks & EDID_QUIRK_FORCE_12BPC) 4106 connector->display_info.bpc = 12; 4107 4108 return num_modes; 4109 } 4110 EXPORT_SYMBOL(drm_add_edid_modes); 4111 4112 /** 4113 * drm_add_modes_noedid - add modes for the connectors without EDID 4114 * @connector: connector we're probing 4115 * @hdisplay: the horizontal display limit 4116 * @vdisplay: the vertical display limit 4117 * 4118 * Add the specified modes to the connector's mode list. Only when the 4119 * hdisplay/vdisplay is not beyond the given limit, it will be added. 4120 * 4121 * Return: The number of modes added or 0 if we couldn't find any. 4122 */ 4123 int drm_add_modes_noedid(struct drm_connector *connector, 4124 int hdisplay, int vdisplay) 4125 { 4126 int i, count, num_modes = 0; 4127 struct drm_display_mode *mode; 4128 struct drm_device *dev = connector->dev; 4129 4130 count = ARRAY_SIZE(drm_dmt_modes); 4131 if (hdisplay < 0) 4132 hdisplay = 0; 4133 if (vdisplay < 0) 4134 vdisplay = 0; 4135 4136 for (i = 0; i < count; i++) { 4137 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4138 if (hdisplay && vdisplay) { 4139 /* 4140 * Only when two are valid, they will be used to check 4141 * whether the mode should be added to the mode list of 4142 * the connector. 4143 */ 4144 if (ptr->hdisplay > hdisplay || 4145 ptr->vdisplay > vdisplay) 4146 continue; 4147 } 4148 if (drm_mode_vrefresh(ptr) > 61) 4149 continue; 4150 mode = drm_mode_duplicate(dev, ptr); 4151 if (mode) { 4152 drm_mode_probed_add(connector, mode); 4153 num_modes++; 4154 } 4155 } 4156 return num_modes; 4157 } 4158 EXPORT_SYMBOL(drm_add_modes_noedid); 4159 4160 /** 4161 * drm_set_preferred_mode - Sets the preferred mode of a connector 4162 * @connector: connector whose mode list should be processed 4163 * @hpref: horizontal resolution of preferred mode 4164 * @vpref: vertical resolution of preferred mode 4165 * 4166 * Marks a mode as preferred if it matches the resolution specified by @hpref 4167 * and @vpref. 4168 */ 4169 void drm_set_preferred_mode(struct drm_connector *connector, 4170 int hpref, int vpref) 4171 { 4172 struct drm_display_mode *mode; 4173 4174 list_for_each_entry(mode, &connector->probed_modes, head) { 4175 if (mode->hdisplay == hpref && 4176 mode->vdisplay == vpref) 4177 mode->type |= DRM_MODE_TYPE_PREFERRED; 4178 } 4179 } 4180 EXPORT_SYMBOL(drm_set_preferred_mode); 4181 4182 /** 4183 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 4184 * data from a DRM display mode 4185 * @frame: HDMI AVI infoframe 4186 * @mode: DRM display mode 4187 * 4188 * Return: 0 on success or a negative error code on failure. 4189 */ 4190 int 4191 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 4192 const struct drm_display_mode *mode) 4193 { 4194 int err; 4195 4196 if (!frame || !mode) 4197 return -EINVAL; 4198 4199 err = hdmi_avi_infoframe_init(frame); 4200 if (err < 0) 4201 return err; 4202 4203 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 4204 frame->pixel_repeat = 1; 4205 4206 frame->video_code = drm_match_cea_mode(mode); 4207 4208 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 4209 4210 /* 4211 * Populate picture aspect ratio from either 4212 * user input (if specified) or from the CEA mode list. 4213 */ 4214 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 4215 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 4216 frame->picture_aspect = mode->picture_aspect_ratio; 4217 else if (frame->video_code > 0) 4218 frame->picture_aspect = drm_get_cea_aspect_ratio( 4219 frame->video_code); 4220 4221 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 4222 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 4223 4224 return 0; 4225 } 4226 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 4227 4228 static enum hdmi_3d_structure 4229 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 4230 { 4231 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 4232 4233 switch (layout) { 4234 case DRM_MODE_FLAG_3D_FRAME_PACKING: 4235 return HDMI_3D_STRUCTURE_FRAME_PACKING; 4236 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4237 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4238 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4239 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4240 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4241 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4242 case DRM_MODE_FLAG_3D_L_DEPTH: 4243 return HDMI_3D_STRUCTURE_L_DEPTH; 4244 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4245 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4246 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4247 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4248 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4249 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4250 default: 4251 return HDMI_3D_STRUCTURE_INVALID; 4252 } 4253 } 4254 4255 /** 4256 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4257 * data from a DRM display mode 4258 * @frame: HDMI vendor infoframe 4259 * @mode: DRM display mode 4260 * 4261 * Note that there's is a need to send HDMI vendor infoframes only when using a 4262 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4263 * function will return -EINVAL, error that can be safely ignored. 4264 * 4265 * Return: 0 on success or a negative error code on failure. 4266 */ 4267 int 4268 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4269 const struct drm_display_mode *mode) 4270 { 4271 int err; 4272 u32 s3d_flags; 4273 u8 vic; 4274 4275 if (!frame || !mode) 4276 return -EINVAL; 4277 4278 vic = drm_match_hdmi_mode(mode); 4279 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4280 4281 if (!vic && !s3d_flags) 4282 return -EINVAL; 4283 4284 if (vic && s3d_flags) 4285 return -EINVAL; 4286 4287 err = hdmi_vendor_infoframe_init(frame); 4288 if (err < 0) 4289 return err; 4290 4291 if (vic) 4292 frame->vic = vic; 4293 else 4294 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4295 4296 return 0; 4297 } 4298 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4299 4300 static int drm_parse_tiled_block(struct drm_connector *connector, 4301 struct displayid_block *block) 4302 { 4303 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4304 u16 w, h; 4305 u8 tile_v_loc, tile_h_loc; 4306 u8 num_v_tile, num_h_tile; 4307 struct drm_tile_group *tg; 4308 4309 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4310 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4311 4312 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4313 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4314 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4315 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4316 4317 connector->has_tile = true; 4318 if (tile->tile_cap & 0x80) 4319 connector->tile_is_single_monitor = true; 4320 4321 connector->num_h_tile = num_h_tile + 1; 4322 connector->num_v_tile = num_v_tile + 1; 4323 connector->tile_h_loc = tile_h_loc; 4324 connector->tile_v_loc = tile_v_loc; 4325 connector->tile_h_size = w + 1; 4326 connector->tile_v_size = h + 1; 4327 4328 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4329 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4330 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4331 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4332 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4333 4334 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4335 if (!tg) { 4336 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4337 } 4338 if (!tg) 4339 return -ENOMEM; 4340 4341 if (connector->tile_group != tg) { 4342 /* if we haven't got a pointer, 4343 take the reference, drop ref to old tile group */ 4344 if (connector->tile_group) { 4345 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4346 } 4347 connector->tile_group = tg; 4348 } else 4349 /* if same tile group, then release the ref we just took. */ 4350 drm_mode_put_tile_group(connector->dev, tg); 4351 return 0; 4352 } 4353 4354 static int drm_parse_display_id(struct drm_connector *connector, 4355 u8 *displayid, int length, 4356 bool is_edid_extension) 4357 { 4358 /* if this is an EDID extension the first byte will be 0x70 */ 4359 int idx = 0; 4360 struct displayid_block *block; 4361 int ret; 4362 4363 if (is_edid_extension) 4364 idx = 1; 4365 4366 ret = validate_displayid(displayid, length, idx); 4367 if (ret) 4368 return ret; 4369 4370 idx += sizeof(struct displayid_hdr); 4371 while (block = (struct displayid_block *)&displayid[idx], 4372 idx + sizeof(struct displayid_block) <= length && 4373 idx + sizeof(struct displayid_block) + block->num_bytes <= length && 4374 block->num_bytes > 0) { 4375 idx += block->num_bytes + sizeof(struct displayid_block); 4376 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 4377 block->tag, block->rev, block->num_bytes); 4378 4379 switch (block->tag) { 4380 case DATA_BLOCK_TILED_DISPLAY: 4381 ret = drm_parse_tiled_block(connector, block); 4382 if (ret) 4383 return ret; 4384 break; 4385 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 4386 /* handled in mode gathering code. */ 4387 break; 4388 default: 4389 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 4390 break; 4391 } 4392 } 4393 return 0; 4394 } 4395 4396 static void drm_get_displayid(struct drm_connector *connector, 4397 struct edid *edid) 4398 { 4399 void *displayid = NULL; 4400 int ret; 4401 connector->has_tile = false; 4402 displayid = drm_find_displayid_extension(edid); 4403 if (!displayid) { 4404 /* drop reference to any tile group we had */ 4405 goto out_drop_ref; 4406 } 4407 4408 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4409 if (ret < 0) 4410 goto out_drop_ref; 4411 if (!connector->has_tile) 4412 goto out_drop_ref; 4413 return; 4414 out_drop_ref: 4415 if (connector->tile_group) { 4416 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4417 connector->tile_group = NULL; 4418 } 4419 return; 4420 } 4421