1 /************************************************************************** 2 3 Copyright © 2006 Dave Airlie 4 5 All Rights Reserved. 6 7 Permission is hereby granted, free of charge, to any person obtaining a 8 copy of this software and associated documentation files (the 9 "Software"), to deal in the Software without restriction, including 10 without limitation the rights to use, copy, modify, merge, publish, 11 distribute, sub license, and/or sell copies of the Software, and to 12 permit persons to whom the Software is furnished to do so, subject to 13 the following conditions: 14 15 The above copyright notice and this permission notice (including the 16 next paragraph) shall be included in all copies or substantial portions 17 of the Software. 18 19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 27 **************************************************************************/ 28 29 #include "dvo.h" 30 31 #define CH7xxx_REG_VID 0x4a 32 #define CH7xxx_REG_DID 0x4b 33 34 #define CH7011_VID 0x83 /* 7010 as well */ 35 #define CH7010B_VID 0x05 36 #define CH7009A_VID 0x84 37 #define CH7009B_VID 0x85 38 #define CH7301_VID 0x95 39 40 #define CH7xxx_VID 0x84 41 #define CH7xxx_DID 0x17 42 #define CH7010_DID 0x16 43 44 #define CH7xxx_NUM_REGS 0x4c 45 46 #define CH7xxx_CM 0x1c 47 #define CH7xxx_CM_XCM (1<<0) 48 #define CH7xxx_CM_MCP (1<<2) 49 #define CH7xxx_INPUT_CLOCK 0x1d 50 #define CH7xxx_GPIO 0x1e 51 #define CH7xxx_GPIO_HPIR (1<<3) 52 #define CH7xxx_IDF 0x1f 53 54 #define CH7xxx_IDF_HSP (1<<3) 55 #define CH7xxx_IDF_VSP (1<<4) 56 57 #define CH7xxx_CONNECTION_DETECT 0x20 58 #define CH7xxx_CDET_DVI (1<<5) 59 60 #define CH7301_DAC_CNTL 0x21 61 #define CH7301_HOTPLUG 0x23 62 #define CH7xxx_TCTL 0x31 63 #define CH7xxx_TVCO 0x32 64 #define CH7xxx_TPCP 0x33 65 #define CH7xxx_TPD 0x34 66 #define CH7xxx_TPVT 0x35 67 #define CH7xxx_TLPF 0x36 68 #define CH7xxx_TCT 0x37 69 #define CH7301_TEST_PATTERN 0x48 70 71 #define CH7xxx_PM 0x49 72 #define CH7xxx_PM_FPD (1<<0) 73 #define CH7301_PM_DACPD0 (1<<1) 74 #define CH7301_PM_DACPD1 (1<<2) 75 #define CH7301_PM_DACPD2 (1<<3) 76 #define CH7xxx_PM_DVIL (1<<6) 77 #define CH7xxx_PM_DVIP (1<<7) 78 79 #define CH7301_SYNC_POLARITY 0x56 80 #define CH7301_SYNC_RGB_YUV (1<<0) 81 #define CH7301_SYNC_POL_DVI (1<<5) 82 83 /** @file 84 * driver for the Chrontel 7xxx DVI chip over DVO. 85 */ 86 87 static struct ch7xxx_id_struct { 88 uint8_t vid; 89 char *name; 90 } ch7xxx_ids[] = { 91 { CH7011_VID, "CH7011" }, 92 { CH7010B_VID, "CH7010B" }, 93 { CH7009A_VID, "CH7009A" }, 94 { CH7009B_VID, "CH7009B" }, 95 { CH7301_VID, "CH7301" }, 96 }; 97 98 static struct ch7xxx_did_struct { 99 uint8_t did; 100 char *name; 101 } ch7xxx_dids[] = { 102 { CH7xxx_DID, "CH7XXX" }, 103 { CH7010_DID, "CH7010B" }, 104 }; 105 106 struct ch7xxx_priv { 107 bool quiet; 108 }; 109 110 static char *ch7xxx_get_id(uint8_t vid) 111 { 112 int i; 113 114 for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) { 115 if (ch7xxx_ids[i].vid == vid) 116 return ch7xxx_ids[i].name; 117 } 118 119 return NULL; 120 } 121 122 static char *ch7xxx_get_did(uint8_t did) 123 { 124 int i; 125 126 for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) { 127 if (ch7xxx_dids[i].did == did) 128 return ch7xxx_dids[i].name; 129 } 130 131 return NULL; 132 } 133 134 /** Reads an 8 bit register */ 135 static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) 136 { 137 struct intel_iic_softc *sc; 138 struct ch7xxx_priv *ch7xxx = dvo->dev_priv; 139 struct i2c_adapter *adapter = dvo->i2c_bus; 140 u8 out_buf[2]; 141 u8 in_buf[2]; 142 143 struct i2c_msg msgs[] = { 144 { 145 .slave = dvo->slave_addr << 1, 146 .flags = 0, 147 .len = 1, 148 .buf = out_buf, 149 }, 150 { 151 .slave = dvo->slave_addr << 1, 152 .flags = I2C_M_RD, 153 .len = 1, 154 .buf = in_buf, 155 } 156 }; 157 158 *ch = 0; /* silence gcc warning */ 159 out_buf[0] = addr; 160 out_buf[1] = 0; 161 162 sc = device_get_softc(adapter); 163 164 if (iicbus_transfer(adapter, msgs, 2) == 0) { 165 *ch = in_buf[0]; 166 return true; 167 } 168 169 if (!ch7xxx->quiet) { 170 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", 171 addr, sc->name, dvo->slave_addr); 172 } 173 return false; 174 } 175 176 /** Writes an 8 bit register */ 177 static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) 178 { 179 struct intel_iic_softc *sc; 180 struct ch7xxx_priv *ch7xxx = dvo->dev_priv; 181 struct i2c_adapter *adapter = dvo->i2c_bus; 182 uint8_t out_buf[2]; 183 struct i2c_msg msg = { 184 .slave = dvo->slave_addr << 1, 185 .flags = 0, 186 .len = 2, 187 .buf = out_buf, 188 }; 189 190 out_buf[0] = addr; 191 out_buf[1] = ch; 192 193 sc = device_get_softc(adapter); 194 195 if (iicbus_transfer(adapter, &msg, 1) == 0) 196 return true; 197 198 if (!ch7xxx->quiet) { 199 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 200 addr, sc->name, dvo->slave_addr); 201 } 202 203 return false; 204 } 205 206 static bool ch7xxx_init(struct intel_dvo_device *dvo, 207 struct i2c_adapter *adapter) 208 { 209 struct intel_iic_softc *sc; 210 /* this will detect the CH7xxx chip on the specified i2c bus */ 211 struct ch7xxx_priv *ch7xxx; 212 uint8_t vendor, device; 213 char *name, *devid; 214 215 sc = device_get_softc(adapter); 216 217 ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL); 218 if (ch7xxx == NULL) 219 return false; 220 221 dvo->i2c_bus = adapter; 222 dvo->dev_priv = ch7xxx; 223 ch7xxx->quiet = true; 224 225 if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor)) 226 goto out; 227 228 name = ch7xxx_get_id(vendor); 229 if (!name) { 230 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " 231 "slave %d.\n", 232 vendor, sc->name, dvo->slave_addr); 233 goto out; 234 } 235 236 237 if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device)) 238 goto out; 239 240 devid = ch7xxx_get_did(device); 241 if (!devid) { 242 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " 243 "slave %d.\n", 244 vendor, sc->name, dvo->slave_addr); 245 goto out; 246 } 247 248 ch7xxx->quiet = false; 249 DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n", 250 name, vendor, device); 251 return true; 252 out: 253 kfree(ch7xxx); 254 return false; 255 } 256 257 static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo) 258 { 259 uint8_t cdet, orig_pm, pm; 260 261 ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm); 262 263 pm = orig_pm; 264 pm &= ~CH7xxx_PM_FPD; 265 pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP; 266 267 ch7xxx_writeb(dvo, CH7xxx_PM, pm); 268 269 ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet); 270 271 ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm); 272 273 if (cdet & CH7xxx_CDET_DVI) 274 return connector_status_connected; 275 return connector_status_disconnected; 276 } 277 278 static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo, 279 struct drm_display_mode *mode) 280 { 281 if (mode->clock > 165000) 282 return MODE_CLOCK_HIGH; 283 284 return MODE_OK; 285 } 286 287 static void ch7xxx_mode_set(struct intel_dvo_device *dvo, 288 const struct drm_display_mode *mode, 289 const struct drm_display_mode *adjusted_mode) 290 { 291 uint8_t tvco, tpcp, tpd, tlpf, idf; 292 293 if (mode->clock <= 65000) { 294 tvco = 0x23; 295 tpcp = 0x08; 296 tpd = 0x16; 297 tlpf = 0x60; 298 } else { 299 tvco = 0x2d; 300 tpcp = 0x06; 301 tpd = 0x26; 302 tlpf = 0xa0; 303 } 304 305 ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00); 306 ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco); 307 ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp); 308 ch7xxx_writeb(dvo, CH7xxx_TPD, tpd); 309 ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30); 310 ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf); 311 ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00); 312 313 ch7xxx_readb(dvo, CH7xxx_IDF, &idf); 314 315 idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP); 316 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 317 idf |= CH7xxx_IDF_HSP; 318 319 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 320 idf |= CH7xxx_IDF_VSP; 321 322 ch7xxx_writeb(dvo, CH7xxx_IDF, idf); 323 } 324 325 /* set the CH7xxx power state */ 326 static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable) 327 { 328 if (enable) 329 ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP); 330 else 331 ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD); 332 } 333 334 static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo) 335 { 336 u8 val; 337 338 ch7xxx_readb(dvo, CH7xxx_PM, &val); 339 340 if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP)) 341 return true; 342 else 343 return false; 344 } 345 346 static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) 347 { 348 int i; 349 350 for (i = 0; i < CH7xxx_NUM_REGS; i++) { 351 uint8_t val; 352 if ((i % 8) == 0) 353 DRM_DEBUG_KMS("\n %02X: ", i); 354 ch7xxx_readb(dvo, i, &val); 355 DRM_DEBUG_KMS("%02X ", val); 356 } 357 } 358 359 static void ch7xxx_destroy(struct intel_dvo_device *dvo) 360 { 361 struct ch7xxx_priv *ch7xxx = dvo->dev_priv; 362 363 if (ch7xxx) { 364 kfree(ch7xxx); 365 dvo->dev_priv = NULL; 366 } 367 } 368 369 struct intel_dvo_dev_ops ch7xxx_ops = { 370 .init = ch7xxx_init, 371 .detect = ch7xxx_detect, 372 .mode_valid = ch7xxx_mode_valid, 373 .mode_set = ch7xxx_mode_set, 374 .dpms = ch7xxx_dpms, 375 .get_hw_state = ch7xxx_get_hw_state, 376 .dump_regs = ch7xxx_dump_regs, 377 .destroy = ch7xxx_destroy, 378 }; 379