1 /************************************************************************** 2 3 Copyright © 2006 Dave Airlie 4 5 All Rights Reserved. 6 7 Permission is hereby granted, free of charge, to any person obtaining a 8 copy of this software and associated documentation files (the 9 "Software"), to deal in the Software without restriction, including 10 without limitation the rights to use, copy, modify, merge, publish, 11 distribute, sub license, and/or sell copies of the Software, and to 12 permit persons to whom the Software is furnished to do so, subject to 13 the following conditions: 14 15 The above copyright notice and this permission notice (including the 16 next paragraph) shall be included in all copies or substantial portions 17 of the Software. 18 19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 27 **************************************************************************/ 28 29 #include "dvo.h" 30 31 #define CH7xxx_REG_VID 0x4a 32 #define CH7xxx_REG_DID 0x4b 33 34 #define CH7011_VID 0x83 /* 7010 as well */ 35 #define CH7010B_VID 0x05 36 #define CH7009A_VID 0x84 37 #define CH7009B_VID 0x85 38 #define CH7301_VID 0x95 39 40 #define CH7xxx_VID 0x84 41 #define CH7xxx_DID 0x17 42 #define CH7010_DID 0x16 43 44 #define CH7xxx_NUM_REGS 0x4c 45 46 #define CH7xxx_CM 0x1c 47 #define CH7xxx_CM_XCM (1<<0) 48 #define CH7xxx_CM_MCP (1<<2) 49 #define CH7xxx_INPUT_CLOCK 0x1d 50 #define CH7xxx_GPIO 0x1e 51 #define CH7xxx_GPIO_HPIR (1<<3) 52 #define CH7xxx_IDF 0x1f 53 54 #define CH7xxx_IDF_HSP (1<<3) 55 #define CH7xxx_IDF_VSP (1<<4) 56 57 #define CH7xxx_CONNECTION_DETECT 0x20 58 #define CH7xxx_CDET_DVI (1<<5) 59 60 #define CH7301_DAC_CNTL 0x21 61 #define CH7301_HOTPLUG 0x23 62 #define CH7xxx_TCTL 0x31 63 #define CH7xxx_TVCO 0x32 64 #define CH7xxx_TPCP 0x33 65 #define CH7xxx_TPD 0x34 66 #define CH7xxx_TPVT 0x35 67 #define CH7xxx_TLPF 0x36 68 #define CH7xxx_TCT 0x37 69 #define CH7301_TEST_PATTERN 0x48 70 71 #define CH7xxx_PM 0x49 72 #define CH7xxx_PM_FPD (1<<0) 73 #define CH7301_PM_DACPD0 (1<<1) 74 #define CH7301_PM_DACPD1 (1<<2) 75 #define CH7301_PM_DACPD2 (1<<3) 76 #define CH7xxx_PM_DVIL (1<<6) 77 #define CH7xxx_PM_DVIP (1<<7) 78 79 #define CH7301_SYNC_POLARITY 0x56 80 #define CH7301_SYNC_RGB_YUV (1<<0) 81 #define CH7301_SYNC_POL_DVI (1<<5) 82 83 /** @file 84 * driver for the Chrontel 7xxx DVI chip over DVO. 85 */ 86 87 static struct ch7xxx_id_struct { 88 uint8_t vid; 89 char *name; 90 } ch7xxx_ids[] = { 91 { CH7011_VID, "CH7011" }, 92 { CH7010B_VID, "CH7010B" }, 93 { CH7009A_VID, "CH7009A" }, 94 { CH7009B_VID, "CH7009B" }, 95 { CH7301_VID, "CH7301" }, 96 }; 97 98 static struct ch7xxx_did_struct { 99 uint8_t did; 100 char *name; 101 } ch7xxx_dids[] = { 102 { CH7xxx_DID, "CH7XXX" }, 103 { CH7010_DID, "CH7010B" }, 104 }; 105 106 struct ch7xxx_priv { 107 bool quiet; 108 }; 109 110 static char *ch7xxx_get_id(uint8_t vid) 111 { 112 int i; 113 114 for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) { 115 if (ch7xxx_ids[i].vid == vid) 116 return ch7xxx_ids[i].name; 117 } 118 119 return NULL; 120 } 121 122 static char *ch7xxx_get_did(uint8_t did) 123 { 124 int i; 125 126 for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) { 127 if (ch7xxx_dids[i].did == did) 128 return ch7xxx_dids[i].name; 129 } 130 131 return NULL; 132 } 133 134 /** Reads an 8 bit register */ 135 static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) 136 { 137 struct ch7xxx_priv *ch7xxx = dvo->dev_priv; 138 struct i2c_adapter *adapter = dvo->i2c_bus; 139 u8 out_buf[2]; 140 u8 in_buf[2]; 141 142 struct i2c_msg msgs[] = { 143 { 144 .addr = dvo->slave_addr, 145 .flags = 0, 146 .len = 1, 147 .buf = out_buf, 148 }, 149 { 150 .addr = dvo->slave_addr, 151 .flags = I2C_M_RD, 152 .len = 1, 153 .buf = in_buf, 154 } 155 }; 156 157 *ch = 0; /* silence gcc warning */ 158 out_buf[0] = addr; 159 out_buf[1] = 0; 160 161 if (i2c_transfer(adapter, msgs, 2) == 2) { 162 *ch = in_buf[0]; 163 return true; 164 } 165 166 if (!ch7xxx->quiet) { 167 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", 168 addr, adapter->name, dvo->slave_addr); 169 } 170 return false; 171 } 172 173 /** Writes an 8 bit register */ 174 static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) 175 { 176 struct ch7xxx_priv *ch7xxx = dvo->dev_priv; 177 struct i2c_adapter *adapter = dvo->i2c_bus; 178 uint8_t out_buf[2]; 179 struct i2c_msg msg = { 180 .addr = dvo->slave_addr, 181 .flags = 0, 182 .len = 2, 183 .buf = out_buf, 184 }; 185 186 out_buf[0] = addr; 187 out_buf[1] = ch; 188 189 if (i2c_transfer(adapter, &msg, 1) == 1) 190 return true; 191 192 if (!ch7xxx->quiet) { 193 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 194 addr, adapter->name, dvo->slave_addr); 195 } 196 197 return false; 198 } 199 200 static bool ch7xxx_init(struct intel_dvo_device *dvo, 201 struct i2c_adapter *adapter) 202 { 203 /* this will detect the CH7xxx chip on the specified i2c bus */ 204 struct ch7xxx_priv *ch7xxx; 205 uint8_t vendor, device; 206 char *name, *devid; 207 208 ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL); 209 if (ch7xxx == NULL) 210 return false; 211 212 dvo->i2c_bus = adapter; 213 dvo->dev_priv = ch7xxx; 214 ch7xxx->quiet = true; 215 216 if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor)) 217 goto out; 218 219 name = ch7xxx_get_id(vendor); 220 if (!name) { 221 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " 222 "slave %d.\n", 223 vendor, adapter->name, dvo->slave_addr); 224 goto out; 225 } 226 227 228 if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device)) 229 goto out; 230 231 devid = ch7xxx_get_did(device); 232 if (!devid) { 233 DRM_DEBUG_KMS("ch7xxx not detected; got 0x%02x from %s " 234 "slave %d.\n", 235 vendor, adapter->name, dvo->slave_addr); 236 goto out; 237 } 238 239 ch7xxx->quiet = false; 240 DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n", 241 name, vendor, device); 242 return true; 243 out: 244 kfree(ch7xxx); 245 return false; 246 } 247 248 static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo) 249 { 250 uint8_t cdet, orig_pm, pm; 251 252 ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm); 253 254 pm = orig_pm; 255 pm &= ~CH7xxx_PM_FPD; 256 pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP; 257 258 ch7xxx_writeb(dvo, CH7xxx_PM, pm); 259 260 ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet); 261 262 ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm); 263 264 if (cdet & CH7xxx_CDET_DVI) 265 return connector_status_connected; 266 return connector_status_disconnected; 267 } 268 269 static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo, 270 struct drm_display_mode *mode) 271 { 272 if (mode->clock > 165000) 273 return MODE_CLOCK_HIGH; 274 275 return MODE_OK; 276 } 277 278 static void ch7xxx_mode_set(struct intel_dvo_device *dvo, 279 const struct drm_display_mode *mode, 280 const struct drm_display_mode *adjusted_mode) 281 { 282 uint8_t tvco, tpcp, tpd, tlpf, idf; 283 284 if (mode->clock <= 65000) { 285 tvco = 0x23; 286 tpcp = 0x08; 287 tpd = 0x16; 288 tlpf = 0x60; 289 } else { 290 tvco = 0x2d; 291 tpcp = 0x06; 292 tpd = 0x26; 293 tlpf = 0xa0; 294 } 295 296 ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00); 297 ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco); 298 ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp); 299 ch7xxx_writeb(dvo, CH7xxx_TPD, tpd); 300 ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30); 301 ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf); 302 ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00); 303 304 ch7xxx_readb(dvo, CH7xxx_IDF, &idf); 305 306 idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP); 307 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 308 idf |= CH7xxx_IDF_HSP; 309 310 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 311 idf |= CH7xxx_IDF_VSP; 312 313 ch7xxx_writeb(dvo, CH7xxx_IDF, idf); 314 } 315 316 /* set the CH7xxx power state */ 317 static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable) 318 { 319 if (enable) 320 ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP); 321 else 322 ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD); 323 } 324 325 static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo) 326 { 327 u8 val; 328 329 ch7xxx_readb(dvo, CH7xxx_PM, &val); 330 331 if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP)) 332 return true; 333 else 334 return false; 335 } 336 337 static void ch7xxx_dump_regs(struct intel_dvo_device *dvo) 338 { 339 int i; 340 341 for (i = 0; i < CH7xxx_NUM_REGS; i++) { 342 uint8_t val; 343 if ((i % 8) == 0) 344 DRM_DEBUG_KMS("\n %02X: ", i); 345 ch7xxx_readb(dvo, i, &val); 346 DRM_DEBUG_KMS("%02X ", val); 347 } 348 } 349 350 static void ch7xxx_destroy(struct intel_dvo_device *dvo) 351 { 352 struct ch7xxx_priv *ch7xxx = dvo->dev_priv; 353 354 if (ch7xxx) { 355 kfree(ch7xxx); 356 dvo->dev_priv = NULL; 357 } 358 } 359 360 const struct intel_dvo_dev_ops ch7xxx_ops = { 361 .init = ch7xxx_init, 362 .detect = ch7xxx_detect, 363 .mode_valid = ch7xxx_mode_valid, 364 .mode_set = ch7xxx_mode_set, 365 .dpms = ch7xxx_dpms, 366 .get_hw_state = ch7xxx_get_hw_state, 367 .dump_regs = ch7xxx_dump_regs, 368 .destroy = ch7xxx_destroy, 369 }; 370