1 /* 2 * Copyright © 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 #include "dvo.h" 29 30 /* 31 * register definitions for the i82807aa. 32 * 33 * Documentation on this chipset can be found in datasheet #29069001 at 34 * intel.com. 35 */ 36 37 /* 38 * VCH Revision & GMBus Base Addr 39 */ 40 #define VR00 0x00 41 # define VR00_BASE_ADDRESS_MASK 0x007f 42 43 /* 44 * Functionality Enable 45 */ 46 #define VR01 0x01 47 48 /* 49 * Enable the panel fitter 50 */ 51 # define VR01_PANEL_FIT_ENABLE (1 << 3) 52 /* 53 * Enables the LCD display. 54 * 55 * This must not be set while VR01_DVO_BYPASS_ENABLE is set. 56 */ 57 # define VR01_LCD_ENABLE (1 << 2) 58 /** Enables the DVO repeater. */ 59 # define VR01_DVO_BYPASS_ENABLE (1 << 1) 60 /** Enables the DVO clock */ 61 # define VR01_DVO_ENABLE (1 << 0) 62 63 /* 64 * LCD Interface Format 65 */ 66 #define VR10 0x10 67 /** Enables LVDS output instead of CMOS */ 68 # define VR10_LVDS_ENABLE (1 << 4) 69 /** Enables 18-bit LVDS output. */ 70 # define VR10_INTERFACE_1X18 (0 << 2) 71 /** Enables 24-bit LVDS or CMOS output */ 72 # define VR10_INTERFACE_1X24 (1 << 2) 73 /** Enables 2x18-bit LVDS or CMOS output. */ 74 # define VR10_INTERFACE_2X18 (2 << 2) 75 /** Enables 2x24-bit LVDS output */ 76 # define VR10_INTERFACE_2X24 (3 << 2) 77 78 /* 79 * VR20 LCD Horizontal Display Size 80 */ 81 #define VR20 0x20 82 83 /* 84 * LCD Vertical Display Size 85 */ 86 #define VR21 0x20 87 88 /* 89 * Panel power down status 90 */ 91 #define VR30 0x30 92 /** Read only bit indicating that the panel is not in a safe poweroff state. */ 93 # define VR30_PANEL_ON (1 << 15) 94 95 #define VR40 0x40 96 # define VR40_STALL_ENABLE (1 << 13) 97 # define VR40_VERTICAL_INTERP_ENABLE (1 << 12) 98 # define VR40_ENHANCED_PANEL_FITTING (1 << 11) 99 # define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10) 100 # define VR40_AUTO_RATIO_ENABLE (1 << 9) 101 # define VR40_CLOCK_GATING_ENABLE (1 << 8) 102 103 /* 104 * Panel Fitting Vertical Ratio 105 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 106 */ 107 #define VR41 0x41 108 109 /* 110 * Panel Fitting Horizontal Ratio 111 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2 112 */ 113 #define VR42 0x42 114 115 /* 116 * Horizontal Image Size 117 */ 118 #define VR43 0x43 119 120 /* VR80 GPIO 0 121 */ 122 #define VR80 0x80 123 #define VR81 0x81 124 #define VR82 0x82 125 #define VR83 0x83 126 #define VR84 0x84 127 #define VR85 0x85 128 #define VR86 0x86 129 #define VR87 0x87 130 131 /* VR88 GPIO 8 132 */ 133 #define VR88 0x88 134 135 /* Graphics BIOS scratch 0 136 */ 137 #define VR8E 0x8E 138 # define VR8E_PANEL_TYPE_MASK (0xf << 0) 139 # define VR8E_PANEL_INTERFACE_CMOS (0 << 4) 140 # define VR8E_PANEL_INTERFACE_LVDS (1 << 4) 141 # define VR8E_FORCE_DEFAULT_PANEL (1 << 5) 142 143 /* Graphics BIOS scratch 1 144 */ 145 #define VR8F 0x8F 146 # define VR8F_VCH_PRESENT (1 << 0) 147 # define VR8F_DISPLAY_CONN (1 << 1) 148 # define VR8F_POWER_MASK (0x3c) 149 # define VR8F_POWER_POS (2) 150 151 152 struct ivch_priv { 153 bool quiet; 154 155 uint16_t width, height; 156 }; 157 158 159 static void ivch_dump_regs(struct intel_dvo_device *dvo); 160 161 /** 162 * Reads a register on the ivch. 163 * 164 * Each of the 256 registers are 16 bits long. 165 */ 166 static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data) 167 { 168 struct intel_iic_softc *sc; 169 struct ivch_priv *priv = dvo->dev_priv; 170 struct i2c_adapter *adapter = dvo->i2c_bus; 171 u8 out_buf[1]; 172 u8 in_buf[2]; 173 174 struct i2c_msg msgs[] = { 175 { 176 .slave = dvo->slave_addr << 1, 177 .flags = I2C_M_RD, 178 .len = 0, 179 }, 180 { 181 .slave = 0 << 1, 182 .flags = I2C_M_NOSTART, 183 .len = 1, 184 .buf = out_buf, 185 }, 186 { 187 .slave = dvo->slave_addr << 1, 188 .flags = I2C_M_RD | I2C_M_NOSTART, 189 .len = 2, 190 .buf = in_buf, 191 } 192 }; 193 194 out_buf[0] = addr; 195 196 sc = device_get_softc(adapter); 197 198 if (iicbus_transfer(adapter, msgs, 3) == 0) { 199 *data = (in_buf[1] << 8) | in_buf[0]; 200 return true; 201 } 202 203 if (!priv->quiet) { 204 DRM_DEBUG_KMS("Unable to read register 0x%02x from " 205 "%s:%02x.\n", 206 addr, sc->name, dvo->slave_addr); 207 } 208 return false; 209 } 210 211 /** Writes a 16-bit register on the ivch */ 212 static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data) 213 { 214 struct intel_iic_softc *sc; 215 struct ivch_priv *priv = dvo->dev_priv; 216 struct i2c_adapter *adapter = dvo->i2c_bus; 217 u8 out_buf[3]; 218 struct i2c_msg msg = { 219 .slave = dvo->slave_addr << 1, 220 .flags = 0, 221 .len = 3, 222 .buf = out_buf, 223 }; 224 225 out_buf[0] = addr; 226 out_buf[1] = data & 0xff; 227 out_buf[2] = data >> 8; 228 229 sc = device_get_softc(adapter); 230 231 if (iicbus_transfer(adapter, &msg, 1) == 0) 232 return true; 233 234 if (!priv->quiet) { 235 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 236 addr, sc->name, dvo->slave_addr); 237 } 238 239 return false; 240 } 241 242 /** Probes the given bus and slave address for an ivch */ 243 static bool ivch_init(struct intel_dvo_device *dvo, 244 struct i2c_adapter *adapter) 245 { 246 struct ivch_priv *priv; 247 uint16_t temp; 248 249 priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL); 250 if (priv == NULL) 251 return false; 252 253 dvo->i2c_bus = adapter; 254 dvo->dev_priv = priv; 255 priv->quiet = true; 256 257 if (!ivch_read(dvo, VR00, &temp)) 258 goto out; 259 priv->quiet = false; 260 261 /* Since the identification bits are probably zeroes, which doesn't seem 262 * very unique, check that the value in the base address field matches 263 * the address it's responding on. 264 */ 265 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { 266 DRM_DEBUG_KMS("ivch detect failed due to address mismatch " 267 "(%d vs %d)\n", 268 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); 269 goto out; 270 } 271 272 ivch_read(dvo, VR20, &priv->width); 273 ivch_read(dvo, VR21, &priv->height); 274 275 return true; 276 277 out: 278 kfree(priv); 279 return false; 280 } 281 282 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo) 283 { 284 return connector_status_connected; 285 } 286 287 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo, 288 struct drm_display_mode *mode) 289 { 290 if (mode->clock > 112000) 291 return MODE_CLOCK_HIGH; 292 293 return MODE_OK; 294 } 295 296 /** Sets the power state of the panel connected to the ivch */ 297 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable) 298 { 299 int i; 300 uint16_t vr01, vr30, backlight; 301 302 /* Set the new power state of the panel. */ 303 if (!ivch_read(dvo, VR01, &vr01)) 304 return; 305 306 if (enable) 307 backlight = 1; 308 else 309 backlight = 0; 310 ivch_write(dvo, VR80, backlight); 311 312 if (enable) 313 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE; 314 else 315 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE); 316 317 ivch_write(dvo, VR01, vr01); 318 319 /* Wait for the panel to make its state transition */ 320 for (i = 0; i < 100; i++) { 321 if (!ivch_read(dvo, VR30, &vr30)) 322 break; 323 324 if (((vr30 & VR30_PANEL_ON) != 0) == enable) 325 break; 326 udelay(1000); 327 } 328 /* wait some more; vch may fail to resync sometimes without this */ 329 udelay(16 * 1000); 330 } 331 332 static bool ivch_get_hw_state(struct intel_dvo_device *dvo) 333 { 334 uint16_t vr01; 335 336 /* Set the new power state of the panel. */ 337 if (!ivch_read(dvo, VR01, &vr01)) 338 return false; 339 340 if (vr01 & VR01_LCD_ENABLE) 341 return true; 342 else 343 return false; 344 } 345 346 static void ivch_mode_set(struct intel_dvo_device *dvo, 347 struct drm_display_mode *mode, 348 struct drm_display_mode *adjusted_mode) 349 { 350 uint16_t vr40 = 0; 351 uint16_t vr01; 352 353 vr01 = 0; 354 vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE | 355 VR40_HORIZONTAL_INTERP_ENABLE); 356 357 if (mode->hdisplay != adjusted_mode->hdisplay || 358 mode->vdisplay != adjusted_mode->vdisplay) { 359 uint16_t x_ratio, y_ratio; 360 361 vr01 |= VR01_PANEL_FIT_ENABLE; 362 vr40 |= VR40_CLOCK_GATING_ENABLE; 363 x_ratio = (((mode->hdisplay - 1) << 16) / 364 (adjusted_mode->hdisplay - 1)) >> 2; 365 y_ratio = (((mode->vdisplay - 1) << 16) / 366 (adjusted_mode->vdisplay - 1)) >> 2; 367 ivch_write(dvo, VR42, x_ratio); 368 ivch_write(dvo, VR41, y_ratio); 369 } else { 370 vr01 &= ~VR01_PANEL_FIT_ENABLE; 371 vr40 &= ~VR40_CLOCK_GATING_ENABLE; 372 } 373 vr40 &= ~VR40_AUTO_RATIO_ENABLE; 374 375 ivch_write(dvo, VR01, vr01); 376 ivch_write(dvo, VR40, vr40); 377 378 ivch_dump_regs(dvo); 379 } 380 381 static void ivch_dump_regs(struct intel_dvo_device *dvo) 382 { 383 uint16_t val; 384 385 ivch_read(dvo, VR00, &val); 386 DRM_DEBUG_KMS("VR00: 0x%04x\n", val); 387 ivch_read(dvo, VR01, &val); 388 DRM_DEBUG_KMS("VR01: 0x%04x\n", val); 389 ivch_read(dvo, VR30, &val); 390 DRM_DEBUG_KMS("VR30: 0x%04x\n", val); 391 ivch_read(dvo, VR40, &val); 392 DRM_DEBUG_KMS("VR40: 0x%04x\n", val); 393 394 /* GPIO registers */ 395 ivch_read(dvo, VR80, &val); 396 DRM_DEBUG_KMS("VR80: 0x%04x\n", val); 397 ivch_read(dvo, VR81, &val); 398 DRM_DEBUG_KMS("VR81: 0x%04x\n", val); 399 ivch_read(dvo, VR82, &val); 400 DRM_DEBUG_KMS("VR82: 0x%04x\n", val); 401 ivch_read(dvo, VR83, &val); 402 DRM_DEBUG_KMS("VR83: 0x%04x\n", val); 403 ivch_read(dvo, VR84, &val); 404 DRM_DEBUG_KMS("VR84: 0x%04x\n", val); 405 ivch_read(dvo, VR85, &val); 406 DRM_DEBUG_KMS("VR85: 0x%04x\n", val); 407 ivch_read(dvo, VR86, &val); 408 DRM_DEBUG_KMS("VR86: 0x%04x\n", val); 409 ivch_read(dvo, VR87, &val); 410 DRM_DEBUG_KMS("VR87: 0x%04x\n", val); 411 ivch_read(dvo, VR88, &val); 412 DRM_DEBUG_KMS("VR88: 0x%04x\n", val); 413 414 /* Scratch register 0 - AIM Panel type */ 415 ivch_read(dvo, VR8E, &val); 416 DRM_DEBUG_KMS("VR8E: 0x%04x\n", val); 417 418 /* Scratch register 1 - Status register */ 419 ivch_read(dvo, VR8F, &val); 420 DRM_DEBUG_KMS("VR8F: 0x%04x\n", val); 421 } 422 423 static void ivch_destroy(struct intel_dvo_device *dvo) 424 { 425 struct ivch_priv *priv = dvo->dev_priv; 426 427 if (priv) { 428 kfree(priv); 429 dvo->dev_priv = NULL; 430 } 431 } 432 433 struct intel_dvo_dev_ops ivch_ops = { 434 .init = ivch_init, 435 .dpms = ivch_dpms, 436 .get_hw_state = ivch_get_hw_state, 437 .mode_valid = ivch_mode_valid, 438 .mode_set = ivch_mode_set, 439 .detect = ivch_detect, 440 .dump_regs = ivch_dump_regs, 441 .destroy = ivch_destroy, 442 }; 443