1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include "debug.h" 37 #include "hypercall.h" 38 #include "mmio.h" 39 #include "reg.h" 40 #include "interrupt.h" 41 #include "gtt.h" 42 #include "display.h" 43 #include "edid.h" 44 #include "execlist.h" 45 #include "scheduler.h" 46 #include "sched_policy.h" 47 #include "render.h" 48 #include "cmd_parser.h" 49 50 #define GVT_MAX_VGPU 8 51 52 enum { 53 INTEL_GVT_HYPERVISOR_XEN = 0, 54 INTEL_GVT_HYPERVISOR_KVM, 55 }; 56 57 struct intel_gvt_host { 58 bool initialized; 59 int hypervisor_type; 60 struct intel_gvt_mpt *mpt; 61 }; 62 63 extern struct intel_gvt_host intel_gvt_host; 64 65 /* Describe per-platform limitations. */ 66 struct intel_gvt_device_info { 67 u32 max_support_vgpus; 68 u32 cfg_space_size; 69 u32 mmio_size; 70 u32 mmio_bar; 71 unsigned long msi_cap_offset; 72 u32 gtt_start_offset; 73 u32 gtt_entry_size; 74 u32 gtt_entry_size_shift; 75 int gmadr_bytes_in_cmd; 76 u32 max_surface_size; 77 }; 78 79 /* GM resources owned by a vGPU */ 80 struct intel_vgpu_gm { 81 u64 aperture_sz; 82 u64 hidden_sz; 83 struct drm_mm_node low_gm_node; 84 struct drm_mm_node high_gm_node; 85 }; 86 87 #define INTEL_GVT_MAX_NUM_FENCES 32 88 89 /* Fences owned by a vGPU */ 90 struct intel_vgpu_fence { 91 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 92 u32 base; 93 u32 size; 94 }; 95 96 struct intel_vgpu_mmio { 97 void *vreg; 98 void *sreg; 99 bool disable_warn_untrack; 100 }; 101 102 #define INTEL_GVT_MAX_CFG_SPACE_SZ 256 103 #define INTEL_GVT_MAX_BAR_NUM 4 104 105 struct intel_vgpu_pci_bar { 106 u64 size; 107 bool tracked; 108 }; 109 110 struct intel_vgpu_cfg_space { 111 unsigned char virtual_cfg_space[INTEL_GVT_MAX_CFG_SPACE_SZ]; 112 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 113 }; 114 115 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 116 117 #define INTEL_GVT_MAX_PIPE 4 118 119 struct intel_vgpu_irq { 120 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 121 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE], 122 INTEL_GVT_EVENT_MAX); 123 }; 124 125 struct intel_vgpu_opregion { 126 void *va; 127 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 128 struct page *pages[INTEL_GVT_OPREGION_PAGES]; 129 }; 130 131 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 132 133 #define INTEL_GVT_MAX_PORT 5 134 135 struct intel_vgpu_display { 136 struct intel_vgpu_i2c_edid i2c_edid; 137 struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT]; 138 struct intel_vgpu_sbi sbi; 139 }; 140 141 struct vgpu_sched_ctl { 142 int weight; 143 }; 144 145 struct intel_vgpu { 146 struct intel_gvt *gvt; 147 int id; 148 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 149 bool active; 150 bool pv_notified; 151 bool failsafe; 152 bool resetting; 153 void *sched_data; 154 struct vgpu_sched_ctl sched_ctl; 155 156 struct intel_vgpu_fence fence; 157 struct intel_vgpu_gm gm; 158 struct intel_vgpu_cfg_space cfg_space; 159 struct intel_vgpu_mmio mmio; 160 struct intel_vgpu_irq irq; 161 struct intel_vgpu_gtt gtt; 162 struct intel_vgpu_opregion opregion; 163 struct intel_vgpu_display display; 164 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 165 struct list_head workload_q_head[I915_NUM_ENGINES]; 166 struct kmem_cache *workloads; 167 atomic_t running_workload_num; 168 ktime_t last_ctx_submit_time; 169 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 170 struct i915_gem_context *shadow_ctx; 171 172 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) 173 struct { 174 struct mdev_device *mdev; 175 struct vfio_region *region; 176 int num_regions; 177 struct eventfd_ctx *intx_trigger; 178 struct eventfd_ctx *msi_trigger; 179 struct rb_root cache; 180 struct mutex cache_lock; 181 struct notifier_block iommu_notifier; 182 struct notifier_block group_notifier; 183 struct kvm *kvm; 184 struct work_struct release_work; 185 atomic_t released; 186 } vdev; 187 #endif 188 }; 189 190 struct intel_gvt_gm { 191 unsigned long vgpu_allocated_low_gm_size; 192 unsigned long vgpu_allocated_high_gm_size; 193 }; 194 195 struct intel_gvt_fence { 196 unsigned long vgpu_allocated_fence_num; 197 }; 198 199 #define INTEL_GVT_MMIO_HASH_BITS 9 200 201 struct intel_gvt_mmio { 202 u32 *mmio_attribute; 203 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 204 }; 205 206 struct intel_gvt_firmware { 207 void *cfg_space; 208 void *mmio; 209 bool firmware_loaded; 210 }; 211 212 struct intel_gvt_opregion { 213 void *opregion_va; 214 u32 opregion_pa; 215 }; 216 217 #define NR_MAX_INTEL_VGPU_TYPES 20 218 struct intel_vgpu_type { 219 char name[16]; 220 unsigned int avail_instance; 221 unsigned int low_gm_size; 222 unsigned int high_gm_size; 223 unsigned int fence; 224 unsigned int weight; 225 enum intel_vgpu_edid resolution; 226 }; 227 228 struct intel_gvt { 229 struct mutex lock; 230 struct drm_i915_private *dev_priv; 231 struct idr vgpu_idr; /* vGPU IDR pool */ 232 233 struct intel_gvt_device_info device_info; 234 struct intel_gvt_gm gm; 235 struct intel_gvt_fence fence; 236 struct intel_gvt_mmio mmio; 237 struct intel_gvt_firmware firmware; 238 struct intel_gvt_irq irq; 239 struct intel_gvt_gtt gtt; 240 struct intel_gvt_opregion opregion; 241 struct intel_gvt_workload_scheduler scheduler; 242 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 243 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 244 struct intel_vgpu_type *types; 245 unsigned int num_types; 246 struct intel_vgpu *idle_vgpu; 247 248 struct task_struct *service_thread; 249 wait_queue_head_t service_thread_wq; 250 unsigned long service_request; 251 }; 252 253 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 254 { 255 return i915->gvt; 256 } 257 258 enum { 259 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 260 INTEL_GVT_REQUEST_SCHED = 1, 261 }; 262 263 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 264 int service) 265 { 266 set_bit(service, (void *)&gvt->service_request); 267 wake_up(&gvt->service_thread_wq); 268 } 269 270 void intel_gvt_free_firmware(struct intel_gvt *gvt); 271 int intel_gvt_load_firmware(struct intel_gvt *gvt); 272 273 /* Aperture/GM space definitions for GVT device */ 274 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 275 #define BYTES_TO_MB(b) ((b) >> 20ULL) 276 277 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 278 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 279 #define HOST_FENCE 4 280 281 /* Aperture/GM space definitions for GVT device */ 282 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) 283 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) 284 285 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total) 286 #define gvt_ggtt_sz(gvt) \ 287 ((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3) 288 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 289 290 #define gvt_aperture_gmadr_base(gvt) (0) 291 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 292 + gvt_aperture_sz(gvt) - 1) 293 294 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 295 + gvt_aperture_sz(gvt)) 296 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 297 + gvt_hidden_sz(gvt) - 1) 298 299 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) 300 301 /* Aperture/GM space definitions for vGPU */ 302 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 303 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 304 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 305 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 306 307 #define vgpu_aperture_pa_base(vgpu) \ 308 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 309 310 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 311 312 #define vgpu_aperture_pa_end(vgpu) \ 313 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 314 315 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 316 #define vgpu_aperture_gmadr_end(vgpu) \ 317 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 318 319 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 320 #define vgpu_hidden_gmadr_end(vgpu) \ 321 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 322 323 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 324 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 325 326 struct intel_vgpu_creation_params { 327 __u64 handle; 328 __u64 low_gm_sz; /* in MB */ 329 __u64 high_gm_sz; /* in MB */ 330 __u64 fence_sz; 331 __u64 resolution; 332 __s32 primary; 333 __u64 vgpu_id; 334 335 __u32 weight; 336 }; 337 338 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 339 struct intel_vgpu_creation_params *param); 340 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 341 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 342 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 343 u32 fence, u64 value); 344 345 /* Macros for easily accessing vGPU virtual/shadow register */ 346 #define vgpu_vreg(vgpu, reg) \ 347 (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 348 #define vgpu_vreg8(vgpu, reg) \ 349 (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 350 #define vgpu_vreg16(vgpu, reg) \ 351 (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 352 #define vgpu_vreg64(vgpu, reg) \ 353 (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 354 #define vgpu_sreg(vgpu, reg) \ 355 (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 356 #define vgpu_sreg8(vgpu, reg) \ 357 (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 358 #define vgpu_sreg16(vgpu, reg) \ 359 (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 360 #define vgpu_sreg64(vgpu, reg) \ 361 (*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 362 363 #define for_each_active_vgpu(gvt, vgpu, id) \ 364 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 365 for_each_if(vgpu->active) 366 367 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 368 u32 offset, u32 val, bool low) 369 { 370 u32 *pval; 371 372 /* BAR offset should be 32 bits algiend */ 373 offset = rounddown(offset, 4); 374 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 375 376 if (low) { 377 /* 378 * only update bit 31 - bit 4, 379 * leave the bit 3 - bit 0 unchanged. 380 */ 381 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 382 } else { 383 *pval = val; 384 } 385 } 386 387 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 388 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 389 390 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 391 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 392 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 393 struct intel_vgpu_type *type); 394 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 395 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 396 unsigned int engine_mask); 397 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 398 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 399 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 400 401 /* validating GM functions */ 402 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 403 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 404 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 405 406 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 407 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 408 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 409 410 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 411 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 412 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 413 414 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 415 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 416 (gmadr <= gvt_aperture_gmadr_end(gvt))) 417 418 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 419 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 420 (gmadr <= gvt_hidden_gmadr_end(gvt))) 421 422 #define gvt_gmadr_is_valid(gvt, gmadr) \ 423 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 424 gvt_gmadr_is_hidden(gvt, gmadr)) 425 426 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 427 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 428 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 429 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 430 unsigned long *h_index); 431 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 432 unsigned long *g_index); 433 434 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 435 bool primary); 436 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 437 438 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 439 void *p_data, unsigned int bytes); 440 441 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 442 void *p_data, unsigned int bytes); 443 444 void intel_gvt_clean_opregion(struct intel_gvt *gvt); 445 int intel_gvt_init_opregion(struct intel_gvt *gvt); 446 447 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 448 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); 449 450 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 451 void populate_pvinfo_page(struct intel_vgpu *vgpu); 452 453 struct intel_gvt_ops { 454 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 455 unsigned int); 456 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 457 unsigned int); 458 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 459 unsigned int); 460 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 461 unsigned int); 462 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 463 struct intel_vgpu_type *); 464 void (*vgpu_destroy)(struct intel_vgpu *); 465 void (*vgpu_reset)(struct intel_vgpu *); 466 void (*vgpu_activate)(struct intel_vgpu *); 467 void (*vgpu_deactivate)(struct intel_vgpu *); 468 }; 469 470 471 enum { 472 GVT_FAILSAFE_UNSUPPORTED_GUEST, 473 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 474 }; 475 476 #include "mpt.h" 477 478 #endif 479