1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include "debug.h" 37 #include "hypercall.h" 38 #include "mmio.h" 39 #include "reg.h" 40 #include "interrupt.h" 41 #include "gtt.h" 42 #include "display.h" 43 #include "edid.h" 44 #include "execlist.h" 45 #include "scheduler.h" 46 #include "sched_policy.h" 47 #include "render.h" 48 #include "cmd_parser.h" 49 50 #define GVT_MAX_VGPU 8 51 52 enum { 53 INTEL_GVT_HYPERVISOR_XEN = 0, 54 INTEL_GVT_HYPERVISOR_KVM, 55 }; 56 57 struct intel_gvt_host { 58 bool initialized; 59 int hypervisor_type; 60 struct intel_gvt_mpt *mpt; 61 }; 62 63 extern struct intel_gvt_host intel_gvt_host; 64 65 /* Describe per-platform limitations. */ 66 struct intel_gvt_device_info { 67 u32 max_support_vgpus; 68 u32 cfg_space_size; 69 u32 mmio_size; 70 u32 mmio_bar; 71 unsigned long msi_cap_offset; 72 u32 gtt_start_offset; 73 u32 gtt_entry_size; 74 u32 gtt_entry_size_shift; 75 int gmadr_bytes_in_cmd; 76 u32 max_surface_size; 77 }; 78 79 /* GM resources owned by a vGPU */ 80 struct intel_vgpu_gm { 81 u64 aperture_sz; 82 u64 hidden_sz; 83 void *aperture_va; 84 struct drm_mm_node low_gm_node; 85 struct drm_mm_node high_gm_node; 86 }; 87 88 #define INTEL_GVT_MAX_NUM_FENCES 32 89 90 /* Fences owned by a vGPU */ 91 struct intel_vgpu_fence { 92 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 93 u32 base; 94 u32 size; 95 }; 96 97 struct intel_vgpu_mmio { 98 void *vreg; 99 void *sreg; 100 bool disable_warn_untrack; 101 }; 102 103 #define INTEL_GVT_MAX_BAR_NUM 4 104 105 struct intel_vgpu_pci_bar { 106 u64 size; 107 bool tracked; 108 }; 109 110 struct intel_vgpu_cfg_space { 111 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 112 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 113 }; 114 115 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 116 117 #define INTEL_GVT_MAX_PIPE 4 118 119 struct intel_vgpu_irq { 120 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 121 DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE], 122 INTEL_GVT_EVENT_MAX); 123 }; 124 125 struct intel_vgpu_opregion { 126 void *va; 127 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 128 struct page *pages[INTEL_GVT_OPREGION_PAGES]; 129 }; 130 131 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 132 133 #define INTEL_GVT_MAX_PORT 5 134 135 struct intel_vgpu_display { 136 struct intel_vgpu_i2c_edid i2c_edid; 137 struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT]; 138 struct intel_vgpu_sbi sbi; 139 }; 140 141 struct vgpu_sched_ctl { 142 int weight; 143 }; 144 145 struct intel_vgpu { 146 struct intel_gvt *gvt; 147 int id; 148 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 149 bool active; 150 bool pv_notified; 151 bool failsafe; 152 unsigned int resetting_eng; 153 void *sched_data; 154 struct vgpu_sched_ctl sched_ctl; 155 156 struct intel_vgpu_fence fence; 157 struct intel_vgpu_gm gm; 158 struct intel_vgpu_cfg_space cfg_space; 159 struct intel_vgpu_mmio mmio; 160 struct intel_vgpu_irq irq; 161 struct intel_vgpu_gtt gtt; 162 struct intel_vgpu_opregion opregion; 163 struct intel_vgpu_display display; 164 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 165 struct list_head workload_q_head[I915_NUM_ENGINES]; 166 struct kmem_cache *workloads; 167 atomic_t running_workload_num; 168 ktime_t last_ctx_submit_time; 169 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 170 struct i915_gem_context *shadow_ctx; 171 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 172 173 #if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT) 174 struct { 175 struct mdev_device *mdev; 176 struct vfio_region *region; 177 int num_regions; 178 struct eventfd_ctx *intx_trigger; 179 struct eventfd_ctx *msi_trigger; 180 struct rb_root cache; 181 struct mutex cache_lock; 182 struct notifier_block iommu_notifier; 183 struct notifier_block group_notifier; 184 struct kvm *kvm; 185 struct work_struct release_work; 186 atomic_t released; 187 } vdev; 188 #endif 189 }; 190 191 struct intel_gvt_gm { 192 unsigned long vgpu_allocated_low_gm_size; 193 unsigned long vgpu_allocated_high_gm_size; 194 }; 195 196 struct intel_gvt_fence { 197 unsigned long vgpu_allocated_fence_num; 198 }; 199 200 /* Special MMIO blocks. */ 201 struct gvt_mmio_block { 202 unsigned int device; 203 i915_reg_t offset; 204 unsigned int size; 205 gvt_mmio_func read; 206 gvt_mmio_func write; 207 }; 208 209 #define INTEL_GVT_MMIO_HASH_BITS 11 210 211 struct intel_gvt_mmio { 212 u8 *mmio_attribute; 213 /* Register contains RO bits */ 214 #define F_RO (1 << 0) 215 /* Register contains graphics address */ 216 #define F_GMADR (1 << 1) 217 /* Mode mask registers with high 16 bits as the mask bits */ 218 #define F_MODE_MASK (1 << 2) 219 /* This reg can be accessed by GPU commands */ 220 #define F_CMD_ACCESS (1 << 3) 221 /* This reg has been accessed by a VM */ 222 #define F_ACCESSED (1 << 4) 223 /* This reg has been accessed through GPU commands */ 224 #define F_CMD_ACCESSED (1 << 5) 225 /* This reg could be accessed by unaligned address */ 226 #define F_UNALIGN (1 << 6) 227 228 struct gvt_mmio_block *mmio_block; 229 unsigned int num_mmio_block; 230 231 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 232 unsigned int num_tracked_mmio; 233 }; 234 235 struct intel_gvt_firmware { 236 void *cfg_space; 237 void *mmio; 238 bool firmware_loaded; 239 }; 240 241 struct intel_gvt_opregion { 242 void *opregion_va; 243 u32 opregion_pa; 244 }; 245 246 #define NR_MAX_INTEL_VGPU_TYPES 20 247 struct intel_vgpu_type { 248 char name[16]; 249 unsigned int avail_instance; 250 unsigned int low_gm_size; 251 unsigned int high_gm_size; 252 unsigned int fence; 253 unsigned int weight; 254 enum intel_vgpu_edid resolution; 255 }; 256 257 struct intel_gvt { 258 struct mutex lock; 259 struct drm_i915_private *dev_priv; 260 struct idr vgpu_idr; /* vGPU IDR pool */ 261 262 struct intel_gvt_device_info device_info; 263 struct intel_gvt_gm gm; 264 struct intel_gvt_fence fence; 265 struct intel_gvt_mmio mmio; 266 struct intel_gvt_firmware firmware; 267 struct intel_gvt_irq irq; 268 struct intel_gvt_gtt gtt; 269 struct intel_gvt_opregion opregion; 270 struct intel_gvt_workload_scheduler scheduler; 271 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 272 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 273 struct intel_vgpu_type *types; 274 unsigned int num_types; 275 struct intel_vgpu *idle_vgpu; 276 277 struct task_struct *service_thread; 278 wait_queue_head_t service_thread_wq; 279 unsigned long service_request; 280 }; 281 282 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 283 { 284 return i915->gvt; 285 } 286 287 enum { 288 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 289 290 /* Scheduling trigger by timer */ 291 INTEL_GVT_REQUEST_SCHED = 1, 292 293 /* Scheduling trigger by event */ 294 INTEL_GVT_REQUEST_EVENT_SCHED = 2, 295 }; 296 297 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 298 int service) 299 { 300 set_bit(service, (void *)&gvt->service_request); 301 wake_up(&gvt->service_thread_wq); 302 } 303 304 void intel_gvt_free_firmware(struct intel_gvt *gvt); 305 int intel_gvt_load_firmware(struct intel_gvt *gvt); 306 307 /* Aperture/GM space definitions for GVT device */ 308 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 309 #define BYTES_TO_MB(b) ((b) >> 20ULL) 310 311 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 312 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 313 #define HOST_FENCE 4 314 315 /* Aperture/GM space definitions for GVT device */ 316 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end) 317 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base) 318 319 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total) 320 #define gvt_ggtt_sz(gvt) \ 321 ((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3) 322 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 323 324 #define gvt_aperture_gmadr_base(gvt) (0) 325 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 326 + gvt_aperture_sz(gvt) - 1) 327 328 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 329 + gvt_aperture_sz(gvt)) 330 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 331 + gvt_hidden_sz(gvt) - 1) 332 333 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs) 334 335 /* Aperture/GM space definitions for vGPU */ 336 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 337 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 338 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 339 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 340 341 #define vgpu_aperture_pa_base(vgpu) \ 342 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 343 344 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 345 346 #define vgpu_aperture_pa_end(vgpu) \ 347 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 348 349 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 350 #define vgpu_aperture_gmadr_end(vgpu) \ 351 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 352 353 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 354 #define vgpu_hidden_gmadr_end(vgpu) \ 355 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 356 357 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 358 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 359 360 struct intel_vgpu_creation_params { 361 __u64 handle; 362 __u64 low_gm_sz; /* in MB */ 363 __u64 high_gm_sz; /* in MB */ 364 __u64 fence_sz; 365 __u64 resolution; 366 __s32 primary; 367 __u64 vgpu_id; 368 369 __u32 weight; 370 }; 371 372 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 373 struct intel_vgpu_creation_params *param); 374 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 375 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 376 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 377 u32 fence, u64 value); 378 379 /* Macros for easily accessing vGPU virtual/shadow register */ 380 #define vgpu_vreg(vgpu, reg) \ 381 (*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 382 #define vgpu_vreg8(vgpu, reg) \ 383 (*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 384 #define vgpu_vreg16(vgpu, reg) \ 385 (*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 386 #define vgpu_vreg64(vgpu, reg) \ 387 (*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg))) 388 #define vgpu_sreg(vgpu, reg) \ 389 (*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 390 #define vgpu_sreg8(vgpu, reg) \ 391 (*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 392 #define vgpu_sreg16(vgpu, reg) \ 393 (*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 394 #define vgpu_sreg64(vgpu, reg) \ 395 (*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg))) 396 397 #define for_each_active_vgpu(gvt, vgpu, id) \ 398 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 399 for_each_if(vgpu->active) 400 401 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 402 u32 offset, u32 val, bool low) 403 { 404 u32 *pval; 405 406 /* BAR offset should be 32 bits algiend */ 407 offset = rounddown(offset, 4); 408 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 409 410 if (low) { 411 /* 412 * only update bit 31 - bit 4, 413 * leave the bit 3 - bit 0 unchanged. 414 */ 415 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 416 } else { 417 *pval = val; 418 } 419 } 420 421 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 422 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 423 424 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 425 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 426 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 427 struct intel_vgpu_type *type); 428 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 429 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 430 unsigned int engine_mask); 431 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 432 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 433 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 434 435 /* validating GM functions */ 436 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 437 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 438 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 439 440 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 441 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 442 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 443 444 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 445 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 446 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 447 448 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 449 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 450 (gmadr <= gvt_aperture_gmadr_end(gvt))) 451 452 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 453 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 454 (gmadr <= gvt_hidden_gmadr_end(gvt))) 455 456 #define gvt_gmadr_is_valid(gvt, gmadr) \ 457 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 458 gvt_gmadr_is_hidden(gvt, gmadr)) 459 460 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 461 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 462 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 463 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 464 unsigned long *h_index); 465 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 466 unsigned long *g_index); 467 468 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 469 bool primary); 470 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 471 472 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 473 void *p_data, unsigned int bytes); 474 475 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 476 void *p_data, unsigned int bytes); 477 478 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 479 { 480 /* We are 64bit bar. */ 481 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 482 PCI_BASE_ADDRESS_MEM_MASK; 483 } 484 485 void intel_gvt_clean_opregion(struct intel_gvt *gvt); 486 int intel_gvt_init_opregion(struct intel_gvt *gvt); 487 488 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 489 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa); 490 491 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 492 void populate_pvinfo_page(struct intel_vgpu *vgpu); 493 494 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 495 496 struct intel_gvt_ops { 497 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 498 unsigned int); 499 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 500 unsigned int); 501 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 502 unsigned int); 503 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 504 unsigned int); 505 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 506 struct intel_vgpu_type *); 507 void (*vgpu_destroy)(struct intel_vgpu *); 508 void (*vgpu_reset)(struct intel_vgpu *); 509 void (*vgpu_activate)(struct intel_vgpu *); 510 void (*vgpu_deactivate)(struct intel_vgpu *); 511 }; 512 513 514 enum { 515 GVT_FAILSAFE_UNSUPPORTED_GUEST, 516 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 517 }; 518 519 static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv) 520 { 521 intel_runtime_pm_get(dev_priv); 522 } 523 524 static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv) 525 { 526 intel_runtime_pm_put(dev_priv); 527 } 528 529 /** 530 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 531 * @gvt: a GVT device 532 * @offset: register offset 533 * 534 */ 535 static inline void intel_gvt_mmio_set_accessed( 536 struct intel_gvt *gvt, unsigned int offset) 537 { 538 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 539 } 540 541 /** 542 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 543 * @gvt: a GVT device 544 * @offset: register offset 545 * 546 */ 547 static inline bool intel_gvt_mmio_is_cmd_access( 548 struct intel_gvt *gvt, unsigned int offset) 549 { 550 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 551 } 552 553 /** 554 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 555 * @gvt: a GVT device 556 * @offset: register offset 557 * 558 */ 559 static inline bool intel_gvt_mmio_is_unalign( 560 struct intel_gvt *gvt, unsigned int offset) 561 { 562 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 563 } 564 565 /** 566 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 567 * @gvt: a GVT device 568 * @offset: register offset 569 * 570 */ 571 static inline void intel_gvt_mmio_set_cmd_accessed( 572 struct intel_gvt *gvt, unsigned int offset) 573 { 574 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED; 575 } 576 577 /** 578 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 579 * @gvt: a GVT device 580 * @offset: register offset 581 * 582 * Returns: 583 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 584 * 585 */ 586 static inline bool intel_gvt_mmio_has_mode_mask( 587 struct intel_gvt *gvt, unsigned int offset) 588 { 589 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 590 } 591 592 #include "trace.h" 593 #include "mpt.h" 594 595 #endif 596