1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Brad Volkin <bradley.d.volkin@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 30 /** 31 * DOC: batch buffer command parser 32 * 33 * Motivation: 34 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 35 * require userspace code to submit batches containing commands such as 36 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 37 * generations of the hardware will noop these commands in "unsecure" batches 38 * (which includes all userspace batches submitted via i915) even though the 39 * commands may be safe and represent the intended programming model of the 40 * device. 41 * 42 * The software command parser is similar in operation to the command parsing 43 * done in hardware for unsecure batches. However, the software parser allows 44 * some operations that would be noop'd by hardware, if the parser determines 45 * the operation is safe, and submits the batch as "secure" to prevent hardware 46 * parsing. 47 * 48 * Threats: 49 * At a high level, the hardware (and software) checks attempt to prevent 50 * granting userspace undue privileges. There are three categories of privilege. 51 * 52 * First, commands which are explicitly defined as privileged or which should 53 * only be used by the kernel driver. The parser generally rejects such 54 * commands, though it may allow some from the drm master process. 55 * 56 * Second, commands which access registers. To support correct/enhanced 57 * userspace functionality, particularly certain OpenGL extensions, the parser 58 * provides a whitelist of registers which userspace may safely access (for both 59 * normal and drm master processes). 60 * 61 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 62 * The parser always rejects such commands. 63 * 64 * The majority of the problematic commands fall in the MI_* range, with only a 65 * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW). 66 * 67 * Implementation: 68 * Each ring maintains tables of commands and registers which the parser uses in 69 * scanning batch buffers submitted to that ring. 70 * 71 * Since the set of commands that the parser must check for is significantly 72 * smaller than the number of commands supported, the parser tables contain only 73 * those commands required by the parser. This generally works because command 74 * opcode ranges have standard command length encodings. So for commands that 75 * the parser does not need to check, it can easily skip them. This is 76 * implementated via a per-ring length decoding vfunc. 77 * 78 * Unfortunately, there are a number of commands that do not follow the standard 79 * length encoding for their opcode range, primarily amongst the MI_* commands. 80 * To handle this, the parser provides a way to define explicit "skip" entries 81 * in the per-ring command tables. 82 * 83 * Other command table entries map fairly directly to high level categories 84 * mentioned above: rejected, master-only, register whitelist. The parser 85 * implements a number of checks, including the privileged memory checks, via a 86 * general bitmasking mechanism. 87 */ 88 89 #define STD_MI_OPCODE_MASK 0xFF800000 90 #define STD_3D_OPCODE_MASK 0xFFFF0000 91 #define STD_2D_OPCODE_MASK 0xFFC00000 92 #define STD_MFX_OPCODE_MASK 0xFFFF0000 93 94 #define CMD(op, opm, f, lm, fl, ...) \ 95 { \ 96 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 97 .cmd = { (op), (opm) }, \ 98 .length = { (lm) }, \ 99 __VA_ARGS__ \ 100 } 101 102 /* Convenience macros to compress the tables */ 103 #define SMI STD_MI_OPCODE_MASK 104 #define S3D STD_3D_OPCODE_MASK 105 #define S2D STD_2D_OPCODE_MASK 106 #define SMFX STD_MFX_OPCODE_MASK 107 #define F true 108 #define S CMD_DESC_SKIP 109 #define R CMD_DESC_REJECT 110 #define W CMD_DESC_REGISTER 111 #define B CMD_DESC_BITMASK 112 #define M CMD_DESC_MASTER 113 114 /* Command Mask Fixed Len Action 115 ---------------------------------------------------------- */ 116 static const struct drm_i915_cmd_descriptor common_cmds[] = { 117 CMD( MI_NOOP, SMI, F, 1, S ), 118 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 119 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ), 120 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 121 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 122 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 123 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 124 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 125 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 126 .reg = { .offset = 1, .mask = 0x007FFFFC } ), 127 CMD( MI_STORE_REGISTER_MEM(1), SMI, !F, 0xFF, W | B, 128 .reg = { .offset = 1, .mask = 0x007FFFFC }, 129 .bits = {{ 130 .offset = 0, 131 .mask = MI_GLOBAL_GTT, 132 .expected = 0, 133 }}, ), 134 CMD( MI_LOAD_REGISTER_MEM, SMI, !F, 0xFF, W | B, 135 .reg = { .offset = 1, .mask = 0x007FFFFC }, 136 .bits = {{ 137 .offset = 0, 138 .mask = MI_GLOBAL_GTT, 139 .expected = 0, 140 }}, ), 141 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 142 }; 143 144 static const struct drm_i915_cmd_descriptor render_cmds[] = { 145 CMD( MI_FLUSH, SMI, F, 1, S ), 146 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 147 CMD( MI_PREDICATE, SMI, F, 1, S ), 148 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 149 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 150 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 151 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 152 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 153 .bits = {{ 154 .offset = 0, 155 .mask = MI_GLOBAL_GTT, 156 .expected = 0, 157 }}, ), 158 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 159 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 160 .bits = {{ 161 .offset = 0, 162 .mask = MI_GLOBAL_GTT, 163 .expected = 0, 164 }}, ), 165 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 166 .bits = {{ 167 .offset = 1, 168 .mask = MI_REPORT_PERF_COUNT_GGTT, 169 .expected = 0, 170 }}, ), 171 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 172 .bits = {{ 173 .offset = 0, 174 .mask = MI_GLOBAL_GTT, 175 .expected = 0, 176 }}, ), 177 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 178 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 179 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 180 .bits = {{ 181 .offset = 2, 182 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 183 .expected = 0, 184 }}, ), 185 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 186 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 187 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 188 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 189 .bits = {{ 190 .offset = 1, 191 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 192 .expected = 0, 193 }, 194 { 195 .offset = 1, 196 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 197 PIPE_CONTROL_STORE_DATA_INDEX), 198 .expected = 0, 199 .condition_offset = 1, 200 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 201 }}, ), 202 }; 203 204 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 205 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 206 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 207 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 208 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 209 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 210 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 211 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, R ), 212 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 213 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 214 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 215 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 216 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 217 218 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 219 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 220 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 221 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 222 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 223 }; 224 225 static const struct drm_i915_cmd_descriptor video_cmds[] = { 226 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 227 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 228 .bits = {{ 229 .offset = 0, 230 .mask = MI_GLOBAL_GTT, 231 .expected = 0, 232 }}, ), 233 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 234 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 235 .bits = {{ 236 .offset = 0, 237 .mask = MI_FLUSH_DW_NOTIFY, 238 .expected = 0, 239 }, 240 { 241 .offset = 1, 242 .mask = MI_FLUSH_DW_USE_GTT, 243 .expected = 0, 244 .condition_offset = 0, 245 .condition_mask = MI_FLUSH_DW_OP_MASK, 246 }, 247 { 248 .offset = 0, 249 .mask = MI_FLUSH_DW_STORE_INDEX, 250 .expected = 0, 251 .condition_offset = 0, 252 .condition_mask = MI_FLUSH_DW_OP_MASK, 253 }}, ), 254 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 255 .bits = {{ 256 .offset = 0, 257 .mask = MI_GLOBAL_GTT, 258 .expected = 0, 259 }}, ), 260 /* 261 * MFX_WAIT doesn't fit the way we handle length for most commands. 262 * It has a length field but it uses a non-standard length bias. 263 * It is always 1 dword though, so just treat it as fixed length. 264 */ 265 CMD( MFX_WAIT, SMFX, F, 1, S ), 266 }; 267 268 static const struct drm_i915_cmd_descriptor vecs_cmds[] = { 269 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 270 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 271 .bits = {{ 272 .offset = 0, 273 .mask = MI_GLOBAL_GTT, 274 .expected = 0, 275 }}, ), 276 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 277 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 278 .bits = {{ 279 .offset = 0, 280 .mask = MI_FLUSH_DW_NOTIFY, 281 .expected = 0, 282 }, 283 { 284 .offset = 1, 285 .mask = MI_FLUSH_DW_USE_GTT, 286 .expected = 0, 287 .condition_offset = 0, 288 .condition_mask = MI_FLUSH_DW_OP_MASK, 289 }, 290 { 291 .offset = 0, 292 .mask = MI_FLUSH_DW_STORE_INDEX, 293 .expected = 0, 294 .condition_offset = 0, 295 .condition_mask = MI_FLUSH_DW_OP_MASK, 296 }}, ), 297 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 298 .bits = {{ 299 .offset = 0, 300 .mask = MI_GLOBAL_GTT, 301 .expected = 0, 302 }}, ), 303 }; 304 305 static const struct drm_i915_cmd_descriptor blt_cmds[] = { 306 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 307 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 308 .bits = {{ 309 .offset = 0, 310 .mask = MI_GLOBAL_GTT, 311 .expected = 0, 312 }}, ), 313 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 314 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 315 .bits = {{ 316 .offset = 0, 317 .mask = MI_FLUSH_DW_NOTIFY, 318 .expected = 0, 319 }, 320 { 321 .offset = 1, 322 .mask = MI_FLUSH_DW_USE_GTT, 323 .expected = 0, 324 .condition_offset = 0, 325 .condition_mask = MI_FLUSH_DW_OP_MASK, 326 }, 327 { 328 .offset = 0, 329 .mask = MI_FLUSH_DW_STORE_INDEX, 330 .expected = 0, 331 .condition_offset = 0, 332 .condition_mask = MI_FLUSH_DW_OP_MASK, 333 }}, ), 334 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 335 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 336 }; 337 338 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 339 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 340 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 341 }; 342 343 #undef CMD 344 #undef SMI 345 #undef S3D 346 #undef S2D 347 #undef SMFX 348 #undef F 349 #undef S 350 #undef R 351 #undef W 352 #undef B 353 #undef M 354 355 static const struct drm_i915_cmd_table gen7_render_cmds[] = { 356 { common_cmds, ARRAY_SIZE(common_cmds) }, 357 { render_cmds, ARRAY_SIZE(render_cmds) }, 358 }; 359 360 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { 361 { common_cmds, ARRAY_SIZE(common_cmds) }, 362 { render_cmds, ARRAY_SIZE(render_cmds) }, 363 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 364 }; 365 366 static const struct drm_i915_cmd_table gen7_video_cmds[] = { 367 { common_cmds, ARRAY_SIZE(common_cmds) }, 368 { video_cmds, ARRAY_SIZE(video_cmds) }, 369 }; 370 371 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { 372 { common_cmds, ARRAY_SIZE(common_cmds) }, 373 { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, 374 }; 375 376 static const struct drm_i915_cmd_table gen7_blt_cmds[] = { 377 { common_cmds, ARRAY_SIZE(common_cmds) }, 378 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 379 }; 380 381 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { 382 { common_cmds, ARRAY_SIZE(common_cmds) }, 383 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 384 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 385 }; 386 387 /* 388 * Register whitelists, sorted by increasing register offset. 389 * 390 * Some registers that userspace accesses are 64 bits. The register 391 * access commands only allow 32-bit accesses. Hence, we have to include 392 * entries for both halves of the 64-bit registers. 393 */ 394 395 /* Convenience macro for adding 64-bit registers */ 396 #define REG64(addr) (addr), (addr + sizeof(u32)) 397 398 static const u32 gen7_render_regs[] = { 399 REG64(HS_INVOCATION_COUNT), 400 REG64(DS_INVOCATION_COUNT), 401 REG64(IA_VERTICES_COUNT), 402 REG64(IA_PRIMITIVES_COUNT), 403 REG64(VS_INVOCATION_COUNT), 404 REG64(GS_INVOCATION_COUNT), 405 REG64(GS_PRIMITIVES_COUNT), 406 REG64(CL_INVOCATION_COUNT), 407 REG64(CL_PRIMITIVES_COUNT), 408 REG64(PS_INVOCATION_COUNT), 409 REG64(PS_DEPTH_COUNT), 410 OACONTROL, /* Only allowed for LRI and SRM. See below. */ 411 GEN7_3DPRIM_END_OFFSET, 412 GEN7_3DPRIM_START_VERTEX, 413 GEN7_3DPRIM_VERTEX_COUNT, 414 GEN7_3DPRIM_INSTANCE_COUNT, 415 GEN7_3DPRIM_START_INSTANCE, 416 GEN7_3DPRIM_BASE_VERTEX, 417 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)), 418 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)), 419 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)), 420 REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)), 421 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)), 422 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)), 423 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)), 424 REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)), 425 GEN7_SO_WRITE_OFFSET(0), 426 GEN7_SO_WRITE_OFFSET(1), 427 GEN7_SO_WRITE_OFFSET(2), 428 GEN7_SO_WRITE_OFFSET(3), 429 GEN7_L3SQCREG1, 430 GEN7_L3CNTLREG2, 431 GEN7_L3CNTLREG3, 432 }; 433 434 static const u32 gen7_blt_regs[] = { 435 BCS_SWCTRL, 436 }; 437 438 static const u32 ivb_master_regs[] = { 439 FORCEWAKE_MT, 440 DERRMR, 441 GEN7_PIPE_DE_LOAD_SL(PIPE_A), 442 GEN7_PIPE_DE_LOAD_SL(PIPE_B), 443 GEN7_PIPE_DE_LOAD_SL(PIPE_C), 444 }; 445 446 static const u32 hsw_master_regs[] = { 447 FORCEWAKE_MT, 448 DERRMR, 449 }; 450 451 #undef REG64 452 453 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 454 { 455 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 456 u32 subclient = 457 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 458 459 if (client == INSTR_MI_CLIENT) 460 return 0x3F; 461 else if (client == INSTR_RC_CLIENT) { 462 if (subclient == INSTR_MEDIA_SUBCLIENT) 463 return 0xFFFF; 464 else 465 return 0xFF; 466 } 467 468 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 469 return 0; 470 } 471 472 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 473 { 474 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 475 u32 subclient = 476 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 477 478 if (client == INSTR_MI_CLIENT) 479 return 0x3F; 480 else if (client == INSTR_RC_CLIENT) { 481 if (subclient == INSTR_MEDIA_SUBCLIENT) 482 return 0xFFF; 483 else 484 return 0xFF; 485 } 486 487 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 488 return 0; 489 } 490 491 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 492 { 493 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 494 495 if (client == INSTR_MI_CLIENT) 496 return 0x3F; 497 else if (client == INSTR_BC_CLIENT) 498 return 0xFF; 499 500 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 501 return 0; 502 } 503 504 static bool validate_cmds_sorted(struct intel_engine_cs *ring, 505 const struct drm_i915_cmd_table *cmd_tables, 506 int cmd_table_count) 507 { 508 int i; 509 bool ret = true; 510 511 if (!cmd_tables || cmd_table_count == 0) 512 return true; 513 514 for (i = 0; i < cmd_table_count; i++) { 515 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 516 u32 previous = 0; 517 int j; 518 519 for (j = 0; j < table->count; j++) { 520 const struct drm_i915_cmd_descriptor *desc = 521 &table->table[i]; 522 u32 curr = desc->cmd.value & desc->cmd.mask; 523 524 if (curr < previous) { 525 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 526 ring->id, i, j, curr, previous); 527 ret = false; 528 } 529 530 previous = curr; 531 } 532 } 533 534 return ret; 535 } 536 537 static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count) 538 { 539 int i; 540 u32 previous = 0; 541 bool ret = true; 542 543 for (i = 0; i < reg_count; i++) { 544 u32 curr = reg_table[i]; 545 546 if (curr < previous) { 547 DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n", 548 ring_id, i, curr, previous); 549 ret = false; 550 } 551 552 previous = curr; 553 } 554 555 return ret; 556 } 557 558 static bool validate_regs_sorted(struct intel_engine_cs *ring) 559 { 560 return check_sorted(ring->id, ring->reg_table, ring->reg_count) && 561 check_sorted(ring->id, ring->master_reg_table, 562 ring->master_reg_count); 563 } 564 565 struct cmd_node { 566 const struct drm_i915_cmd_descriptor *desc; 567 struct hlist_node node; 568 }; 569 570 /* 571 * Different command ranges have different numbers of bits for the opcode. For 572 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 573 * problem is that, for example, MI commands use bits 22:16 for other fields 574 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 575 * we mask a command from a batch it could hash to the wrong bucket due to 576 * non-opcode bits being set. But if we don't include those bits, some 3D 577 * commands may hash to the same bucket due to not including opcode bits that 578 * make the command unique. For now, we will risk hashing to the same bucket. 579 * 580 * If we attempt to generate a perfect hash, we should be able to look at bits 581 * 31:29 of a command from a batch buffer and use the full mask for that 582 * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this. 583 */ 584 #define CMD_HASH_MASK STD_MI_OPCODE_MASK 585 586 static int init_hash_table(struct intel_engine_cs *ring, 587 const struct drm_i915_cmd_table *cmd_tables, 588 int cmd_table_count) 589 { 590 #if 0 591 int i, j; 592 593 hash_init(ring->cmd_hash); 594 595 for (i = 0; i < cmd_table_count; i++) { 596 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 597 598 for (j = 0; j < table->count; j++) { 599 const struct drm_i915_cmd_descriptor *desc = 600 &table->table[j]; 601 struct cmd_node *desc_node = 602 kmalloc(sizeof(*desc_node), M_DRM, M_WAITOK); 603 604 if (!desc_node) 605 return -ENOMEM; 606 607 desc_node->desc = desc; 608 hash_add(ring->cmd_hash, &desc_node->node, 609 desc->cmd.value & CMD_HASH_MASK); 610 } 611 } 612 #endif 613 614 return 0; 615 } 616 617 static void fini_hash_table(struct intel_engine_cs *ring) 618 { 619 #if 0 620 struct hlist_node *tmp; 621 struct cmd_node *desc_node; 622 int i; 623 624 hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) { 625 hash_del(&desc_node->node); 626 kfree(desc_node); 627 } 628 #endif 629 } 630 631 /** 632 * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer 633 * @ring: the ringbuffer to initialize 634 * 635 * Optionally initializes fields related to batch buffer command parsing in the 636 * struct intel_engine_cs based on whether the platform requires software 637 * command parsing. 638 * 639 * Return: non-zero if initialization fails 640 */ 641 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring) 642 { 643 const struct drm_i915_cmd_table *cmd_tables; 644 int cmd_table_count; 645 int ret; 646 647 if (!IS_GEN7(ring->dev)) 648 return 0; 649 650 switch (ring->id) { 651 case RCS: 652 if (IS_HASWELL(ring->dev)) { 653 cmd_tables = hsw_render_ring_cmds; 654 cmd_table_count = 655 ARRAY_SIZE(hsw_render_ring_cmds); 656 } else { 657 cmd_tables = gen7_render_cmds; 658 cmd_table_count = ARRAY_SIZE(gen7_render_cmds); 659 } 660 661 ring->reg_table = gen7_render_regs; 662 ring->reg_count = ARRAY_SIZE(gen7_render_regs); 663 664 if (IS_HASWELL(ring->dev)) { 665 ring->master_reg_table = hsw_master_regs; 666 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); 667 } else { 668 ring->master_reg_table = ivb_master_regs; 669 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); 670 } 671 672 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 673 break; 674 case VCS: 675 cmd_tables = gen7_video_cmds; 676 cmd_table_count = ARRAY_SIZE(gen7_video_cmds); 677 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 678 break; 679 case BCS: 680 if (IS_HASWELL(ring->dev)) { 681 cmd_tables = hsw_blt_ring_cmds; 682 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); 683 } else { 684 cmd_tables = gen7_blt_cmds; 685 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); 686 } 687 688 ring->reg_table = gen7_blt_regs; 689 ring->reg_count = ARRAY_SIZE(gen7_blt_regs); 690 691 if (IS_HASWELL(ring->dev)) { 692 ring->master_reg_table = hsw_master_regs; 693 ring->master_reg_count = ARRAY_SIZE(hsw_master_regs); 694 } else { 695 ring->master_reg_table = ivb_master_regs; 696 ring->master_reg_count = ARRAY_SIZE(ivb_master_regs); 697 } 698 699 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 700 break; 701 case VECS: 702 cmd_tables = hsw_vebox_cmds; 703 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); 704 /* VECS can use the same length_mask function as VCS */ 705 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 706 break; 707 default: 708 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n", 709 ring->id); 710 BUG(); 711 } 712 713 BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count)); 714 BUG_ON(!validate_regs_sorted(ring)); 715 716 ret = init_hash_table(ring, cmd_tables, cmd_table_count); 717 if (ret) { 718 DRM_ERROR("CMD: cmd_parser_init failed!\n"); 719 fini_hash_table(ring); 720 return ret; 721 } 722 723 ring->needs_cmd_parser = true; 724 725 return 0; 726 } 727 728 /** 729 * i915_cmd_parser_fini_ring() - clean up cmd parser related fields 730 * @ring: the ringbuffer to clean up 731 * 732 * Releases any resources related to command parsing that may have been 733 * initialized for the specified ring. 734 */ 735 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring) 736 { 737 if (!ring->needs_cmd_parser) 738 return; 739 740 fini_hash_table(ring); 741 } 742 743 static const struct drm_i915_cmd_descriptor* 744 find_cmd_in_table(struct intel_engine_cs *ring, 745 u32 cmd_header) 746 { 747 #if 0 748 struct cmd_node *desc_node; 749 750 hash_for_each_possible(ring->cmd_hash, desc_node, node, 751 cmd_header & CMD_HASH_MASK) { 752 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 753 u32 masked_cmd = desc->cmd.mask & cmd_header; 754 u32 masked_value = desc->cmd.value & desc->cmd.mask; 755 756 if (masked_cmd == masked_value) 757 return desc; 758 } 759 #endif 760 761 return NULL; 762 } 763 764 /* 765 * Returns a pointer to a descriptor for the command specified by cmd_header. 766 * 767 * The caller must supply space for a default descriptor via the default_desc 768 * parameter. If no descriptor for the specified command exists in the ring's 769 * command parser tables, this function fills in default_desc based on the 770 * ring's default length encoding and returns default_desc. 771 */ 772 static const struct drm_i915_cmd_descriptor* 773 find_cmd(struct intel_engine_cs *ring, 774 u32 cmd_header, 775 struct drm_i915_cmd_descriptor *default_desc) 776 { 777 const struct drm_i915_cmd_descriptor *desc; 778 u32 mask; 779 780 desc = find_cmd_in_table(ring, cmd_header); 781 if (desc) 782 return desc; 783 784 mask = ring->get_cmd_length_mask(cmd_header); 785 if (!mask) 786 return NULL; 787 788 BUG_ON(!default_desc); 789 default_desc->flags = CMD_DESC_SKIP; 790 default_desc->length.mask = mask; 791 792 return default_desc; 793 } 794 795 static bool valid_reg(const u32 *table, int count, u32 addr) 796 { 797 if (table && count != 0) { 798 int i; 799 800 for (i = 0; i < count; i++) { 801 if (table[i] == addr) 802 return true; 803 } 804 } 805 806 return false; 807 } 808 809 static u32 *vmap_batch(struct drm_i915_gem_object *obj) 810 { 811 int i; 812 void *addr = NULL; 813 struct vm_page **pages; 814 815 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); 816 if (pages == NULL) { 817 DRM_DEBUG_DRIVER("Failed to get space for pages\n"); 818 goto finish; 819 } 820 821 i = 0; 822 while (i < obj->base.size >> PAGE_SHIFT) { 823 pages[i] = obj->pages[i]; 824 i++; 825 } 826 827 #if 0 828 addr = vmap(pages, i, 0, PAGE_KERNEL); 829 if (addr == NULL) { 830 DRM_DEBUG_DRIVER("Failed to vmap pages\n"); 831 goto finish; 832 } 833 #endif 834 835 finish: 836 if (pages) 837 drm_free_large(pages); 838 return (u32*)addr; 839 } 840 841 /** 842 * i915_needs_cmd_parser() - should a given ring use software command parsing? 843 * @ring: the ring in question 844 * 845 * Only certain platforms require software batch buffer command parsing, and 846 * only when enabled via module paramter. 847 * 848 * Return: true if the ring requires software command parsing 849 */ 850 bool i915_needs_cmd_parser(struct intel_engine_cs *ring) 851 { 852 if (!ring->needs_cmd_parser) 853 return false; 854 855 /* 856 * XXX: VLV is Gen7 and therefore has cmd_tables, but has PPGTT 857 * disabled. That will cause all of the parser's PPGTT checks to 858 * fail. For now, disable parsing when PPGTT is off. 859 */ 860 if (USES_PPGTT(ring->dev)) 861 return false; 862 863 return (i915.enable_cmd_parser == 1); 864 } 865 866 static bool check_cmd(const struct intel_engine_cs *ring, 867 const struct drm_i915_cmd_descriptor *desc, 868 const u32 *cmd, 869 const bool is_master, 870 bool *oacontrol_set) 871 { 872 if (desc->flags & CMD_DESC_REJECT) { 873 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); 874 return false; 875 } 876 877 if ((desc->flags & CMD_DESC_MASTER) && !is_master) { 878 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", 879 *cmd); 880 return false; 881 } 882 883 if (desc->flags & CMD_DESC_REGISTER) { 884 u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask; 885 886 /* 887 * OACONTROL requires some special handling for writes. We 888 * want to make sure that any batch which enables OA also 889 * disables it before the end of the batch. The goal is to 890 * prevent one process from snooping on the perf data from 891 * another process. To do that, we need to check the value 892 * that will be written to the register. Hence, limit 893 * OACONTROL writes to only MI_LOAD_REGISTER_IMM commands. 894 */ 895 if (reg_addr == OACONTROL) { 896 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) 897 return false; 898 899 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) 900 *oacontrol_set = (cmd[2] != 0); 901 } 902 903 if (!valid_reg(ring->reg_table, 904 ring->reg_count, reg_addr)) { 905 if (!is_master || 906 !valid_reg(ring->master_reg_table, 907 ring->master_reg_count, 908 reg_addr)) { 909 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n", 910 reg_addr, 911 *cmd, 912 ring->id); 913 return false; 914 } 915 } 916 } 917 918 if (desc->flags & CMD_DESC_BITMASK) { 919 int i; 920 921 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 922 u32 dword; 923 924 if (desc->bits[i].mask == 0) 925 break; 926 927 if (desc->bits[i].condition_mask != 0) { 928 u32 offset = 929 desc->bits[i].condition_offset; 930 u32 condition = cmd[offset] & 931 desc->bits[i].condition_mask; 932 933 if (condition == 0) 934 continue; 935 } 936 937 dword = cmd[desc->bits[i].offset] & 938 desc->bits[i].mask; 939 940 if (dword != desc->bits[i].expected) { 941 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n", 942 *cmd, 943 desc->bits[i].mask, 944 desc->bits[i].expected, 945 dword, ring->id); 946 return false; 947 } 948 } 949 } 950 951 return true; 952 } 953 954 #define LENGTH_BIAS 2 955 956 /** 957 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations 958 * @ring: the ring on which the batch is to execute 959 * @batch_obj: the batch buffer in question 960 * @batch_start_offset: byte offset in the batch at which execution starts 961 * @is_master: is the submitting process the drm master? 962 * 963 * Parses the specified batch buffer looking for privilege violations as 964 * described in the overview. 965 * 966 * Return: non-zero if the parser finds violations or otherwise fails 967 */ 968 int i915_parse_cmds(struct intel_engine_cs *ring, 969 struct drm_i915_gem_object *batch_obj, 970 u32 batch_start_offset, 971 bool is_master) 972 { 973 int ret = 0; 974 u32 *cmd, *batch_base, *batch_end; 975 struct drm_i915_cmd_descriptor default_desc = { 0 }; 976 int needs_clflush = 0; 977 bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ 978 979 ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush); 980 if (ret) { 981 DRM_DEBUG_DRIVER("CMD: failed to prep read\n"); 982 return ret; 983 } 984 985 batch_base = vmap_batch(batch_obj); 986 if (!batch_base) { 987 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n"); 988 i915_gem_object_unpin_pages(batch_obj); 989 return -ENOMEM; 990 } 991 992 if (needs_clflush) 993 drm_clflush_virt_range((char *)batch_base, batch_obj->base.size); 994 995 cmd = batch_base + (batch_start_offset / sizeof(*cmd)); 996 batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end)); 997 998 while (cmd < batch_end) { 999 const struct drm_i915_cmd_descriptor *desc; 1000 u32 length; 1001 1002 if (*cmd == MI_BATCH_BUFFER_END) 1003 break; 1004 1005 desc = find_cmd(ring, *cmd, &default_desc); 1006 if (!desc) { 1007 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", 1008 *cmd); 1009 ret = -EINVAL; 1010 break; 1011 } 1012 1013 if (desc->flags & CMD_DESC_FIXED) 1014 length = desc->length.fixed; 1015 else 1016 length = ((*cmd & desc->length.mask) + LENGTH_BIAS); 1017 1018 if ((batch_end - cmd) < length) { 1019 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1020 *cmd, 1021 length, 1022 batch_end - cmd); 1023 ret = -EINVAL; 1024 break; 1025 } 1026 1027 if (!check_cmd(ring, desc, cmd, is_master, &oacontrol_set)) { 1028 ret = -EINVAL; 1029 break; 1030 } 1031 1032 cmd += length; 1033 } 1034 1035 if (oacontrol_set) { 1036 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); 1037 ret = -EINVAL; 1038 } 1039 1040 if (cmd >= batch_end) { 1041 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1042 ret = -EINVAL; 1043 } 1044 1045 #if 0 1046 vunmap(batch_base); 1047 #endif 1048 1049 i915_gem_object_unpin_pages(batch_obj); 1050 1051 return ret; 1052 } 1053 1054 /** 1055 * i915_cmd_parser_get_version() - get the cmd parser version number 1056 * 1057 * The cmd parser maintains a simple increasing integer version number suitable 1058 * for passing to userspace clients to determine what operations are permitted. 1059 * 1060 * Return: the current version number of the cmd parser 1061 */ 1062 int i915_cmd_parser_get_version(void) 1063 { 1064 /* 1065 * Command parser version history 1066 * 1067 * 1. Initial version. Checks batches and reports violations, but leaves 1068 * hardware parsing enabled (so does not allow new use cases). 1069 */ 1070 return 1; 1071 } 1072