1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Brad Volkin <bradley.d.volkin@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 30 /** 31 * DOC: batch buffer command parser 32 * 33 * Motivation: 34 * Certain OpenGL features (e.g. transform feedback, performance monitoring) 35 * require userspace code to submit batches containing commands such as 36 * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some 37 * generations of the hardware will noop these commands in "unsecure" batches 38 * (which includes all userspace batches submitted via i915) even though the 39 * commands may be safe and represent the intended programming model of the 40 * device. 41 * 42 * The software command parser is similar in operation to the command parsing 43 * done in hardware for unsecure batches. However, the software parser allows 44 * some operations that would be noop'd by hardware, if the parser determines 45 * the operation is safe, and submits the batch as "secure" to prevent hardware 46 * parsing. 47 * 48 * Threats: 49 * At a high level, the hardware (and software) checks attempt to prevent 50 * granting userspace undue privileges. There are three categories of privilege. 51 * 52 * First, commands which are explicitly defined as privileged or which should 53 * only be used by the kernel driver. The parser generally rejects such 54 * commands, though it may allow some from the drm master process. 55 * 56 * Second, commands which access registers. To support correct/enhanced 57 * userspace functionality, particularly certain OpenGL extensions, the parser 58 * provides a whitelist of registers which userspace may safely access (for both 59 * normal and drm master processes). 60 * 61 * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc). 62 * The parser always rejects such commands. 63 * 64 * The majority of the problematic commands fall in the MI_* range, with only a 65 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW). 66 * 67 * Implementation: 68 * Each engine maintains tables of commands and registers which the parser 69 * uses in scanning batch buffers submitted to that engine. 70 * 71 * Since the set of commands that the parser must check for is significantly 72 * smaller than the number of commands supported, the parser tables contain only 73 * those commands required by the parser. This generally works because command 74 * opcode ranges have standard command length encodings. So for commands that 75 * the parser does not need to check, it can easily skip them. This is 76 * implemented via a per-engine length decoding vfunc. 77 * 78 * Unfortunately, there are a number of commands that do not follow the standard 79 * length encoding for their opcode range, primarily amongst the MI_* commands. 80 * To handle this, the parser provides a way to define explicit "skip" entries 81 * in the per-engine command tables. 82 * 83 * Other command table entries map fairly directly to high level categories 84 * mentioned above: rejected, master-only, register whitelist. The parser 85 * implements a number of checks, including the privileged memory checks, via a 86 * general bitmasking mechanism. 87 */ 88 89 #define STD_MI_OPCODE_SHIFT (32 - 9) 90 #define STD_3D_OPCODE_SHIFT (32 - 16) 91 #define STD_2D_OPCODE_SHIFT (32 - 10) 92 #define STD_MFX_OPCODE_SHIFT (32 - 16) 93 #define MIN_OPCODE_SHIFT 16 94 95 #define CMD(op, opm, f, lm, fl, ...) \ 96 { \ 97 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0), \ 98 .cmd = { (op), ~0u << (opm) }, \ 99 .length = { (lm) }, \ 100 __VA_ARGS__ \ 101 } 102 103 /* Convenience macros to compress the tables */ 104 #define SMI STD_MI_OPCODE_SHIFT 105 #define S3D STD_3D_OPCODE_SHIFT 106 #define S2D STD_2D_OPCODE_SHIFT 107 #define SMFX STD_MFX_OPCODE_SHIFT 108 #define F true 109 #define S CMD_DESC_SKIP 110 #define R CMD_DESC_REJECT 111 #define W CMD_DESC_REGISTER 112 #define B CMD_DESC_BITMASK 113 #define M CMD_DESC_MASTER 114 115 /* Command Mask Fixed Len Action 116 ---------------------------------------------------------- */ 117 static const struct drm_i915_cmd_descriptor common_cmds[] = { 118 CMD( MI_NOOP, SMI, F, 1, S ), 119 CMD( MI_USER_INTERRUPT, SMI, F, 1, R ), 120 CMD( MI_WAIT_FOR_EVENT, SMI, F, 1, M ), 121 CMD( MI_ARB_CHECK, SMI, F, 1, S ), 122 CMD( MI_REPORT_HEAD, SMI, F, 1, S ), 123 CMD( MI_SUSPEND_FLUSH, SMI, F, 1, S ), 124 CMD( MI_SEMAPHORE_MBOX, SMI, !F, 0xFF, R ), 125 CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), 126 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, 127 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), 128 CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, 129 .reg = { .offset = 1, .mask = 0x007FFFFC }, 130 .bits = {{ 131 .offset = 0, 132 .mask = MI_GLOBAL_GTT, 133 .expected = 0, 134 }}, ), 135 CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, 136 .reg = { .offset = 1, .mask = 0x007FFFFC }, 137 .bits = {{ 138 .offset = 0, 139 .mask = MI_GLOBAL_GTT, 140 .expected = 0, 141 }}, ), 142 /* 143 * MI_BATCH_BUFFER_START requires some special handling. It's not 144 * really a 'skip' action but it doesn't seem like it's worth adding 145 * a new action. See i915_parse_cmds(). 146 */ 147 CMD( MI_BATCH_BUFFER_START, SMI, !F, 0xFF, S ), 148 }; 149 150 static const struct drm_i915_cmd_descriptor render_cmds[] = { 151 CMD( MI_FLUSH, SMI, F, 1, S ), 152 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 153 CMD( MI_PREDICATE, SMI, F, 1, S ), 154 CMD( MI_TOPOLOGY_FILTER, SMI, F, 1, S ), 155 CMD( MI_SET_APPID, SMI, F, 1, S ), 156 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 157 CMD( MI_SET_CONTEXT, SMI, !F, 0xFF, R ), 158 CMD( MI_URB_CLEAR, SMI, !F, 0xFF, S ), 159 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3F, B, 160 .bits = {{ 161 .offset = 0, 162 .mask = MI_GLOBAL_GTT, 163 .expected = 0, 164 }}, ), 165 CMD( MI_UPDATE_GTT, SMI, !F, 0xFF, R ), 166 CMD( MI_CLFLUSH, SMI, !F, 0x3FF, B, 167 .bits = {{ 168 .offset = 0, 169 .mask = MI_GLOBAL_GTT, 170 .expected = 0, 171 }}, ), 172 CMD( MI_REPORT_PERF_COUNT, SMI, !F, 0x3F, B, 173 .bits = {{ 174 .offset = 1, 175 .mask = MI_REPORT_PERF_COUNT_GGTT, 176 .expected = 0, 177 }}, ), 178 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 179 .bits = {{ 180 .offset = 0, 181 .mask = MI_GLOBAL_GTT, 182 .expected = 0, 183 }}, ), 184 CMD( GFX_OP_3DSTATE_VF_STATISTICS, S3D, F, 1, S ), 185 CMD( PIPELINE_SELECT, S3D, F, 1, S ), 186 CMD( MEDIA_VFE_STATE, S3D, !F, 0xFFFF, B, 187 .bits = {{ 188 .offset = 2, 189 .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK, 190 .expected = 0, 191 }}, ), 192 CMD( GPGPU_OBJECT, S3D, !F, 0xFF, S ), 193 CMD( GPGPU_WALKER, S3D, !F, 0xFF, S ), 194 CMD( GFX_OP_3DSTATE_SO_DECL_LIST, S3D, !F, 0x1FF, S ), 195 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B, 196 .bits = {{ 197 .offset = 1, 198 .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY), 199 .expected = 0, 200 }, 201 { 202 .offset = 1, 203 .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB | 204 PIPE_CONTROL_STORE_DATA_INDEX), 205 .expected = 0, 206 .condition_offset = 1, 207 .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK, 208 }}, ), 209 }; 210 211 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = { 212 CMD( MI_SET_PREDICATE, SMI, F, 1, S ), 213 CMD( MI_RS_CONTROL, SMI, F, 1, S ), 214 CMD( MI_URB_ATOMIC_ALLOC, SMI, F, 1, S ), 215 CMD( MI_SET_APPID, SMI, F, 1, S ), 216 CMD( MI_RS_CONTEXT, SMI, F, 1, S ), 217 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 218 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 219 CMD( MI_LOAD_REGISTER_REG, SMI, !F, 0xFF, W, 220 .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 1 } ), 221 CMD( MI_RS_STORE_DATA_IMM, SMI, !F, 0xFF, S ), 222 CMD( MI_LOAD_URB_MEM, SMI, !F, 0xFF, S ), 223 CMD( MI_STORE_URB_MEM, SMI, !F, 0xFF, S ), 224 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_VS, S3D, !F, 0x7FF, S ), 225 CMD( GFX_OP_3DSTATE_DX9_CONSTANTF_PS, S3D, !F, 0x7FF, S ), 226 227 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS, S3D, !F, 0x1FF, S ), 228 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS, S3D, !F, 0x1FF, S ), 229 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS, S3D, !F, 0x1FF, S ), 230 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS, S3D, !F, 0x1FF, S ), 231 CMD( GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS, S3D, !F, 0x1FF, S ), 232 }; 233 234 static const struct drm_i915_cmd_descriptor video_cmds[] = { 235 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 236 CMD( MI_SET_APPID, SMI, F, 1, S ), 237 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 238 .bits = {{ 239 .offset = 0, 240 .mask = MI_GLOBAL_GTT, 241 .expected = 0, 242 }}, ), 243 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 244 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 245 .bits = {{ 246 .offset = 0, 247 .mask = MI_FLUSH_DW_NOTIFY, 248 .expected = 0, 249 }, 250 { 251 .offset = 1, 252 .mask = MI_FLUSH_DW_USE_GTT, 253 .expected = 0, 254 .condition_offset = 0, 255 .condition_mask = MI_FLUSH_DW_OP_MASK, 256 }, 257 { 258 .offset = 0, 259 .mask = MI_FLUSH_DW_STORE_INDEX, 260 .expected = 0, 261 .condition_offset = 0, 262 .condition_mask = MI_FLUSH_DW_OP_MASK, 263 }}, ), 264 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 265 .bits = {{ 266 .offset = 0, 267 .mask = MI_GLOBAL_GTT, 268 .expected = 0, 269 }}, ), 270 /* 271 * MFX_WAIT doesn't fit the way we handle length for most commands. 272 * It has a length field but it uses a non-standard length bias. 273 * It is always 1 dword though, so just treat it as fixed length. 274 */ 275 CMD( MFX_WAIT, SMFX, F, 1, S ), 276 }; 277 278 static const struct drm_i915_cmd_descriptor vecs_cmds[] = { 279 CMD( MI_ARB_ON_OFF, SMI, F, 1, R ), 280 CMD( MI_SET_APPID, SMI, F, 1, S ), 281 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0xFF, B, 282 .bits = {{ 283 .offset = 0, 284 .mask = MI_GLOBAL_GTT, 285 .expected = 0, 286 }}, ), 287 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 288 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 289 .bits = {{ 290 .offset = 0, 291 .mask = MI_FLUSH_DW_NOTIFY, 292 .expected = 0, 293 }, 294 { 295 .offset = 1, 296 .mask = MI_FLUSH_DW_USE_GTT, 297 .expected = 0, 298 .condition_offset = 0, 299 .condition_mask = MI_FLUSH_DW_OP_MASK, 300 }, 301 { 302 .offset = 0, 303 .mask = MI_FLUSH_DW_STORE_INDEX, 304 .expected = 0, 305 .condition_offset = 0, 306 .condition_mask = MI_FLUSH_DW_OP_MASK, 307 }}, ), 308 CMD( MI_CONDITIONAL_BATCH_BUFFER_END, SMI, !F, 0xFF, B, 309 .bits = {{ 310 .offset = 0, 311 .mask = MI_GLOBAL_GTT, 312 .expected = 0, 313 }}, ), 314 }; 315 316 static const struct drm_i915_cmd_descriptor blt_cmds[] = { 317 CMD( MI_DISPLAY_FLIP, SMI, !F, 0xFF, R ), 318 CMD( MI_STORE_DWORD_IMM, SMI, !F, 0x3FF, B, 319 .bits = {{ 320 .offset = 0, 321 .mask = MI_GLOBAL_GTT, 322 .expected = 0, 323 }}, ), 324 CMD( MI_UPDATE_GTT, SMI, !F, 0x3F, R ), 325 CMD( MI_FLUSH_DW, SMI, !F, 0x3F, B, 326 .bits = {{ 327 .offset = 0, 328 .mask = MI_FLUSH_DW_NOTIFY, 329 .expected = 0, 330 }, 331 { 332 .offset = 1, 333 .mask = MI_FLUSH_DW_USE_GTT, 334 .expected = 0, 335 .condition_offset = 0, 336 .condition_mask = MI_FLUSH_DW_OP_MASK, 337 }, 338 { 339 .offset = 0, 340 .mask = MI_FLUSH_DW_STORE_INDEX, 341 .expected = 0, 342 .condition_offset = 0, 343 .condition_mask = MI_FLUSH_DW_OP_MASK, 344 }}, ), 345 CMD( COLOR_BLT, S2D, !F, 0x3F, S ), 346 CMD( SRC_COPY_BLT, S2D, !F, 0x3F, S ), 347 }; 348 349 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = { 350 CMD( MI_LOAD_SCAN_LINES_INCL, SMI, !F, 0x3F, M ), 351 CMD( MI_LOAD_SCAN_LINES_EXCL, SMI, !F, 0x3F, R ), 352 }; 353 354 static const struct drm_i915_cmd_descriptor noop_desc = 355 CMD(MI_NOOP, SMI, F, 1, S); 356 357 #undef CMD 358 #undef SMI 359 #undef S3D 360 #undef S2D 361 #undef SMFX 362 #undef F 363 #undef S 364 #undef R 365 #undef W 366 #undef B 367 #undef M 368 369 static const struct drm_i915_cmd_table gen7_render_cmds[] = { 370 { common_cmds, ARRAY_SIZE(common_cmds) }, 371 { render_cmds, ARRAY_SIZE(render_cmds) }, 372 }; 373 374 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = { 375 { common_cmds, ARRAY_SIZE(common_cmds) }, 376 { render_cmds, ARRAY_SIZE(render_cmds) }, 377 { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) }, 378 }; 379 380 static const struct drm_i915_cmd_table gen7_video_cmds[] = { 381 { common_cmds, ARRAY_SIZE(common_cmds) }, 382 { video_cmds, ARRAY_SIZE(video_cmds) }, 383 }; 384 385 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = { 386 { common_cmds, ARRAY_SIZE(common_cmds) }, 387 { vecs_cmds, ARRAY_SIZE(vecs_cmds) }, 388 }; 389 390 static const struct drm_i915_cmd_table gen7_blt_cmds[] = { 391 { common_cmds, ARRAY_SIZE(common_cmds) }, 392 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 393 }; 394 395 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = { 396 { common_cmds, ARRAY_SIZE(common_cmds) }, 397 { blt_cmds, ARRAY_SIZE(blt_cmds) }, 398 { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) }, 399 }; 400 401 /* 402 * Register whitelists, sorted by increasing register offset. 403 */ 404 405 /* 406 * An individual whitelist entry granting access to register addr. If 407 * mask is non-zero the argument of immediate register writes will be 408 * AND-ed with mask, and the command will be rejected if the result 409 * doesn't match value. 410 * 411 * Registers with non-zero mask are only allowed to be written using 412 * LRI. 413 */ 414 struct drm_i915_reg_descriptor { 415 i915_reg_t addr; 416 u32 mask; 417 u32 value; 418 }; 419 420 /* Convenience macro for adding 32-bit registers. */ 421 #define REG32(_reg, ...) \ 422 { .addr = (_reg), __VA_ARGS__ } 423 424 /* 425 * Convenience macro for adding 64-bit registers. 426 * 427 * Some registers that userspace accesses are 64 bits. The register 428 * access commands only allow 32-bit accesses. Hence, we have to include 429 * entries for both halves of the 64-bit registers. 430 */ 431 #define REG64(_reg) \ 432 { .addr = _reg }, \ 433 { .addr = _reg ## _UDW } 434 435 #define REG64_IDX(_reg, idx) \ 436 { .addr = _reg(idx) }, \ 437 { .addr = _reg ## _UDW(idx) } 438 439 static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 440 REG64(GPGPU_THREADS_DISPATCHED), 441 REG64(HS_INVOCATION_COUNT), 442 REG64(DS_INVOCATION_COUNT), 443 REG64(IA_VERTICES_COUNT), 444 REG64(IA_PRIMITIVES_COUNT), 445 REG64(VS_INVOCATION_COUNT), 446 REG64(GS_INVOCATION_COUNT), 447 REG64(GS_PRIMITIVES_COUNT), 448 REG64(CL_INVOCATION_COUNT), 449 REG64(CL_PRIMITIVES_COUNT), 450 REG64(PS_INVOCATION_COUNT), 451 REG64(PS_DEPTH_COUNT), 452 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 453 REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */ 454 REG64(MI_PREDICATE_SRC0), 455 REG64(MI_PREDICATE_SRC1), 456 REG32(GEN7_3DPRIM_END_OFFSET), 457 REG32(GEN7_3DPRIM_START_VERTEX), 458 REG32(GEN7_3DPRIM_VERTEX_COUNT), 459 REG32(GEN7_3DPRIM_INSTANCE_COUNT), 460 REG32(GEN7_3DPRIM_START_INSTANCE), 461 REG32(GEN7_3DPRIM_BASE_VERTEX), 462 REG32(GEN7_GPGPU_DISPATCHDIMX), 463 REG32(GEN7_GPGPU_DISPATCHDIMY), 464 REG32(GEN7_GPGPU_DISPATCHDIMZ), 465 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 466 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0), 467 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1), 468 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2), 469 REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3), 470 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0), 471 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1), 472 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2), 473 REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3), 474 REG32(GEN7_SO_WRITE_OFFSET(0)), 475 REG32(GEN7_SO_WRITE_OFFSET(1)), 476 REG32(GEN7_SO_WRITE_OFFSET(2)), 477 REG32(GEN7_SO_WRITE_OFFSET(3)), 478 REG32(GEN7_L3SQCREG1), 479 REG32(GEN7_L3CNTLREG2), 480 REG32(GEN7_L3CNTLREG3), 481 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 482 }; 483 484 static const struct drm_i915_reg_descriptor hsw_render_regs[] = { 485 REG64_IDX(HSW_CS_GPR, 0), 486 REG64_IDX(HSW_CS_GPR, 1), 487 REG64_IDX(HSW_CS_GPR, 2), 488 REG64_IDX(HSW_CS_GPR, 3), 489 REG64_IDX(HSW_CS_GPR, 4), 490 REG64_IDX(HSW_CS_GPR, 5), 491 REG64_IDX(HSW_CS_GPR, 6), 492 REG64_IDX(HSW_CS_GPR, 7), 493 REG64_IDX(HSW_CS_GPR, 8), 494 REG64_IDX(HSW_CS_GPR, 9), 495 REG64_IDX(HSW_CS_GPR, 10), 496 REG64_IDX(HSW_CS_GPR, 11), 497 REG64_IDX(HSW_CS_GPR, 12), 498 REG64_IDX(HSW_CS_GPR, 13), 499 REG64_IDX(HSW_CS_GPR, 14), 500 REG64_IDX(HSW_CS_GPR, 15), 501 REG32(HSW_SCRATCH1, 502 .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE, 503 .value = 0), 504 REG32(HSW_ROW_CHICKEN3, 505 .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 | 506 HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE), 507 .value = 0), 508 }; 509 510 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = { 511 REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE), 512 REG64_IDX(RING_TIMESTAMP, BSD_RING_BASE), 513 REG32(BCS_SWCTRL), 514 REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE), 515 }; 516 517 static const struct drm_i915_reg_descriptor ivb_master_regs[] = { 518 REG32(FORCEWAKE_MT), 519 REG32(DERRMR), 520 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)), 521 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)), 522 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)), 523 }; 524 525 static const struct drm_i915_reg_descriptor hsw_master_regs[] = { 526 REG32(FORCEWAKE_MT), 527 REG32(DERRMR), 528 }; 529 530 #undef REG64 531 #undef REG32 532 533 struct drm_i915_reg_table { 534 const struct drm_i915_reg_descriptor *regs; 535 int num_regs; 536 bool master; 537 }; 538 539 static const struct drm_i915_reg_table ivb_render_reg_tables[] = { 540 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, 541 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, 542 }; 543 544 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = { 545 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, 546 { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true }, 547 }; 548 549 static const struct drm_i915_reg_table hsw_render_reg_tables[] = { 550 { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false }, 551 { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false }, 552 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, 553 }; 554 555 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = { 556 { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false }, 557 { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true }, 558 }; 559 560 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header) 561 { 562 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 563 u32 subclient = 564 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 565 566 if (client == INSTR_MI_CLIENT) 567 return 0x3F; 568 else if (client == INSTR_RC_CLIENT) { 569 if (subclient == INSTR_MEDIA_SUBCLIENT) 570 return 0xFFFF; 571 else 572 return 0xFF; 573 } 574 575 DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header); 576 return 0; 577 } 578 579 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header) 580 { 581 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 582 u32 subclient = 583 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT; 584 u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT; 585 586 if (client == INSTR_MI_CLIENT) 587 return 0x3F; 588 else if (client == INSTR_RC_CLIENT) { 589 if (subclient == INSTR_MEDIA_SUBCLIENT) { 590 if (op == 6) 591 return 0xFFFF; 592 else 593 return 0xFFF; 594 } else 595 return 0xFF; 596 } 597 598 DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header); 599 return 0; 600 } 601 602 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header) 603 { 604 u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT; 605 606 if (client == INSTR_MI_CLIENT) 607 return 0x3F; 608 else if (client == INSTR_BC_CLIENT) 609 return 0xFF; 610 611 DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header); 612 return 0; 613 } 614 615 static bool validate_cmds_sorted(const struct intel_engine_cs *engine, 616 const struct drm_i915_cmd_table *cmd_tables, 617 int cmd_table_count) 618 { 619 int i; 620 bool ret = true; 621 622 if (!cmd_tables || cmd_table_count == 0) 623 return true; 624 625 for (i = 0; i < cmd_table_count; i++) { 626 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 627 u32 previous = 0; 628 int j; 629 630 for (j = 0; j < table->count; j++) { 631 const struct drm_i915_cmd_descriptor *desc = 632 &table->table[j]; 633 u32 curr = desc->cmd.value & desc->cmd.mask; 634 635 if (curr < previous) { 636 DRM_ERROR("CMD: %s [%d] command table not sorted: " 637 "table=%d entry=%d cmd=0x%08X prev=0x%08X\n", 638 engine->name, engine->id, 639 i, j, curr, previous); 640 ret = false; 641 } 642 643 previous = curr; 644 } 645 } 646 647 return ret; 648 } 649 650 static bool check_sorted(const struct intel_engine_cs *engine, 651 const struct drm_i915_reg_descriptor *reg_table, 652 int reg_count) 653 { 654 int i; 655 u32 previous = 0; 656 bool ret = true; 657 658 for (i = 0; i < reg_count; i++) { 659 u32 curr = i915_mmio_reg_offset(reg_table[i].addr); 660 661 if (curr < previous) { 662 DRM_ERROR("CMD: %s [%d] register table not sorted: " 663 "entry=%d reg=0x%08X prev=0x%08X\n", 664 engine->name, engine->id, 665 i, curr, previous); 666 ret = false; 667 } 668 669 previous = curr; 670 } 671 672 return ret; 673 } 674 675 static bool validate_regs_sorted(struct intel_engine_cs *engine) 676 { 677 int i; 678 const struct drm_i915_reg_table *table; 679 680 for (i = 0; i < engine->reg_table_count; i++) { 681 table = &engine->reg_tables[i]; 682 if (!check_sorted(engine, table->regs, table->num_regs)) 683 return false; 684 } 685 686 return true; 687 } 688 689 struct cmd_node { 690 const struct drm_i915_cmd_descriptor *desc; 691 struct hlist_node node; 692 }; 693 694 /* 695 * Different command ranges have different numbers of bits for the opcode. For 696 * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The 697 * problem is that, for example, MI commands use bits 22:16 for other fields 698 * such as GGTT vs PPGTT bits. If we include those bits in the mask then when 699 * we mask a command from a batch it could hash to the wrong bucket due to 700 * non-opcode bits being set. But if we don't include those bits, some 3D 701 * commands may hash to the same bucket due to not including opcode bits that 702 * make the command unique. For now, we will risk hashing to the same bucket. 703 */ 704 static inline u32 cmd_header_key(u32 x) 705 { 706 u32 shift; 707 708 switch (x >> INSTR_CLIENT_SHIFT) { 709 default: 710 case INSTR_MI_CLIENT: 711 shift = STD_MI_OPCODE_SHIFT; 712 break; 713 case INSTR_RC_CLIENT: 714 shift = STD_3D_OPCODE_SHIFT; 715 break; 716 case INSTR_BC_CLIENT: 717 shift = STD_2D_OPCODE_SHIFT; 718 break; 719 } 720 721 return x >> shift; 722 } 723 724 static int init_hash_table(struct intel_engine_cs *engine, 725 const struct drm_i915_cmd_table *cmd_tables, 726 int cmd_table_count) 727 { 728 int i, j; 729 730 hash_init(engine->cmd_hash); 731 732 for (i = 0; i < cmd_table_count; i++) { 733 const struct drm_i915_cmd_table *table = &cmd_tables[i]; 734 735 for (j = 0; j < table->count; j++) { 736 const struct drm_i915_cmd_descriptor *desc = 737 &table->table[j]; 738 struct cmd_node *desc_node = 739 kmalloc(sizeof(*desc_node), M_DRM, GFP_KERNEL); 740 741 if (!desc_node) 742 return -ENOMEM; 743 744 desc_node->desc = desc; 745 hash_add(engine->cmd_hash, &desc_node->node, 746 cmd_header_key(desc->cmd.value)); 747 } 748 } 749 750 return 0; 751 } 752 753 static void fini_hash_table(struct intel_engine_cs *engine) 754 { 755 struct hlist_node *tmp; 756 struct cmd_node *desc_node; 757 int i; 758 759 hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) { 760 hash_del(&desc_node->node); 761 kfree(desc_node); 762 } 763 } 764 765 /** 766 * intel_engine_init_cmd_parser() - set cmd parser related fields for an engine 767 * @engine: the engine to initialize 768 * 769 * Optionally initializes fields related to batch buffer command parsing in the 770 * struct intel_engine_cs based on whether the platform requires software 771 * command parsing. 772 */ 773 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) 774 { 775 const struct drm_i915_cmd_table *cmd_tables; 776 int cmd_table_count; 777 int ret; 778 779 if (!IS_GEN7(engine->i915)) 780 return; 781 782 switch (engine->id) { 783 case RCS: 784 if (IS_HASWELL(engine->i915)) { 785 cmd_tables = hsw_render_ring_cmds; 786 cmd_table_count = 787 ARRAY_SIZE(hsw_render_ring_cmds); 788 } else { 789 cmd_tables = gen7_render_cmds; 790 cmd_table_count = ARRAY_SIZE(gen7_render_cmds); 791 } 792 793 if (IS_HASWELL(engine->i915)) { 794 engine->reg_tables = hsw_render_reg_tables; 795 engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables); 796 } else { 797 engine->reg_tables = ivb_render_reg_tables; 798 engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables); 799 } 800 801 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask; 802 break; 803 case VCS: 804 cmd_tables = gen7_video_cmds; 805 cmd_table_count = ARRAY_SIZE(gen7_video_cmds); 806 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 807 break; 808 case BCS: 809 if (IS_HASWELL(engine->i915)) { 810 cmd_tables = hsw_blt_ring_cmds; 811 cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds); 812 } else { 813 cmd_tables = gen7_blt_cmds; 814 cmd_table_count = ARRAY_SIZE(gen7_blt_cmds); 815 } 816 817 if (IS_HASWELL(engine->i915)) { 818 engine->reg_tables = hsw_blt_reg_tables; 819 engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables); 820 } else { 821 engine->reg_tables = ivb_blt_reg_tables; 822 engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables); 823 } 824 825 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask; 826 break; 827 case VECS: 828 cmd_tables = hsw_vebox_cmds; 829 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds); 830 /* VECS can use the same length_mask function as VCS */ 831 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask; 832 break; 833 default: 834 MISSING_CASE(engine->id); 835 return; 836 } 837 838 if (!validate_cmds_sorted(engine, cmd_tables, cmd_table_count)) { 839 DRM_ERROR("%s: command descriptions are not sorted\n", 840 engine->name); 841 return; 842 } 843 if (!validate_regs_sorted(engine)) { 844 DRM_ERROR("%s: registers are not sorted\n", engine->name); 845 return; 846 } 847 848 ret = init_hash_table(engine, cmd_tables, cmd_table_count); 849 if (ret) { 850 DRM_ERROR("%s: initialised failed!\n", engine->name); 851 fini_hash_table(engine); 852 return; 853 } 854 855 engine->needs_cmd_parser = true; 856 } 857 858 /** 859 * intel_engine_cleanup_cmd_parser() - clean up cmd parser related fields 860 * @engine: the engine to clean up 861 * 862 * Releases any resources related to command parsing that may have been 863 * initialized for the specified engine. 864 */ 865 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine) 866 { 867 if (!engine->needs_cmd_parser) 868 return; 869 870 fini_hash_table(engine); 871 } 872 873 static const struct drm_i915_cmd_descriptor* 874 find_cmd_in_table(struct intel_engine_cs *engine, 875 u32 cmd_header) 876 { 877 struct cmd_node *desc_node; 878 879 hash_for_each_possible(engine->cmd_hash, desc_node, node, 880 cmd_header_key(cmd_header)) { 881 const struct drm_i915_cmd_descriptor *desc = desc_node->desc; 882 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 883 return desc; 884 } 885 886 return NULL; 887 } 888 889 /* 890 * Returns a pointer to a descriptor for the command specified by cmd_header. 891 * 892 * The caller must supply space for a default descriptor via the default_desc 893 * parameter. If no descriptor for the specified command exists in the engine's 894 * command parser tables, this function fills in default_desc based on the 895 * engine's default length encoding and returns default_desc. 896 */ 897 static const struct drm_i915_cmd_descriptor* 898 find_cmd(struct intel_engine_cs *engine, 899 u32 cmd_header, 900 const struct drm_i915_cmd_descriptor *desc, 901 struct drm_i915_cmd_descriptor *default_desc) 902 { 903 u32 mask; 904 905 if (((cmd_header ^ desc->cmd.value) & desc->cmd.mask) == 0) 906 return desc; 907 908 desc = find_cmd_in_table(engine, cmd_header); 909 if (desc) 910 return desc; 911 912 mask = engine->get_cmd_length_mask(cmd_header); 913 if (!mask) 914 return NULL; 915 916 default_desc->cmd.value = cmd_header; 917 default_desc->cmd.mask = ~0u << MIN_OPCODE_SHIFT; 918 default_desc->length.mask = mask; 919 default_desc->flags = CMD_DESC_SKIP; 920 return default_desc; 921 } 922 923 static const struct drm_i915_reg_descriptor * 924 __find_reg(const struct drm_i915_reg_descriptor *table, int count, u32 addr) 925 { 926 int start = 0, end = count; 927 while (start < end) { 928 int mid = start + (end - start) / 2; 929 int ret = addr - i915_mmio_reg_offset(table[mid].addr); 930 if (ret < 0) 931 end = mid; 932 else if (ret > 0) 933 start = mid + 1; 934 else 935 return &table[mid]; 936 } 937 return NULL; 938 } 939 940 static const struct drm_i915_reg_descriptor * 941 find_reg(const struct intel_engine_cs *engine, bool is_master, u32 addr) 942 { 943 const struct drm_i915_reg_table *table = engine->reg_tables; 944 int count = engine->reg_table_count; 945 946 do { 947 if (!table->master || is_master) { 948 const struct drm_i915_reg_descriptor *reg; 949 950 reg = __find_reg(table->regs, table->num_regs, addr); 951 if (reg != NULL) 952 return reg; 953 } 954 } while (table++, --count); 955 956 return NULL; 957 } 958 959 /* Returns a vmap'd pointer to dst_obj, which the caller must unmap */ 960 static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 961 struct drm_i915_gem_object *src_obj, 962 u32 batch_start_offset, 963 u32 batch_len, 964 bool *needs_clflush_after) 965 { 966 unsigned int src_needs_clflush; 967 unsigned int dst_needs_clflush; 968 void *dst, *src; 969 int ret; 970 971 ret = i915_gem_obj_prepare_shmem_read(src_obj, &src_needs_clflush); 972 if (ret) 973 return ERR_PTR(ret); 974 975 ret = i915_gem_obj_prepare_shmem_write(dst_obj, &dst_needs_clflush); 976 if (ret) { 977 dst = ERR_PTR(ret); 978 goto unpin_src; 979 } 980 981 dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB); 982 if (IS_ERR(dst)) 983 goto unpin_dst; 984 985 src = ERR_PTR(-ENODEV); 986 if (src_needs_clflush && 987 i915_memcpy_from_wc((void *)(uintptr_t)batch_start_offset, NULL, 0)) { 988 src = i915_gem_object_pin_map(src_obj, I915_MAP_WC); 989 if (!IS_ERR(src)) { 990 i915_memcpy_from_wc(dst, 991 src + batch_start_offset, 992 ALIGN(batch_len, 16)); 993 i915_gem_object_unpin_map(src_obj); 994 } 995 } 996 if (IS_ERR(src)) { 997 void *ptr; 998 int offset, n; 999 1000 offset = offset_in_page(batch_start_offset); 1001 1002 /* We can avoid clflushing partial cachelines before the write 1003 * if we only every write full cache-lines. Since we know that 1004 * both the source and destination are in multiples of 1005 * PAGE_SIZE, we can simply round up to the next cacheline. 1006 * We don't care about copying too much here as we only 1007 * validate up to the end of the batch. 1008 */ 1009 if (dst_needs_clflush & CLFLUSH_BEFORE) 1010 batch_len = roundup(batch_len, 1011 boot_cpu_data.x86_clflush_size); 1012 1013 ptr = dst; 1014 for (n = batch_start_offset >> PAGE_SHIFT; batch_len; n++) { 1015 int len = min_t(int, batch_len, PAGE_SIZE - offset); 1016 1017 src = kmap_atomic(i915_gem_object_get_page(src_obj, n)); 1018 if (src_needs_clflush) 1019 drm_clflush_virt_range(src + offset, len); 1020 memcpy(ptr, src + offset, len); 1021 kunmap_atomic(src); 1022 1023 ptr += len; 1024 batch_len -= len; 1025 offset = 0; 1026 } 1027 } 1028 1029 /* dst_obj is returned with vmap pinned */ 1030 *needs_clflush_after = dst_needs_clflush & CLFLUSH_AFTER; 1031 1032 unpin_dst: 1033 i915_gem_obj_finish_shmem_access(dst_obj); 1034 unpin_src: 1035 i915_gem_obj_finish_shmem_access(src_obj); 1036 return dst; 1037 } 1038 1039 /** 1040 * intel_engine_needs_cmd_parser() - should a given engine use software 1041 * command parsing? 1042 * @engine: the engine in question 1043 * 1044 * Only certain platforms require software batch buffer command parsing, and 1045 * only when enabled via module parameter. 1046 * 1047 * Return: true if the engine requires software command parsing 1048 */ 1049 bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine) 1050 { 1051 if (!engine->needs_cmd_parser) 1052 return false; 1053 1054 if (!USES_PPGTT(engine->i915)) 1055 return false; 1056 1057 return (i915.enable_cmd_parser == 1); 1058 } 1059 1060 static bool check_cmd(const struct intel_engine_cs *engine, 1061 const struct drm_i915_cmd_descriptor *desc, 1062 const u32 *cmd, u32 length, 1063 const bool is_master, 1064 bool *oacontrol_set) 1065 { 1066 if (desc->flags & CMD_DESC_SKIP) 1067 return true; 1068 1069 if (desc->flags & CMD_DESC_REJECT) { 1070 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd); 1071 return false; 1072 } 1073 1074 if ((desc->flags & CMD_DESC_MASTER) && !is_master) { 1075 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n", 1076 *cmd); 1077 return false; 1078 } 1079 1080 if (desc->flags & CMD_DESC_REGISTER) { 1081 /* 1082 * Get the distance between individual register offset 1083 * fields if the command can perform more than one 1084 * access at a time. 1085 */ 1086 const u32 step = desc->reg.step ? desc->reg.step : length; 1087 u32 offset; 1088 1089 for (offset = desc->reg.offset; offset < length; 1090 offset += step) { 1091 const u32 reg_addr = cmd[offset] & desc->reg.mask; 1092 const struct drm_i915_reg_descriptor *reg = 1093 find_reg(engine, is_master, reg_addr); 1094 1095 if (!reg) { 1096 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (exec_id=%d)\n", 1097 reg_addr, *cmd, engine->exec_id); 1098 return false; 1099 } 1100 1101 /* 1102 * OACONTROL requires some special handling for 1103 * writes. We want to make sure that any batch which 1104 * enables OA also disables it before the end of the 1105 * batch. The goal is to prevent one process from 1106 * snooping on the perf data from another process. To do 1107 * that, we need to check the value that will be written 1108 * to the register. Hence, limit OACONTROL writes to 1109 * only MI_LOAD_REGISTER_IMM commands. 1110 */ 1111 if (reg_addr == i915_mmio_reg_offset(OACONTROL)) { 1112 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1113 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); 1114 return false; 1115 } 1116 1117 if (desc->cmd.value == MI_LOAD_REGISTER_REG) { 1118 DRM_DEBUG_DRIVER("CMD: Rejected LRR to OACONTROL\n"); 1119 return false; 1120 } 1121 1122 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1)) 1123 *oacontrol_set = (cmd[offset + 1] != 0); 1124 } 1125 1126 /* 1127 * Check the value written to the register against the 1128 * allowed mask/value pair given in the whitelist entry. 1129 */ 1130 if (reg->mask) { 1131 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { 1132 DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n", 1133 reg_addr); 1134 return false; 1135 } 1136 1137 if (desc->cmd.value == MI_LOAD_REGISTER_REG) { 1138 DRM_DEBUG_DRIVER("CMD: Rejected LRR to masked register 0x%08X\n", 1139 reg_addr); 1140 return false; 1141 } 1142 1143 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) && 1144 (offset + 2 > length || 1145 (cmd[offset + 1] & reg->mask) != reg->value)) { 1146 DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n", 1147 reg_addr); 1148 return false; 1149 } 1150 } 1151 } 1152 } 1153 1154 if (desc->flags & CMD_DESC_BITMASK) { 1155 int i; 1156 1157 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) { 1158 u32 dword; 1159 1160 if (desc->bits[i].mask == 0) 1161 break; 1162 1163 if (desc->bits[i].condition_mask != 0) { 1164 u32 offset = 1165 desc->bits[i].condition_offset; 1166 u32 condition = cmd[offset] & 1167 desc->bits[i].condition_mask; 1168 1169 if (condition == 0) 1170 continue; 1171 } 1172 1173 dword = cmd[desc->bits[i].offset] & 1174 desc->bits[i].mask; 1175 1176 if (dword != desc->bits[i].expected) { 1177 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (exec_id=%d)\n", 1178 *cmd, 1179 desc->bits[i].mask, 1180 desc->bits[i].expected, 1181 dword, engine->exec_id); 1182 return false; 1183 } 1184 } 1185 } 1186 1187 return true; 1188 } 1189 1190 #define LENGTH_BIAS 2 1191 1192 /** 1193 * i915_parse_cmds() - parse a submitted batch buffer for privilege violations 1194 * @engine: the engine on which the batch is to execute 1195 * @batch_obj: the batch buffer in question 1196 * @shadow_batch_obj: copy of the batch buffer in question 1197 * @batch_start_offset: byte offset in the batch at which execution starts 1198 * @batch_len: length of the commands in batch_obj 1199 * @is_master: is the submitting process the drm master? 1200 * 1201 * Parses the specified batch buffer looking for privilege violations as 1202 * described in the overview. 1203 * 1204 * Return: non-zero if the parser finds violations or otherwise fails; -EACCES 1205 * if the batch appears legal but should use hardware parsing 1206 */ 1207 int intel_engine_cmd_parser(struct intel_engine_cs *engine, 1208 struct drm_i915_gem_object *batch_obj, 1209 struct drm_i915_gem_object *shadow_batch_obj, 1210 u32 batch_start_offset, 1211 u32 batch_len, 1212 bool is_master) 1213 { 1214 u32 *cmd, *batch_end; 1215 struct drm_i915_cmd_descriptor default_desc = noop_desc; 1216 const struct drm_i915_cmd_descriptor *desc = &default_desc; 1217 bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */ 1218 bool needs_clflush_after = false; 1219 int ret = 0; 1220 1221 cmd = copy_batch(shadow_batch_obj, batch_obj, 1222 batch_start_offset, batch_len, 1223 &needs_clflush_after); 1224 if (IS_ERR(cmd)) { 1225 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n"); 1226 return PTR_ERR(cmd); 1227 } 1228 1229 /* 1230 * We use the batch length as size because the shadow object is as 1231 * large or larger and copy_batch() will write MI_NOPs to the extra 1232 * space. Parsing should be faster in some cases this way. 1233 */ 1234 batch_end = cmd + (batch_len / sizeof(*batch_end)); 1235 while (cmd < batch_end) { 1236 u32 length; 1237 1238 if (*cmd == MI_BATCH_BUFFER_END) 1239 break; 1240 1241 desc = find_cmd(engine, *cmd, desc, &default_desc); 1242 if (!desc) { 1243 DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n", 1244 *cmd); 1245 ret = -EINVAL; 1246 break; 1247 } 1248 1249 /* 1250 * If the batch buffer contains a chained batch, return an 1251 * error that tells the caller to abort and dispatch the 1252 * workload as a non-secure batch. 1253 */ 1254 if (desc->cmd.value == MI_BATCH_BUFFER_START) { 1255 ret = -EACCES; 1256 break; 1257 } 1258 1259 if (desc->flags & CMD_DESC_FIXED) 1260 length = desc->length.fixed; 1261 else 1262 length = ((*cmd & desc->length.mask) + LENGTH_BIAS); 1263 1264 if ((batch_end - cmd) < length) { 1265 DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n", 1266 *cmd, 1267 length, 1268 batch_end - cmd); 1269 ret = -EINVAL; 1270 break; 1271 } 1272 1273 if (!check_cmd(engine, desc, cmd, length, is_master, 1274 &oacontrol_set)) { 1275 ret = -EINVAL; 1276 break; 1277 } 1278 1279 cmd += length; 1280 } 1281 1282 if (oacontrol_set) { 1283 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n"); 1284 ret = -EINVAL; 1285 } 1286 1287 if (cmd >= batch_end) { 1288 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n"); 1289 ret = -EINVAL; 1290 } 1291 1292 if (ret == 0 && needs_clflush_after) 1293 drm_clflush_virt_range(shadow_batch_obj->mapping, batch_len); 1294 i915_gem_object_unpin_map(shadow_batch_obj); 1295 1296 return ret; 1297 } 1298 1299 /** 1300 * i915_cmd_parser_get_version() - get the cmd parser version number 1301 * @dev_priv: i915 device private 1302 * 1303 * The cmd parser maintains a simple increasing integer version number suitable 1304 * for passing to userspace clients to determine what operations are permitted. 1305 * 1306 * Return: the current version number of the cmd parser 1307 */ 1308 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv) 1309 { 1310 struct intel_engine_cs *engine; 1311 enum intel_engine_id id; 1312 bool active = false; 1313 1314 /* If the command parser is not enabled, report 0 - unsupported */ 1315 for_each_engine(engine, dev_priv, id) { 1316 if (intel_engine_needs_cmd_parser(engine)) { 1317 active = true; 1318 break; 1319 } 1320 } 1321 if (!active) 1322 return 0; 1323 1324 /* 1325 * Command parser version history 1326 * 1327 * 1. Initial version. Checks batches and reports violations, but leaves 1328 * hardware parsing enabled (so does not allow new use cases). 1329 * 2. Allow access to the MI_PREDICATE_SRC0 and 1330 * MI_PREDICATE_SRC1 registers. 1331 * 3. Allow access to the GPGPU_THREADS_DISPATCHED register. 1332 * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3. 1333 * 5. GPGPU dispatch compute indirect registers. 1334 * 6. TIMESTAMP register and Haswell CS GPR registers 1335 * 7. Allow MI_LOAD_REGISTER_REG between whitelisted registers. 1336 */ 1337 return 7; 1338 } 1339