1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <drm/drmP.h> 31 #include <drm/i915_drm.h> 32 #include "i915_drv.h" 33 #include <drm/drm_pciids.h> 34 #include "intel_drv.h" 35 36 #include <linux/module.h> 37 #include <drm/drm_crtc_helper.h> 38 39 static struct drm_driver driver; 40 41 #define GEN_DEFAULT_PIPEOFFSETS \ 42 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 43 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 44 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 45 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 46 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 47 48 #define GEN_CHV_PIPEOFFSETS \ 49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 50 CHV_PIPE_C_OFFSET }, \ 51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 52 CHV_TRANSCODER_C_OFFSET, }, \ 53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 54 CHV_PALETTE_C_OFFSET } 55 56 #define CURSOR_OFFSETS \ 57 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 58 59 #define IVB_CURSOR_OFFSETS \ 60 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 61 62 static const struct intel_device_info intel_i830_info = { 63 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, 64 .has_overlay = 1, .overlay_needs_physical = 1, 65 .ring_mask = RENDER_RING, 66 GEN_DEFAULT_PIPEOFFSETS, 67 CURSOR_OFFSETS, 68 }; 69 70 static const struct intel_device_info intel_845g_info = { 71 .gen = 2, .num_pipes = 1, 72 .has_overlay = 1, .overlay_needs_physical = 1, 73 .ring_mask = RENDER_RING, 74 GEN_DEFAULT_PIPEOFFSETS, 75 CURSOR_OFFSETS, 76 }; 77 78 static const struct intel_device_info intel_i85x_info = { 79 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, 80 .cursor_needs_physical = 1, 81 .has_overlay = 1, .overlay_needs_physical = 1, 82 .has_fbc = 1, 83 .ring_mask = RENDER_RING, 84 GEN_DEFAULT_PIPEOFFSETS, 85 CURSOR_OFFSETS, 86 }; 87 88 static const struct intel_device_info intel_i865g_info = { 89 .gen = 2, .num_pipes = 1, 90 .has_overlay = 1, .overlay_needs_physical = 1, 91 .ring_mask = RENDER_RING, 92 GEN_DEFAULT_PIPEOFFSETS, 93 CURSOR_OFFSETS, 94 }; 95 96 static const struct intel_device_info intel_i915g_info = { 97 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, 98 .has_overlay = 1, .overlay_needs_physical = 1, 99 .ring_mask = RENDER_RING, 100 GEN_DEFAULT_PIPEOFFSETS, 101 CURSOR_OFFSETS, 102 }; 103 static const struct intel_device_info intel_i915gm_info = { 104 .gen = 3, .is_mobile = 1, .num_pipes = 2, 105 .cursor_needs_physical = 1, 106 .has_overlay = 1, .overlay_needs_physical = 1, 107 .supports_tv = 1, 108 .has_fbc = 1, 109 .ring_mask = RENDER_RING, 110 GEN_DEFAULT_PIPEOFFSETS, 111 CURSOR_OFFSETS, 112 }; 113 static const struct intel_device_info intel_i945g_info = { 114 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, 115 .has_overlay = 1, .overlay_needs_physical = 1, 116 .ring_mask = RENDER_RING, 117 GEN_DEFAULT_PIPEOFFSETS, 118 CURSOR_OFFSETS, 119 }; 120 static const struct intel_device_info intel_i945gm_info = { 121 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, 122 .has_hotplug = 1, .cursor_needs_physical = 1, 123 .has_overlay = 1, .overlay_needs_physical = 1, 124 .supports_tv = 1, 125 .has_fbc = 1, 126 .ring_mask = RENDER_RING, 127 GEN_DEFAULT_PIPEOFFSETS, 128 CURSOR_OFFSETS, 129 }; 130 131 static const struct intel_device_info intel_i965g_info = { 132 .gen = 4, .is_broadwater = 1, .num_pipes = 2, 133 .has_hotplug = 1, 134 .has_overlay = 1, 135 .ring_mask = RENDER_RING, 136 GEN_DEFAULT_PIPEOFFSETS, 137 CURSOR_OFFSETS, 138 }; 139 140 static const struct intel_device_info intel_i965gm_info = { 141 .gen = 4, .is_crestline = 1, .num_pipes = 2, 142 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, 143 .has_overlay = 1, 144 .supports_tv = 1, 145 .ring_mask = RENDER_RING, 146 GEN_DEFAULT_PIPEOFFSETS, 147 CURSOR_OFFSETS, 148 }; 149 150 static const struct intel_device_info intel_g33_info = { 151 .gen = 3, .is_g33 = 1, .num_pipes = 2, 152 .need_gfx_hws = 1, .has_hotplug = 1, 153 .has_overlay = 1, 154 .ring_mask = RENDER_RING, 155 GEN_DEFAULT_PIPEOFFSETS, 156 CURSOR_OFFSETS, 157 }; 158 159 static const struct intel_device_info intel_g45_info = { 160 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, 161 .has_pipe_cxsr = 1, .has_hotplug = 1, 162 .ring_mask = RENDER_RING | BSD_RING, 163 GEN_DEFAULT_PIPEOFFSETS, 164 CURSOR_OFFSETS, 165 }; 166 167 static const struct intel_device_info intel_gm45_info = { 168 .gen = 4, .is_g4x = 1, .num_pipes = 2, 169 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, 170 .has_pipe_cxsr = 1, .has_hotplug = 1, 171 .supports_tv = 1, 172 .ring_mask = RENDER_RING | BSD_RING, 173 GEN_DEFAULT_PIPEOFFSETS, 174 CURSOR_OFFSETS, 175 }; 176 177 static const struct intel_device_info intel_pineview_info = { 178 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, 179 .need_gfx_hws = 1, .has_hotplug = 1, 180 .has_overlay = 1, 181 GEN_DEFAULT_PIPEOFFSETS, 182 CURSOR_OFFSETS, 183 }; 184 185 static const struct intel_device_info intel_ironlake_d_info = { 186 .gen = 5, .num_pipes = 2, 187 .need_gfx_hws = 1, .has_hotplug = 1, 188 .ring_mask = RENDER_RING | BSD_RING, 189 GEN_DEFAULT_PIPEOFFSETS, 190 CURSOR_OFFSETS, 191 }; 192 193 static const struct intel_device_info intel_ironlake_m_info = { 194 .gen = 5, .is_mobile = 1, .num_pipes = 2, 195 .need_gfx_hws = 1, .has_hotplug = 1, 196 .has_fbc = 1, 197 .ring_mask = RENDER_RING | BSD_RING, 198 GEN_DEFAULT_PIPEOFFSETS, 199 CURSOR_OFFSETS, 200 }; 201 202 static const struct intel_device_info intel_sandybridge_d_info = { 203 .gen = 6, .num_pipes = 2, 204 .need_gfx_hws = 1, .has_hotplug = 1, 205 .has_fbc = 1, 206 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 207 .has_llc = 1, 208 GEN_DEFAULT_PIPEOFFSETS, 209 CURSOR_OFFSETS, 210 }; 211 212 static const struct intel_device_info intel_sandybridge_m_info = { 213 .gen = 6, .is_mobile = 1, .num_pipes = 2, 214 .need_gfx_hws = 1, .has_hotplug = 1, 215 .has_fbc = 1, 216 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 217 .has_llc = 1, 218 GEN_DEFAULT_PIPEOFFSETS, 219 CURSOR_OFFSETS, 220 }; 221 222 #define GEN7_FEATURES \ 223 .gen = 7, .num_pipes = 3, \ 224 .need_gfx_hws = 1, .has_hotplug = 1, \ 225 .has_fbc = 1, \ 226 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 227 .has_llc = 1 228 229 static const struct intel_device_info intel_ivybridge_d_info = { 230 GEN7_FEATURES, 231 .is_ivybridge = 1, 232 GEN_DEFAULT_PIPEOFFSETS, 233 IVB_CURSOR_OFFSETS, 234 }; 235 236 static const struct intel_device_info intel_ivybridge_m_info = { 237 GEN7_FEATURES, 238 .is_ivybridge = 1, 239 .is_mobile = 1, 240 GEN_DEFAULT_PIPEOFFSETS, 241 IVB_CURSOR_OFFSETS, 242 }; 243 244 static const struct intel_device_info intel_ivybridge_q_info = { 245 GEN7_FEATURES, 246 .is_ivybridge = 1, 247 .num_pipes = 0, /* legal, last one wins */ 248 GEN_DEFAULT_PIPEOFFSETS, 249 IVB_CURSOR_OFFSETS, 250 }; 251 252 static const struct intel_device_info intel_valleyview_m_info = { 253 GEN7_FEATURES, 254 .is_mobile = 1, 255 .num_pipes = 2, 256 .is_valleyview = 1, 257 .display_mmio_offset = VLV_DISPLAY_BASE, 258 .has_fbc = 0, /* legal, last one wins */ 259 .has_llc = 0, /* legal, last one wins */ 260 GEN_DEFAULT_PIPEOFFSETS, 261 CURSOR_OFFSETS, 262 }; 263 264 static const struct intel_device_info intel_valleyview_d_info = { 265 GEN7_FEATURES, 266 .num_pipes = 2, 267 .is_valleyview = 1, 268 .display_mmio_offset = VLV_DISPLAY_BASE, 269 .has_fbc = 0, /* legal, last one wins */ 270 .has_llc = 0, /* legal, last one wins */ 271 GEN_DEFAULT_PIPEOFFSETS, 272 CURSOR_OFFSETS, 273 }; 274 275 static const struct intel_device_info intel_haswell_d_info = { 276 GEN7_FEATURES, 277 .is_haswell = 1, 278 .has_ddi = 1, 279 .has_fpga_dbg = 1, 280 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 281 GEN_DEFAULT_PIPEOFFSETS, 282 IVB_CURSOR_OFFSETS, 283 }; 284 285 static const struct intel_device_info intel_haswell_m_info = { 286 GEN7_FEATURES, 287 .is_haswell = 1, 288 .is_mobile = 1, 289 .has_ddi = 1, 290 .has_fpga_dbg = 1, 291 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 292 GEN_DEFAULT_PIPEOFFSETS, 293 IVB_CURSOR_OFFSETS, 294 }; 295 296 static const struct intel_device_info intel_broadwell_d_info = { 297 .gen = 8, .num_pipes = 3, 298 .need_gfx_hws = 1, .has_hotplug = 1, 299 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 300 .has_llc = 1, 301 .has_ddi = 1, 302 .has_fpga_dbg = 1, 303 .has_fbc = 1, 304 GEN_DEFAULT_PIPEOFFSETS, 305 IVB_CURSOR_OFFSETS, 306 }; 307 308 static const struct intel_device_info intel_broadwell_m_info = { 309 .gen = 8, .is_mobile = 1, .num_pipes = 3, 310 .need_gfx_hws = 1, .has_hotplug = 1, 311 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 312 .has_llc = 1, 313 .has_ddi = 1, 314 .has_fpga_dbg = 1, 315 .has_fbc = 1, 316 GEN_DEFAULT_PIPEOFFSETS, 317 IVB_CURSOR_OFFSETS, 318 }; 319 320 static const struct intel_device_info intel_broadwell_gt3d_info = { 321 .gen = 8, .num_pipes = 3, 322 .need_gfx_hws = 1, .has_hotplug = 1, 323 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 324 .has_llc = 1, 325 .has_ddi = 1, 326 .has_fpga_dbg = 1, 327 .has_fbc = 1, 328 GEN_DEFAULT_PIPEOFFSETS, 329 IVB_CURSOR_OFFSETS, 330 }; 331 332 static const struct intel_device_info intel_broadwell_gt3m_info = { 333 .gen = 8, .is_mobile = 1, .num_pipes = 3, 334 .need_gfx_hws = 1, .has_hotplug = 1, 335 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 336 .has_llc = 1, 337 .has_ddi = 1, 338 .has_fpga_dbg = 1, 339 .has_fbc = 1, 340 GEN_DEFAULT_PIPEOFFSETS, 341 IVB_CURSOR_OFFSETS, 342 }; 343 344 static const struct intel_device_info intel_cherryview_info = { 345 .is_preliminary = 1, 346 .gen = 8, .num_pipes = 3, 347 .need_gfx_hws = 1, .has_hotplug = 1, 348 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 349 .is_valleyview = 1, 350 .display_mmio_offset = VLV_DISPLAY_BASE, 351 GEN_CHV_PIPEOFFSETS, 352 CURSOR_OFFSETS, 353 }; 354 355 /* 356 * Make sure any device matches here are from most specific to most 357 * general. For example, since the Quanta match is based on the subsystem 358 * and subvendor IDs, we need it to come before the more general IVB 359 * PCI ID matches, otherwise we'll use the wrong info struct above. 360 */ 361 #define INTEL_PCI_IDS \ 362 INTEL_I830_IDS(&intel_i830_info), \ 363 INTEL_I845G_IDS(&intel_845g_info), \ 364 INTEL_I85X_IDS(&intel_i85x_info), \ 365 INTEL_I865G_IDS(&intel_i865g_info), \ 366 INTEL_I915G_IDS(&intel_i915g_info), \ 367 INTEL_I915GM_IDS(&intel_i915gm_info), \ 368 INTEL_I945G_IDS(&intel_i945g_info), \ 369 INTEL_I945GM_IDS(&intel_i945gm_info), \ 370 INTEL_I965G_IDS(&intel_i965g_info), \ 371 INTEL_G33_IDS(&intel_g33_info), \ 372 INTEL_I965GM_IDS(&intel_i965gm_info), \ 373 INTEL_GM45_IDS(&intel_gm45_info), \ 374 INTEL_G45_IDS(&intel_g45_info), \ 375 INTEL_PINEVIEW_IDS(&intel_pineview_info), \ 376 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ 377 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ 378 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ 379 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ 380 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ 381 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ 382 INTEL_HSW_D_IDS(&intel_haswell_d_info), \ 383 INTEL_HSW_M_IDS(&intel_haswell_m_info), \ 384 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ 385 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ 386 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ 387 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ 388 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ 389 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \ 390 INTEL_CHV_IDS(&intel_cherryview_info) 391 392 static const struct pci_device_id pciidlist[] = { /* aka */ 393 INTEL_PCI_IDS, 394 {0, 0} 395 }; 396 397 #define PCI_VENDOR_INTEL 0x8086 398 399 void intel_detect_pch(struct drm_device *dev) 400 { 401 struct drm_i915_private *dev_priv = dev->dev_private; 402 struct device *pch = NULL; 403 struct pci_devinfo *di; 404 405 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting 406 * (which really amounts to a PCH but no South Display). 407 */ 408 if (INTEL_INFO(dev)->num_pipes == 0) { 409 dev_priv->pch_type = PCH_NOP; 410 return; 411 } 412 413 /* XXX The ISA bridge probe causes some old Core2 machines to hang */ 414 if (INTEL_INFO(dev)->gen < 5) 415 return; 416 417 /* 418 * The reason to probe ISA bridge instead of Dev31:Fun0 is to 419 * make graphics device passthrough work easy for VMM, that only 420 * need to expose ISA bridge to let driver know the real hardware 421 * underneath. This is a requirement from virtualization team. 422 * 423 * In some virtualized environments (e.g. XEN), there is irrelevant 424 * ISA bridge in the system. To work reliably, we should scan trhough 425 * all the ISA bridge devices and check for the first match, instead 426 * of only checking the first one. 427 */ 428 di = NULL; 429 430 while ((pch = pci_iterate_class(&di, PCIC_BRIDGE, PCIS_BRIDGE_ISA))) { 431 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) { 432 unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK; 433 dev_priv->pch_id = id; 434 435 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { 436 dev_priv->pch_type = PCH_IBX; 437 DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); 438 WARN_ON(!IS_GEN5(dev)); 439 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { 440 dev_priv->pch_type = PCH_CPT; 441 DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 442 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 443 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { 444 /* PantherPoint is CPT compatible */ 445 dev_priv->pch_type = PCH_CPT; 446 DRM_DEBUG_KMS("Found PantherPoint PCH\n"); 447 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 448 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 449 dev_priv->pch_type = PCH_LPT; 450 DRM_DEBUG_KMS("Found LynxPoint PCH\n"); 451 WARN_ON(!IS_HASWELL(dev)); 452 WARN_ON(IS_ULT(dev)); 453 } else if (IS_BROADWELL(dev)) { 454 dev_priv->pch_type = PCH_LPT; 455 dev_priv->pch_id = 456 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; 457 DRM_DEBUG_KMS("This is Broadwell, assuming " 458 "LynxPoint LP PCH\n"); 459 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 460 dev_priv->pch_type = PCH_LPT; 461 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); 462 WARN_ON(!IS_HASWELL(dev)); 463 WARN_ON(!IS_ULT(dev)); 464 } else 465 continue; 466 467 break; 468 } 469 } 470 if (!pch) 471 DRM_DEBUG_KMS("No PCH found.\n"); 472 473 #if 0 474 pci_dev_put(pch); 475 #endif 476 } 477 478 bool i915_semaphore_is_enabled(struct drm_device *dev) 479 { 480 if (INTEL_INFO(dev)->gen < 6) 481 return false; 482 483 if (i915.semaphores >= 0) 484 return i915.semaphores; 485 486 /* Until we get further testing... */ 487 if (IS_GEN8(dev)) 488 return false; 489 490 #ifdef CONFIG_INTEL_IOMMU 491 /* Enable semaphores on SNB when IO remapping is off */ 492 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) 493 return false; 494 #endif 495 496 return true; 497 } 498 499 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv) 500 { 501 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 502 503 dev_priv->long_hpd_port_mask = 0; 504 dev_priv->short_hpd_port_mask = 0; 505 dev_priv->hpd_event_bits = 0; 506 507 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 508 509 cancel_work_sync(&dev_priv->dig_port_work); 510 cancel_work_sync(&dev_priv->hotplug_work); 511 cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work); 512 } 513 514 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 515 { 516 struct drm_device *dev = dev_priv->dev; 517 struct drm_encoder *encoder; 518 519 drm_modeset_lock_all(dev); 520 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 521 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 522 523 if (intel_encoder->suspend) 524 intel_encoder->suspend(intel_encoder); 525 } 526 drm_modeset_unlock_all(dev); 527 } 528 529 static int i915_drm_freeze(struct drm_device *dev) 530 { 531 struct drm_i915_private *dev_priv = dev->dev_private; 532 struct drm_crtc *crtc; 533 pci_power_t opregion_target_state; 534 535 /* ignore lid events during suspend */ 536 mutex_lock(&dev_priv->modeset_restore_lock); 537 dev_priv->modeset_restore = MODESET_SUSPENDED; 538 mutex_unlock(&dev_priv->modeset_restore_lock); 539 540 /* We do a lot of poking in a lot of registers, make sure they work 541 * properly. */ 542 intel_display_set_init_power(dev_priv, true); 543 544 drm_kms_helper_poll_disable(dev); 545 546 #if 0 547 pci_save_state(dev->pdev); 548 #endif 549 550 /* If KMS is active, we do the leavevt stuff here */ 551 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 552 int error; 553 554 error = i915_gem_suspend(dev); 555 if (error) { 556 dev_err(dev->pdev->dev, 557 "GEM idle failed, resume might fail\n"); 558 return error; 559 } 560 561 /* 562 * Disable CRTCs directly since we want to preserve sw state 563 * for _thaw. Also, power gate the CRTC power wells. 564 */ 565 drm_modeset_lock_all(dev); 566 for_each_crtc(dev, crtc) 567 intel_crtc_control(crtc, false); 568 drm_modeset_unlock_all(dev); 569 570 #if 0 571 intel_dp_mst_suspend(dev); 572 573 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 574 #endif 575 576 intel_runtime_pm_disable_interrupts(dev); 577 intel_hpd_cancel_work(dev_priv); 578 579 intel_suspend_encoders(dev_priv); 580 581 intel_suspend_gt_powersave(dev); 582 583 intel_modeset_suspend_hw(dev); 584 } 585 586 i915_gem_suspend_gtt_mappings(dev); 587 588 i915_save_state(dev); 589 590 opregion_target_state = PCI_D3cold; 591 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 592 if (acpi_target_system_state() < ACPI_STATE_S3) 593 opregion_target_state = PCI_D1; 594 #endif 595 intel_opregion_notify_adapter(dev, opregion_target_state); 596 597 #if 0 598 intel_uncore_forcewake_reset(dev, false); 599 #endif 600 intel_opregion_fini(dev); 601 602 #if 0 603 console_lock(); 604 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED); 605 console_unlock(); 606 #endif 607 608 dev_priv->suspend_count++; 609 610 intel_display_set_init_power(dev_priv, false); 611 612 return 0; 613 } 614 615 int i915_suspend(device_t kdev) 616 { 617 struct drm_device *dev = device_get_softc(kdev); 618 int error; 619 620 if (!dev || !dev->dev_private) { 621 DRM_ERROR("dev: %p\n", dev); 622 DRM_ERROR("DRM not initialized, aborting suspend.\n"); 623 return -ENODEV; 624 } 625 626 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 627 return 0; 628 629 error = i915_drm_freeze(dev); 630 if (error) 631 return error; 632 633 #if 0 634 if (state.event == PM_EVENT_SUSPEND) { 635 /* Shut down the device */ 636 pci_disable_device(dev->pdev); 637 pci_set_power_state(dev->pdev, PCI_D3hot); 638 } 639 #endif 640 641 error = bus_generic_suspend(kdev); 642 return (error); 643 } 644 645 #if 0 646 void intel_console_resume(struct work_struct *work) 647 { 648 struct drm_i915_private *dev_priv = 649 container_of(work, struct drm_i915_private, 650 console_resume_work); 651 struct drm_device *dev = dev_priv->dev; 652 653 console_lock(); 654 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); 655 console_unlock(); 656 } 657 658 static int i915_drm_thaw_early(struct drm_device *dev) 659 { 660 struct drm_i915_private *dev_priv = dev->dev_private; 661 662 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 663 hsw_disable_pc8(dev_priv); 664 665 intel_uncore_early_sanitize(dev, true); 666 intel_uncore_sanitize(dev); 667 intel_power_domains_init_hw(dev_priv); 668 669 return 0; 670 } 671 #endif 672 673 static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) 674 { 675 struct drm_i915_private *dev_priv = dev->dev_private; 676 677 if (drm_core_check_feature(dev, DRIVER_MODESET) && 678 restore_gtt_mappings) { 679 mutex_lock(&dev->struct_mutex); 680 i915_gem_restore_gtt_mappings(dev); 681 mutex_unlock(&dev->struct_mutex); 682 } 683 684 intel_power_domains_init_hw(dev_priv); 685 686 i915_restore_state(dev); 687 intel_opregion_setup(dev); 688 689 /* KMS EnterVT equivalent */ 690 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 691 intel_init_pch_refclk(dev); 692 drm_mode_config_reset(dev); 693 694 mutex_lock(&dev->struct_mutex); 695 if (i915_gem_init_hw(dev)) { 696 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); 697 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); 698 } 699 mutex_unlock(&dev->struct_mutex); 700 701 intel_runtime_pm_restore_interrupts(dev); 702 703 intel_modeset_init_hw(dev); 704 705 drm_modeset_lock_all(dev); 706 intel_modeset_setup_hw_state(dev, true); 707 drm_modeset_unlock_all(dev); 708 709 /* 710 * ... but also need to make sure that hotplug processing 711 * doesn't cause havoc. Like in the driver load code we don't 712 * bother with the tiny race here where we might loose hotplug 713 * notifications. 714 * */ 715 intel_hpd_init(dev); 716 /* Config may have changed between suspend and resume */ 717 drm_helper_hpd_irq_event(dev); 718 } 719 720 intel_opregion_init(dev); 721 722 /* 723 * The console lock can be pretty contented on resume due 724 * to all the printk activity. Try to keep it out of the hot 725 * path of resume if possible. 726 */ 727 #if 0 728 if (console_trylock()) { 729 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING); 730 console_unlock(); 731 } else { 732 schedule_work(&dev_priv->console_resume_work); 733 } 734 #endif 735 736 mutex_lock(&dev_priv->modeset_restore_lock); 737 dev_priv->modeset_restore = MODESET_DONE; 738 mutex_unlock(&dev_priv->modeset_restore_lock); 739 740 #if 0 741 intel_opregion_notify_adapter(dev, PCI_D0); 742 #endif 743 744 return 0; 745 } 746 747 #if 0 748 static int i915_drm_thaw(struct drm_device *dev) 749 { 750 if (drm_core_check_feature(dev, DRIVER_MODESET)) 751 i915_check_and_clear_faults(dev); 752 753 return __i915_drm_thaw(dev, true); 754 } 755 #endif 756 757 int i915_resume(struct drm_device *dev) 758 { 759 struct drm_i915_private *dev_priv = dev->dev_private; 760 int ret; 761 762 /* 763 * Platforms with opregion should have sane BIOS, older ones (gen3 and 764 * earlier) need to restore the GTT mappings since the BIOS might clear 765 * all our scratch PTEs. 766 */ 767 ret = __i915_drm_thaw(dev, !dev_priv->opregion.header); 768 if (ret) 769 return ret; 770 771 drm_kms_helper_poll_enable(dev); 772 return 0; 773 } 774 775 /* XXX Hack for the old *BSD drm code base 776 * The device id field is set at probe time */ 777 static drm_pci_id_list_t i915_attach_list[] = { 778 {0x8086, 0, 0, "Intel i915 GPU"}, 779 {0, 0, 0, NULL} 780 }; 781 782 struct intel_device_info * 783 i915_get_device_id(int device) 784 { 785 const struct pci_device_id *did; 786 787 for (did = &pciidlist[0]; did->device != 0; did++) { 788 if (did->device != device) 789 continue; 790 return (struct intel_device_info *)did->driver_data; 791 } 792 return (NULL); 793 } 794 795 extern devclass_t drm_devclass; 796 797 /** 798 * i915_reset - reset chip after a hang 799 * @dev: drm device to reset 800 * 801 * Reset the chip. Useful if a hang is detected. Returns zero on successful 802 * reset or otherwise an error code. 803 * 804 * Procedure is fairly simple: 805 * - reset the chip using the reset reg 806 * - re-init context state 807 * - re-init hardware status page 808 * - re-init ring buffer 809 * - re-init interrupt state 810 * - re-init display 811 */ 812 int i915_reset(struct drm_device *dev) 813 { 814 struct drm_i915_private *dev_priv = dev->dev_private; 815 bool simulated; 816 int ret; 817 818 if (!i915.reset) 819 return 0; 820 821 mutex_lock(&dev->struct_mutex); 822 823 i915_gem_reset(dev); 824 825 simulated = dev_priv->gpu_error.stop_rings != 0; 826 827 ret = intel_gpu_reset(dev); 828 829 /* Also reset the gpu hangman. */ 830 if (simulated) { 831 DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); 832 dev_priv->gpu_error.stop_rings = 0; 833 if (ret == -ENODEV) { 834 DRM_INFO("Reset not implemented, but ignoring " 835 "error for simulated gpu hangs\n"); 836 ret = 0; 837 } 838 } 839 840 if (ret) { 841 DRM_ERROR("Failed to reset chip: %i\n", ret); 842 mutex_unlock(&dev->struct_mutex); 843 return ret; 844 } 845 846 /* Ok, now get things going again... */ 847 848 /* 849 * Everything depends on having the GTT running, so we need to start 850 * there. Fortunately we don't need to do this unless we reset the 851 * chip at a PCI level. 852 * 853 * Next we need to restore the context, but we don't use those 854 * yet either... 855 * 856 * Ring buffer needs to be re-initialized in the KMS case, or if X 857 * was running at the time of the reset (i.e. we weren't VT 858 * switched away). 859 */ 860 if (drm_core_check_feature(dev, DRIVER_MODESET) || 861 !dev_priv->ums.mm_suspended) { 862 dev_priv->ums.mm_suspended = 0; 863 864 ret = i915_gem_init_hw(dev); 865 mutex_unlock(&dev->struct_mutex); 866 if (ret) { 867 DRM_ERROR("Failed hw init on reset %d\n", ret); 868 return ret; 869 } 870 871 /* 872 * FIXME: This races pretty badly against concurrent holders of 873 * ring interrupts. This is possible since we've started to drop 874 * dev->struct_mutex in select places when waiting for the gpu. 875 */ 876 877 /* 878 * rps/rc6 re-init is necessary to restore state lost after the 879 * reset and the re-install of gt irqs. Skip for ironlake per 880 * previous concerns that it doesn't respond well to some forms 881 * of re-init after reset. 882 */ 883 if (INTEL_INFO(dev)->gen > 5) 884 intel_reset_gt_powersave(dev); 885 886 intel_hpd_init(dev); 887 } else { 888 mutex_unlock(&dev->struct_mutex); 889 } 890 891 return 0; 892 } 893 894 static int i915_pci_probe(device_t kdev) 895 { 896 int device, i = 0; 897 898 if (pci_get_class(kdev) != PCIC_DISPLAY) 899 return ENXIO; 900 901 if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL) 902 return ENXIO; 903 904 device = pci_get_device(kdev); 905 906 for (i = 0; pciidlist[i].device != 0; i++) { 907 if (pciidlist[i].device == device) { 908 i915_attach_list[0].device = device; 909 return 0; 910 } 911 } 912 913 return ENXIO; 914 } 915 916 #if 0 917 static void 918 i915_pci_remove(struct pci_dev *pdev) 919 { 920 struct drm_device *dev = pci_get_drvdata(pdev); 921 922 drm_put_dev(dev); 923 } 924 925 static int i915_pm_suspend(struct device *dev) 926 { 927 struct pci_dev *pdev = to_pci_dev(dev); 928 struct drm_device *drm_dev = pci_get_drvdata(pdev); 929 930 if (!drm_dev || !drm_dev->dev_private) { 931 dev_err(dev, "DRM not initialized, aborting suspend.\n"); 932 return -ENODEV; 933 } 934 935 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 936 return 0; 937 938 return i915_drm_freeze(drm_dev); 939 } 940 941 static int i915_pm_suspend_late(struct device *dev) 942 { 943 struct pci_dev *pdev = to_pci_dev(dev); 944 struct drm_device *drm_dev = pci_get_drvdata(pdev); 945 struct drm_i915_private *dev_priv = drm_dev->dev_private; 946 947 /* 948 * We have a suspedn ordering issue with the snd-hda driver also 949 * requiring our device to be power up. Due to the lack of a 950 * parent/child relationship we currently solve this with an late 951 * suspend hook. 952 * 953 * FIXME: This should be solved with a special hdmi sink device or 954 * similar so that power domains can be employed. 955 */ 956 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 957 return 0; 958 959 if (IS_HASWELL(drm_dev) || IS_BROADWELL(drm_dev)) 960 hsw_enable_pc8(dev_priv); 961 962 pci_disable_device(pdev); 963 pci_set_power_state(pdev, PCI_D3hot); 964 965 return 0; 966 } 967 968 static int i915_pm_resume(struct device *dev) 969 { 970 struct pci_dev *pdev = to_pci_dev(dev); 971 struct drm_device *drm_dev = pci_get_drvdata(pdev); 972 973 return i915_resume(drm_dev); 974 } 975 976 static int i915_pm_freeze(struct device *dev) 977 { 978 struct pci_dev *pdev = to_pci_dev(dev); 979 struct drm_device *drm_dev = pci_get_drvdata(pdev); 980 struct drm_i915_private *dev_priv = drm_dev->dev_private; 981 982 if (!drm_dev || !drm_dev->dev_private) { 983 dev_err(dev, "DRM not initialized, aborting suspend.\n"); 984 return -ENODEV; 985 } 986 987 return i915_drm_freeze(drm_dev); 988 } 989 990 static int i915_pm_thaw(struct device *dev) 991 { 992 struct pci_dev *pdev = to_pci_dev(dev); 993 struct drm_device *drm_dev = pci_get_drvdata(pdev); 994 995 return i915_drm_thaw(drm_dev); 996 } 997 998 static int i915_pm_poweroff(struct device *dev) 999 { 1000 struct pci_dev *pdev = to_pci_dev(dev); 1001 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1002 1003 return i915_drm_freeze(drm_dev); 1004 } 1005 1006 static int hsw_runtime_suspend(struct drm_i915_private *dev_priv) 1007 { 1008 hsw_enable_pc8(dev_priv); 1009 1010 return 0; 1011 } 1012 1013 static int snb_runtime_resume(struct drm_i915_private *dev_priv) 1014 { 1015 struct drm_device *dev = dev_priv->dev; 1016 1017 intel_init_pch_refclk(dev); 1018 1019 return 0; 1020 } 1021 1022 static int hsw_runtime_resume(struct drm_i915_private *dev_priv) 1023 { 1024 hsw_disable_pc8(dev_priv); 1025 1026 return 0; 1027 } 1028 1029 /* 1030 * Save all Gunit registers that may be lost after a D3 and a subsequent 1031 * S0i[R123] transition. The list of registers needing a save/restore is 1032 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit 1033 * registers in the following way: 1034 * - Driver: saved/restored by the driver 1035 * - Punit : saved/restored by the Punit firmware 1036 * - No, w/o marking: no need to save/restore, since the register is R/O or 1037 * used internally by the HW in a way that doesn't depend 1038 * keeping the content across a suspend/resume. 1039 * - Debug : used for debugging 1040 * 1041 * We save/restore all registers marked with 'Driver', with the following 1042 * exceptions: 1043 * - Registers out of use, including also registers marked with 'Debug'. 1044 * These have no effect on the driver's operation, so we don't save/restore 1045 * them to reduce the overhead. 1046 * - Registers that are fully setup by an initialization function called from 1047 * the resume path. For example many clock gating and RPS/RC6 registers. 1048 * - Registers that provide the right functionality with their reset defaults. 1049 * 1050 * TODO: Except for registers that based on the above 3 criteria can be safely 1051 * ignored, we save/restore all others, practically treating the HW context as 1052 * a black-box for the driver. Further investigation is needed to reduce the 1053 * saved/restored registers even further, by following the same 3 criteria. 1054 */ 1055 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1056 { 1057 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1058 int i; 1059 1060 /* GAM 0x4000-0x4770 */ 1061 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); 1062 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); 1063 s->arb_mode = I915_READ(ARB_MODE); 1064 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); 1065 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); 1066 1067 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1068 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); 1069 1070 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); 1071 s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); 1072 1073 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); 1074 s->ecochk = I915_READ(GAM_ECOCHK); 1075 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); 1076 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); 1077 1078 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); 1079 1080 /* MBC 0x9024-0x91D0, 0x8500 */ 1081 s->g3dctl = I915_READ(VLV_G3DCTL); 1082 s->gsckgctl = I915_READ(VLV_GSCKGCTL); 1083 s->mbctl = I915_READ(GEN6_MBCTL); 1084 1085 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1086 s->ucgctl1 = I915_READ(GEN6_UCGCTL1); 1087 s->ucgctl3 = I915_READ(GEN6_UCGCTL3); 1088 s->rcgctl1 = I915_READ(GEN6_RCGCTL1); 1089 s->rcgctl2 = I915_READ(GEN6_RCGCTL2); 1090 s->rstctl = I915_READ(GEN6_RSTCTL); 1091 s->misccpctl = I915_READ(GEN7_MISCCPCTL); 1092 1093 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1094 s->gfxpause = I915_READ(GEN6_GFXPAUSE); 1095 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); 1096 s->rpdeuc = I915_READ(GEN6_RPDEUC); 1097 s->ecobus = I915_READ(ECOBUS); 1098 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); 1099 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); 1100 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); 1101 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); 1102 s->rcedata = I915_READ(VLV_RCEDATA); 1103 s->spare2gh = I915_READ(VLV_SPAREG2H); 1104 1105 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1106 s->gt_imr = I915_READ(GTIMR); 1107 s->gt_ier = I915_READ(GTIER); 1108 s->pm_imr = I915_READ(GEN6_PMIMR); 1109 s->pm_ier = I915_READ(GEN6_PMIER); 1110 1111 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1112 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); 1113 1114 /* GT SA CZ domain, 0x100000-0x138124 */ 1115 s->tilectl = I915_READ(TILECTL); 1116 s->gt_fifoctl = I915_READ(GTFIFOCTL); 1117 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); 1118 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1119 s->pmwgicz = I915_READ(VLV_PMWGICZ); 1120 1121 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1122 s->gu_ctl0 = I915_READ(VLV_GU_CTL0); 1123 s->gu_ctl1 = I915_READ(VLV_GU_CTL1); 1124 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); 1125 1126 /* 1127 * Not saving any of: 1128 * DFT, 0x9800-0x9EC0 1129 * SARB, 0xB000-0xB1FC 1130 * GAC, 0x5208-0x524C, 0x14000-0x14C000 1131 * PCI CFG 1132 */ 1133 } 1134 1135 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1136 { 1137 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1138 u32 val; 1139 int i; 1140 1141 /* GAM 0x4000-0x4770 */ 1142 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); 1143 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); 1144 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); 1145 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); 1146 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); 1147 1148 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1149 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); 1150 1151 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); 1152 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count); 1153 1154 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); 1155 I915_WRITE(GAM_ECOCHK, s->ecochk); 1156 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); 1157 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); 1158 1159 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); 1160 1161 /* MBC 0x9024-0x91D0, 0x8500 */ 1162 I915_WRITE(VLV_G3DCTL, s->g3dctl); 1163 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); 1164 I915_WRITE(GEN6_MBCTL, s->mbctl); 1165 1166 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1167 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); 1168 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); 1169 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); 1170 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); 1171 I915_WRITE(GEN6_RSTCTL, s->rstctl); 1172 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); 1173 1174 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1175 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); 1176 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); 1177 I915_WRITE(GEN6_RPDEUC, s->rpdeuc); 1178 I915_WRITE(ECOBUS, s->ecobus); 1179 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); 1180 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); 1181 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); 1182 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); 1183 I915_WRITE(VLV_RCEDATA, s->rcedata); 1184 I915_WRITE(VLV_SPAREG2H, s->spare2gh); 1185 1186 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1187 I915_WRITE(GTIMR, s->gt_imr); 1188 I915_WRITE(GTIER, s->gt_ier); 1189 I915_WRITE(GEN6_PMIMR, s->pm_imr); 1190 I915_WRITE(GEN6_PMIER, s->pm_ier); 1191 1192 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1193 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); 1194 1195 /* GT SA CZ domain, 0x100000-0x138124 */ 1196 I915_WRITE(TILECTL, s->tilectl); 1197 I915_WRITE(GTFIFOCTL, s->gt_fifoctl); 1198 /* 1199 * Preserve the GT allow wake and GFX force clock bit, they are not 1200 * be restored, as they are used to control the s0ix suspend/resume 1201 * sequence by the caller. 1202 */ 1203 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1204 val &= VLV_GTLC_ALLOWWAKEREQ; 1205 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; 1206 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1207 1208 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1209 val &= VLV_GFX_CLK_FORCE_ON_BIT; 1210 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; 1211 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1212 1213 I915_WRITE(VLV_PMWGICZ, s->pmwgicz); 1214 1215 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1216 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); 1217 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); 1218 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); 1219 } 1220 #endif 1221 1222 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) 1223 { 1224 u32 val; 1225 int err; 1226 1227 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1228 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on); 1229 1230 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) 1231 /* Wait for a previous force-off to settle */ 1232 if (force_on) { 1233 err = wait_for(!COND, 20); 1234 if (err) { 1235 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n", 1236 I915_READ(VLV_GTLC_SURVIVABILITY_REG)); 1237 return err; 1238 } 1239 } 1240 1241 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1242 val &= ~VLV_GFX_CLK_FORCE_ON_BIT; 1243 if (force_on) 1244 val |= VLV_GFX_CLK_FORCE_ON_BIT; 1245 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1246 1247 if (!force_on) 1248 return 0; 1249 1250 err = wait_for(COND, 20); 1251 if (err) 1252 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", 1253 I915_READ(VLV_GTLC_SURVIVABILITY_REG)); 1254 1255 return err; 1256 #undef COND 1257 } 1258 1259 #if 0 1260 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) 1261 { 1262 u32 val; 1263 int err = 0; 1264 1265 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1266 val &= ~VLV_GTLC_ALLOWWAKEREQ; 1267 if (allow) 1268 val |= VLV_GTLC_ALLOWWAKEREQ; 1269 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1270 POSTING_READ(VLV_GTLC_WAKE_CTRL); 1271 1272 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ 1273 allow) 1274 err = wait_for(COND, 1); 1275 if (err) 1276 DRM_ERROR("timeout disabling GT waking\n"); 1277 return err; 1278 #undef COND 1279 } 1280 1281 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, 1282 bool wait_for_on) 1283 { 1284 u32 mask; 1285 u32 val; 1286 int err; 1287 1288 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; 1289 val = wait_for_on ? mask : 0; 1290 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) 1291 if (COND) 1292 return 0; 1293 1294 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", 1295 wait_for_on ? "on" : "off", 1296 I915_READ(VLV_GTLC_PW_STATUS)); 1297 1298 /* 1299 * RC6 transitioning can be delayed up to 2 msec (see 1300 * valleyview_enable_rps), use 3 msec for safety. 1301 */ 1302 err = wait_for(COND, 3); 1303 if (err) 1304 DRM_ERROR("timeout waiting for GT wells to go %s\n", 1305 wait_for_on ? "on" : "off"); 1306 1307 return err; 1308 #undef COND 1309 } 1310 1311 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) 1312 { 1313 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) 1314 return; 1315 1316 DRM_ERROR("GT register access while GT waking disabled\n"); 1317 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); 1318 } 1319 1320 static int vlv_runtime_suspend(struct drm_i915_private *dev_priv) 1321 { 1322 u32 mask; 1323 int err; 1324 1325 /* 1326 * Bspec defines the following GT well on flags as debug only, so 1327 * don't treat them as hard failures. 1328 */ 1329 (void)vlv_wait_for_gt_wells(dev_priv, false); 1330 1331 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; 1332 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); 1333 1334 vlv_check_no_gt_access(dev_priv); 1335 1336 err = vlv_force_gfx_clock(dev_priv, true); 1337 if (err) 1338 goto err1; 1339 1340 err = vlv_allow_gt_wake(dev_priv, false); 1341 if (err) 1342 goto err2; 1343 vlv_save_gunit_s0ix_state(dev_priv); 1344 1345 err = vlv_force_gfx_clock(dev_priv, false); 1346 if (err) 1347 goto err2; 1348 1349 return 0; 1350 1351 err2: 1352 /* For safety always re-enable waking and disable gfx clock forcing */ 1353 vlv_allow_gt_wake(dev_priv, true); 1354 err1: 1355 vlv_force_gfx_clock(dev_priv, false); 1356 1357 return err; 1358 } 1359 1360 static int vlv_runtime_resume(struct drm_i915_private *dev_priv) 1361 { 1362 struct drm_device *dev = dev_priv->dev; 1363 int err; 1364 int ret; 1365 1366 /* 1367 * If any of the steps fail just try to continue, that's the best we 1368 * can do at this point. Return the first error code (which will also 1369 * leave RPM permanently disabled). 1370 */ 1371 ret = vlv_force_gfx_clock(dev_priv, true); 1372 1373 vlv_restore_gunit_s0ix_state(dev_priv); 1374 1375 err = vlv_allow_gt_wake(dev_priv, true); 1376 if (!ret) 1377 ret = err; 1378 1379 err = vlv_force_gfx_clock(dev_priv, false); 1380 if (!ret) 1381 ret = err; 1382 1383 vlv_check_no_gt_access(dev_priv); 1384 1385 intel_init_clock_gating(dev); 1386 i915_gem_restore_fences(dev); 1387 1388 return ret; 1389 } 1390 1391 static int intel_runtime_suspend(struct device *device) 1392 { 1393 struct pci_dev *pdev = to_pci_dev(device); 1394 struct drm_device *dev = pci_get_drvdata(pdev); 1395 struct drm_i915_private *dev_priv = dev->dev_private; 1396 int ret; 1397 1398 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) 1399 return -ENODEV; 1400 1401 WARN_ON(!HAS_RUNTIME_PM(dev)); 1402 assert_force_wake_inactive(dev_priv); 1403 1404 DRM_DEBUG_KMS("Suspending device\n"); 1405 1406 /* 1407 * We could deadlock here in case another thread holding struct_mutex 1408 * calls RPM suspend concurrently, since the RPM suspend will wait 1409 * first for this RPM suspend to finish. In this case the concurrent 1410 * RPM resume will be followed by its RPM suspend counterpart. Still 1411 * for consistency return -EAGAIN, which will reschedule this suspend. 1412 */ 1413 if (!mutex_trylock(&dev->struct_mutex)) { 1414 DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); 1415 /* 1416 * Bump the expiration timestamp, otherwise the suspend won't 1417 * be rescheduled. 1418 */ 1419 pm_runtime_mark_last_busy(device); 1420 1421 return -EAGAIN; 1422 } 1423 /* 1424 * We are safe here against re-faults, since the fault handler takes 1425 * an RPM reference. 1426 */ 1427 i915_gem_release_all_mmaps(dev_priv); 1428 mutex_unlock(&dev->struct_mutex); 1429 1430 /* 1431 * rps.work can't be rearmed here, since we get here only after making 1432 * sure the GPU is idle and the RPS freq is set to the minimum. See 1433 * intel_mark_idle(). 1434 */ 1435 cancel_work_sync(&dev_priv->rps.work); 1436 intel_runtime_pm_disable_interrupts(dev); 1437 1438 if (IS_GEN6(dev)) { 1439 ret = 0; 1440 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 1441 ret = hsw_runtime_suspend(dev_priv); 1442 } else if (IS_VALLEYVIEW(dev)) { 1443 ret = vlv_runtime_suspend(dev_priv); 1444 } else { 1445 ret = -ENODEV; 1446 WARN_ON(1); 1447 } 1448 1449 if (ret) { 1450 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); 1451 intel_runtime_pm_restore_interrupts(dev); 1452 1453 return ret; 1454 } 1455 1456 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); 1457 dev_priv->pm.suspended = true; 1458 1459 /* 1460 * current versions of firmware which depend on this opregion 1461 * notification have repurposed the D1 definition to mean 1462 * "runtime suspended" vs. what you would normally expect (D3) 1463 * to distinguish it from notifications that might be sent 1464 * via the suspend path. 1465 */ 1466 intel_opregion_notify_adapter(dev, PCI_D1); 1467 1468 DRM_DEBUG_KMS("Device suspended\n"); 1469 return 0; 1470 } 1471 1472 static int intel_runtime_resume(struct device *device) 1473 { 1474 struct pci_dev *pdev = to_pci_dev(device); 1475 struct drm_device *dev = pci_get_drvdata(pdev); 1476 struct drm_i915_private *dev_priv = dev->dev_private; 1477 int ret; 1478 1479 WARN_ON(!HAS_RUNTIME_PM(dev)); 1480 1481 DRM_DEBUG_KMS("Resuming device\n"); 1482 1483 intel_opregion_notify_adapter(dev, PCI_D0); 1484 dev_priv->pm.suspended = false; 1485 1486 if (IS_GEN6(dev)) { 1487 ret = snb_runtime_resume(dev_priv); 1488 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 1489 ret = hsw_runtime_resume(dev_priv); 1490 } else if (IS_VALLEYVIEW(dev)) { 1491 ret = vlv_runtime_resume(dev_priv); 1492 } else { 1493 WARN_ON(1); 1494 ret = -ENODEV; 1495 } 1496 1497 /* 1498 * No point of rolling back things in case of an error, as the best 1499 * we can do is to hope that things will still work (and disable RPM). 1500 */ 1501 i915_gem_init_swizzling(dev); 1502 gen6_update_ring_freq(dev); 1503 1504 intel_runtime_pm_restore_interrupts(dev); 1505 intel_reset_gt_powersave(dev); 1506 1507 if (ret) 1508 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); 1509 else 1510 DRM_DEBUG_KMS("Device resumed\n"); 1511 1512 return ret; 1513 } 1514 1515 static const struct dev_pm_ops i915_pm_ops = { 1516 .suspend = i915_pm_suspend, 1517 .resume = i915_pm_resume, 1518 .freeze = i915_pm_freeze, 1519 .thaw = i915_pm_thaw, 1520 .poweroff = i915_pm_poweroff, 1521 .restore = i915_pm_resume, 1522 .runtime_suspend = intel_runtime_suspend, 1523 .runtime_resume = intel_runtime_resume, 1524 }; 1525 1526 static const struct vm_operations_struct i915_gem_vm_ops = { 1527 .fault = i915_gem_fault, 1528 .open = drm_gem_vm_open, 1529 .close = drm_gem_vm_close, 1530 }; 1531 1532 static const struct file_operations i915_driver_fops = { 1533 .owner = THIS_MODULE, 1534 .open = drm_open, 1535 .release = drm_release, 1536 .unlocked_ioctl = drm_ioctl, 1537 .mmap = drm_gem_mmap, 1538 .poll = drm_poll, 1539 .read = drm_read, 1540 #ifdef CONFIG_COMPAT 1541 .compat_ioctl = i915_compat_ioctl, 1542 #endif 1543 .llseek = noop_llseek, 1544 }; 1545 #endif 1546 1547 static struct cdev_pager_ops i915_gem_vm_ops = { 1548 .cdev_pg_fault = i915_gem_fault, 1549 .cdev_pg_ctor = i915_gem_pager_ctor, 1550 .cdev_pg_dtor = i915_gem_pager_dtor 1551 }; 1552 1553 static struct drm_driver driver = { 1554 /* Don't use MTRRs here; the Xserver or userspace app should 1555 * deal with them for Intel hardware. 1556 */ 1557 .driver_features = 1558 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | 1559 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, 1560 1561 .load = i915_driver_load, 1562 .unload = i915_driver_unload, 1563 .open = i915_driver_open, 1564 .lastclose = i915_driver_lastclose, 1565 .preclose = i915_driver_preclose, 1566 .postclose = i915_driver_postclose, 1567 1568 .device_is_agp = i915_driver_device_is_agp, 1569 .gem_free_object = i915_gem_free_object, 1570 .gem_pager_ops = &i915_gem_vm_ops, 1571 .dumb_create = i915_gem_dumb_create, 1572 .dumb_map_offset = i915_gem_mmap_gtt, 1573 .dumb_destroy = drm_gem_dumb_destroy, 1574 .ioctls = i915_ioctls, 1575 1576 .name = DRIVER_NAME, 1577 .desc = DRIVER_DESC, 1578 .date = DRIVER_DATE, 1579 .major = DRIVER_MAJOR, 1580 .minor = DRIVER_MINOR, 1581 .patchlevel = DRIVER_PATCHLEVEL, 1582 }; 1583 1584 static int __init i915_init(void); 1585 1586 static int 1587 i915_attach(device_t kdev) 1588 { 1589 struct drm_device *dev = device_get_softc(kdev); 1590 1591 i915_init(); 1592 1593 dev->driver = &driver; 1594 return (drm_attach(kdev, i915_attach_list)); 1595 } 1596 1597 static device_method_t i915_methods[] = { 1598 /* Device interface */ 1599 DEVMETHOD(device_probe, i915_pci_probe), 1600 DEVMETHOD(device_attach, i915_attach), 1601 DEVMETHOD(device_suspend, i915_suspend), 1602 DEVMETHOD(device_resume, i915_resume), 1603 DEVMETHOD(device_detach, drm_release), 1604 DEVMETHOD_END 1605 }; 1606 1607 static driver_t i915_driver = { 1608 "drm", 1609 i915_methods, 1610 sizeof(struct drm_device) 1611 }; 1612 1613 static int __init i915_init(void) 1614 { 1615 driver.num_ioctls = i915_max_ioctl; 1616 1617 /* 1618 * If CONFIG_DRM_I915_KMS is set, default to KMS unless 1619 * explicitly disabled with the module pararmeter. 1620 * 1621 * Otherwise, just follow the parameter (defaulting to off). 1622 * 1623 * Allow optional vga_text_mode_force boot option to override 1624 * the default behavior. 1625 */ 1626 #if defined(CONFIG_DRM_I915_KMS) 1627 if (i915.modeset != 0) 1628 driver.driver_features |= DRIVER_MODESET; 1629 #endif 1630 if (i915.modeset == 1) 1631 driver.driver_features |= DRIVER_MODESET; 1632 1633 #ifdef CONFIG_VGA_CONSOLE 1634 if (vgacon_text_force() && i915.modeset == -1) 1635 driver.driver_features &= ~DRIVER_MODESET; 1636 #endif 1637 1638 if (!(driver.driver_features & DRIVER_MODESET)) { 1639 driver.get_vblank_timestamp = NULL; 1640 #ifndef CONFIG_DRM_I915_UMS 1641 /* Silently fail loading to not upset userspace. */ 1642 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); 1643 return 0; 1644 #endif 1645 } 1646 1647 #if 0 1648 return drm_pci_init(&driver, &i915_pci_driver); 1649 #else 1650 return 1; 1651 #endif 1652 } 1653 1654 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, NULL, NULL, 1655 SI_ORDER_ANY); 1656 MODULE_DEPEND(i915kms, drm, 1, 1, 1); 1657 MODULE_DEPEND(i915kms, agp, 1, 1, 1); 1658 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1); 1659 MODULE_DEPEND(i915kms, iic, 1, 1, 1); 1660 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1); 1661