1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <drm/drmP.h> 31 #include <drm/i915_drm.h> 32 #include "i915_drv.h" 33 #include <drm/drm_pciids.h> 34 #include "intel_drv.h" 35 36 #include <linux/module.h> 37 #include <drm/drm_crtc_helper.h> 38 39 static struct drm_driver driver; 40 41 #define GEN_DEFAULT_PIPEOFFSETS \ 42 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 43 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 44 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 45 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 46 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 47 48 #define GEN_CHV_PIPEOFFSETS \ 49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 50 CHV_PIPE_C_OFFSET }, \ 51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 52 CHV_TRANSCODER_C_OFFSET, }, \ 53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 54 CHV_PALETTE_C_OFFSET } 55 56 #define CURSOR_OFFSETS \ 57 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 58 59 #define IVB_CURSOR_OFFSETS \ 60 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 61 62 static const struct intel_device_info intel_i830_info = { 63 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, 64 .has_overlay = 1, .overlay_needs_physical = 1, 65 .ring_mask = RENDER_RING, 66 GEN_DEFAULT_PIPEOFFSETS, 67 CURSOR_OFFSETS, 68 }; 69 70 static const struct intel_device_info intel_845g_info = { 71 .gen = 2, .num_pipes = 1, 72 .has_overlay = 1, .overlay_needs_physical = 1, 73 .ring_mask = RENDER_RING, 74 GEN_DEFAULT_PIPEOFFSETS, 75 CURSOR_OFFSETS, 76 }; 77 78 static const struct intel_device_info intel_i85x_info = { 79 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, 80 .cursor_needs_physical = 1, 81 .has_overlay = 1, .overlay_needs_physical = 1, 82 .has_fbc = 1, 83 .ring_mask = RENDER_RING, 84 GEN_DEFAULT_PIPEOFFSETS, 85 CURSOR_OFFSETS, 86 }; 87 88 static const struct intel_device_info intel_i865g_info = { 89 .gen = 2, .num_pipes = 1, 90 .has_overlay = 1, .overlay_needs_physical = 1, 91 .ring_mask = RENDER_RING, 92 GEN_DEFAULT_PIPEOFFSETS, 93 CURSOR_OFFSETS, 94 }; 95 96 static const struct intel_device_info intel_i915g_info = { 97 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, 98 .has_overlay = 1, .overlay_needs_physical = 1, 99 .ring_mask = RENDER_RING, 100 GEN_DEFAULT_PIPEOFFSETS, 101 CURSOR_OFFSETS, 102 }; 103 static const struct intel_device_info intel_i915gm_info = { 104 .gen = 3, .is_mobile = 1, .num_pipes = 2, 105 .cursor_needs_physical = 1, 106 .has_overlay = 1, .overlay_needs_physical = 1, 107 .supports_tv = 1, 108 .has_fbc = 1, 109 .ring_mask = RENDER_RING, 110 GEN_DEFAULT_PIPEOFFSETS, 111 CURSOR_OFFSETS, 112 }; 113 static const struct intel_device_info intel_i945g_info = { 114 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, 115 .has_overlay = 1, .overlay_needs_physical = 1, 116 .ring_mask = RENDER_RING, 117 GEN_DEFAULT_PIPEOFFSETS, 118 CURSOR_OFFSETS, 119 }; 120 static const struct intel_device_info intel_i945gm_info = { 121 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, 122 .has_hotplug = 1, .cursor_needs_physical = 1, 123 .has_overlay = 1, .overlay_needs_physical = 1, 124 .supports_tv = 1, 125 .has_fbc = 1, 126 .ring_mask = RENDER_RING, 127 GEN_DEFAULT_PIPEOFFSETS, 128 CURSOR_OFFSETS, 129 }; 130 131 static const struct intel_device_info intel_i965g_info = { 132 .gen = 4, .is_broadwater = 1, .num_pipes = 2, 133 .has_hotplug = 1, 134 .has_overlay = 1, 135 .ring_mask = RENDER_RING, 136 GEN_DEFAULT_PIPEOFFSETS, 137 CURSOR_OFFSETS, 138 }; 139 140 static const struct intel_device_info intel_i965gm_info = { 141 .gen = 4, .is_crestline = 1, .num_pipes = 2, 142 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, 143 .has_overlay = 1, 144 .supports_tv = 1, 145 .ring_mask = RENDER_RING, 146 GEN_DEFAULT_PIPEOFFSETS, 147 CURSOR_OFFSETS, 148 }; 149 150 static const struct intel_device_info intel_g33_info = { 151 .gen = 3, .is_g33 = 1, .num_pipes = 2, 152 .need_gfx_hws = 1, .has_hotplug = 1, 153 .has_overlay = 1, 154 .ring_mask = RENDER_RING, 155 GEN_DEFAULT_PIPEOFFSETS, 156 CURSOR_OFFSETS, 157 }; 158 159 static const struct intel_device_info intel_g45_info = { 160 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, 161 .has_pipe_cxsr = 1, .has_hotplug = 1, 162 .ring_mask = RENDER_RING | BSD_RING, 163 GEN_DEFAULT_PIPEOFFSETS, 164 CURSOR_OFFSETS, 165 }; 166 167 static const struct intel_device_info intel_gm45_info = { 168 .gen = 4, .is_g4x = 1, .num_pipes = 2, 169 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, 170 .has_pipe_cxsr = 1, .has_hotplug = 1, 171 .supports_tv = 1, 172 .ring_mask = RENDER_RING | BSD_RING, 173 GEN_DEFAULT_PIPEOFFSETS, 174 CURSOR_OFFSETS, 175 }; 176 177 static const struct intel_device_info intel_pineview_info = { 178 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, 179 .need_gfx_hws = 1, .has_hotplug = 1, 180 .has_overlay = 1, 181 GEN_DEFAULT_PIPEOFFSETS, 182 CURSOR_OFFSETS, 183 }; 184 185 static const struct intel_device_info intel_ironlake_d_info = { 186 .gen = 5, .num_pipes = 2, 187 .need_gfx_hws = 1, .has_hotplug = 1, 188 .ring_mask = RENDER_RING | BSD_RING, 189 GEN_DEFAULT_PIPEOFFSETS, 190 CURSOR_OFFSETS, 191 }; 192 193 static const struct intel_device_info intel_ironlake_m_info = { 194 .gen = 5, .is_mobile = 1, .num_pipes = 2, 195 .need_gfx_hws = 1, .has_hotplug = 1, 196 .has_fbc = 1, 197 .ring_mask = RENDER_RING | BSD_RING, 198 GEN_DEFAULT_PIPEOFFSETS, 199 CURSOR_OFFSETS, 200 }; 201 202 static const struct intel_device_info intel_sandybridge_d_info = { 203 .gen = 6, .num_pipes = 2, 204 .need_gfx_hws = 1, .has_hotplug = 1, 205 .has_fbc = 1, 206 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 207 .has_llc = 1, 208 GEN_DEFAULT_PIPEOFFSETS, 209 CURSOR_OFFSETS, 210 }; 211 212 static const struct intel_device_info intel_sandybridge_m_info = { 213 .gen = 6, .is_mobile = 1, .num_pipes = 2, 214 .need_gfx_hws = 1, .has_hotplug = 1, 215 .has_fbc = 1, 216 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 217 .has_llc = 1, 218 GEN_DEFAULT_PIPEOFFSETS, 219 CURSOR_OFFSETS, 220 }; 221 222 #define GEN7_FEATURES \ 223 .gen = 7, .num_pipes = 3, \ 224 .need_gfx_hws = 1, .has_hotplug = 1, \ 225 .has_fbc = 1, \ 226 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 227 .has_llc = 1, \ 228 GEN_DEFAULT_PIPEOFFSETS, \ 229 IVB_CURSOR_OFFSETS 230 231 static const struct intel_device_info intel_ivybridge_d_info = { 232 GEN7_FEATURES, 233 .is_ivybridge = 1, 234 }; 235 236 static const struct intel_device_info intel_ivybridge_m_info = { 237 GEN7_FEATURES, 238 .is_ivybridge = 1, 239 .is_mobile = 1, 240 }; 241 242 static const struct intel_device_info intel_ivybridge_q_info = { 243 GEN7_FEATURES, 244 .is_ivybridge = 1, 245 .num_pipes = 0, /* legal, last one wins */ 246 }; 247 248 #define VLV_FEATURES \ 249 .gen = 7, .num_pipes = 2, \ 250 .need_gfx_hws = 1, .has_hotplug = 1, \ 251 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 252 .display_mmio_offset = VLV_DISPLAY_BASE, \ 253 GEN_DEFAULT_PIPEOFFSETS, \ 254 CURSOR_OFFSETS 255 256 static const struct intel_device_info intel_valleyview_m_info = { 257 VLV_FEATURES, 258 .is_valleyview = 1, 259 .is_mobile = 1, 260 }; 261 262 static const struct intel_device_info intel_valleyview_d_info = { 263 VLV_FEATURES, 264 .is_valleyview = 1, 265 }; 266 267 #define HSW_FEATURES \ 268 GEN7_FEATURES, \ 269 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 270 .has_ddi = 1, \ 271 .has_fpga_dbg = 1 272 273 static const struct intel_device_info intel_haswell_d_info = { 274 HSW_FEATURES, 275 .is_haswell = 1, 276 }; 277 278 static const struct intel_device_info intel_haswell_m_info = { 279 HSW_FEATURES, 280 .is_haswell = 1, 281 .is_mobile = 1, 282 }; 283 284 static const struct intel_device_info intel_broadwell_d_info = { 285 HSW_FEATURES, 286 .gen = 8, 287 }; 288 289 static const struct intel_device_info intel_broadwell_m_info = { 290 HSW_FEATURES, 291 .gen = 8, .is_mobile = 1, 292 }; 293 294 static const struct intel_device_info intel_broadwell_gt3d_info = { 295 HSW_FEATURES, 296 .gen = 8, 297 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 298 }; 299 300 static const struct intel_device_info intel_broadwell_gt3m_info = { 301 HSW_FEATURES, 302 .gen = 8, .is_mobile = 1, 303 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 304 }; 305 306 static const struct intel_device_info intel_cherryview_info = { 307 .gen = 8, .num_pipes = 3, 308 .need_gfx_hws = 1, .has_hotplug = 1, 309 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 310 .is_cherryview = 1, 311 .display_mmio_offset = VLV_DISPLAY_BASE, 312 GEN_CHV_PIPEOFFSETS, 313 CURSOR_OFFSETS, 314 }; 315 316 static const struct intel_device_info intel_skylake_info = { 317 HSW_FEATURES, 318 .is_skylake = 1, 319 .gen = 9, 320 }; 321 322 static const struct intel_device_info intel_skylake_gt3_info = { 323 HSW_FEATURES, 324 .is_skylake = 1, 325 .gen = 9, 326 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 327 }; 328 329 static const struct intel_device_info intel_broxton_info = { 330 .is_preliminary = 1, 331 .is_broxton = 1, 332 .gen = 9, 333 .need_gfx_hws = 1, .has_hotplug = 1, 334 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 335 .num_pipes = 3, 336 .has_ddi = 1, 337 .has_fpga_dbg = 1, 338 .has_fbc = 1, 339 GEN_DEFAULT_PIPEOFFSETS, 340 IVB_CURSOR_OFFSETS, 341 }; 342 343 static const struct intel_device_info intel_kabylake_info = { 344 HSW_FEATURES, 345 .is_preliminary = 1, 346 .is_kabylake = 1, 347 .gen = 9, 348 }; 349 350 static const struct intel_device_info intel_kabylake_gt3_info = { 351 HSW_FEATURES, 352 .is_preliminary = 1, 353 .is_kabylake = 1, 354 .gen = 9, 355 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 356 }; 357 358 /* 359 * Make sure any device matches here are from most specific to most 360 * general. For example, since the Quanta match is based on the subsystem 361 * and subvendor IDs, we need it to come before the more general IVB 362 * PCI ID matches, otherwise we'll use the wrong info struct above. 363 */ 364 365 static const struct pci_device_id pciidlist[] = { 366 INTEL_I830_IDS(&intel_i830_info), 367 INTEL_I845G_IDS(&intel_845g_info), 368 INTEL_I85X_IDS(&intel_i85x_info), 369 INTEL_I865G_IDS(&intel_i865g_info), 370 INTEL_I915G_IDS(&intel_i915g_info), 371 INTEL_I915GM_IDS(&intel_i915gm_info), 372 INTEL_I945G_IDS(&intel_i945g_info), 373 INTEL_I945GM_IDS(&intel_i945gm_info), 374 INTEL_I965G_IDS(&intel_i965g_info), 375 INTEL_G33_IDS(&intel_g33_info), 376 INTEL_I965GM_IDS(&intel_i965gm_info), 377 INTEL_GM45_IDS(&intel_gm45_info), 378 INTEL_G45_IDS(&intel_g45_info), 379 INTEL_PINEVIEW_IDS(&intel_pineview_info), 380 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 381 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 382 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), 383 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), 384 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 385 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 386 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 387 INTEL_HSW_D_IDS(&intel_haswell_d_info), 388 INTEL_HSW_M_IDS(&intel_haswell_m_info), 389 INTEL_VLV_M_IDS(&intel_valleyview_m_info), 390 INTEL_VLV_D_IDS(&intel_valleyview_d_info), 391 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), 392 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), 393 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), 394 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), 395 INTEL_CHV_IDS(&intel_cherryview_info), 396 INTEL_SKL_GT1_IDS(&intel_skylake_info), 397 INTEL_SKL_GT2_IDS(&intel_skylake_info), 398 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 399 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), 400 INTEL_BXT_IDS(&intel_broxton_info), 401 INTEL_KBL_GT1_IDS(&intel_kabylake_info), 402 INTEL_KBL_GT2_IDS(&intel_kabylake_info), 403 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 404 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 405 {0, 0, 0} 406 }; 407 408 #define PCI_VENDOR_INTEL 0x8086 409 410 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) 411 { 412 enum intel_pch ret = PCH_NOP; 413 414 /* 415 * In a virtualized passthrough environment we can be in a 416 * setup where the ISA bridge is not able to be passed through. 417 * In this case, a south bridge can be emulated and we have to 418 * make an educated guess as to which PCH is really there. 419 */ 420 421 if (IS_GEN5(dev)) { 422 ret = PCH_IBX; 423 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); 424 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { 425 ret = PCH_CPT; 426 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); 427 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 428 ret = PCH_LPT; 429 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); 430 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 431 ret = PCH_SPT; 432 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); 433 } 434 435 return ret; 436 } 437 438 void intel_detect_pch(struct drm_device *dev) 439 { 440 struct drm_i915_private *dev_priv = dev->dev_private; 441 device_t pch = NULL; 442 struct pci_devinfo *di; 443 444 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting 445 * (which really amounts to a PCH but no South Display). 446 */ 447 if (INTEL_INFO(dev)->num_pipes == 0) { 448 dev_priv->pch_type = PCH_NOP; 449 return; 450 } 451 452 /* XXX The ISA bridge probe causes some old Core2 machines to hang */ 453 if (INTEL_INFO(dev)->gen < 5) 454 return; 455 456 /* 457 * The reason to probe ISA bridge instead of Dev31:Fun0 is to 458 * make graphics device passthrough work easy for VMM, that only 459 * need to expose ISA bridge to let driver know the real hardware 460 * underneath. This is a requirement from virtualization team. 461 * 462 * In some virtualized environments (e.g. XEN), there is irrelevant 463 * ISA bridge in the system. To work reliably, we should scan trhough 464 * all the ISA bridge devices and check for the first match, instead 465 * of only checking the first one. 466 */ 467 di = NULL; 468 469 while ((pch = pci_iterate_class(&di, PCIC_BRIDGE, PCIS_BRIDGE_ISA))) { 470 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) { 471 unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK; 472 dev_priv->pch_id = id; 473 474 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { 475 dev_priv->pch_type = PCH_IBX; 476 DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); 477 WARN_ON(!IS_GEN5(dev)); 478 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { 479 dev_priv->pch_type = PCH_CPT; 480 DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 481 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 482 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { 483 /* PantherPoint is CPT compatible */ 484 dev_priv->pch_type = PCH_CPT; 485 DRM_DEBUG_KMS("Found PantherPoint PCH\n"); 486 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 487 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 488 dev_priv->pch_type = PCH_LPT; 489 DRM_DEBUG_KMS("Found LynxPoint PCH\n"); 490 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); 491 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); 492 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 493 dev_priv->pch_type = PCH_LPT; 494 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); 495 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); 496 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); 497 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { 498 dev_priv->pch_type = PCH_SPT; 499 DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); 500 WARN_ON(!IS_SKYLAKE(dev) && 501 !IS_KABYLAKE(dev)); 502 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { 503 dev_priv->pch_type = PCH_SPT; 504 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); 505 WARN_ON(!IS_SKYLAKE(dev) && 506 !IS_KABYLAKE(dev)); 507 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) || 508 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE)) { 509 dev_priv->pch_type = intel_virt_detect_pch(dev); 510 } else 511 continue; 512 513 break; 514 } 515 } 516 if (!pch) 517 DRM_DEBUG_KMS("No PCH found.\n"); 518 519 #if 0 520 pci_dev_put(pch); 521 #endif 522 } 523 524 bool i915_semaphore_is_enabled(struct drm_device *dev) 525 { 526 if (INTEL_INFO(dev)->gen < 6) 527 return false; 528 529 if (i915.semaphores >= 0) 530 return i915.semaphores; 531 532 /* TODO: make semaphores and Execlists play nicely together */ 533 if (i915.enable_execlists) 534 return false; 535 536 /* Until we get further testing... */ 537 if (IS_GEN8(dev)) 538 return false; 539 540 #ifdef CONFIG_INTEL_IOMMU 541 /* Enable semaphores on SNB when IO remapping is off */ 542 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) 543 return false; 544 #endif 545 546 return true; 547 } 548 549 #ifdef __DragonFly__ 550 #define IS_BUILTIN(blah) 0 551 #endif 552 553 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 554 { 555 struct drm_device *dev = dev_priv->dev; 556 struct intel_encoder *encoder; 557 558 drm_modeset_lock_all(dev); 559 for_each_intel_encoder(dev, encoder) 560 if (encoder->suspend) 561 encoder->suspend(encoder); 562 drm_modeset_unlock_all(dev); 563 } 564 565 static int intel_suspend_complete(struct drm_i915_private *dev_priv); 566 static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 567 bool rpm_resume); 568 static int bxt_resume_prepare(struct drm_i915_private *dev_priv); 569 570 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 571 { 572 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 573 if (acpi_target_system_state() < ACPI_STATE_S3) 574 return true; 575 #endif 576 return false; 577 } 578 579 static int i915_drm_suspend(struct drm_device *dev) 580 { 581 struct drm_i915_private *dev_priv = dev->dev_private; 582 pci_power_t opregion_target_state; 583 int error; 584 585 /* ignore lid events during suspend */ 586 mutex_lock(&dev_priv->modeset_restore_lock); 587 dev_priv->modeset_restore = MODESET_SUSPENDED; 588 mutex_unlock(&dev_priv->modeset_restore_lock); 589 590 disable_rpm_wakeref_asserts(dev_priv); 591 592 /* We do a lot of poking in a lot of registers, make sure they work 593 * properly. */ 594 intel_display_set_init_power(dev_priv, true); 595 596 drm_kms_helper_poll_disable(dev); 597 598 #if 0 599 pci_save_state(dev->pdev); 600 #endif 601 602 error = i915_gem_suspend(dev); 603 if (error) { 604 dev_err(dev->dev, 605 "GEM idle failed, resume might fail\n"); 606 goto out; 607 } 608 609 intel_guc_suspend(dev); 610 611 intel_suspend_gt_powersave(dev); 612 613 /* 614 * Disable CRTCs directly since we want to preserve sw state 615 * for _thaw. Also, power gate the CRTC power wells. 616 */ 617 drm_modeset_lock_all(dev); 618 intel_display_suspend(dev); 619 drm_modeset_unlock_all(dev); 620 621 #if 0 622 intel_dp_mst_suspend(dev); 623 #endif 624 625 intel_runtime_pm_disable_interrupts(dev_priv); 626 intel_hpd_cancel_work(dev_priv); 627 628 intel_suspend_encoders(dev_priv); 629 630 intel_suspend_hw(dev); 631 632 i915_gem_suspend_gtt_mappings(dev); 633 634 i915_save_state(dev); 635 636 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 637 intel_opregion_notify_adapter(dev, opregion_target_state); 638 639 intel_uncore_forcewake_reset(dev, false); 640 intel_opregion_fini(dev); 641 642 #if 0 643 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 644 #endif 645 646 dev_priv->suspend_count++; 647 648 intel_display_set_init_power(dev_priv, false); 649 650 if (HAS_CSR(dev_priv)) 651 flush_work(&dev_priv->csr.work); 652 653 out: 654 enable_rpm_wakeref_asserts(dev_priv); 655 656 return error; 657 } 658 659 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) 660 { 661 struct drm_i915_private *dev_priv = drm_dev->dev_private; 662 bool fw_csr; 663 int ret; 664 665 disable_rpm_wakeref_asserts(dev_priv); 666 667 fw_csr = suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; 668 /* 669 * In case of firmware assisted context save/restore don't manually 670 * deinit the power domains. This also means the CSR/DMC firmware will 671 * stay active, it will power down any HW resources as required and 672 * also enable deeper system power states that would be blocked if the 673 * firmware was inactive. 674 */ 675 if (!fw_csr) 676 intel_power_domains_suspend(dev_priv); 677 678 ret = intel_suspend_complete(dev_priv); 679 680 if (ret) { 681 DRM_ERROR("Suspend complete failed: %d\n", ret); 682 if (!fw_csr) 683 intel_power_domains_init_hw(dev_priv, true); 684 685 goto out; 686 } 687 688 #if 0 689 pci_disable_device(drm_dev->pdev); 690 /* 691 * During hibernation on some platforms the BIOS may try to access 692 * the device even though it's already in D3 and hang the machine. So 693 * leave the device in D0 on those platforms and hope the BIOS will 694 * power down the device properly. The issue was seen on multiple old 695 * GENs with different BIOS vendors, so having an explicit blacklist 696 * is inpractical; apply the workaround on everything pre GEN6. The 697 * platforms where the issue was seen: 698 * Lenovo Thinkpad X301, X61s, X60, T60, X41 699 * Fujitsu FSC S7110 700 * Acer Aspire 1830T 701 */ 702 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) 703 pci_set_power_state(drm_dev->pdev, PCI_D3hot); 704 #endif 705 706 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv); 707 708 out: 709 enable_rpm_wakeref_asserts(dev_priv); 710 711 return ret; 712 } 713 714 int i915_suspend_switcheroo(device_t kdev) 715 { 716 struct drm_device *dev = device_get_softc(kdev); 717 int error; 718 719 if (!dev || !dev->dev_private) { 720 DRM_ERROR("dev: %p\n", dev); 721 DRM_ERROR("DRM not initialized, aborting suspend.\n"); 722 return -ENODEV; 723 } 724 725 #if 0 726 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && 727 state.event != PM_EVENT_FREEZE)) 728 return -EINVAL; 729 #endif 730 731 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 732 return 0; 733 734 error = i915_drm_suspend(dev); 735 if (error) 736 return error; 737 738 return i915_drm_suspend_late(dev, false); 739 } 740 741 static int i915_drm_resume(struct drm_device *dev) 742 { 743 struct drm_i915_private *dev_priv = dev->dev_private; 744 745 disable_rpm_wakeref_asserts(dev_priv); 746 747 mutex_lock(&dev->struct_mutex); 748 i915_gem_restore_gtt_mappings(dev); 749 mutex_unlock(&dev->struct_mutex); 750 751 i915_restore_state(dev); 752 intel_opregion_setup(dev); 753 754 intel_init_pch_refclk(dev); 755 drm_mode_config_reset(dev); 756 757 /* 758 * Interrupts have to be enabled before any batches are run. If not the 759 * GPU will hang. i915_gem_init_hw() will initiate batches to 760 * update/restore the context. 761 * 762 * Modeset enabling in intel_modeset_init_hw() also needs working 763 * interrupts. 764 */ 765 intel_runtime_pm_enable_interrupts(dev_priv); 766 767 mutex_lock(&dev->struct_mutex); 768 if (i915_gem_init_hw(dev)) { 769 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); 770 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); 771 } 772 mutex_unlock(&dev->struct_mutex); 773 774 intel_guc_resume(dev); 775 776 intel_modeset_init_hw(dev); 777 778 spin_lock_irq(&dev_priv->irq_lock); 779 if (dev_priv->display.hpd_irq_setup) 780 dev_priv->display.hpd_irq_setup(dev); 781 spin_unlock_irq(&dev_priv->irq_lock); 782 783 drm_modeset_lock_all(dev); 784 intel_display_resume(dev); 785 drm_modeset_unlock_all(dev); 786 787 intel_dp_mst_resume(dev); 788 789 /* 790 * ... but also need to make sure that hotplug processing 791 * doesn't cause havoc. Like in the driver load code we don't 792 * bother with the tiny race here where we might loose hotplug 793 * notifications. 794 * */ 795 intel_hpd_init(dev_priv); 796 /* Config may have changed between suspend and resume */ 797 drm_helper_hpd_irq_event(dev); 798 799 intel_opregion_init(dev); 800 801 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 802 803 mutex_lock(&dev_priv->modeset_restore_lock); 804 dev_priv->modeset_restore = MODESET_DONE; 805 mutex_unlock(&dev_priv->modeset_restore_lock); 806 807 #if 0 808 intel_opregion_notify_adapter(dev, PCI_D0); 809 #endif 810 811 drm_kms_helper_poll_enable(dev); 812 813 enable_rpm_wakeref_asserts(dev_priv); 814 815 return 0; 816 } 817 818 static int i915_drm_resume_early(struct drm_device *dev) 819 { 820 struct drm_i915_private *dev_priv = dev->dev_private; 821 int ret = 0; 822 823 /* 824 * We have a resume ordering issue with the snd-hda driver also 825 * requiring our device to be power up. Due to the lack of a 826 * parent/child relationship we currently solve this with an early 827 * resume hook. 828 * 829 * FIXME: This should be solved with a special hdmi sink device or 830 * similar so that power domains can be employed. 831 */ 832 #if 0 833 if (pci_enable_device(dev->pdev)) { 834 ret = -EIO; 835 goto out; 836 } 837 838 pci_set_master(dev->pdev); 839 #endif 840 841 disable_rpm_wakeref_asserts(dev_priv); 842 843 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 844 ret = vlv_resume_prepare(dev_priv, false); 845 if (ret) 846 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", 847 ret); 848 849 intel_uncore_early_sanitize(dev, true); 850 851 if (IS_BROXTON(dev)) 852 ret = bxt_resume_prepare(dev_priv); 853 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 854 hsw_disable_pc8(dev_priv); 855 856 intel_uncore_sanitize(dev); 857 858 if (!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) 859 intel_power_domains_init_hw(dev_priv, true); 860 861 #if 0 862 out: 863 #endif 864 dev_priv->suspended_to_idle = false; 865 866 enable_rpm_wakeref_asserts(dev_priv); 867 868 return ret; 869 } 870 871 int i915_resume_switcheroo(struct drm_device *dev) 872 { 873 int ret; 874 875 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 876 return 0; 877 878 ret = i915_drm_resume_early(dev); 879 if (ret) 880 return ret; 881 882 return i915_drm_resume(dev); 883 } 884 885 /* XXX Hack for the old *BSD drm code base 886 * The device id field is set at probe time */ 887 static drm_pci_id_list_t i915_attach_list[] = { 888 {0x8086, 0, 0, "Intel i915 GPU"}, 889 {0, 0, 0, NULL} 890 }; 891 892 struct intel_device_info * 893 i915_get_device_id(int device) 894 { 895 const struct pci_device_id *did; 896 897 for (did = &pciidlist[0]; did->device != 0; did++) { 898 if (did->device != device) 899 continue; 900 return (struct intel_device_info *)did->driver_data; 901 } 902 return (NULL); 903 } 904 905 extern devclass_t drm_devclass; 906 907 /** 908 * i915_reset - reset chip after a hang 909 * @dev: drm device to reset 910 * 911 * Reset the chip. Useful if a hang is detected. Returns zero on successful 912 * reset or otherwise an error code. 913 * 914 * Procedure is fairly simple: 915 * - reset the chip using the reset reg 916 * - re-init context state 917 * - re-init hardware status page 918 * - re-init ring buffer 919 * - re-init interrupt state 920 * - re-init display 921 */ 922 int i915_reset(struct drm_device *dev) 923 { 924 struct drm_i915_private *dev_priv = dev->dev_private; 925 bool simulated; 926 int ret; 927 928 intel_reset_gt_powersave(dev); 929 930 mutex_lock(&dev->struct_mutex); 931 932 i915_gem_reset(dev); 933 934 simulated = dev_priv->gpu_error.stop_rings != 0; 935 936 ret = intel_gpu_reset(dev); 937 938 /* Also reset the gpu hangman. */ 939 if (simulated) { 940 DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); 941 dev_priv->gpu_error.stop_rings = 0; 942 if (ret == -ENODEV) { 943 DRM_INFO("Reset not implemented, but ignoring " 944 "error for simulated gpu hangs\n"); 945 ret = 0; 946 } 947 } 948 949 if (i915_stop_ring_allow_warn(dev_priv)) 950 pr_notice("drm/i915: Resetting chip after gpu hang\n"); 951 952 if (ret) { 953 DRM_ERROR("Failed to reset chip: %i\n", ret); 954 mutex_unlock(&dev->struct_mutex); 955 return ret; 956 } 957 958 intel_overlay_reset(dev_priv); 959 960 /* Ok, now get things going again... */ 961 962 /* 963 * Everything depends on having the GTT running, so we need to start 964 * there. Fortunately we don't need to do this unless we reset the 965 * chip at a PCI level. 966 * 967 * Next we need to restore the context, but we don't use those 968 * yet either... 969 * 970 * Ring buffer needs to be re-initialized in the KMS case, or if X 971 * was running at the time of the reset (i.e. we weren't VT 972 * switched away). 973 */ 974 975 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ 976 dev_priv->gpu_error.reload_in_reset = true; 977 978 ret = i915_gem_init_hw(dev); 979 980 dev_priv->gpu_error.reload_in_reset = false; 981 982 mutex_unlock(&dev->struct_mutex); 983 if (ret) { 984 DRM_ERROR("Failed hw init on reset %d\n", ret); 985 return ret; 986 } 987 988 /* 989 * rps/rc6 re-init is necessary to restore state lost after the 990 * reset and the re-install of gt irqs. Skip for ironlake per 991 * previous concerns that it doesn't respond well to some forms 992 * of re-init after reset. 993 */ 994 if (INTEL_INFO(dev)->gen > 5) 995 intel_enable_gt_powersave(dev); 996 997 return 0; 998 } 999 1000 static int i915_pci_probe(device_t kdev) 1001 { 1002 int device, i = 0; 1003 1004 if (pci_get_class(kdev) != PCIC_DISPLAY) 1005 return ENXIO; 1006 1007 if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL) 1008 return ENXIO; 1009 1010 device = pci_get_device(kdev); 1011 1012 for (i = 0; pciidlist[i].device != 0; i++) { 1013 if (pciidlist[i].device == device) { 1014 i915_attach_list[0].device = device; 1015 return 0; 1016 } 1017 } 1018 1019 return ENXIO; 1020 } 1021 1022 #if 0 1023 static void 1024 i915_pci_remove(struct pci_dev *pdev) 1025 { 1026 struct drm_device *dev = pci_get_drvdata(pdev); 1027 1028 drm_put_dev(dev); 1029 } 1030 1031 static int i915_pm_suspend(struct device *dev) 1032 { 1033 struct pci_dev *pdev = to_pci_dev(dev); 1034 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1035 1036 if (!drm_dev || !drm_dev->dev_private) { 1037 dev_err(dev, "DRM not initialized, aborting suspend.\n"); 1038 return -ENODEV; 1039 } 1040 1041 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1042 return 0; 1043 1044 return i915_drm_suspend(drm_dev); 1045 } 1046 1047 static int i915_pm_suspend_late(struct device *dev) 1048 { 1049 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1050 1051 /* 1052 * We have a suspend ordering issue with the snd-hda driver also 1053 * requiring our device to be power up. Due to the lack of a 1054 * parent/child relationship we currently solve this with an late 1055 * suspend hook. 1056 * 1057 * FIXME: This should be solved with a special hdmi sink device or 1058 * similar so that power domains can be employed. 1059 */ 1060 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1061 return 0; 1062 1063 return i915_drm_suspend_late(drm_dev, false); 1064 } 1065 1066 static int i915_pm_poweroff_late(struct device *dev) 1067 { 1068 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1069 1070 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1071 return 0; 1072 1073 return i915_drm_suspend_late(drm_dev, true); 1074 } 1075 1076 static int i915_pm_resume_early(struct device *dev) 1077 { 1078 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1079 1080 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1081 return 0; 1082 1083 return i915_drm_resume_early(drm_dev); 1084 } 1085 1086 static int i915_pm_resume(struct device *dev) 1087 { 1088 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1089 1090 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1091 return 0; 1092 1093 return i915_drm_resume(drm_dev); 1094 } 1095 #endif 1096 1097 static int hsw_suspend_complete(struct drm_i915_private *dev_priv) 1098 { 1099 hsw_enable_pc8(dev_priv); 1100 1101 return 0; 1102 } 1103 1104 static int bxt_suspend_complete(struct drm_i915_private *dev_priv) 1105 { 1106 struct drm_device *dev = dev_priv->dev; 1107 1108 /* TODO: when DC5 support is added disable DC5 here. */ 1109 1110 broxton_ddi_phy_uninit(dev); 1111 broxton_uninit_cdclk(dev); 1112 bxt_enable_dc9(dev_priv); 1113 1114 return 0; 1115 } 1116 1117 static int bxt_resume_prepare(struct drm_i915_private *dev_priv) 1118 { 1119 struct drm_device *dev = dev_priv->dev; 1120 1121 /* TODO: when CSR FW support is added make sure the FW is loaded */ 1122 1123 bxt_disable_dc9(dev_priv); 1124 1125 /* 1126 * TODO: when DC5 support is added enable DC5 here if the CSR FW 1127 * is available. 1128 */ 1129 broxton_init_cdclk(dev); 1130 broxton_ddi_phy_init(dev); 1131 intel_prepare_ddi(dev); 1132 1133 return 0; 1134 } 1135 1136 /* 1137 * Save all Gunit registers that may be lost after a D3 and a subsequent 1138 * S0i[R123] transition. The list of registers needing a save/restore is 1139 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit 1140 * registers in the following way: 1141 * - Driver: saved/restored by the driver 1142 * - Punit : saved/restored by the Punit firmware 1143 * - No, w/o marking: no need to save/restore, since the register is R/O or 1144 * used internally by the HW in a way that doesn't depend 1145 * keeping the content across a suspend/resume. 1146 * - Debug : used for debugging 1147 * 1148 * We save/restore all registers marked with 'Driver', with the following 1149 * exceptions: 1150 * - Registers out of use, including also registers marked with 'Debug'. 1151 * These have no effect on the driver's operation, so we don't save/restore 1152 * them to reduce the overhead. 1153 * - Registers that are fully setup by an initialization function called from 1154 * the resume path. For example many clock gating and RPS/RC6 registers. 1155 * - Registers that provide the right functionality with their reset defaults. 1156 * 1157 * TODO: Except for registers that based on the above 3 criteria can be safely 1158 * ignored, we save/restore all others, practically treating the HW context as 1159 * a black-box for the driver. Further investigation is needed to reduce the 1160 * saved/restored registers even further, by following the same 3 criteria. 1161 */ 1162 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1163 { 1164 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1165 int i; 1166 1167 /* GAM 0x4000-0x4770 */ 1168 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); 1169 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); 1170 s->arb_mode = I915_READ(ARB_MODE); 1171 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); 1172 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); 1173 1174 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1175 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); 1176 1177 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); 1178 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); 1179 1180 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); 1181 s->ecochk = I915_READ(GAM_ECOCHK); 1182 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); 1183 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); 1184 1185 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); 1186 1187 /* MBC 0x9024-0x91D0, 0x8500 */ 1188 s->g3dctl = I915_READ(VLV_G3DCTL); 1189 s->gsckgctl = I915_READ(VLV_GSCKGCTL); 1190 s->mbctl = I915_READ(GEN6_MBCTL); 1191 1192 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1193 s->ucgctl1 = I915_READ(GEN6_UCGCTL1); 1194 s->ucgctl3 = I915_READ(GEN6_UCGCTL3); 1195 s->rcgctl1 = I915_READ(GEN6_RCGCTL1); 1196 s->rcgctl2 = I915_READ(GEN6_RCGCTL2); 1197 s->rstctl = I915_READ(GEN6_RSTCTL); 1198 s->misccpctl = I915_READ(GEN7_MISCCPCTL); 1199 1200 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1201 s->gfxpause = I915_READ(GEN6_GFXPAUSE); 1202 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); 1203 s->rpdeuc = I915_READ(GEN6_RPDEUC); 1204 s->ecobus = I915_READ(ECOBUS); 1205 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); 1206 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); 1207 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); 1208 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); 1209 s->rcedata = I915_READ(VLV_RCEDATA); 1210 s->spare2gh = I915_READ(VLV_SPAREG2H); 1211 1212 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1213 s->gt_imr = I915_READ(GTIMR); 1214 s->gt_ier = I915_READ(GTIER); 1215 s->pm_imr = I915_READ(GEN6_PMIMR); 1216 s->pm_ier = I915_READ(GEN6_PMIER); 1217 1218 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1219 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); 1220 1221 /* GT SA CZ domain, 0x100000-0x138124 */ 1222 s->tilectl = I915_READ(TILECTL); 1223 s->gt_fifoctl = I915_READ(GTFIFOCTL); 1224 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); 1225 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1226 s->pmwgicz = I915_READ(VLV_PMWGICZ); 1227 1228 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1229 s->gu_ctl0 = I915_READ(VLV_GU_CTL0); 1230 s->gu_ctl1 = I915_READ(VLV_GU_CTL1); 1231 s->pcbr = I915_READ(VLV_PCBR); 1232 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); 1233 1234 /* 1235 * Not saving any of: 1236 * DFT, 0x9800-0x9EC0 1237 * SARB, 0xB000-0xB1FC 1238 * GAC, 0x5208-0x524C, 0x14000-0x14C000 1239 * PCI CFG 1240 */ 1241 } 1242 1243 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1244 { 1245 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1246 u32 val; 1247 int i; 1248 1249 /* GAM 0x4000-0x4770 */ 1250 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); 1251 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); 1252 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); 1253 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); 1254 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); 1255 1256 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1257 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); 1258 1259 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); 1260 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); 1261 1262 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); 1263 I915_WRITE(GAM_ECOCHK, s->ecochk); 1264 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); 1265 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); 1266 1267 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); 1268 1269 /* MBC 0x9024-0x91D0, 0x8500 */ 1270 I915_WRITE(VLV_G3DCTL, s->g3dctl); 1271 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); 1272 I915_WRITE(GEN6_MBCTL, s->mbctl); 1273 1274 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1275 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); 1276 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); 1277 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); 1278 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); 1279 I915_WRITE(GEN6_RSTCTL, s->rstctl); 1280 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); 1281 1282 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1283 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); 1284 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); 1285 I915_WRITE(GEN6_RPDEUC, s->rpdeuc); 1286 I915_WRITE(ECOBUS, s->ecobus); 1287 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); 1288 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); 1289 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); 1290 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); 1291 I915_WRITE(VLV_RCEDATA, s->rcedata); 1292 I915_WRITE(VLV_SPAREG2H, s->spare2gh); 1293 1294 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1295 I915_WRITE(GTIMR, s->gt_imr); 1296 I915_WRITE(GTIER, s->gt_ier); 1297 I915_WRITE(GEN6_PMIMR, s->pm_imr); 1298 I915_WRITE(GEN6_PMIER, s->pm_ier); 1299 1300 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1301 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); 1302 1303 /* GT SA CZ domain, 0x100000-0x138124 */ 1304 I915_WRITE(TILECTL, s->tilectl); 1305 I915_WRITE(GTFIFOCTL, s->gt_fifoctl); 1306 /* 1307 * Preserve the GT allow wake and GFX force clock bit, they are not 1308 * be restored, as they are used to control the s0ix suspend/resume 1309 * sequence by the caller. 1310 */ 1311 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1312 val &= VLV_GTLC_ALLOWWAKEREQ; 1313 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; 1314 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1315 1316 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1317 val &= VLV_GFX_CLK_FORCE_ON_BIT; 1318 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; 1319 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1320 1321 I915_WRITE(VLV_PMWGICZ, s->pmwgicz); 1322 1323 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1324 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); 1325 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); 1326 I915_WRITE(VLV_PCBR, s->pcbr); 1327 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); 1328 } 1329 1330 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) 1331 { 1332 u32 val; 1333 int err; 1334 1335 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) 1336 1337 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1338 val &= ~VLV_GFX_CLK_FORCE_ON_BIT; 1339 if (force_on) 1340 val |= VLV_GFX_CLK_FORCE_ON_BIT; 1341 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1342 1343 if (!force_on) 1344 return 0; 1345 1346 err = wait_for(COND, 20); 1347 if (err) 1348 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", 1349 I915_READ(VLV_GTLC_SURVIVABILITY_REG)); 1350 1351 return err; 1352 #undef COND 1353 } 1354 1355 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) 1356 { 1357 u32 val; 1358 int err = 0; 1359 1360 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1361 val &= ~VLV_GTLC_ALLOWWAKEREQ; 1362 if (allow) 1363 val |= VLV_GTLC_ALLOWWAKEREQ; 1364 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1365 POSTING_READ(VLV_GTLC_WAKE_CTRL); 1366 1367 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ 1368 allow) 1369 err = wait_for(COND, 1); 1370 if (err) 1371 DRM_ERROR("timeout disabling GT waking\n"); 1372 return err; 1373 #undef COND 1374 } 1375 1376 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, 1377 bool wait_for_on) 1378 { 1379 u32 mask; 1380 u32 val; 1381 int err; 1382 1383 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; 1384 val = wait_for_on ? mask : 0; 1385 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) 1386 if (COND) 1387 return 0; 1388 1389 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", 1390 wait_for_on ? "on" : "off", 1391 I915_READ(VLV_GTLC_PW_STATUS)); 1392 1393 /* 1394 * RC6 transitioning can be delayed up to 2 msec (see 1395 * valleyview_enable_rps), use 3 msec for safety. 1396 */ 1397 err = wait_for(COND, 3); 1398 if (err) 1399 DRM_ERROR("timeout waiting for GT wells to go %s\n", 1400 wait_for_on ? "on" : "off"); 1401 1402 return err; 1403 #undef COND 1404 } 1405 1406 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) 1407 { 1408 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) 1409 return; 1410 1411 DRM_ERROR("GT register access while GT waking disabled\n"); 1412 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); 1413 } 1414 1415 static int vlv_suspend_complete(struct drm_i915_private *dev_priv) 1416 { 1417 u32 mask; 1418 int err; 1419 1420 /* 1421 * Bspec defines the following GT well on flags as debug only, so 1422 * don't treat them as hard failures. 1423 */ 1424 (void)vlv_wait_for_gt_wells(dev_priv, false); 1425 1426 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; 1427 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); 1428 1429 vlv_check_no_gt_access(dev_priv); 1430 1431 err = vlv_force_gfx_clock(dev_priv, true); 1432 if (err) 1433 goto err1; 1434 1435 err = vlv_allow_gt_wake(dev_priv, false); 1436 if (err) 1437 goto err2; 1438 1439 if (!IS_CHERRYVIEW(dev_priv->dev)) 1440 vlv_save_gunit_s0ix_state(dev_priv); 1441 1442 err = vlv_force_gfx_clock(dev_priv, false); 1443 if (err) 1444 goto err2; 1445 1446 return 0; 1447 1448 err2: 1449 /* For safety always re-enable waking and disable gfx clock forcing */ 1450 vlv_allow_gt_wake(dev_priv, true); 1451 err1: 1452 vlv_force_gfx_clock(dev_priv, false); 1453 1454 return err; 1455 } 1456 1457 static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 1458 bool rpm_resume) 1459 { 1460 struct drm_device *dev = dev_priv->dev; 1461 int err; 1462 int ret; 1463 1464 /* 1465 * If any of the steps fail just try to continue, that's the best we 1466 * can do at this point. Return the first error code (which will also 1467 * leave RPM permanently disabled). 1468 */ 1469 ret = vlv_force_gfx_clock(dev_priv, true); 1470 1471 if (!IS_CHERRYVIEW(dev_priv->dev)) 1472 vlv_restore_gunit_s0ix_state(dev_priv); 1473 1474 err = vlv_allow_gt_wake(dev_priv, true); 1475 if (!ret) 1476 ret = err; 1477 1478 err = vlv_force_gfx_clock(dev_priv, false); 1479 if (!ret) 1480 ret = err; 1481 1482 vlv_check_no_gt_access(dev_priv); 1483 1484 if (rpm_resume) { 1485 intel_init_clock_gating(dev); 1486 i915_gem_restore_fences(dev); 1487 } 1488 1489 return ret; 1490 } 1491 1492 #if 0 1493 static int intel_runtime_suspend(struct device *device) 1494 { 1495 struct pci_dev *pdev = to_pci_dev(device); 1496 struct drm_device *dev = pci_get_drvdata(pdev); 1497 struct drm_i915_private *dev_priv = dev->dev_private; 1498 int ret; 1499 1500 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) 1501 return -ENODEV; 1502 1503 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) 1504 return -ENODEV; 1505 1506 DRM_DEBUG_KMS("Suspending device\n"); 1507 1508 /* 1509 * We could deadlock here in case another thread holding struct_mutex 1510 * calls RPM suspend concurrently, since the RPM suspend will wait 1511 * first for this RPM suspend to finish. In this case the concurrent 1512 * RPM resume will be followed by its RPM suspend counterpart. Still 1513 * for consistency return -EAGAIN, which will reschedule this suspend. 1514 */ 1515 if (!mutex_trylock(&dev->struct_mutex)) { 1516 DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); 1517 /* 1518 * Bump the expiration timestamp, otherwise the suspend won't 1519 * be rescheduled. 1520 */ 1521 pm_runtime_mark_last_busy(device); 1522 1523 return -EAGAIN; 1524 } 1525 1526 disable_rpm_wakeref_asserts(dev_priv); 1527 1528 /* 1529 * We are safe here against re-faults, since the fault handler takes 1530 * an RPM reference. 1531 */ 1532 i915_gem_release_all_mmaps(dev_priv); 1533 mutex_unlock(&dev->struct_mutex); 1534 1535 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); 1536 1537 intel_guc_suspend(dev); 1538 1539 intel_suspend_gt_powersave(dev); 1540 intel_runtime_pm_disable_interrupts(dev_priv); 1541 1542 ret = intel_suspend_complete(dev_priv); 1543 if (ret) { 1544 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); 1545 intel_runtime_pm_enable_interrupts(dev_priv); 1546 1547 enable_rpm_wakeref_asserts(dev_priv); 1548 1549 return ret; 1550 } 1551 1552 intel_uncore_forcewake_reset(dev, false); 1553 1554 enable_rpm_wakeref_asserts(dev_priv); 1555 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); 1556 dev_priv->pm.suspended = true; 1557 1558 /* 1559 * FIXME: We really should find a document that references the arguments 1560 * used below! 1561 */ 1562 if (IS_BROADWELL(dev)) { 1563 /* 1564 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1565 * being detected, and the call we do at intel_runtime_resume() 1566 * won't be able to restore them. Since PCI_D3hot matches the 1567 * actual specification and appears to be working, use it. 1568 */ 1569 intel_opregion_notify_adapter(dev, PCI_D3hot); 1570 } else { 1571 /* 1572 * current versions of firmware which depend on this opregion 1573 * notification have repurposed the D1 definition to mean 1574 * "runtime suspended" vs. what you would normally expect (D3) 1575 * to distinguish it from notifications that might be sent via 1576 * the suspend path. 1577 */ 1578 intel_opregion_notify_adapter(dev, PCI_D1); 1579 } 1580 1581 assert_forcewakes_inactive(dev_priv); 1582 1583 DRM_DEBUG_KMS("Device suspended\n"); 1584 return 0; 1585 } 1586 1587 static int intel_runtime_resume(struct device *device) 1588 { 1589 struct pci_dev *pdev = to_pci_dev(device); 1590 struct drm_device *dev = pci_get_drvdata(pdev); 1591 struct drm_i915_private *dev_priv = dev->dev_private; 1592 int ret = 0; 1593 1594 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) 1595 return -ENODEV; 1596 1597 DRM_DEBUG_KMS("Resuming device\n"); 1598 1599 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); 1600 disable_rpm_wakeref_asserts(dev_priv); 1601 1602 intel_opregion_notify_adapter(dev, PCI_D0); 1603 dev_priv->pm.suspended = false; 1604 1605 intel_guc_resume(dev); 1606 1607 if (IS_GEN6(dev_priv)) 1608 intel_init_pch_refclk(dev); 1609 1610 if (IS_BROXTON(dev)) 1611 ret = bxt_resume_prepare(dev_priv); 1612 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1613 hsw_disable_pc8(dev_priv); 1614 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1615 ret = vlv_resume_prepare(dev_priv, true); 1616 1617 /* 1618 * No point of rolling back things in case of an error, as the best 1619 * we can do is to hope that things will still work (and disable RPM). 1620 */ 1621 i915_gem_init_swizzling(dev); 1622 gen6_update_ring_freq(dev); 1623 1624 intel_runtime_pm_enable_interrupts(dev_priv); 1625 1626 /* 1627 * On VLV/CHV display interrupts are part of the display 1628 * power well, so hpd is reinitialized from there. For 1629 * everyone else do it here. 1630 */ 1631 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1632 intel_hpd_init(dev_priv); 1633 1634 intel_enable_gt_powersave(dev); 1635 1636 enable_rpm_wakeref_asserts(dev_priv); 1637 1638 if (ret) 1639 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); 1640 else 1641 DRM_DEBUG_KMS("Device resumed\n"); 1642 1643 return ret; 1644 } 1645 #endif 1646 1647 /* 1648 * This function implements common functionality of runtime and system 1649 * suspend sequence. 1650 */ 1651 static int intel_suspend_complete(struct drm_i915_private *dev_priv) 1652 { 1653 int ret; 1654 1655 if (IS_BROXTON(dev_priv)) 1656 ret = bxt_suspend_complete(dev_priv); 1657 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1658 ret = hsw_suspend_complete(dev_priv); 1659 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1660 ret = vlv_suspend_complete(dev_priv); 1661 else 1662 ret = 0; 1663 1664 return ret; 1665 } 1666 1667 #if 0 1668 static const struct dev_pm_ops i915_pm_ops = { 1669 /* 1670 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1671 * PMSG_RESUME] 1672 */ 1673 .suspend = i915_pm_suspend, 1674 .suspend_late = i915_pm_suspend_late, 1675 .resume_early = i915_pm_resume_early, 1676 .resume = i915_pm_resume, 1677 1678 /* 1679 * S4 event handlers 1680 * @freeze, @freeze_late : called (1) before creating the 1681 * hibernation image [PMSG_FREEZE] and 1682 * (2) after rebooting, before restoring 1683 * the image [PMSG_QUIESCE] 1684 * @thaw, @thaw_early : called (1) after creating the hibernation 1685 * image, before writing it [PMSG_THAW] 1686 * and (2) after failing to create or 1687 * restore the image [PMSG_RECOVER] 1688 * @poweroff, @poweroff_late: called after writing the hibernation 1689 * image, before rebooting [PMSG_HIBERNATE] 1690 * @restore, @restore_early : called after rebooting and restoring the 1691 * hibernation image [PMSG_RESTORE] 1692 */ 1693 .freeze = i915_pm_suspend, 1694 .freeze_late = i915_pm_suspend_late, 1695 .thaw_early = i915_pm_resume_early, 1696 .thaw = i915_pm_resume, 1697 .poweroff = i915_pm_suspend, 1698 .poweroff_late = i915_pm_poweroff_late, 1699 .restore_early = i915_pm_resume_early, 1700 .restore = i915_pm_resume, 1701 1702 /* S0ix (via runtime suspend) event handlers */ 1703 .runtime_suspend = intel_runtime_suspend, 1704 .runtime_resume = intel_runtime_resume, 1705 }; 1706 1707 static const struct vm_operations_struct i915_gem_vm_ops = { 1708 .fault = i915_gem_fault, 1709 .open = drm_gem_vm_open, 1710 .close = drm_gem_vm_close, 1711 }; 1712 1713 static const struct file_operations i915_driver_fops = { 1714 .owner = THIS_MODULE, 1715 .open = drm_open, 1716 .release = drm_release, 1717 .unlocked_ioctl = drm_ioctl, 1718 .mmap = drm_gem_mmap, 1719 .poll = drm_poll, 1720 .read = drm_read, 1721 #ifdef CONFIG_COMPAT 1722 .compat_ioctl = i915_compat_ioctl, 1723 #endif 1724 .llseek = noop_llseek, 1725 }; 1726 #endif 1727 1728 static struct cdev_pager_ops i915_gem_vm_ops = { 1729 .cdev_pg_fault = i915_gem_fault, 1730 .cdev_pg_ctor = i915_gem_pager_ctor, 1731 .cdev_pg_dtor = i915_gem_pager_dtor 1732 }; 1733 1734 static struct drm_driver driver = { 1735 /* Don't use MTRRs here; the Xserver or userspace app should 1736 * deal with them for Intel hardware. 1737 */ 1738 .driver_features = 1739 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 1740 DRIVER_RENDER | DRIVER_MODESET, 1741 .load = i915_driver_load, 1742 .unload = i915_driver_unload, 1743 .open = i915_driver_open, 1744 .lastclose = i915_driver_lastclose, 1745 .preclose = i915_driver_preclose, 1746 .postclose = i915_driver_postclose, 1747 1748 #if defined(CONFIG_DEBUG_FS) 1749 .debugfs_init = i915_debugfs_init, 1750 .debugfs_cleanup = i915_debugfs_cleanup, 1751 #endif 1752 .gem_free_object = i915_gem_free_object, 1753 .gem_pager_ops = &i915_gem_vm_ops, 1754 1755 .dumb_create = i915_gem_dumb_create, 1756 .dumb_map_offset = i915_gem_mmap_gtt, 1757 .dumb_destroy = drm_gem_dumb_destroy, 1758 .ioctls = i915_ioctls, 1759 .name = DRIVER_NAME, 1760 .desc = DRIVER_DESC, 1761 .date = DRIVER_DATE, 1762 .major = DRIVER_MAJOR, 1763 .minor = DRIVER_MINOR, 1764 .patchlevel = DRIVER_PATCHLEVEL, 1765 }; 1766 1767 static int __init i915_init(void); 1768 1769 static int 1770 i915_attach(device_t kdev) 1771 { 1772 struct drm_device *dev = device_get_softc(kdev); 1773 int error; 1774 int dummy; 1775 1776 i915_init(); 1777 1778 dev->driver = &driver; 1779 error = drm_attach(kdev, i915_attach_list); 1780 1781 /* 1782 * XXX hack - give the kvm_console time to come up before X starts 1783 * messing with everything, avoiding at least one deadlock. 1784 */ 1785 tsleep(&dummy, 0, "i915_attach", hz*2); 1786 1787 return error; 1788 } 1789 1790 static device_method_t i915_methods[] = { 1791 /* Device interface */ 1792 DEVMETHOD(device_probe, i915_pci_probe), 1793 DEVMETHOD(device_attach, i915_attach), 1794 DEVMETHOD(device_suspend, i915_suspend_switcheroo), 1795 DEVMETHOD(device_resume, i915_resume_switcheroo), 1796 DEVMETHOD(device_detach, drm_release), 1797 DEVMETHOD_END 1798 }; 1799 1800 static driver_t i915_driver = { 1801 "drm", 1802 i915_methods, 1803 sizeof(struct drm_device) 1804 }; 1805 1806 static int __init i915_init(void) 1807 { 1808 driver.num_ioctls = i915_max_ioctl; 1809 1810 /* 1811 * Enable KMS by default, unless explicitly overriden by 1812 * either the i915.modeset prarameter or by the 1813 * vga_text_mode_force boot option. 1814 */ 1815 1816 if (i915.modeset == 0) 1817 driver.driver_features &= ~DRIVER_MODESET; 1818 1819 #ifdef CONFIG_VGA_CONSOLE 1820 if (vgacon_text_force() && i915.modeset == -1) 1821 driver.driver_features &= ~DRIVER_MODESET; 1822 #endif 1823 1824 if (!(driver.driver_features & DRIVER_MODESET)) { 1825 /* Silently fail loading to not upset userspace. */ 1826 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); 1827 return 0; 1828 } 1829 1830 if (i915.nuclear_pageflip) 1831 driver.driver_features |= DRIVER_ATOMIC; 1832 1833 #if 0 1834 return drm_pci_init(&driver, &i915_pci_driver); 1835 #else 1836 return 1; 1837 #endif 1838 } 1839 1840 #if 0 1841 static void __exit i915_exit(void) 1842 { 1843 if (!(driver.driver_features & DRIVER_MODESET)) 1844 return; /* Never loaded a driver. */ 1845 1846 drm_pci_exit(&driver, &i915_pci_driver); 1847 } 1848 #endif 1849 1850 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY); 1851 MODULE_DEPEND(i915, drm, 1, 1, 1); 1852 MODULE_DEPEND(i915, iicbus, 1, 1, 1); 1853 MODULE_DEPEND(i915, iic, 1, 1, 1); 1854 MODULE_DEPEND(i915, iicbb, 1, 1, 1); 1855 #ifdef CONFIG_ACPI 1856 MODULE_DEPEND(i915, acpi, 1, 1, 1); 1857 #endif 1858