1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <linux/device.h> 31 #include <drm/drmP.h> 32 #include <drm/i915_drm.h> 33 #include "i915_drv.h" 34 #include "i915_trace.h" 35 #include "intel_drv.h" 36 37 #include <linux/console.h> 38 #include <linux/module.h> 39 #include <linux/vga_switcheroo.h> 40 #include <drm/drm_crtc_helper.h> 41 42 static struct drm_driver driver; 43 44 #define GEN_DEFAULT_PIPEOFFSETS \ 45 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 46 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 47 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 48 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 49 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 50 51 #define GEN_CHV_PIPEOFFSETS \ 52 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 53 CHV_PIPE_C_OFFSET }, \ 54 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 55 CHV_TRANSCODER_C_OFFSET, }, \ 56 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 57 CHV_PALETTE_C_OFFSET } 58 59 #define CURSOR_OFFSETS \ 60 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 61 62 #define IVB_CURSOR_OFFSETS \ 63 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 64 65 #define BDW_COLORS \ 66 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 } 67 #define CHV_COLORS \ 68 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 } 69 70 static const struct intel_device_info intel_i830_info = { 71 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, 72 .has_overlay = 1, .overlay_needs_physical = 1, 73 .ring_mask = RENDER_RING, 74 GEN_DEFAULT_PIPEOFFSETS, 75 CURSOR_OFFSETS, 76 }; 77 78 static const struct intel_device_info intel_845g_info = { 79 .gen = 2, .num_pipes = 1, 80 .has_overlay = 1, .overlay_needs_physical = 1, 81 .ring_mask = RENDER_RING, 82 GEN_DEFAULT_PIPEOFFSETS, 83 CURSOR_OFFSETS, 84 }; 85 86 static const struct intel_device_info intel_i85x_info = { 87 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, 88 .cursor_needs_physical = 1, 89 .has_overlay = 1, .overlay_needs_physical = 1, 90 .has_fbc = 1, 91 .ring_mask = RENDER_RING, 92 GEN_DEFAULT_PIPEOFFSETS, 93 CURSOR_OFFSETS, 94 }; 95 96 static const struct intel_device_info intel_i865g_info = { 97 .gen = 2, .num_pipes = 1, 98 .has_overlay = 1, .overlay_needs_physical = 1, 99 .ring_mask = RENDER_RING, 100 GEN_DEFAULT_PIPEOFFSETS, 101 CURSOR_OFFSETS, 102 }; 103 104 static const struct intel_device_info intel_i915g_info = { 105 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, 106 .has_overlay = 1, .overlay_needs_physical = 1, 107 .ring_mask = RENDER_RING, 108 GEN_DEFAULT_PIPEOFFSETS, 109 CURSOR_OFFSETS, 110 }; 111 static const struct intel_device_info intel_i915gm_info = { 112 .gen = 3, .is_mobile = 1, .num_pipes = 2, 113 .cursor_needs_physical = 1, 114 .has_overlay = 1, .overlay_needs_physical = 1, 115 .supports_tv = 1, 116 .has_fbc = 1, 117 .ring_mask = RENDER_RING, 118 GEN_DEFAULT_PIPEOFFSETS, 119 CURSOR_OFFSETS, 120 }; 121 static const struct intel_device_info intel_i945g_info = { 122 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, 123 .has_overlay = 1, .overlay_needs_physical = 1, 124 .ring_mask = RENDER_RING, 125 GEN_DEFAULT_PIPEOFFSETS, 126 CURSOR_OFFSETS, 127 }; 128 static const struct intel_device_info intel_i945gm_info = { 129 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, 130 .has_hotplug = 1, .cursor_needs_physical = 1, 131 .has_overlay = 1, .overlay_needs_physical = 1, 132 .supports_tv = 1, 133 .has_fbc = 1, 134 .ring_mask = RENDER_RING, 135 GEN_DEFAULT_PIPEOFFSETS, 136 CURSOR_OFFSETS, 137 }; 138 139 static const struct intel_device_info intel_i965g_info = { 140 .gen = 4, .is_broadwater = 1, .num_pipes = 2, 141 .has_hotplug = 1, 142 .has_overlay = 1, 143 .ring_mask = RENDER_RING, 144 GEN_DEFAULT_PIPEOFFSETS, 145 CURSOR_OFFSETS, 146 }; 147 148 static const struct intel_device_info intel_i965gm_info = { 149 .gen = 4, .is_crestline = 1, .num_pipes = 2, 150 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, 151 .has_overlay = 1, 152 .supports_tv = 1, 153 .ring_mask = RENDER_RING, 154 GEN_DEFAULT_PIPEOFFSETS, 155 CURSOR_OFFSETS, 156 }; 157 158 static const struct intel_device_info intel_g33_info = { 159 .gen = 3, .is_g33 = 1, .num_pipes = 2, 160 .need_gfx_hws = 1, .has_hotplug = 1, 161 .has_overlay = 1, 162 .ring_mask = RENDER_RING, 163 GEN_DEFAULT_PIPEOFFSETS, 164 CURSOR_OFFSETS, 165 }; 166 167 static const struct intel_device_info intel_g45_info = { 168 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, 169 .has_pipe_cxsr = 1, .has_hotplug = 1, 170 .ring_mask = RENDER_RING | BSD_RING, 171 GEN_DEFAULT_PIPEOFFSETS, 172 CURSOR_OFFSETS, 173 }; 174 175 static const struct intel_device_info intel_gm45_info = { 176 .gen = 4, .is_g4x = 1, .num_pipes = 2, 177 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, 178 .has_pipe_cxsr = 1, .has_hotplug = 1, 179 .supports_tv = 1, 180 .ring_mask = RENDER_RING | BSD_RING, 181 GEN_DEFAULT_PIPEOFFSETS, 182 CURSOR_OFFSETS, 183 }; 184 185 static const struct intel_device_info intel_pineview_info = { 186 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, 187 .need_gfx_hws = 1, .has_hotplug = 1, 188 .has_overlay = 1, 189 GEN_DEFAULT_PIPEOFFSETS, 190 CURSOR_OFFSETS, 191 }; 192 193 static const struct intel_device_info intel_ironlake_d_info = { 194 .gen = 5, .num_pipes = 2, 195 .need_gfx_hws = 1, .has_hotplug = 1, 196 .ring_mask = RENDER_RING | BSD_RING, 197 GEN_DEFAULT_PIPEOFFSETS, 198 CURSOR_OFFSETS, 199 }; 200 201 static const struct intel_device_info intel_ironlake_m_info = { 202 .gen = 5, .is_mobile = 1, .num_pipes = 2, 203 .need_gfx_hws = 1, .has_hotplug = 1, 204 .has_fbc = 1, 205 .ring_mask = RENDER_RING | BSD_RING, 206 GEN_DEFAULT_PIPEOFFSETS, 207 CURSOR_OFFSETS, 208 }; 209 210 static const struct intel_device_info intel_sandybridge_d_info = { 211 .gen = 6, .num_pipes = 2, 212 .need_gfx_hws = 1, .has_hotplug = 1, 213 .has_fbc = 1, 214 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 215 .has_llc = 1, 216 GEN_DEFAULT_PIPEOFFSETS, 217 CURSOR_OFFSETS, 218 }; 219 220 static const struct intel_device_info intel_sandybridge_m_info = { 221 .gen = 6, .is_mobile = 1, .num_pipes = 2, 222 .need_gfx_hws = 1, .has_hotplug = 1, 223 .has_fbc = 1, 224 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 225 .has_llc = 1, 226 GEN_DEFAULT_PIPEOFFSETS, 227 CURSOR_OFFSETS, 228 }; 229 230 #define GEN7_FEATURES \ 231 .gen = 7, .num_pipes = 3, \ 232 .need_gfx_hws = 1, .has_hotplug = 1, \ 233 .has_fbc = 1, \ 234 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 235 .has_llc = 1, \ 236 GEN_DEFAULT_PIPEOFFSETS, \ 237 IVB_CURSOR_OFFSETS 238 239 static const struct intel_device_info intel_ivybridge_d_info = { 240 GEN7_FEATURES, 241 .is_ivybridge = 1, 242 }; 243 244 static const struct intel_device_info intel_ivybridge_m_info = { 245 GEN7_FEATURES, 246 .is_ivybridge = 1, 247 .is_mobile = 1, 248 }; 249 250 static const struct intel_device_info intel_ivybridge_q_info = { 251 GEN7_FEATURES, 252 .is_ivybridge = 1, 253 .num_pipes = 0, /* legal, last one wins */ 254 }; 255 256 #define VLV_FEATURES \ 257 .gen = 7, .num_pipes = 2, \ 258 .need_gfx_hws = 1, .has_hotplug = 1, \ 259 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 260 .display_mmio_offset = VLV_DISPLAY_BASE, \ 261 GEN_DEFAULT_PIPEOFFSETS, \ 262 CURSOR_OFFSETS 263 264 static const struct intel_device_info intel_valleyview_m_info = { 265 VLV_FEATURES, 266 .is_valleyview = 1, 267 .is_mobile = 1, 268 }; 269 270 static const struct intel_device_info intel_valleyview_d_info = { 271 VLV_FEATURES, 272 .is_valleyview = 1, 273 }; 274 275 #define HSW_FEATURES \ 276 GEN7_FEATURES, \ 277 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \ 278 .has_ddi = 1, \ 279 .has_fpga_dbg = 1 280 281 static const struct intel_device_info intel_haswell_d_info = { 282 HSW_FEATURES, 283 .is_haswell = 1, 284 }; 285 286 static const struct intel_device_info intel_haswell_m_info = { 287 HSW_FEATURES, 288 .is_haswell = 1, 289 .is_mobile = 1, 290 }; 291 292 #define BDW_FEATURES \ 293 HSW_FEATURES, \ 294 BDW_COLORS 295 296 static const struct intel_device_info intel_broadwell_d_info = { 297 BDW_FEATURES, 298 .gen = 8, 299 }; 300 301 static const struct intel_device_info intel_broadwell_m_info = { 302 BDW_FEATURES, 303 .gen = 8, .is_mobile = 1, 304 }; 305 306 static const struct intel_device_info intel_broadwell_gt3d_info = { 307 BDW_FEATURES, 308 .gen = 8, 309 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 310 }; 311 312 static const struct intel_device_info intel_broadwell_gt3m_info = { 313 BDW_FEATURES, 314 .gen = 8, .is_mobile = 1, 315 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 316 }; 317 318 static const struct intel_device_info intel_cherryview_info = { 319 .gen = 8, .num_pipes = 3, 320 .need_gfx_hws = 1, .has_hotplug = 1, 321 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 322 .is_cherryview = 1, 323 .display_mmio_offset = VLV_DISPLAY_BASE, 324 GEN_CHV_PIPEOFFSETS, 325 CURSOR_OFFSETS, 326 CHV_COLORS, 327 }; 328 329 static const struct intel_device_info intel_skylake_info = { 330 BDW_FEATURES, 331 .is_skylake = 1, 332 .gen = 9, 333 }; 334 335 static const struct intel_device_info intel_skylake_gt3_info = { 336 BDW_FEATURES, 337 .is_skylake = 1, 338 .gen = 9, 339 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 340 }; 341 342 static const struct intel_device_info intel_broxton_info = { 343 .is_preliminary = 1, 344 .is_broxton = 1, 345 .gen = 9, 346 .need_gfx_hws = 1, .has_hotplug = 1, 347 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 348 .num_pipes = 3, 349 .has_ddi = 1, 350 .has_fpga_dbg = 1, 351 .has_fbc = 1, 352 GEN_DEFAULT_PIPEOFFSETS, 353 IVB_CURSOR_OFFSETS, 354 BDW_COLORS, 355 }; 356 357 static const struct intel_device_info intel_kabylake_info = { 358 BDW_FEATURES, 359 .is_kabylake = 1, 360 .gen = 9, 361 }; 362 363 static const struct intel_device_info intel_kabylake_gt2_info = { 364 BDW_FEATURES, 365 .is_kabylake = 1, 366 .gen = 9, 367 }; 368 369 static const struct intel_device_info intel_kabylake_gt3_info = { 370 BDW_FEATURES, 371 .is_kabylake = 1, 372 .gen = 9, 373 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 374 }; 375 376 static const struct intel_device_info intel_coffeelake_gt1_info = { 377 BDW_FEATURES, \ 378 .is_kabylake = 1, 379 .gen = 9, 380 }; 381 382 static const struct intel_device_info intel_coffeelake_gt2_info = { 383 BDW_FEATURES, \ 384 .is_kabylake = 1, 385 .gen = 9, 386 }; 387 388 static const struct intel_device_info intel_coffeelake_gt3_info = { 389 BDW_FEATURES, \ 390 .is_kabylake = 1, 391 .gen = 9, 392 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 393 }; 394 395 /* 396 * Make sure any device matches here are from most specific to most 397 * general. For example, since the Quanta match is based on the subsystem 398 * and subvendor IDs, we need it to come before the more general IVB 399 * PCI ID matches, otherwise we'll use the wrong info struct above. 400 */ 401 402 static const struct pci_device_id pciidlist[] = { 403 INTEL_I830_IDS(&intel_i830_info), 404 INTEL_I845G_IDS(&intel_845g_info), 405 INTEL_I85X_IDS(&intel_i85x_info), 406 INTEL_I865G_IDS(&intel_i865g_info), 407 INTEL_I915G_IDS(&intel_i915g_info), 408 INTEL_I915GM_IDS(&intel_i915gm_info), 409 INTEL_I945G_IDS(&intel_i945g_info), 410 INTEL_I945GM_IDS(&intel_i945gm_info), 411 INTEL_I965G_IDS(&intel_i965g_info), 412 INTEL_G33_IDS(&intel_g33_info), 413 INTEL_I965GM_IDS(&intel_i965gm_info), 414 INTEL_GM45_IDS(&intel_gm45_info), 415 INTEL_G45_IDS(&intel_g45_info), 416 INTEL_PINEVIEW_IDS(&intel_pineview_info), 417 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), 418 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), 419 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), 420 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), 421 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 422 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 423 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 424 INTEL_HSW_D_IDS(&intel_haswell_d_info), 425 INTEL_HSW_M_IDS(&intel_haswell_m_info), 426 INTEL_VLV_M_IDS(&intel_valleyview_m_info), 427 INTEL_VLV_D_IDS(&intel_valleyview_d_info), 428 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), 429 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), 430 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), 431 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), 432 INTEL_CHV_IDS(&intel_cherryview_info), 433 INTEL_SKL_GT1_IDS(&intel_skylake_info), 434 INTEL_SKL_GT2_IDS(&intel_skylake_info), 435 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), 436 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info), 437 INTEL_BXT_IDS(&intel_broxton_info), 438 INTEL_KBL_GT1_IDS(&intel_kabylake_info), 439 INTEL_KBL_GT2_IDS(&intel_kabylake_info), 440 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info), 441 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info), 442 INTEL_AML_GT2_IDS(&intel_kabylake_gt2_info), 443 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info), 444 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info), 445 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info), 446 INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info), 447 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info), 448 INTEL_WHL_U_GT1_IDS(&intel_coffeelake_gt1_info), 449 INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info), 450 INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info), 451 {0, 0, 0} 452 }; 453 454 #define PCI_VENDOR_INTEL 0x8086 455 456 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev) 457 { 458 enum intel_pch ret = PCH_NOP; 459 460 /* 461 * In a virtualized passthrough environment we can be in a 462 * setup where the ISA bridge is not able to be passed through. 463 * In this case, a south bridge can be emulated and we have to 464 * make an educated guess as to which PCH is really there. 465 */ 466 467 if (IS_GEN5(dev)) { 468 ret = PCH_IBX; 469 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n"); 470 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { 471 ret = PCH_CPT; 472 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n"); 473 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 474 ret = PCH_LPT; 475 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n"); 476 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 477 ret = PCH_SPT; 478 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n"); 479 } 480 481 return ret; 482 } 483 484 void intel_detect_pch(struct drm_device *dev) 485 { 486 struct drm_i915_private *dev_priv = dev->dev_private; 487 device_t pch = NULL; 488 struct pci_devinfo *di; 489 490 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting 491 * (which really amounts to a PCH but no South Display). 492 */ 493 if (INTEL_INFO(dev)->num_pipes == 0) { 494 dev_priv->pch_type = PCH_NOP; 495 return; 496 } 497 498 /* XXX The ISA bridge probe causes some old Core2 machines to hang */ 499 if (INTEL_INFO(dev)->gen < 5) 500 return; 501 502 /* 503 * The reason to probe ISA bridge instead of Dev31:Fun0 is to 504 * make graphics device passthrough work easy for VMM, that only 505 * need to expose ISA bridge to let driver know the real hardware 506 * underneath. This is a requirement from virtualization team. 507 * 508 * In some virtualized environments (e.g. XEN), there is irrelevant 509 * ISA bridge in the system. To work reliably, we should scan trhough 510 * all the ISA bridge devices and check for the first match, instead 511 * of only checking the first one. 512 */ 513 di = NULL; 514 515 while ((pch = pci_iterate_class(&di, PCIC_BRIDGE, PCIS_BRIDGE_ISA))) { 516 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) { 517 unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK; 518 dev_priv->pch_id = id; 519 520 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { 521 dev_priv->pch_type = PCH_IBX; 522 DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); 523 WARN_ON(!IS_GEN5(dev)); 524 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { 525 dev_priv->pch_type = PCH_CPT; 526 DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 527 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 528 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { 529 /* PantherPoint is CPT compatible */ 530 dev_priv->pch_type = PCH_CPT; 531 DRM_DEBUG_KMS("Found PantherPoint PCH\n"); 532 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 533 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 534 dev_priv->pch_type = PCH_LPT; 535 DRM_DEBUG_KMS("Found LynxPoint PCH\n"); 536 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); 537 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); 538 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 539 dev_priv->pch_type = PCH_LPT; 540 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); 541 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); 542 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); 543 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { 544 dev_priv->pch_type = PCH_SPT; 545 DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); 546 WARN_ON(!IS_SKYLAKE(dev) && 547 !IS_KABYLAKE(dev)); 548 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { 549 dev_priv->pch_type = PCH_SPT; 550 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); 551 WARN_ON(!IS_SKYLAKE(dev) && 552 !IS_KABYLAKE(dev)); 553 } else if (id == INTEL_PCH_KBP_DEVICE_ID_TYPE) { 554 dev_priv->pch_type = PCH_KBP; 555 DRM_DEBUG_KMS("Found KabyPoint PCH\n"); 556 WARN_ON(!IS_KABYLAKE(dev)); 557 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) || 558 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) || 559 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) && 560 1)) { 561 dev_priv->pch_type = intel_virt_detect_pch(dev); 562 } else 563 continue; 564 565 break; 566 } 567 } 568 if (!pch) 569 DRM_DEBUG_KMS("No PCH found.\n"); 570 571 #if 0 572 pci_dev_put(pch); 573 #endif 574 } 575 576 bool i915_semaphore_is_enabled(struct drm_device *dev) 577 { 578 if (INTEL_INFO(dev)->gen < 6) 579 return false; 580 581 if (i915.semaphores >= 0) 582 return i915.semaphores; 583 584 /* TODO: make semaphores and Execlists play nicely together */ 585 if (i915.enable_execlists) 586 return false; 587 588 /* Until we get further testing... */ 589 if (IS_GEN8(dev)) 590 return false; 591 592 #ifdef CONFIG_INTEL_IOMMU 593 /* Enable semaphores on SNB when IO remapping is off */ 594 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) 595 return false; 596 #endif 597 598 return true; 599 } 600 601 #ifdef __DragonFly__ 602 #define IS_BUILTIN(blah) 0 603 #endif 604 605 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 606 { 607 struct drm_device *dev = dev_priv->dev; 608 struct intel_encoder *encoder; 609 610 drm_modeset_lock_all(dev); 611 for_each_intel_encoder(dev, encoder) 612 if (encoder->suspend) 613 encoder->suspend(encoder); 614 drm_modeset_unlock_all(dev); 615 } 616 617 static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 618 bool rpm_resume); 619 static int vlv_suspend_complete(struct drm_i915_private *dev_priv); 620 621 static bool suspend_to_idle(struct drm_i915_private *dev_priv) 622 { 623 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 624 if (acpi_target_system_state() < ACPI_STATE_S3) 625 return true; 626 #endif 627 return false; 628 } 629 630 static int i915_drm_suspend(struct drm_device *dev) 631 { 632 struct drm_i915_private *dev_priv = dev->dev_private; 633 pci_power_t opregion_target_state; 634 int error; 635 636 /* ignore lid events during suspend */ 637 mutex_lock(&dev_priv->modeset_restore_lock); 638 dev_priv->modeset_restore = MODESET_SUSPENDED; 639 mutex_unlock(&dev_priv->modeset_restore_lock); 640 641 disable_rpm_wakeref_asserts(dev_priv); 642 643 /* We do a lot of poking in a lot of registers, make sure they work 644 * properly. */ 645 intel_display_set_init_power(dev_priv, true); 646 647 drm_kms_helper_poll_disable(dev); 648 649 #if 0 650 pci_save_state(dev->pdev); 651 #endif 652 653 error = i915_gem_suspend(dev); 654 if (error) { 655 dev_err(dev->dev, 656 "GEM idle failed, resume might fail\n"); 657 goto out; 658 } 659 660 intel_guc_suspend(dev); 661 662 intel_suspend_gt_powersave(dev); 663 664 intel_display_suspend(dev); 665 666 #if 0 667 intel_dp_mst_suspend(dev); 668 #endif 669 670 intel_runtime_pm_disable_interrupts(dev_priv); 671 intel_hpd_cancel_work(dev_priv); 672 673 intel_suspend_encoders(dev_priv); 674 675 intel_suspend_hw(dev); 676 677 i915_gem_suspend_gtt_mappings(dev); 678 679 i915_save_state(dev); 680 681 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; 682 intel_opregion_notify_adapter(dev, opregion_target_state); 683 684 intel_uncore_forcewake_reset(dev, false); 685 intel_opregion_fini(dev); 686 687 #if 0 688 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 689 #endif 690 691 dev_priv->suspend_count++; 692 693 intel_display_set_init_power(dev_priv, false); 694 695 intel_csr_ucode_suspend(dev_priv); 696 697 out: 698 enable_rpm_wakeref_asserts(dev_priv); 699 700 return error; 701 } 702 703 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) 704 { 705 struct drm_i915_private *dev_priv = drm_dev->dev_private; 706 bool fw_csr; 707 int ret; 708 709 disable_rpm_wakeref_asserts(dev_priv); 710 711 fw_csr = !IS_BROXTON(dev_priv) && 712 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload; 713 /* 714 * In case of firmware assisted context save/restore don't manually 715 * deinit the power domains. This also means the CSR/DMC firmware will 716 * stay active, it will power down any HW resources as required and 717 * also enable deeper system power states that would be blocked if the 718 * firmware was inactive. 719 */ 720 if (!fw_csr) 721 intel_power_domains_suspend(dev_priv); 722 723 ret = 0; 724 if (IS_BROXTON(dev_priv)) 725 bxt_enable_dc9(dev_priv); 726 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 727 hsw_enable_pc8(dev_priv); 728 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 729 ret = vlv_suspend_complete(dev_priv); 730 731 if (ret) { 732 DRM_ERROR("Suspend complete failed: %d\n", ret); 733 if (!fw_csr) 734 intel_power_domains_init_hw(dev_priv, true); 735 736 goto out; 737 } 738 739 #if 0 740 pci_disable_device(drm_dev->pdev); 741 /* 742 * During hibernation on some platforms the BIOS may try to access 743 * the device even though it's already in D3 and hang the machine. So 744 * leave the device in D0 on those platforms and hope the BIOS will 745 * power down the device properly. The issue was seen on multiple old 746 * GENs with different BIOS vendors, so having an explicit blacklist 747 * is inpractical; apply the workaround on everything pre GEN6. The 748 * platforms where the issue was seen: 749 * Lenovo Thinkpad X301, X61s, X60, T60, X41 750 * Fujitsu FSC S7110 751 * Acer Aspire 1830T 752 */ 753 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) 754 pci_set_power_state(drm_dev->pdev, PCI_D3hot); 755 #endif 756 757 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv); 758 759 out: 760 enable_rpm_wakeref_asserts(dev_priv); 761 762 return ret; 763 } 764 765 int i915_suspend_switcheroo(device_t kdev) 766 { 767 struct drm_device *dev = device_get_softc(kdev); 768 int error; 769 770 if (!dev || !dev->dev_private) { 771 DRM_ERROR("dev: %p\n", dev); 772 DRM_ERROR("DRM not initialized, aborting suspend.\n"); 773 return -ENODEV; 774 } 775 776 #if 0 777 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && 778 state.event != PM_EVENT_FREEZE)) 779 return -EINVAL; 780 #endif 781 782 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 783 return 0; 784 785 error = i915_drm_suspend(dev); 786 if (error) 787 return error; 788 789 return i915_drm_suspend_late(dev, false); 790 } 791 792 static int i915_drm_resume(struct drm_device *dev) 793 { 794 struct drm_i915_private *dev_priv = dev->dev_private; 795 int ret; 796 797 disable_rpm_wakeref_asserts(dev_priv); 798 799 ret = i915_ggtt_enable_hw(dev); 800 if (ret) 801 DRM_ERROR("failed to re-enable GGTT\n"); 802 803 intel_csr_ucode_resume(dev_priv); 804 805 mutex_lock(&dev->struct_mutex); 806 i915_gem_restore_gtt_mappings(dev); 807 mutex_unlock(&dev->struct_mutex); 808 809 i915_restore_state(dev); 810 intel_opregion_setup(dev); 811 812 intel_init_pch_refclk(dev); 813 drm_mode_config_reset(dev); 814 815 /* 816 * Interrupts have to be enabled before any batches are run. If not the 817 * GPU will hang. i915_gem_init_hw() will initiate batches to 818 * update/restore the context. 819 * 820 * Modeset enabling in intel_modeset_init_hw() also needs working 821 * interrupts. 822 */ 823 intel_runtime_pm_enable_interrupts(dev_priv); 824 825 mutex_lock(&dev->struct_mutex); 826 if (i915_gem_init_hw(dev)) { 827 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); 828 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); 829 } 830 mutex_unlock(&dev->struct_mutex); 831 832 intel_guc_resume(dev); 833 834 intel_modeset_init_hw(dev); 835 836 spin_lock_irq(&dev_priv->irq_lock); 837 if (dev_priv->display.hpd_irq_setup) 838 dev_priv->display.hpd_irq_setup(dev); 839 spin_unlock_irq(&dev_priv->irq_lock); 840 841 intel_dp_mst_resume(dev); 842 843 intel_display_resume(dev); 844 845 /* 846 * ... but also need to make sure that hotplug processing 847 * doesn't cause havoc. Like in the driver load code we don't 848 * bother with the tiny race here where we might loose hotplug 849 * notifications. 850 * */ 851 intel_hpd_init(dev_priv); 852 /* Config may have changed between suspend and resume */ 853 drm_helper_hpd_irq_event(dev); 854 855 intel_opregion_init(dev); 856 857 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 858 859 mutex_lock(&dev_priv->modeset_restore_lock); 860 dev_priv->modeset_restore = MODESET_DONE; 861 mutex_unlock(&dev_priv->modeset_restore_lock); 862 863 #if 0 864 intel_opregion_notify_adapter(dev, PCI_D0); 865 #endif 866 867 drm_kms_helper_poll_enable(dev); 868 869 enable_rpm_wakeref_asserts(dev_priv); 870 871 return 0; 872 } 873 874 static int i915_drm_resume_early(struct drm_device *dev) 875 { 876 struct drm_i915_private *dev_priv = dev->dev_private; 877 int ret = 0; 878 879 /* 880 * We have a resume ordering issue with the snd-hda driver also 881 * requiring our device to be power up. Due to the lack of a 882 * parent/child relationship we currently solve this with an early 883 * resume hook. 884 * 885 * FIXME: This should be solved with a special hdmi sink device or 886 * similar so that power domains can be employed. 887 */ 888 889 /* 890 * Note that we need to set the power state explicitly, since we 891 * powered off the device during freeze and the PCI core won't power 892 * it back up for us during thaw. Powering off the device during 893 * freeze is not a hard requirement though, and during the 894 * suspend/resume phases the PCI core makes sure we get here with the 895 * device powered on. So in case we change our freeze logic and keep 896 * the device powered we can also remove the following set power state 897 * call. 898 */ 899 #if 0 900 ret = pci_set_power_state(dev->pdev, PCI_D0); 901 if (ret) { 902 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret); 903 goto out; 904 } 905 906 /* 907 * Note that pci_enable_device() first enables any parent bridge 908 * device and only then sets the power state for this device. The 909 * bridge enabling is a nop though, since bridge devices are resumed 910 * first. The order of enabling power and enabling the device is 911 * imposed by the PCI core as described above, so here we preserve the 912 * same order for the freeze/thaw phases. 913 * 914 * TODO: eventually we should remove pci_disable_device() / 915 * pci_enable_enable_device() from suspend/resume. Due to how they 916 * depend on the device enable refcount we can't anyway depend on them 917 * disabling/enabling the device. 918 */ 919 if (pci_enable_device(dev->pdev)) { 920 ret = -EIO; 921 goto out; 922 } 923 924 pci_set_master(dev->pdev); 925 #endif 926 927 disable_rpm_wakeref_asserts(dev_priv); 928 929 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 930 ret = vlv_resume_prepare(dev_priv, false); 931 if (ret) 932 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", 933 ret); 934 935 intel_uncore_early_sanitize(dev, true); 936 937 if (IS_BROXTON(dev)) { 938 if (!dev_priv->suspended_to_idle) 939 gen9_sanitize_dc_state(dev_priv); 940 bxt_disable_dc9(dev_priv); 941 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 942 hsw_disable_pc8(dev_priv); 943 } 944 945 intel_uncore_sanitize(dev); 946 947 if (IS_BROXTON(dev_priv) || 948 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload)) 949 intel_power_domains_init_hw(dev_priv, true); 950 951 enable_rpm_wakeref_asserts(dev_priv); 952 953 #if 0 954 out: 955 #endif 956 dev_priv->suspended_to_idle = false; 957 958 return ret; 959 } 960 961 int i915_resume_switcheroo(struct drm_device *dev) 962 { 963 int ret; 964 965 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 966 return 0; 967 968 ret = i915_drm_resume_early(dev); 969 if (ret) 970 return ret; 971 972 return i915_drm_resume(dev); 973 } 974 975 /* XXX Hack for the old *BSD drm code base 976 * The device id field is set at probe time */ 977 static drm_pci_id_list_t i915_attach_list[] = { 978 {0x8086, 0, 0, "Intel i915 GPU"}, 979 {0, 0, 0, NULL} 980 }; 981 982 struct intel_device_info * 983 i915_get_device_id(int device) 984 { 985 const struct pci_device_id *did; 986 987 for (did = &pciidlist[0]; did->device != 0; did++) { 988 if (did->device != device) 989 continue; 990 return (struct intel_device_info *)did->driver_data; 991 } 992 return (NULL); 993 } 994 995 static int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 996 struct sysctl_oid *top) 997 { 998 return drm_add_busid_modesetting(dev, ctx, top); 999 } 1000 1001 extern devclass_t drm_devclass; 1002 1003 /** 1004 * i915_reset - reset chip after a hang 1005 * @dev: drm device to reset 1006 * 1007 * Reset the chip. Useful if a hang is detected. Returns zero on successful 1008 * reset or otherwise an error code. 1009 * 1010 * Procedure is fairly simple: 1011 * - reset the chip using the reset reg 1012 * - re-init context state 1013 * - re-init hardware status page 1014 * - re-init ring buffer 1015 * - re-init interrupt state 1016 * - re-init display 1017 */ 1018 int i915_reset(struct drm_device *dev) 1019 { 1020 struct drm_i915_private *dev_priv = dev->dev_private; 1021 struct i915_gpu_error *error = &dev_priv->gpu_error; 1022 unsigned reset_counter; 1023 int ret; 1024 1025 intel_reset_gt_powersave(dev); 1026 1027 mutex_lock(&dev->struct_mutex); 1028 1029 /* Clear any previous failed attempts at recovery. Time to try again. */ 1030 atomic_andnot(I915_WEDGED, &error->reset_counter); 1031 1032 /* Clear the reset-in-progress flag and increment the reset epoch. */ 1033 reset_counter = atomic_inc_return(&error->reset_counter); 1034 if (WARN_ON(__i915_reset_in_progress(reset_counter))) { 1035 ret = -EIO; 1036 goto error; 1037 } 1038 1039 i915_gem_reset(dev); 1040 1041 ret = intel_gpu_reset(dev, ALL_ENGINES); 1042 1043 /* Also reset the gpu hangman. */ 1044 if (error->stop_rings != 0) { 1045 DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); 1046 error->stop_rings = 0; 1047 if (ret == -ENODEV) { 1048 DRM_INFO("Reset not implemented, but ignoring " 1049 "error for simulated gpu hangs\n"); 1050 ret = 0; 1051 } 1052 } 1053 1054 if (i915_stop_ring_allow_warn(dev_priv)) 1055 pr_notice("drm/i915: Resetting chip after gpu hang\n"); 1056 1057 if (ret) { 1058 if (ret != -ENODEV) 1059 DRM_ERROR("Failed to reset chip: %i\n", ret); 1060 else 1061 DRM_DEBUG_DRIVER("GPU reset disabled\n"); 1062 goto error; 1063 } 1064 1065 intel_overlay_reset(dev_priv); 1066 1067 /* Ok, now get things going again... */ 1068 1069 /* 1070 * Everything depends on having the GTT running, so we need to start 1071 * there. Fortunately we don't need to do this unless we reset the 1072 * chip at a PCI level. 1073 * 1074 * Next we need to restore the context, but we don't use those 1075 * yet either... 1076 * 1077 * Ring buffer needs to be re-initialized in the KMS case, or if X 1078 * was running at the time of the reset (i.e. we weren't VT 1079 * switched away). 1080 */ 1081 ret = i915_gem_init_hw(dev); 1082 if (ret) { 1083 DRM_ERROR("Failed hw init on reset %d\n", ret); 1084 goto error; 1085 } 1086 1087 mutex_unlock(&dev->struct_mutex); 1088 1089 /* 1090 * rps/rc6 re-init is necessary to restore state lost after the 1091 * reset and the re-install of gt irqs. Skip for ironlake per 1092 * previous concerns that it doesn't respond well to some forms 1093 * of re-init after reset. 1094 */ 1095 if (INTEL_INFO(dev)->gen > 5) 1096 intel_enable_gt_powersave(dev); 1097 1098 return 0; 1099 1100 error: 1101 atomic_or(I915_WEDGED, &error->reset_counter); 1102 mutex_unlock(&dev->struct_mutex); 1103 return ret; 1104 } 1105 1106 static int i915_pci_probe(device_t kdev) 1107 { 1108 int device, i = 0; 1109 1110 if (pci_get_class(kdev) != PCIC_DISPLAY) 1111 return ENXIO; 1112 1113 if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL) 1114 return ENXIO; 1115 1116 device = pci_get_device(kdev); 1117 1118 for (i = 0; pciidlist[i].device != 0; i++) { 1119 if (pciidlist[i].device == device) { 1120 i915_attach_list[0].device = device; 1121 return 0; 1122 } 1123 } 1124 1125 return ENXIO; 1126 } 1127 1128 #if 0 1129 static void 1130 i915_pci_remove(struct pci_dev *pdev) 1131 { 1132 struct drm_device *dev = pci_get_drvdata(pdev); 1133 1134 drm_put_dev(dev); 1135 } 1136 1137 static int i915_pm_suspend(struct device *dev) 1138 { 1139 struct pci_dev *pdev = to_pci_dev(dev); 1140 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1141 1142 if (!drm_dev || !drm_dev->dev_private) { 1143 dev_err(dev, "DRM not initialized, aborting suspend.\n"); 1144 return -ENODEV; 1145 } 1146 1147 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1148 return 0; 1149 1150 return i915_drm_suspend(drm_dev); 1151 } 1152 1153 static int i915_pm_suspend_late(struct device *dev) 1154 { 1155 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1156 1157 /* 1158 * We have a suspend ordering issue with the snd-hda driver also 1159 * requiring our device to be power up. Due to the lack of a 1160 * parent/child relationship we currently solve this with an late 1161 * suspend hook. 1162 * 1163 * FIXME: This should be solved with a special hdmi sink device or 1164 * similar so that power domains can be employed. 1165 */ 1166 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1167 return 0; 1168 1169 return i915_drm_suspend_late(drm_dev, false); 1170 } 1171 1172 static int i915_pm_poweroff_late(struct device *dev) 1173 { 1174 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1175 1176 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1177 return 0; 1178 1179 return i915_drm_suspend_late(drm_dev, true); 1180 } 1181 1182 static int i915_pm_resume_early(struct device *dev) 1183 { 1184 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1185 1186 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1187 return 0; 1188 1189 return i915_drm_resume_early(drm_dev); 1190 } 1191 1192 static int i915_pm_resume(struct device *dev) 1193 { 1194 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1195 1196 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1197 return 0; 1198 1199 return i915_drm_resume(drm_dev); 1200 } 1201 #endif 1202 1203 /* 1204 * Save all Gunit registers that may be lost after a D3 and a subsequent 1205 * S0i[R123] transition. The list of registers needing a save/restore is 1206 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit 1207 * registers in the following way: 1208 * - Driver: saved/restored by the driver 1209 * - Punit : saved/restored by the Punit firmware 1210 * - No, w/o marking: no need to save/restore, since the register is R/O or 1211 * used internally by the HW in a way that doesn't depend 1212 * keeping the content across a suspend/resume. 1213 * - Debug : used for debugging 1214 * 1215 * We save/restore all registers marked with 'Driver', with the following 1216 * exceptions: 1217 * - Registers out of use, including also registers marked with 'Debug'. 1218 * These have no effect on the driver's operation, so we don't save/restore 1219 * them to reduce the overhead. 1220 * - Registers that are fully setup by an initialization function called from 1221 * the resume path. For example many clock gating and RPS/RC6 registers. 1222 * - Registers that provide the right functionality with their reset defaults. 1223 * 1224 * TODO: Except for registers that based on the above 3 criteria can be safely 1225 * ignored, we save/restore all others, practically treating the HW context as 1226 * a black-box for the driver. Further investigation is needed to reduce the 1227 * saved/restored registers even further, by following the same 3 criteria. 1228 */ 1229 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1230 { 1231 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1232 int i; 1233 1234 /* GAM 0x4000-0x4770 */ 1235 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); 1236 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); 1237 s->arb_mode = I915_READ(ARB_MODE); 1238 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); 1239 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); 1240 1241 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1242 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); 1243 1244 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); 1245 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); 1246 1247 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); 1248 s->ecochk = I915_READ(GAM_ECOCHK); 1249 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); 1250 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); 1251 1252 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); 1253 1254 /* MBC 0x9024-0x91D0, 0x8500 */ 1255 s->g3dctl = I915_READ(VLV_G3DCTL); 1256 s->gsckgctl = I915_READ(VLV_GSCKGCTL); 1257 s->mbctl = I915_READ(GEN6_MBCTL); 1258 1259 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1260 s->ucgctl1 = I915_READ(GEN6_UCGCTL1); 1261 s->ucgctl3 = I915_READ(GEN6_UCGCTL3); 1262 s->rcgctl1 = I915_READ(GEN6_RCGCTL1); 1263 s->rcgctl2 = I915_READ(GEN6_RCGCTL2); 1264 s->rstctl = I915_READ(GEN6_RSTCTL); 1265 s->misccpctl = I915_READ(GEN7_MISCCPCTL); 1266 1267 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1268 s->gfxpause = I915_READ(GEN6_GFXPAUSE); 1269 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); 1270 s->rpdeuc = I915_READ(GEN6_RPDEUC); 1271 s->ecobus = I915_READ(ECOBUS); 1272 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); 1273 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); 1274 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); 1275 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); 1276 s->rcedata = I915_READ(VLV_RCEDATA); 1277 s->spare2gh = I915_READ(VLV_SPAREG2H); 1278 1279 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1280 s->gt_imr = I915_READ(GTIMR); 1281 s->gt_ier = I915_READ(GTIER); 1282 s->pm_imr = I915_READ(GEN6_PMIMR); 1283 s->pm_ier = I915_READ(GEN6_PMIER); 1284 1285 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1286 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i)); 1287 1288 /* GT SA CZ domain, 0x100000-0x138124 */ 1289 s->tilectl = I915_READ(TILECTL); 1290 s->gt_fifoctl = I915_READ(GTFIFOCTL); 1291 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); 1292 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1293 s->pmwgicz = I915_READ(VLV_PMWGICZ); 1294 1295 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1296 s->gu_ctl0 = I915_READ(VLV_GU_CTL0); 1297 s->gu_ctl1 = I915_READ(VLV_GU_CTL1); 1298 s->pcbr = I915_READ(VLV_PCBR); 1299 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); 1300 1301 /* 1302 * Not saving any of: 1303 * DFT, 0x9800-0x9EC0 1304 * SARB, 0xB000-0xB1FC 1305 * GAC, 0x5208-0x524C, 0x14000-0x14C000 1306 * PCI CFG 1307 */ 1308 } 1309 1310 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1311 { 1312 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1313 u32 val; 1314 int i; 1315 1316 /* GAM 0x4000-0x4770 */ 1317 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); 1318 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); 1319 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); 1320 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); 1321 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); 1322 1323 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1324 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]); 1325 1326 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); 1327 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); 1328 1329 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); 1330 I915_WRITE(GAM_ECOCHK, s->ecochk); 1331 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); 1332 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); 1333 1334 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); 1335 1336 /* MBC 0x9024-0x91D0, 0x8500 */ 1337 I915_WRITE(VLV_G3DCTL, s->g3dctl); 1338 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); 1339 I915_WRITE(GEN6_MBCTL, s->mbctl); 1340 1341 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1342 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); 1343 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); 1344 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); 1345 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); 1346 I915_WRITE(GEN6_RSTCTL, s->rstctl); 1347 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); 1348 1349 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1350 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); 1351 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); 1352 I915_WRITE(GEN6_RPDEUC, s->rpdeuc); 1353 I915_WRITE(ECOBUS, s->ecobus); 1354 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); 1355 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); 1356 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); 1357 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); 1358 I915_WRITE(VLV_RCEDATA, s->rcedata); 1359 I915_WRITE(VLV_SPAREG2H, s->spare2gh); 1360 1361 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1362 I915_WRITE(GTIMR, s->gt_imr); 1363 I915_WRITE(GTIER, s->gt_ier); 1364 I915_WRITE(GEN6_PMIMR, s->pm_imr); 1365 I915_WRITE(GEN6_PMIER, s->pm_ier); 1366 1367 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1368 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]); 1369 1370 /* GT SA CZ domain, 0x100000-0x138124 */ 1371 I915_WRITE(TILECTL, s->tilectl); 1372 I915_WRITE(GTFIFOCTL, s->gt_fifoctl); 1373 /* 1374 * Preserve the GT allow wake and GFX force clock bit, they are not 1375 * be restored, as they are used to control the s0ix suspend/resume 1376 * sequence by the caller. 1377 */ 1378 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1379 val &= VLV_GTLC_ALLOWWAKEREQ; 1380 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; 1381 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1382 1383 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1384 val &= VLV_GFX_CLK_FORCE_ON_BIT; 1385 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; 1386 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1387 1388 I915_WRITE(VLV_PMWGICZ, s->pmwgicz); 1389 1390 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1391 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); 1392 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); 1393 I915_WRITE(VLV_PCBR, s->pcbr); 1394 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); 1395 } 1396 1397 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) 1398 { 1399 u32 val; 1400 int err; 1401 1402 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) 1403 1404 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1405 val &= ~VLV_GFX_CLK_FORCE_ON_BIT; 1406 if (force_on) 1407 val |= VLV_GFX_CLK_FORCE_ON_BIT; 1408 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1409 1410 if (!force_on) 1411 return 0; 1412 1413 err = wait_for(COND, 20); 1414 if (err) 1415 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", 1416 I915_READ(VLV_GTLC_SURVIVABILITY_REG)); 1417 1418 return err; 1419 #undef COND 1420 } 1421 1422 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) 1423 { 1424 u32 val; 1425 int err = 0; 1426 1427 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1428 val &= ~VLV_GTLC_ALLOWWAKEREQ; 1429 if (allow) 1430 val |= VLV_GTLC_ALLOWWAKEREQ; 1431 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1432 POSTING_READ(VLV_GTLC_WAKE_CTRL); 1433 1434 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ 1435 allow) 1436 err = wait_for(COND, 1); 1437 if (err) 1438 DRM_ERROR("timeout disabling GT waking\n"); 1439 return err; 1440 #undef COND 1441 } 1442 1443 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, 1444 bool wait_for_on) 1445 { 1446 u32 mask; 1447 u32 val; 1448 int err; 1449 1450 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; 1451 val = wait_for_on ? mask : 0; 1452 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) 1453 if (COND) 1454 return 0; 1455 1456 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", 1457 onoff(wait_for_on), 1458 I915_READ(VLV_GTLC_PW_STATUS)); 1459 1460 /* 1461 * RC6 transitioning can be delayed up to 2 msec (see 1462 * valleyview_enable_rps), use 3 msec for safety. 1463 */ 1464 err = wait_for(COND, 3); 1465 if (err) 1466 DRM_ERROR("timeout waiting for GT wells to go %s\n", 1467 onoff(wait_for_on)); 1468 1469 return err; 1470 #undef COND 1471 } 1472 1473 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) 1474 { 1475 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) 1476 return; 1477 1478 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n"); 1479 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); 1480 } 1481 1482 static int vlv_suspend_complete(struct drm_i915_private *dev_priv) 1483 { 1484 u32 mask; 1485 int err; 1486 1487 /* 1488 * Bspec defines the following GT well on flags as debug only, so 1489 * don't treat them as hard failures. 1490 */ 1491 (void)vlv_wait_for_gt_wells(dev_priv, false); 1492 1493 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; 1494 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); 1495 1496 vlv_check_no_gt_access(dev_priv); 1497 1498 err = vlv_force_gfx_clock(dev_priv, true); 1499 if (err) 1500 goto err1; 1501 1502 err = vlv_allow_gt_wake(dev_priv, false); 1503 if (err) 1504 goto err2; 1505 1506 if (!IS_CHERRYVIEW(dev_priv)) 1507 vlv_save_gunit_s0ix_state(dev_priv); 1508 1509 err = vlv_force_gfx_clock(dev_priv, false); 1510 if (err) 1511 goto err2; 1512 1513 return 0; 1514 1515 err2: 1516 /* For safety always re-enable waking and disable gfx clock forcing */ 1517 vlv_allow_gt_wake(dev_priv, true); 1518 err1: 1519 vlv_force_gfx_clock(dev_priv, false); 1520 1521 return err; 1522 } 1523 1524 static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 1525 bool rpm_resume) 1526 { 1527 struct drm_device *dev = dev_priv->dev; 1528 int err; 1529 int ret; 1530 1531 /* 1532 * If any of the steps fail just try to continue, that's the best we 1533 * can do at this point. Return the first error code (which will also 1534 * leave RPM permanently disabled). 1535 */ 1536 ret = vlv_force_gfx_clock(dev_priv, true); 1537 1538 if (!IS_CHERRYVIEW(dev_priv)) 1539 vlv_restore_gunit_s0ix_state(dev_priv); 1540 1541 err = vlv_allow_gt_wake(dev_priv, true); 1542 if (!ret) 1543 ret = err; 1544 1545 err = vlv_force_gfx_clock(dev_priv, false); 1546 if (!ret) 1547 ret = err; 1548 1549 vlv_check_no_gt_access(dev_priv); 1550 1551 if (rpm_resume) { 1552 intel_init_clock_gating(dev); 1553 i915_gem_restore_fences(dev); 1554 } 1555 1556 return ret; 1557 } 1558 1559 #if 0 1560 static int intel_runtime_suspend(struct device *device) 1561 { 1562 struct pci_dev *pdev = to_pci_dev(device); 1563 struct drm_device *dev = pci_get_drvdata(pdev); 1564 struct drm_i915_private *dev_priv = dev->dev_private; 1565 int ret; 1566 1567 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) 1568 return -ENODEV; 1569 1570 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) 1571 return -ENODEV; 1572 1573 DRM_DEBUG_KMS("Suspending device\n"); 1574 1575 /* 1576 * We could deadlock here in case another thread holding struct_mutex 1577 * calls RPM suspend concurrently, since the RPM suspend will wait 1578 * first for this RPM suspend to finish. In this case the concurrent 1579 * RPM resume will be followed by its RPM suspend counterpart. Still 1580 * for consistency return -EAGAIN, which will reschedule this suspend. 1581 */ 1582 if (!mutex_trylock(&dev->struct_mutex)) { 1583 DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); 1584 /* 1585 * Bump the expiration timestamp, otherwise the suspend won't 1586 * be rescheduled. 1587 */ 1588 pm_runtime_mark_last_busy(device); 1589 1590 return -EAGAIN; 1591 } 1592 1593 disable_rpm_wakeref_asserts(dev_priv); 1594 1595 /* 1596 * We are safe here against re-faults, since the fault handler takes 1597 * an RPM reference. 1598 */ 1599 i915_gem_release_all_mmaps(dev_priv); 1600 mutex_unlock(&dev->struct_mutex); 1601 1602 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); 1603 1604 intel_guc_suspend(dev); 1605 1606 intel_suspend_gt_powersave(dev); 1607 intel_runtime_pm_disable_interrupts(dev_priv); 1608 1609 ret = 0; 1610 if (IS_BROXTON(dev_priv)) { 1611 bxt_display_core_uninit(dev_priv); 1612 bxt_enable_dc9(dev_priv); 1613 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1614 hsw_enable_pc8(dev_priv); 1615 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1616 ret = vlv_suspend_complete(dev_priv); 1617 } 1618 1619 if (ret) { 1620 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); 1621 intel_runtime_pm_enable_interrupts(dev_priv); 1622 1623 enable_rpm_wakeref_asserts(dev_priv); 1624 1625 return ret; 1626 } 1627 1628 intel_uncore_forcewake_reset(dev, false); 1629 1630 enable_rpm_wakeref_asserts(dev_priv); 1631 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); 1632 1633 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv)) 1634 DRM_ERROR("Unclaimed access detected prior to suspending\n"); 1635 1636 dev_priv->pm.suspended = true; 1637 1638 /* 1639 * FIXME: We really should find a document that references the arguments 1640 * used below! 1641 */ 1642 if (IS_BROADWELL(dev)) { 1643 /* 1644 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1645 * being detected, and the call we do at intel_runtime_resume() 1646 * won't be able to restore them. Since PCI_D3hot matches the 1647 * actual specification and appears to be working, use it. 1648 */ 1649 intel_opregion_notify_adapter(dev, PCI_D3hot); 1650 } else { 1651 /* 1652 * current versions of firmware which depend on this opregion 1653 * notification have repurposed the D1 definition to mean 1654 * "runtime suspended" vs. what you would normally expect (D3) 1655 * to distinguish it from notifications that might be sent via 1656 * the suspend path. 1657 */ 1658 intel_opregion_notify_adapter(dev, PCI_D1); 1659 } 1660 1661 assert_forcewakes_inactive(dev_priv); 1662 1663 if (!IS_VALLEYVIEW(dev_priv) || !IS_CHERRYVIEW(dev_priv)) 1664 intel_hpd_poll_init(dev_priv); 1665 1666 DRM_DEBUG_KMS("Device suspended\n"); 1667 return 0; 1668 } 1669 1670 static int intel_runtime_resume(struct device *device) 1671 { 1672 struct pci_dev *pdev = to_pci_dev(device); 1673 struct drm_device *dev = pci_get_drvdata(pdev); 1674 struct drm_i915_private *dev_priv = dev->dev_private; 1675 int ret = 0; 1676 1677 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) 1678 return -ENODEV; 1679 1680 DRM_DEBUG_KMS("Resuming device\n"); 1681 1682 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count)); 1683 disable_rpm_wakeref_asserts(dev_priv); 1684 1685 intel_opregion_notify_adapter(dev, PCI_D0); 1686 dev_priv->pm.suspended = false; 1687 if (intel_uncore_unclaimed_mmio(dev_priv)) 1688 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); 1689 1690 intel_guc_resume(dev); 1691 1692 if (IS_GEN6(dev_priv)) 1693 intel_init_pch_refclk(dev); 1694 1695 if (IS_BROXTON(dev)) { 1696 bxt_disable_dc9(dev_priv); 1697 bxt_display_core_init(dev_priv, true); 1698 if (dev_priv->csr.dmc_payload && 1699 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)) 1700 gen9_enable_dc5(dev_priv); 1701 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1702 hsw_disable_pc8(dev_priv); 1703 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 1704 ret = vlv_resume_prepare(dev_priv, true); 1705 } 1706 1707 /* 1708 * No point of rolling back things in case of an error, as the best 1709 * we can do is to hope that things will still work (and disable RPM). 1710 */ 1711 i915_gem_init_swizzling(dev); 1712 gen6_update_ring_freq(dev); 1713 1714 intel_runtime_pm_enable_interrupts(dev_priv); 1715 1716 /* 1717 * On VLV/CHV display interrupts are part of the display 1718 * power well, so hpd is reinitialized from there. For 1719 * everyone else do it here. 1720 */ 1721 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) 1722 intel_hpd_init(dev_priv); 1723 1724 intel_enable_gt_powersave(dev); 1725 1726 enable_rpm_wakeref_asserts(dev_priv); 1727 1728 if (ret) 1729 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); 1730 else 1731 DRM_DEBUG_KMS("Device resumed\n"); 1732 1733 return ret; 1734 } 1735 1736 static const struct dev_pm_ops i915_pm_ops = { 1737 /* 1738 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1739 * PMSG_RESUME] 1740 */ 1741 .suspend = i915_pm_suspend, 1742 .suspend_late = i915_pm_suspend_late, 1743 .resume_early = i915_pm_resume_early, 1744 .resume = i915_pm_resume, 1745 1746 /* 1747 * S4 event handlers 1748 * @freeze, @freeze_late : called (1) before creating the 1749 * hibernation image [PMSG_FREEZE] and 1750 * (2) after rebooting, before restoring 1751 * the image [PMSG_QUIESCE] 1752 * @thaw, @thaw_early : called (1) after creating the hibernation 1753 * image, before writing it [PMSG_THAW] 1754 * and (2) after failing to create or 1755 * restore the image [PMSG_RECOVER] 1756 * @poweroff, @poweroff_late: called after writing the hibernation 1757 * image, before rebooting [PMSG_HIBERNATE] 1758 * @restore, @restore_early : called after rebooting and restoring the 1759 * hibernation image [PMSG_RESTORE] 1760 */ 1761 .freeze = i915_pm_suspend, 1762 .freeze_late = i915_pm_suspend_late, 1763 .thaw_early = i915_pm_resume_early, 1764 .thaw = i915_pm_resume, 1765 .poweroff = i915_pm_suspend, 1766 .poweroff_late = i915_pm_poweroff_late, 1767 .restore_early = i915_pm_resume_early, 1768 .restore = i915_pm_resume, 1769 1770 /* S0ix (via runtime suspend) event handlers */ 1771 .runtime_suspend = intel_runtime_suspend, 1772 .runtime_resume = intel_runtime_resume, 1773 }; 1774 1775 static const struct vm_operations_struct i915_gem_vm_ops = { 1776 .fault = i915_gem_fault, 1777 .open = drm_gem_vm_open, 1778 .close = drm_gem_vm_close, 1779 }; 1780 1781 static const struct file_operations i915_driver_fops = { 1782 .owner = THIS_MODULE, 1783 .open = drm_open, 1784 .release = drm_release, 1785 .unlocked_ioctl = drm_ioctl, 1786 .mmap = drm_gem_mmap, 1787 .poll = drm_poll, 1788 .read = drm_read, 1789 #ifdef CONFIG_COMPAT 1790 .compat_ioctl = i915_compat_ioctl, 1791 #endif 1792 .llseek = noop_llseek, 1793 }; 1794 #endif 1795 1796 static struct cdev_pager_ops i915_gem_vm_ops = { 1797 .cdev_pg_fault = i915_gem_fault, 1798 .cdev_pg_ctor = i915_gem_pager_ctor, 1799 .cdev_pg_dtor = i915_gem_pager_dtor 1800 }; 1801 1802 static struct drm_driver driver = { 1803 /* Don't use MTRRs here; the Xserver or userspace app should 1804 * deal with them for Intel hardware. 1805 */ 1806 .driver_features = 1807 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 1808 DRIVER_RENDER | DRIVER_MODESET, 1809 .load = i915_driver_load, 1810 .unload = i915_driver_unload, 1811 .open = i915_driver_open, 1812 .lastclose = i915_driver_lastclose, 1813 .preclose = i915_driver_preclose, 1814 .postclose = i915_driver_postclose, 1815 1816 #if defined(CONFIG_DEBUG_FS) 1817 .debugfs_init = i915_debugfs_init, 1818 .debugfs_cleanup = i915_debugfs_cleanup, 1819 #endif 1820 .gem_free_object = i915_gem_free_object, 1821 .gem_vm_ops = &i915_gem_vm_ops, 1822 1823 .dumb_create = i915_gem_dumb_create, 1824 .dumb_map_offset = i915_gem_mmap_gtt, 1825 .dumb_destroy = drm_gem_dumb_destroy, 1826 .ioctls = i915_ioctls, 1827 .sysctl_init = i915_sysctl_init, 1828 .name = DRIVER_NAME, 1829 .desc = DRIVER_DESC, 1830 .date = DRIVER_DATE, 1831 .major = DRIVER_MAJOR, 1832 .minor = DRIVER_MINOR, 1833 .patchlevel = DRIVER_PATCHLEVEL, 1834 }; 1835 1836 static int __init i915_init(void); 1837 1838 static int 1839 i915_attach(device_t kdev) 1840 { 1841 struct drm_device *dev = device_get_softc(kdev); 1842 int error; 1843 int dummy; 1844 1845 dev->driver = &driver; 1846 error = drm_attach(kdev, i915_attach_list); 1847 1848 /* 1849 * XXX hack - give the kvm_console time to come up before X starts 1850 * messing with everything, avoiding at least one deadlock. 1851 */ 1852 tsleep(&dummy, 0, "i915_attach", hz*2); 1853 1854 return error; 1855 } 1856 1857 static device_method_t i915_methods[] = { 1858 /* Device interface */ 1859 DEVMETHOD(device_probe, i915_pci_probe), 1860 DEVMETHOD(device_attach, i915_attach), 1861 DEVMETHOD(device_suspend, i915_suspend_switcheroo), 1862 DEVMETHOD(device_resume, i915_resume_switcheroo), 1863 DEVMETHOD(device_detach, drm_release), 1864 DEVMETHOD_END 1865 }; 1866 1867 static driver_t i915_driver = { 1868 "drm", 1869 i915_methods, 1870 sizeof(struct drm_device) 1871 }; 1872 1873 static int __init i915_init(void) 1874 { 1875 driver.num_ioctls = i915_max_ioctl; 1876 1877 /* 1878 * Enable KMS by default, unless explicitly overriden by 1879 * either the i915.modeset prarameter or by the 1880 * vga_text_mode_force boot option. 1881 */ 1882 1883 if (i915.modeset == 0) 1884 driver.driver_features &= ~DRIVER_MODESET; 1885 1886 if (vgacon_text_force() && i915.modeset == -1) 1887 driver.driver_features &= ~DRIVER_MODESET; 1888 1889 if (!(driver.driver_features & DRIVER_MODESET)) { 1890 /* Silently fail loading to not upset userspace. */ 1891 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); 1892 return 0; 1893 } 1894 1895 if (i915.nuclear_pageflip) 1896 driver.driver_features |= DRIVER_ATOMIC; 1897 1898 #if 0 1899 return drm_pci_init(&driver, &i915_pci_driver); 1900 #else 1901 return 1; 1902 #endif 1903 } 1904 1905 #if 0 1906 static void __exit i915_exit(void) 1907 { 1908 if (!(driver.driver_features & DRIVER_MODESET)) 1909 return; /* Never loaded a driver. */ 1910 1911 drm_pci_exit(&driver, &i915_pci_driver); 1912 } 1913 #endif 1914 1915 module_init(i915_init); 1916 1917 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY); 1918 MODULE_DEPEND(i915, drm, 1, 1, 1); 1919 #ifdef CONFIG_ACPI 1920 MODULE_DEPEND(i915, acpi, 1, 1, 1); 1921 #endif 1922