1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #include <drm/drmP.h> 31 #include <drm/i915_drm.h> 32 #include "i915_drv.h" 33 #include <drm/drm_pciids.h> 34 #include "intel_drv.h" 35 36 #include <linux/module.h> 37 #include <drm/drm_crtc_helper.h> 38 39 static struct drm_driver driver; 40 41 #define GEN_DEFAULT_PIPEOFFSETS \ 42 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 43 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \ 44 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 45 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \ 46 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET } 47 48 #define GEN_CHV_PIPEOFFSETS \ 49 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \ 50 CHV_PIPE_C_OFFSET }, \ 51 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \ 52 CHV_TRANSCODER_C_OFFSET, }, \ 53 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \ 54 CHV_PALETTE_C_OFFSET } 55 56 #define CURSOR_OFFSETS \ 57 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET } 58 59 #define IVB_CURSOR_OFFSETS \ 60 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET } 61 62 static const struct intel_device_info intel_i830_info = { 63 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, 64 .has_overlay = 1, .overlay_needs_physical = 1, 65 .ring_mask = RENDER_RING, 66 GEN_DEFAULT_PIPEOFFSETS, 67 CURSOR_OFFSETS, 68 }; 69 70 static const struct intel_device_info intel_845g_info = { 71 .gen = 2, .num_pipes = 1, 72 .has_overlay = 1, .overlay_needs_physical = 1, 73 .ring_mask = RENDER_RING, 74 GEN_DEFAULT_PIPEOFFSETS, 75 CURSOR_OFFSETS, 76 }; 77 78 static const struct intel_device_info intel_i85x_info = { 79 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2, 80 .cursor_needs_physical = 1, 81 .has_overlay = 1, .overlay_needs_physical = 1, 82 .has_fbc = 1, 83 .ring_mask = RENDER_RING, 84 GEN_DEFAULT_PIPEOFFSETS, 85 CURSOR_OFFSETS, 86 }; 87 88 static const struct intel_device_info intel_i865g_info = { 89 .gen = 2, .num_pipes = 1, 90 .has_overlay = 1, .overlay_needs_physical = 1, 91 .ring_mask = RENDER_RING, 92 GEN_DEFAULT_PIPEOFFSETS, 93 CURSOR_OFFSETS, 94 }; 95 96 static const struct intel_device_info intel_i915g_info = { 97 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2, 98 .has_overlay = 1, .overlay_needs_physical = 1, 99 .ring_mask = RENDER_RING, 100 GEN_DEFAULT_PIPEOFFSETS, 101 CURSOR_OFFSETS, 102 }; 103 static const struct intel_device_info intel_i915gm_info = { 104 .gen = 3, .is_mobile = 1, .num_pipes = 2, 105 .cursor_needs_physical = 1, 106 .has_overlay = 1, .overlay_needs_physical = 1, 107 .supports_tv = 1, 108 .has_fbc = 1, 109 .ring_mask = RENDER_RING, 110 GEN_DEFAULT_PIPEOFFSETS, 111 CURSOR_OFFSETS, 112 }; 113 static const struct intel_device_info intel_i945g_info = { 114 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2, 115 .has_overlay = 1, .overlay_needs_physical = 1, 116 .ring_mask = RENDER_RING, 117 GEN_DEFAULT_PIPEOFFSETS, 118 CURSOR_OFFSETS, 119 }; 120 static const struct intel_device_info intel_i945gm_info = { 121 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2, 122 .has_hotplug = 1, .cursor_needs_physical = 1, 123 .has_overlay = 1, .overlay_needs_physical = 1, 124 .supports_tv = 1, 125 .has_fbc = 1, 126 .ring_mask = RENDER_RING, 127 GEN_DEFAULT_PIPEOFFSETS, 128 CURSOR_OFFSETS, 129 }; 130 131 static const struct intel_device_info intel_i965g_info = { 132 .gen = 4, .is_broadwater = 1, .num_pipes = 2, 133 .has_hotplug = 1, 134 .has_overlay = 1, 135 .ring_mask = RENDER_RING, 136 GEN_DEFAULT_PIPEOFFSETS, 137 CURSOR_OFFSETS, 138 }; 139 140 static const struct intel_device_info intel_i965gm_info = { 141 .gen = 4, .is_crestline = 1, .num_pipes = 2, 142 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, 143 .has_overlay = 1, 144 .supports_tv = 1, 145 .ring_mask = RENDER_RING, 146 GEN_DEFAULT_PIPEOFFSETS, 147 CURSOR_OFFSETS, 148 }; 149 150 static const struct intel_device_info intel_g33_info = { 151 .gen = 3, .is_g33 = 1, .num_pipes = 2, 152 .need_gfx_hws = 1, .has_hotplug = 1, 153 .has_overlay = 1, 154 .ring_mask = RENDER_RING, 155 GEN_DEFAULT_PIPEOFFSETS, 156 CURSOR_OFFSETS, 157 }; 158 159 static const struct intel_device_info intel_g45_info = { 160 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2, 161 .has_pipe_cxsr = 1, .has_hotplug = 1, 162 .ring_mask = RENDER_RING | BSD_RING, 163 GEN_DEFAULT_PIPEOFFSETS, 164 CURSOR_OFFSETS, 165 }; 166 167 static const struct intel_device_info intel_gm45_info = { 168 .gen = 4, .is_g4x = 1, .num_pipes = 2, 169 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, 170 .has_pipe_cxsr = 1, .has_hotplug = 1, 171 .supports_tv = 1, 172 .ring_mask = RENDER_RING | BSD_RING, 173 GEN_DEFAULT_PIPEOFFSETS, 174 CURSOR_OFFSETS, 175 }; 176 177 static const struct intel_device_info intel_pineview_info = { 178 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2, 179 .need_gfx_hws = 1, .has_hotplug = 1, 180 .has_overlay = 1, 181 GEN_DEFAULT_PIPEOFFSETS, 182 CURSOR_OFFSETS, 183 }; 184 185 static const struct intel_device_info intel_ironlake_d_info = { 186 .gen = 5, .num_pipes = 2, 187 .need_gfx_hws = 1, .has_hotplug = 1, 188 .ring_mask = RENDER_RING | BSD_RING, 189 GEN_DEFAULT_PIPEOFFSETS, 190 CURSOR_OFFSETS, 191 }; 192 193 static const struct intel_device_info intel_ironlake_m_info = { 194 .gen = 5, .is_mobile = 1, .num_pipes = 2, 195 .need_gfx_hws = 1, .has_hotplug = 1, 196 .has_fbc = 1, 197 .ring_mask = RENDER_RING | BSD_RING, 198 GEN_DEFAULT_PIPEOFFSETS, 199 CURSOR_OFFSETS, 200 }; 201 202 static const struct intel_device_info intel_sandybridge_d_info = { 203 .gen = 6, .num_pipes = 2, 204 .need_gfx_hws = 1, .has_hotplug = 1, 205 .has_fbc = 1, 206 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 207 .has_llc = 1, 208 GEN_DEFAULT_PIPEOFFSETS, 209 CURSOR_OFFSETS, 210 }; 211 212 static const struct intel_device_info intel_sandybridge_m_info = { 213 .gen = 6, .is_mobile = 1, .num_pipes = 2, 214 .need_gfx_hws = 1, .has_hotplug = 1, 215 .has_fbc = 1, 216 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 217 .has_llc = 1, 218 GEN_DEFAULT_PIPEOFFSETS, 219 CURSOR_OFFSETS, 220 }; 221 222 #define GEN7_FEATURES \ 223 .gen = 7, .num_pipes = 3, \ 224 .need_gfx_hws = 1, .has_hotplug = 1, \ 225 .has_fbc = 1, \ 226 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 227 .has_llc = 1 228 229 static const struct intel_device_info intel_ivybridge_d_info = { 230 GEN7_FEATURES, 231 .is_ivybridge = 1, 232 GEN_DEFAULT_PIPEOFFSETS, 233 IVB_CURSOR_OFFSETS, 234 }; 235 236 static const struct intel_device_info intel_ivybridge_m_info = { 237 GEN7_FEATURES, 238 .is_ivybridge = 1, 239 .is_mobile = 1, 240 GEN_DEFAULT_PIPEOFFSETS, 241 IVB_CURSOR_OFFSETS, 242 }; 243 244 static const struct intel_device_info intel_ivybridge_q_info = { 245 GEN7_FEATURES, 246 .is_ivybridge = 1, 247 .num_pipes = 0, /* legal, last one wins */ 248 GEN_DEFAULT_PIPEOFFSETS, 249 IVB_CURSOR_OFFSETS, 250 }; 251 252 static const struct intel_device_info intel_valleyview_m_info = { 253 GEN7_FEATURES, 254 .is_mobile = 1, 255 .num_pipes = 2, 256 .is_valleyview = 1, 257 .display_mmio_offset = VLV_DISPLAY_BASE, 258 .has_fbc = 0, /* legal, last one wins */ 259 .has_llc = 0, /* legal, last one wins */ 260 GEN_DEFAULT_PIPEOFFSETS, 261 CURSOR_OFFSETS, 262 }; 263 264 static const struct intel_device_info intel_valleyview_d_info = { 265 GEN7_FEATURES, 266 .num_pipes = 2, 267 .is_valleyview = 1, 268 .display_mmio_offset = VLV_DISPLAY_BASE, 269 .has_fbc = 0, /* legal, last one wins */ 270 .has_llc = 0, /* legal, last one wins */ 271 GEN_DEFAULT_PIPEOFFSETS, 272 CURSOR_OFFSETS, 273 }; 274 275 static const struct intel_device_info intel_haswell_d_info = { 276 GEN7_FEATURES, 277 .is_haswell = 1, 278 .has_ddi = 1, 279 .has_fpga_dbg = 1, 280 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 281 GEN_DEFAULT_PIPEOFFSETS, 282 IVB_CURSOR_OFFSETS, 283 }; 284 285 static const struct intel_device_info intel_haswell_m_info = { 286 GEN7_FEATURES, 287 .is_haswell = 1, 288 .is_mobile = 1, 289 .has_ddi = 1, 290 .has_fpga_dbg = 1, 291 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 292 GEN_DEFAULT_PIPEOFFSETS, 293 IVB_CURSOR_OFFSETS, 294 }; 295 296 static const struct intel_device_info intel_broadwell_d_info = { 297 .gen = 8, .num_pipes = 3, 298 .need_gfx_hws = 1, .has_hotplug = 1, 299 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 300 .has_llc = 1, 301 .has_ddi = 1, 302 .has_fpga_dbg = 1, 303 .has_fbc = 1, 304 GEN_DEFAULT_PIPEOFFSETS, 305 IVB_CURSOR_OFFSETS, 306 }; 307 308 static const struct intel_device_info intel_broadwell_m_info = { 309 .gen = 8, .is_mobile = 1, .num_pipes = 3, 310 .need_gfx_hws = 1, .has_hotplug = 1, 311 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 312 .has_llc = 1, 313 .has_ddi = 1, 314 .has_fpga_dbg = 1, 315 .has_fbc = 1, 316 GEN_DEFAULT_PIPEOFFSETS, 317 IVB_CURSOR_OFFSETS, 318 }; 319 320 static const struct intel_device_info intel_broadwell_gt3d_info = { 321 .gen = 8, .num_pipes = 3, 322 .need_gfx_hws = 1, .has_hotplug = 1, 323 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 324 .has_llc = 1, 325 .has_ddi = 1, 326 .has_fpga_dbg = 1, 327 .has_fbc = 1, 328 GEN_DEFAULT_PIPEOFFSETS, 329 IVB_CURSOR_OFFSETS, 330 }; 331 332 static const struct intel_device_info intel_broadwell_gt3m_info = { 333 .gen = 8, .is_mobile = 1, .num_pipes = 3, 334 .need_gfx_hws = 1, .has_hotplug = 1, 335 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 336 .has_llc = 1, 337 .has_ddi = 1, 338 .has_fpga_dbg = 1, 339 .has_fbc = 1, 340 GEN_DEFAULT_PIPEOFFSETS, 341 IVB_CURSOR_OFFSETS, 342 }; 343 344 static const struct intel_device_info intel_cherryview_info = { 345 .gen = 8, .num_pipes = 3, 346 .need_gfx_hws = 1, .has_hotplug = 1, 347 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 348 .is_valleyview = 1, 349 .display_mmio_offset = VLV_DISPLAY_BASE, 350 GEN_CHV_PIPEOFFSETS, 351 CURSOR_OFFSETS, 352 }; 353 354 static const struct intel_device_info intel_skylake_info = { 355 .is_skylake = 1, 356 .gen = 9, .num_pipes = 3, 357 .need_gfx_hws = 1, .has_hotplug = 1, 358 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 359 .has_llc = 1, 360 .has_ddi = 1, 361 .has_fbc = 1, 362 GEN_DEFAULT_PIPEOFFSETS, 363 IVB_CURSOR_OFFSETS, 364 }; 365 366 static const struct intel_device_info intel_skylake_gt3_info = { 367 .is_skylake = 1, 368 .gen = 9, .num_pipes = 3, 369 .need_gfx_hws = 1, .has_hotplug = 1, 370 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 371 .has_llc = 1, 372 .has_ddi = 1, 373 .has_fbc = 1, 374 GEN_DEFAULT_PIPEOFFSETS, 375 IVB_CURSOR_OFFSETS, 376 }; 377 378 static const struct intel_device_info intel_broxton_info = { 379 .is_preliminary = 1, 380 .gen = 9, 381 .need_gfx_hws = 1, .has_hotplug = 1, 382 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 383 .num_pipes = 3, 384 .has_ddi = 1, 385 .has_fbc = 1, 386 GEN_DEFAULT_PIPEOFFSETS, 387 IVB_CURSOR_OFFSETS, 388 }; 389 390 /* 391 * Make sure any device matches here are from most specific to most 392 * general. For example, since the Quanta match is based on the subsystem 393 * and subvendor IDs, we need it to come before the more general IVB 394 * PCI ID matches, otherwise we'll use the wrong info struct above. 395 */ 396 #define INTEL_PCI_IDS \ 397 INTEL_I830_IDS(&intel_i830_info), \ 398 INTEL_I845G_IDS(&intel_845g_info), \ 399 INTEL_I85X_IDS(&intel_i85x_info), \ 400 INTEL_I865G_IDS(&intel_i865g_info), \ 401 INTEL_I915G_IDS(&intel_i915g_info), \ 402 INTEL_I915GM_IDS(&intel_i915gm_info), \ 403 INTEL_I945G_IDS(&intel_i945g_info), \ 404 INTEL_I945GM_IDS(&intel_i945gm_info), \ 405 INTEL_I965G_IDS(&intel_i965g_info), \ 406 INTEL_G33_IDS(&intel_g33_info), \ 407 INTEL_I965GM_IDS(&intel_i965gm_info), \ 408 INTEL_GM45_IDS(&intel_gm45_info), \ 409 INTEL_G45_IDS(&intel_g45_info), \ 410 INTEL_PINEVIEW_IDS(&intel_pineview_info), \ 411 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \ 412 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \ 413 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \ 414 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \ 415 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \ 416 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \ 417 INTEL_HSW_D_IDS(&intel_haswell_d_info), \ 418 INTEL_HSW_M_IDS(&intel_haswell_m_info), \ 419 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \ 420 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \ 421 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \ 422 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \ 423 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \ 424 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \ 425 INTEL_CHV_IDS(&intel_cherryview_info), \ 426 INTEL_SKL_GT1_IDS(&intel_skylake_info), \ 427 INTEL_SKL_GT2_IDS(&intel_skylake_info), \ 428 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \ 429 INTEL_BXT_IDS(&intel_broxton_info) 430 431 static const struct pci_device_id pciidlist[] = { /* aka */ 432 INTEL_PCI_IDS, 433 {0, 0} 434 }; 435 436 #define PCI_VENDOR_INTEL 0x8086 437 438 void intel_detect_pch(struct drm_device *dev) 439 { 440 struct drm_i915_private *dev_priv = dev->dev_private; 441 struct device *pch = NULL; 442 struct pci_devinfo *di; 443 444 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting 445 * (which really amounts to a PCH but no South Display). 446 */ 447 if (INTEL_INFO(dev)->num_pipes == 0) { 448 dev_priv->pch_type = PCH_NOP; 449 return; 450 } 451 452 /* XXX The ISA bridge probe causes some old Core2 machines to hang */ 453 if (INTEL_INFO(dev)->gen < 5) 454 return; 455 456 /* 457 * The reason to probe ISA bridge instead of Dev31:Fun0 is to 458 * make graphics device passthrough work easy for VMM, that only 459 * need to expose ISA bridge to let driver know the real hardware 460 * underneath. This is a requirement from virtualization team. 461 * 462 * In some virtualized environments (e.g. XEN), there is irrelevant 463 * ISA bridge in the system. To work reliably, we should scan trhough 464 * all the ISA bridge devices and check for the first match, instead 465 * of only checking the first one. 466 */ 467 di = NULL; 468 469 while ((pch = pci_iterate_class(&di, PCIC_BRIDGE, PCIS_BRIDGE_ISA))) { 470 if (pci_get_vendor(pch) == PCI_VENDOR_INTEL) { 471 unsigned short id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK; 472 dev_priv->pch_id = id; 473 474 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { 475 dev_priv->pch_type = PCH_IBX; 476 DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); 477 WARN_ON(!IS_GEN5(dev)); 478 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { 479 dev_priv->pch_type = PCH_CPT; 480 DRM_DEBUG_KMS("Found CougarPoint PCH\n"); 481 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 482 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { 483 /* PantherPoint is CPT compatible */ 484 dev_priv->pch_type = PCH_CPT; 485 DRM_DEBUG_KMS("Found PantherPoint PCH\n"); 486 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev))); 487 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { 488 dev_priv->pch_type = PCH_LPT; 489 DRM_DEBUG_KMS("Found LynxPoint PCH\n"); 490 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); 491 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev)); 492 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 493 dev_priv->pch_type = PCH_LPT; 494 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n"); 495 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev)); 496 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev)); 497 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) { 498 dev_priv->pch_type = PCH_SPT; 499 DRM_DEBUG_KMS("Found SunrisePoint PCH\n"); 500 WARN_ON(!IS_SKYLAKE(dev)); 501 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) { 502 dev_priv->pch_type = PCH_SPT; 503 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n"); 504 WARN_ON(!IS_SKYLAKE(dev)); 505 } else 506 continue; 507 508 break; 509 } 510 } 511 if (!pch) 512 DRM_DEBUG_KMS("No PCH found.\n"); 513 514 #if 0 515 pci_dev_put(pch); 516 #endif 517 } 518 519 bool i915_semaphore_is_enabled(struct drm_device *dev) 520 { 521 if (INTEL_INFO(dev)->gen < 6) 522 return false; 523 524 if (i915.semaphores >= 0) 525 return i915.semaphores; 526 527 /* TODO: make semaphores and Execlists play nicely together */ 528 if (i915.enable_execlists) 529 return false; 530 531 /* Until we get further testing... */ 532 if (IS_GEN8(dev)) 533 return false; 534 535 #ifdef CONFIG_INTEL_IOMMU 536 /* Enable semaphores on SNB when IO remapping is off */ 537 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) 538 return false; 539 #endif 540 541 return true; 542 } 543 544 #ifdef __DragonFly__ 545 #define IS_BUILTIN(blah) 0 546 #endif 547 548 void i915_firmware_load_error_print(const char *fw_path, int err) 549 { 550 DRM_ERROR("failed to load firmware %s (%d)\n", fw_path, err); 551 552 /* 553 * If the reason is not known assume -ENOENT since that's the most 554 * usual failure mode. 555 */ 556 if (!err) 557 err = -ENOENT; 558 559 if (!(IS_BUILTIN(CONFIG_DRM_I915) && err == -ENOENT)) 560 return; 561 562 DRM_ERROR( 563 "The driver is built-in, so to load the firmware you need to\n" 564 "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n" 565 "in your initrd/initramfs image.\n"); 566 } 567 568 static void intel_suspend_encoders(struct drm_i915_private *dev_priv) 569 { 570 struct drm_device *dev = dev_priv->dev; 571 struct drm_encoder *encoder; 572 573 drm_modeset_lock_all(dev); 574 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 575 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 576 577 if (intel_encoder->suspend) 578 intel_encoder->suspend(intel_encoder); 579 } 580 drm_modeset_unlock_all(dev); 581 } 582 583 static int intel_suspend_complete(struct drm_i915_private *dev_priv); 584 static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 585 bool rpm_resume); 586 static int skl_resume_prepare(struct drm_i915_private *dev_priv); 587 static int bxt_resume_prepare(struct drm_i915_private *dev_priv); 588 589 590 static int i915_drm_suspend(struct drm_device *dev) 591 { 592 struct drm_i915_private *dev_priv = dev->dev_private; 593 pci_power_t opregion_target_state; 594 int error; 595 596 /* ignore lid events during suspend */ 597 mutex_lock(&dev_priv->modeset_restore_lock); 598 dev_priv->modeset_restore = MODESET_SUSPENDED; 599 mutex_unlock(&dev_priv->modeset_restore_lock); 600 601 /* We do a lot of poking in a lot of registers, make sure they work 602 * properly. */ 603 intel_display_set_init_power(dev_priv, true); 604 605 drm_kms_helper_poll_disable(dev); 606 607 #if 0 608 pci_save_state(dev->pdev); 609 #endif 610 611 error = i915_gem_suspend(dev); 612 if (error) { 613 dev_err(dev->pdev->dev, 614 "GEM idle failed, resume might fail\n"); 615 return error; 616 } 617 618 intel_suspend_gt_powersave(dev); 619 620 /* 621 * Disable CRTCs directly since we want to preserve sw state 622 * for _thaw. Also, power gate the CRTC power wells. 623 */ 624 drm_modeset_lock_all(dev); 625 intel_display_suspend(dev); 626 drm_modeset_unlock_all(dev); 627 628 #if 0 629 intel_dp_mst_suspend(dev); 630 #endif 631 632 intel_runtime_pm_disable_interrupts(dev_priv); 633 intel_hpd_cancel_work(dev_priv); 634 635 intel_suspend_encoders(dev_priv); 636 637 intel_suspend_hw(dev); 638 639 i915_gem_suspend_gtt_mappings(dev); 640 641 i915_save_state(dev); 642 643 opregion_target_state = PCI_D3cold; 644 #if IS_ENABLED(CONFIG_ACPI_SLEEP) 645 if (acpi_target_system_state() < ACPI_STATE_S3) 646 opregion_target_state = PCI_D1; 647 #endif 648 intel_opregion_notify_adapter(dev, opregion_target_state); 649 650 intel_uncore_forcewake_reset(dev, false); 651 intel_opregion_fini(dev); 652 653 #if 0 654 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true); 655 #endif 656 657 dev_priv->suspend_count++; 658 659 intel_display_set_init_power(dev_priv, false); 660 661 return 0; 662 } 663 664 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation) 665 { 666 struct drm_i915_private *dev_priv = drm_dev->dev_private; 667 int ret; 668 669 ret = intel_suspend_complete(dev_priv); 670 671 if (ret) { 672 DRM_ERROR("Suspend complete failed: %d\n", ret); 673 674 return ret; 675 } 676 677 #if 0 678 pci_disable_device(drm_dev->pdev); 679 /* 680 * During hibernation on some platforms the BIOS may try to access 681 * the device even though it's already in D3 and hang the machine. So 682 * leave the device in D0 on those platforms and hope the BIOS will 683 * power down the device properly. The issue was seen on multiple old 684 * GENs with different BIOS vendors, so having an explicit blacklist 685 * is inpractical; apply the workaround on everything pre GEN6. The 686 * platforms where the issue was seen: 687 * Lenovo Thinkpad X301, X61s, X60, T60, X41 688 * Fujitsu FSC S7110 689 * Acer Aspire 1830T 690 */ 691 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6)) 692 pci_set_power_state(drm_dev->pdev, PCI_D3hot); 693 #endif 694 695 return 0; 696 } 697 698 int i915_suspend_legacy(device_t kdev) 699 { 700 struct drm_device *dev = device_get_softc(kdev); 701 int error; 702 703 if (!dev || !dev->dev_private) { 704 DRM_ERROR("dev: %p\n", dev); 705 DRM_ERROR("DRM not initialized, aborting suspend.\n"); 706 return -ENODEV; 707 } 708 709 #if 0 710 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && 711 state.event != PM_EVENT_FREEZE)) 712 return -EINVAL; 713 #endif 714 715 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 716 return 0; 717 718 error = i915_drm_suspend(dev); 719 if (error) 720 return error; 721 722 return i915_drm_suspend_late(dev, false); 723 } 724 725 static int i915_drm_resume(struct drm_device *dev) 726 { 727 struct drm_i915_private *dev_priv = dev->dev_private; 728 729 mutex_lock(&dev->struct_mutex); 730 i915_gem_restore_gtt_mappings(dev); 731 mutex_unlock(&dev->struct_mutex); 732 733 i915_restore_state(dev); 734 intel_opregion_setup(dev); 735 736 intel_init_pch_refclk(dev); 737 drm_mode_config_reset(dev); 738 739 /* 740 * Interrupts have to be enabled before any batches are run. If not the 741 * GPU will hang. i915_gem_init_hw() will initiate batches to 742 * update/restore the context. 743 * 744 * Modeset enabling in intel_modeset_init_hw() also needs working 745 * interrupts. 746 */ 747 intel_runtime_pm_enable_interrupts(dev_priv); 748 749 mutex_lock(&dev->struct_mutex); 750 if (i915_gem_init_hw(dev)) { 751 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); 752 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); 753 } 754 mutex_unlock(&dev->struct_mutex); 755 756 intel_modeset_init_hw(dev); 757 758 spin_lock_irq(&dev_priv->irq_lock); 759 if (dev_priv->display.hpd_irq_setup) 760 dev_priv->display.hpd_irq_setup(dev); 761 spin_unlock_irq(&dev_priv->irq_lock); 762 763 drm_modeset_lock_all(dev); 764 intel_display_resume(dev); 765 drm_modeset_unlock_all(dev); 766 767 intel_dp_mst_resume(dev); 768 769 /* 770 * ... but also need to make sure that hotplug processing 771 * doesn't cause havoc. Like in the driver load code we don't 772 * bother with the tiny race here where we might loose hotplug 773 * notifications. 774 * */ 775 intel_hpd_init(dev_priv); 776 /* Config may have changed between suspend and resume */ 777 drm_helper_hpd_irq_event(dev); 778 779 intel_opregion_init(dev); 780 781 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false); 782 783 mutex_lock(&dev_priv->modeset_restore_lock); 784 dev_priv->modeset_restore = MODESET_DONE; 785 mutex_unlock(&dev_priv->modeset_restore_lock); 786 787 #if 0 788 intel_opregion_notify_adapter(dev, PCI_D0); 789 #endif 790 791 drm_kms_helper_poll_enable(dev); 792 793 return 0; 794 } 795 796 static int i915_drm_resume_early(struct drm_device *dev) 797 { 798 struct drm_i915_private *dev_priv = dev->dev_private; 799 int ret = 0; 800 801 /* 802 * We have a resume ordering issue with the snd-hda driver also 803 * requiring our device to be power up. Due to the lack of a 804 * parent/child relationship we currently solve this with an early 805 * resume hook. 806 * 807 * FIXME: This should be solved with a special hdmi sink device or 808 * similar so that power domains can be employed. 809 */ 810 #if 0 811 if (pci_enable_device(dev->pdev)) 812 return -EIO; 813 814 pci_set_master(dev->pdev); 815 #endif 816 817 if (IS_VALLEYVIEW(dev_priv)) 818 ret = vlv_resume_prepare(dev_priv, false); 819 if (ret) 820 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n", 821 ret); 822 823 intel_uncore_early_sanitize(dev, true); 824 825 if (IS_BROXTON(dev)) 826 ret = bxt_resume_prepare(dev_priv); 827 else if (IS_SKYLAKE(dev_priv)) 828 ret = skl_resume_prepare(dev_priv); 829 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 830 hsw_disable_pc8(dev_priv); 831 832 intel_uncore_sanitize(dev); 833 intel_power_domains_init_hw(dev_priv); 834 835 return ret; 836 } 837 838 int i915_resume_legacy(struct drm_device *dev) 839 { 840 int ret; 841 842 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 843 return 0; 844 845 ret = i915_drm_resume_early(dev); 846 if (ret) 847 return ret; 848 849 return i915_drm_resume(dev); 850 } 851 852 /* XXX Hack for the old *BSD drm code base 853 * The device id field is set at probe time */ 854 static drm_pci_id_list_t i915_attach_list[] = { 855 {0x8086, 0, 0, "Intel i915 GPU"}, 856 {0, 0, 0, NULL} 857 }; 858 859 struct intel_device_info * 860 i915_get_device_id(int device) 861 { 862 const struct pci_device_id *did; 863 864 for (did = &pciidlist[0]; did->device != 0; did++) { 865 if (did->device != device) 866 continue; 867 return (struct intel_device_info *)did->driver_data; 868 } 869 return (NULL); 870 } 871 872 extern devclass_t drm_devclass; 873 874 /** 875 * i915_reset - reset chip after a hang 876 * @dev: drm device to reset 877 * 878 * Reset the chip. Useful if a hang is detected. Returns zero on successful 879 * reset or otherwise an error code. 880 * 881 * Procedure is fairly simple: 882 * - reset the chip using the reset reg 883 * - re-init context state 884 * - re-init hardware status page 885 * - re-init ring buffer 886 * - re-init interrupt state 887 * - re-init display 888 */ 889 int i915_reset(struct drm_device *dev) 890 { 891 struct drm_i915_private *dev_priv = dev->dev_private; 892 bool simulated; 893 int ret; 894 895 intel_reset_gt_powersave(dev); 896 897 mutex_lock(&dev->struct_mutex); 898 899 i915_gem_reset(dev); 900 901 simulated = dev_priv->gpu_error.stop_rings != 0; 902 903 ret = intel_gpu_reset(dev); 904 905 /* Also reset the gpu hangman. */ 906 if (simulated) { 907 DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); 908 dev_priv->gpu_error.stop_rings = 0; 909 if (ret == -ENODEV) { 910 DRM_INFO("Reset not implemented, but ignoring " 911 "error for simulated gpu hangs\n"); 912 ret = 0; 913 } 914 } 915 916 if (i915_stop_ring_allow_warn(dev_priv)) 917 pr_notice("drm/i915: Resetting chip after gpu hang\n"); 918 919 if (ret) { 920 DRM_ERROR("Failed to reset chip: %i\n", ret); 921 mutex_unlock(&dev->struct_mutex); 922 return ret; 923 } 924 925 intel_overlay_reset(dev_priv); 926 927 /* Ok, now get things going again... */ 928 929 /* 930 * Everything depends on having the GTT running, so we need to start 931 * there. Fortunately we don't need to do this unless we reset the 932 * chip at a PCI level. 933 * 934 * Next we need to restore the context, but we don't use those 935 * yet either... 936 * 937 * Ring buffer needs to be re-initialized in the KMS case, or if X 938 * was running at the time of the reset (i.e. we weren't VT 939 * switched away). 940 */ 941 942 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ 943 dev_priv->gpu_error.reload_in_reset = true; 944 945 ret = i915_gem_init_hw(dev); 946 947 dev_priv->gpu_error.reload_in_reset = false; 948 949 mutex_unlock(&dev->struct_mutex); 950 if (ret) { 951 DRM_ERROR("Failed hw init on reset %d\n", ret); 952 return ret; 953 } 954 955 /* 956 * rps/rc6 re-init is necessary to restore state lost after the 957 * reset and the re-install of gt irqs. Skip for ironlake per 958 * previous concerns that it doesn't respond well to some forms 959 * of re-init after reset. 960 */ 961 if (INTEL_INFO(dev)->gen > 5) 962 intel_enable_gt_powersave(dev); 963 964 return 0; 965 } 966 967 static int i915_pci_probe(device_t kdev) 968 { 969 int device, i = 0; 970 971 if (pci_get_class(kdev) != PCIC_DISPLAY) 972 return ENXIO; 973 974 if (pci_get_vendor(kdev) != PCI_VENDOR_INTEL) 975 return ENXIO; 976 977 device = pci_get_device(kdev); 978 979 for (i = 0; pciidlist[i].device != 0; i++) { 980 if (pciidlist[i].device == device) { 981 i915_attach_list[0].device = device; 982 return 0; 983 } 984 } 985 986 return ENXIO; 987 } 988 989 #if 0 990 static void 991 i915_pci_remove(struct pci_dev *pdev) 992 { 993 struct drm_device *dev = pci_get_drvdata(pdev); 994 995 drm_put_dev(dev); 996 } 997 998 static int i915_pm_suspend(struct device *dev) 999 { 1000 struct pci_dev *pdev = to_pci_dev(dev); 1001 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1002 1003 if (!drm_dev || !drm_dev->dev_private) { 1004 dev_err(dev, "DRM not initialized, aborting suspend.\n"); 1005 return -ENODEV; 1006 } 1007 1008 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1009 return 0; 1010 1011 return i915_drm_suspend(drm_dev); 1012 } 1013 1014 static int i915_pm_suspend_late(struct device *dev) 1015 { 1016 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1017 1018 /* 1019 * We have a suspend ordering issue with the snd-hda driver also 1020 * requiring our device to be power up. Due to the lack of a 1021 * parent/child relationship we currently solve this with an late 1022 * suspend hook. 1023 * 1024 * FIXME: This should be solved with a special hdmi sink device or 1025 * similar so that power domains can be employed. 1026 */ 1027 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1028 return 0; 1029 1030 return i915_drm_suspend_late(drm_dev, false); 1031 } 1032 1033 static int i915_pm_poweroff_late(struct device *dev) 1034 { 1035 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1036 1037 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1038 return 0; 1039 1040 return i915_drm_suspend_late(drm_dev, true); 1041 } 1042 1043 static int i915_pm_resume_early(struct device *dev) 1044 { 1045 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1046 1047 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1048 return 0; 1049 1050 return i915_drm_resume_early(drm_dev); 1051 } 1052 1053 static int i915_pm_resume(struct device *dev) 1054 { 1055 struct drm_device *drm_dev = dev_to_i915(dev)->dev; 1056 1057 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1058 return 0; 1059 1060 return i915_drm_resume(drm_dev); 1061 } 1062 #endif 1063 1064 static int skl_suspend_complete(struct drm_i915_private *dev_priv) 1065 { 1066 /* Enabling DC6 is not a hard requirement to enter runtime D3 */ 1067 1068 /* 1069 * This is to ensure that CSR isn't identified as loaded before 1070 * CSR-loading program is called during runtime-resume. 1071 */ 1072 intel_csr_load_status_set(dev_priv, FW_UNINITIALIZED); 1073 1074 skl_uninit_cdclk(dev_priv); 1075 1076 return 0; 1077 } 1078 1079 static int hsw_suspend_complete(struct drm_i915_private *dev_priv) 1080 { 1081 hsw_enable_pc8(dev_priv); 1082 1083 return 0; 1084 } 1085 1086 static int bxt_suspend_complete(struct drm_i915_private *dev_priv) 1087 { 1088 struct drm_device *dev = dev_priv->dev; 1089 1090 /* TODO: when DC5 support is added disable DC5 here. */ 1091 1092 broxton_ddi_phy_uninit(dev); 1093 broxton_uninit_cdclk(dev); 1094 bxt_enable_dc9(dev_priv); 1095 1096 return 0; 1097 } 1098 1099 static int bxt_resume_prepare(struct drm_i915_private *dev_priv) 1100 { 1101 struct drm_device *dev = dev_priv->dev; 1102 1103 /* TODO: when CSR FW support is added make sure the FW is loaded */ 1104 1105 bxt_disable_dc9(dev_priv); 1106 1107 /* 1108 * TODO: when DC5 support is added enable DC5 here if the CSR FW 1109 * is available. 1110 */ 1111 broxton_init_cdclk(dev); 1112 broxton_ddi_phy_init(dev); 1113 intel_prepare_ddi(dev); 1114 1115 return 0; 1116 } 1117 1118 static int skl_resume_prepare(struct drm_i915_private *dev_priv) 1119 { 1120 struct drm_device *dev = dev_priv->dev; 1121 1122 skl_init_cdclk(dev_priv); 1123 intel_csr_load_program(dev); 1124 1125 return 0; 1126 } 1127 1128 /* 1129 * Save all Gunit registers that may be lost after a D3 and a subsequent 1130 * S0i[R123] transition. The list of registers needing a save/restore is 1131 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit 1132 * registers in the following way: 1133 * - Driver: saved/restored by the driver 1134 * - Punit : saved/restored by the Punit firmware 1135 * - No, w/o marking: no need to save/restore, since the register is R/O or 1136 * used internally by the HW in a way that doesn't depend 1137 * keeping the content across a suspend/resume. 1138 * - Debug : used for debugging 1139 * 1140 * We save/restore all registers marked with 'Driver', with the following 1141 * exceptions: 1142 * - Registers out of use, including also registers marked with 'Debug'. 1143 * These have no effect on the driver's operation, so we don't save/restore 1144 * them to reduce the overhead. 1145 * - Registers that are fully setup by an initialization function called from 1146 * the resume path. For example many clock gating and RPS/RC6 registers. 1147 * - Registers that provide the right functionality with their reset defaults. 1148 * 1149 * TODO: Except for registers that based on the above 3 criteria can be safely 1150 * ignored, we save/restore all others, practically treating the HW context as 1151 * a black-box for the driver. Further investigation is needed to reduce the 1152 * saved/restored registers even further, by following the same 3 criteria. 1153 */ 1154 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1155 { 1156 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1157 int i; 1158 1159 /* GAM 0x4000-0x4770 */ 1160 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); 1161 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); 1162 s->arb_mode = I915_READ(ARB_MODE); 1163 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); 1164 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); 1165 1166 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1167 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); 1168 1169 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); 1170 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); 1171 1172 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); 1173 s->ecochk = I915_READ(GAM_ECOCHK); 1174 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); 1175 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); 1176 1177 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); 1178 1179 /* MBC 0x9024-0x91D0, 0x8500 */ 1180 s->g3dctl = I915_READ(VLV_G3DCTL); 1181 s->gsckgctl = I915_READ(VLV_GSCKGCTL); 1182 s->mbctl = I915_READ(GEN6_MBCTL); 1183 1184 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1185 s->ucgctl1 = I915_READ(GEN6_UCGCTL1); 1186 s->ucgctl3 = I915_READ(GEN6_UCGCTL3); 1187 s->rcgctl1 = I915_READ(GEN6_RCGCTL1); 1188 s->rcgctl2 = I915_READ(GEN6_RCGCTL2); 1189 s->rstctl = I915_READ(GEN6_RSTCTL); 1190 s->misccpctl = I915_READ(GEN7_MISCCPCTL); 1191 1192 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1193 s->gfxpause = I915_READ(GEN6_GFXPAUSE); 1194 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); 1195 s->rpdeuc = I915_READ(GEN6_RPDEUC); 1196 s->ecobus = I915_READ(ECOBUS); 1197 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); 1198 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); 1199 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); 1200 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); 1201 s->rcedata = I915_READ(VLV_RCEDATA); 1202 s->spare2gh = I915_READ(VLV_SPAREG2H); 1203 1204 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1205 s->gt_imr = I915_READ(GTIMR); 1206 s->gt_ier = I915_READ(GTIER); 1207 s->pm_imr = I915_READ(GEN6_PMIMR); 1208 s->pm_ier = I915_READ(GEN6_PMIER); 1209 1210 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1211 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); 1212 1213 /* GT SA CZ domain, 0x100000-0x138124 */ 1214 s->tilectl = I915_READ(TILECTL); 1215 s->gt_fifoctl = I915_READ(GTFIFOCTL); 1216 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); 1217 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1218 s->pmwgicz = I915_READ(VLV_PMWGICZ); 1219 1220 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1221 s->gu_ctl0 = I915_READ(VLV_GU_CTL0); 1222 s->gu_ctl1 = I915_READ(VLV_GU_CTL1); 1223 s->pcbr = I915_READ(VLV_PCBR); 1224 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); 1225 1226 /* 1227 * Not saving any of: 1228 * DFT, 0x9800-0x9EC0 1229 * SARB, 0xB000-0xB1FC 1230 * GAC, 0x5208-0x524C, 0x14000-0x14C000 1231 * PCI CFG 1232 */ 1233 } 1234 1235 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv) 1236 { 1237 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state; 1238 u32 val; 1239 int i; 1240 1241 /* GAM 0x4000-0x4770 */ 1242 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark); 1243 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl); 1244 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16)); 1245 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0); 1246 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1); 1247 1248 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++) 1249 I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]); 1250 1251 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count); 1252 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count); 1253 1254 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp); 1255 I915_WRITE(GAM_ECOCHK, s->ecochk); 1256 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp); 1257 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp); 1258 1259 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr); 1260 1261 /* MBC 0x9024-0x91D0, 0x8500 */ 1262 I915_WRITE(VLV_G3DCTL, s->g3dctl); 1263 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl); 1264 I915_WRITE(GEN6_MBCTL, s->mbctl); 1265 1266 /* GCP 0x9400-0x9424, 0x8100-0x810C */ 1267 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1); 1268 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3); 1269 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1); 1270 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2); 1271 I915_WRITE(GEN6_RSTCTL, s->rstctl); 1272 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); 1273 1274 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */ 1275 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause); 1276 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc); 1277 I915_WRITE(GEN6_RPDEUC, s->rpdeuc); 1278 I915_WRITE(ECOBUS, s->ecobus); 1279 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl); 1280 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout); 1281 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw); 1282 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr); 1283 I915_WRITE(VLV_RCEDATA, s->rcedata); 1284 I915_WRITE(VLV_SPAREG2H, s->spare2gh); 1285 1286 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */ 1287 I915_WRITE(GTIMR, s->gt_imr); 1288 I915_WRITE(GTIER, s->gt_ier); 1289 I915_WRITE(GEN6_PMIMR, s->pm_imr); 1290 I915_WRITE(GEN6_PMIER, s->pm_ier); 1291 1292 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++) 1293 I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]); 1294 1295 /* GT SA CZ domain, 0x100000-0x138124 */ 1296 I915_WRITE(TILECTL, s->tilectl); 1297 I915_WRITE(GTFIFOCTL, s->gt_fifoctl); 1298 /* 1299 * Preserve the GT allow wake and GFX force clock bit, they are not 1300 * be restored, as they are used to control the s0ix suspend/resume 1301 * sequence by the caller. 1302 */ 1303 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1304 val &= VLV_GTLC_ALLOWWAKEREQ; 1305 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ; 1306 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1307 1308 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1309 val &= VLV_GFX_CLK_FORCE_ON_BIT; 1310 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT; 1311 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1312 1313 I915_WRITE(VLV_PMWGICZ, s->pmwgicz); 1314 1315 /* Gunit-Display CZ domain, 0x182028-0x1821CF */ 1316 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0); 1317 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1); 1318 I915_WRITE(VLV_PCBR, s->pcbr); 1319 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2); 1320 } 1321 1322 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on) 1323 { 1324 u32 val; 1325 int err; 1326 1327 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) 1328 1329 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1330 val &= ~VLV_GFX_CLK_FORCE_ON_BIT; 1331 if (force_on) 1332 val |= VLV_GFX_CLK_FORCE_ON_BIT; 1333 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val); 1334 1335 if (!force_on) 1336 return 0; 1337 1338 err = wait_for(COND, 20); 1339 if (err) 1340 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n", 1341 I915_READ(VLV_GTLC_SURVIVABILITY_REG)); 1342 1343 return err; 1344 #undef COND 1345 } 1346 1347 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow) 1348 { 1349 u32 val; 1350 int err = 0; 1351 1352 val = I915_READ(VLV_GTLC_WAKE_CTRL); 1353 val &= ~VLV_GTLC_ALLOWWAKEREQ; 1354 if (allow) 1355 val |= VLV_GTLC_ALLOWWAKEREQ; 1356 I915_WRITE(VLV_GTLC_WAKE_CTRL, val); 1357 POSTING_READ(VLV_GTLC_WAKE_CTRL); 1358 1359 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ 1360 allow) 1361 err = wait_for(COND, 1); 1362 if (err) 1363 DRM_ERROR("timeout disabling GT waking\n"); 1364 return err; 1365 #undef COND 1366 } 1367 1368 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, 1369 bool wait_for_on) 1370 { 1371 u32 mask; 1372 u32 val; 1373 int err; 1374 1375 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK; 1376 val = wait_for_on ? mask : 0; 1377 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) 1378 if (COND) 1379 return 0; 1380 1381 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n", 1382 wait_for_on ? "on" : "off", 1383 I915_READ(VLV_GTLC_PW_STATUS)); 1384 1385 /* 1386 * RC6 transitioning can be delayed up to 2 msec (see 1387 * valleyview_enable_rps), use 3 msec for safety. 1388 */ 1389 err = wait_for(COND, 3); 1390 if (err) 1391 DRM_ERROR("timeout waiting for GT wells to go %s\n", 1392 wait_for_on ? "on" : "off"); 1393 1394 return err; 1395 #undef COND 1396 } 1397 1398 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv) 1399 { 1400 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) 1401 return; 1402 1403 DRM_ERROR("GT register access while GT waking disabled\n"); 1404 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR); 1405 } 1406 1407 static int vlv_suspend_complete(struct drm_i915_private *dev_priv) 1408 { 1409 u32 mask; 1410 int err; 1411 1412 /* 1413 * Bspec defines the following GT well on flags as debug only, so 1414 * don't treat them as hard failures. 1415 */ 1416 (void)vlv_wait_for_gt_wells(dev_priv, false); 1417 1418 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS; 1419 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); 1420 1421 vlv_check_no_gt_access(dev_priv); 1422 1423 err = vlv_force_gfx_clock(dev_priv, true); 1424 if (err) 1425 goto err1; 1426 1427 err = vlv_allow_gt_wake(dev_priv, false); 1428 if (err) 1429 goto err2; 1430 1431 if (!IS_CHERRYVIEW(dev_priv->dev)) 1432 vlv_save_gunit_s0ix_state(dev_priv); 1433 1434 err = vlv_force_gfx_clock(dev_priv, false); 1435 if (err) 1436 goto err2; 1437 1438 return 0; 1439 1440 err2: 1441 /* For safety always re-enable waking and disable gfx clock forcing */ 1442 vlv_allow_gt_wake(dev_priv, true); 1443 err1: 1444 vlv_force_gfx_clock(dev_priv, false); 1445 1446 return err; 1447 } 1448 1449 static int vlv_resume_prepare(struct drm_i915_private *dev_priv, 1450 bool rpm_resume) 1451 { 1452 struct drm_device *dev = dev_priv->dev; 1453 int err; 1454 int ret; 1455 1456 /* 1457 * If any of the steps fail just try to continue, that's the best we 1458 * can do at this point. Return the first error code (which will also 1459 * leave RPM permanently disabled). 1460 */ 1461 ret = vlv_force_gfx_clock(dev_priv, true); 1462 1463 if (!IS_CHERRYVIEW(dev_priv->dev)) 1464 vlv_restore_gunit_s0ix_state(dev_priv); 1465 1466 err = vlv_allow_gt_wake(dev_priv, true); 1467 if (!ret) 1468 ret = err; 1469 1470 err = vlv_force_gfx_clock(dev_priv, false); 1471 if (!ret) 1472 ret = err; 1473 1474 vlv_check_no_gt_access(dev_priv); 1475 1476 if (rpm_resume) { 1477 intel_init_clock_gating(dev); 1478 i915_gem_restore_fences(dev); 1479 } 1480 1481 return ret; 1482 } 1483 1484 #if 0 1485 static int intel_runtime_suspend(struct device *device) 1486 { 1487 struct pci_dev *pdev = to_pci_dev(device); 1488 struct drm_device *dev = pci_get_drvdata(pdev); 1489 struct drm_i915_private *dev_priv = dev->dev_private; 1490 int ret; 1491 1492 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))) 1493 return -ENODEV; 1494 1495 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) 1496 return -ENODEV; 1497 1498 DRM_DEBUG_KMS("Suspending device\n"); 1499 1500 /* 1501 * We could deadlock here in case another thread holding struct_mutex 1502 * calls RPM suspend concurrently, since the RPM suspend will wait 1503 * first for this RPM suspend to finish. In this case the concurrent 1504 * RPM resume will be followed by its RPM suspend counterpart. Still 1505 * for consistency return -EAGAIN, which will reschedule this suspend. 1506 */ 1507 if (!mutex_trylock(&dev->struct_mutex)) { 1508 DRM_DEBUG_KMS("device lock contention, deffering suspend\n"); 1509 /* 1510 * Bump the expiration timestamp, otherwise the suspend won't 1511 * be rescheduled. 1512 */ 1513 pm_runtime_mark_last_busy(device); 1514 1515 return -EAGAIN; 1516 } 1517 /* 1518 * We are safe here against re-faults, since the fault handler takes 1519 * an RPM reference. 1520 */ 1521 i915_gem_release_all_mmaps(dev_priv); 1522 mutex_unlock(&dev->struct_mutex); 1523 1524 intel_suspend_gt_powersave(dev); 1525 intel_runtime_pm_disable_interrupts(dev_priv); 1526 1527 ret = intel_suspend_complete(dev_priv); 1528 if (ret) { 1529 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret); 1530 intel_runtime_pm_enable_interrupts(dev_priv); 1531 1532 return ret; 1533 } 1534 1535 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); 1536 intel_uncore_forcewake_reset(dev, false); 1537 dev_priv->pm.suspended = true; 1538 1539 /* 1540 * FIXME: We really should find a document that references the arguments 1541 * used below! 1542 */ 1543 if (IS_BROADWELL(dev)) { 1544 /* 1545 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop 1546 * being detected, and the call we do at intel_runtime_resume() 1547 * won't be able to restore them. Since PCI_D3hot matches the 1548 * actual specification and appears to be working, use it. 1549 */ 1550 intel_opregion_notify_adapter(dev, PCI_D3hot); 1551 } else { 1552 /* 1553 * current versions of firmware which depend on this opregion 1554 * notification have repurposed the D1 definition to mean 1555 * "runtime suspended" vs. what you would normally expect (D3) 1556 * to distinguish it from notifications that might be sent via 1557 * the suspend path. 1558 */ 1559 intel_opregion_notify_adapter(dev, PCI_D1); 1560 } 1561 1562 assert_forcewakes_inactive(dev_priv); 1563 1564 DRM_DEBUG_KMS("Device suspended\n"); 1565 return 0; 1566 } 1567 1568 static int intel_runtime_resume(struct device *device) 1569 { 1570 struct pci_dev *pdev = to_pci_dev(device); 1571 struct drm_device *dev = pci_get_drvdata(pdev); 1572 struct drm_i915_private *dev_priv = dev->dev_private; 1573 int ret = 0; 1574 1575 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))) 1576 return -ENODEV; 1577 1578 DRM_DEBUG_KMS("Resuming device\n"); 1579 1580 intel_opregion_notify_adapter(dev, PCI_D0); 1581 dev_priv->pm.suspended = false; 1582 1583 if (IS_GEN6(dev_priv)) 1584 intel_init_pch_refclk(dev); 1585 1586 if (IS_BROXTON(dev)) 1587 ret = bxt_resume_prepare(dev_priv); 1588 else if (IS_SKYLAKE(dev)) 1589 ret = skl_resume_prepare(dev_priv); 1590 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1591 hsw_disable_pc8(dev_priv); 1592 else if (IS_VALLEYVIEW(dev_priv)) 1593 ret = vlv_resume_prepare(dev_priv, true); 1594 1595 /* 1596 * No point of rolling back things in case of an error, as the best 1597 * we can do is to hope that things will still work (and disable RPM). 1598 */ 1599 i915_gem_init_swizzling(dev); 1600 gen6_update_ring_freq(dev); 1601 1602 intel_runtime_pm_enable_interrupts(dev_priv); 1603 intel_enable_gt_powersave(dev); 1604 1605 if (ret) 1606 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret); 1607 else 1608 DRM_DEBUG_KMS("Device resumed\n"); 1609 1610 return ret; 1611 } 1612 #endif 1613 1614 /* 1615 * This function implements common functionality of runtime and system 1616 * suspend sequence. 1617 */ 1618 static int intel_suspend_complete(struct drm_i915_private *dev_priv) 1619 { 1620 int ret; 1621 1622 if (IS_BROXTON(dev_priv)) 1623 ret = bxt_suspend_complete(dev_priv); 1624 else if (IS_SKYLAKE(dev_priv)) 1625 ret = skl_suspend_complete(dev_priv); 1626 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) 1627 ret = hsw_suspend_complete(dev_priv); 1628 else if (IS_VALLEYVIEW(dev_priv)) 1629 ret = vlv_suspend_complete(dev_priv); 1630 else 1631 ret = 0; 1632 1633 return ret; 1634 } 1635 1636 #if 0 1637 static const struct dev_pm_ops i915_pm_ops = { 1638 /* 1639 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, 1640 * PMSG_RESUME] 1641 */ 1642 .suspend = i915_pm_suspend, 1643 .suspend_late = i915_pm_suspend_late, 1644 .resume_early = i915_pm_resume_early, 1645 .resume = i915_pm_resume, 1646 1647 /* 1648 * S4 event handlers 1649 * @freeze, @freeze_late : called (1) before creating the 1650 * hibernation image [PMSG_FREEZE] and 1651 * (2) after rebooting, before restoring 1652 * the image [PMSG_QUIESCE] 1653 * @thaw, @thaw_early : called (1) after creating the hibernation 1654 * image, before writing it [PMSG_THAW] 1655 * and (2) after failing to create or 1656 * restore the image [PMSG_RECOVER] 1657 * @poweroff, @poweroff_late: called after writing the hibernation 1658 * image, before rebooting [PMSG_HIBERNATE] 1659 * @restore, @restore_early : called after rebooting and restoring the 1660 * hibernation image [PMSG_RESTORE] 1661 */ 1662 .freeze = i915_pm_suspend, 1663 .freeze_late = i915_pm_suspend_late, 1664 .thaw_early = i915_pm_resume_early, 1665 .thaw = i915_pm_resume, 1666 .poweroff = i915_pm_suspend, 1667 .poweroff_late = i915_pm_poweroff_late, 1668 .restore_early = i915_pm_resume_early, 1669 .restore = i915_pm_resume, 1670 1671 /* S0ix (via runtime suspend) event handlers */ 1672 .runtime_suspend = intel_runtime_suspend, 1673 .runtime_resume = intel_runtime_resume, 1674 }; 1675 1676 static const struct vm_operations_struct i915_gem_vm_ops = { 1677 .fault = i915_gem_fault, 1678 .open = drm_gem_vm_open, 1679 .close = drm_gem_vm_close, 1680 }; 1681 1682 static const struct file_operations i915_driver_fops = { 1683 .owner = THIS_MODULE, 1684 .open = drm_open, 1685 .release = drm_release, 1686 .unlocked_ioctl = drm_ioctl, 1687 .mmap = drm_gem_mmap, 1688 .poll = drm_poll, 1689 .read = drm_read, 1690 #ifdef CONFIG_COMPAT 1691 .compat_ioctl = i915_compat_ioctl, 1692 #endif 1693 .llseek = noop_llseek, 1694 }; 1695 #endif 1696 1697 static struct cdev_pager_ops i915_gem_vm_ops = { 1698 .cdev_pg_fault = i915_gem_fault, 1699 .cdev_pg_ctor = i915_gem_pager_ctor, 1700 .cdev_pg_dtor = i915_gem_pager_dtor 1701 }; 1702 1703 static struct drm_driver driver = { 1704 /* Don't use MTRRs here; the Xserver or userspace app should 1705 * deal with them for Intel hardware. 1706 */ 1707 .driver_features = 1708 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 1709 DRIVER_RENDER, 1710 .load = i915_driver_load, 1711 .unload = i915_driver_unload, 1712 .open = i915_driver_open, 1713 .lastclose = i915_driver_lastclose, 1714 .preclose = i915_driver_preclose, 1715 .postclose = i915_driver_postclose, 1716 1717 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ 1718 1719 #if defined(CONFIG_DEBUG_FS) 1720 .debugfs_init = i915_debugfs_init, 1721 .debugfs_cleanup = i915_debugfs_cleanup, 1722 #endif 1723 .gem_free_object = i915_gem_free_object, 1724 .gem_pager_ops = &i915_gem_vm_ops, 1725 1726 .dumb_create = i915_gem_dumb_create, 1727 .dumb_map_offset = i915_gem_mmap_gtt, 1728 .dumb_destroy = drm_gem_dumb_destroy, 1729 .ioctls = i915_ioctls, 1730 .name = DRIVER_NAME, 1731 .desc = DRIVER_DESC, 1732 .date = DRIVER_DATE, 1733 .major = DRIVER_MAJOR, 1734 .minor = DRIVER_MINOR, 1735 .patchlevel = DRIVER_PATCHLEVEL, 1736 }; 1737 1738 static int __init i915_init(void); 1739 1740 static int 1741 i915_attach(device_t kdev) 1742 { 1743 struct drm_device *dev = device_get_softc(kdev); 1744 int error; 1745 int dummy; 1746 1747 i915_init(); 1748 1749 dev->driver = &driver; 1750 error = drm_attach(kdev, i915_attach_list); 1751 1752 /* 1753 * XXX hack - give the kvm_console time to come up before X starts 1754 * messing with everything, avoiding at least one deadlock. 1755 */ 1756 tsleep(&dummy, 0, "i915_attach", hz*2); 1757 1758 return error; 1759 } 1760 1761 static device_method_t i915_methods[] = { 1762 /* Device interface */ 1763 DEVMETHOD(device_probe, i915_pci_probe), 1764 DEVMETHOD(device_attach, i915_attach), 1765 DEVMETHOD(device_suspend, i915_suspend_legacy), 1766 DEVMETHOD(device_resume, i915_resume_legacy), 1767 DEVMETHOD(device_detach, drm_release), 1768 DEVMETHOD_END 1769 }; 1770 1771 static driver_t i915_driver = { 1772 "drm", 1773 i915_methods, 1774 sizeof(struct drm_device) 1775 }; 1776 1777 static int __init i915_init(void) 1778 { 1779 driver.num_ioctls = i915_max_ioctl; 1780 1781 /* 1782 * Enable KMS by default, unless explicitly overriden by 1783 * either the i915.modeset prarameter or by the 1784 * vga_text_mode_force boot option. 1785 */ 1786 driver.driver_features |= DRIVER_MODESET; 1787 1788 if (i915.modeset == 0) 1789 driver.driver_features &= ~DRIVER_MODESET; 1790 1791 #ifdef CONFIG_VGA_CONSOLE 1792 if (vgacon_text_force() && i915.modeset == -1) 1793 driver.driver_features &= ~DRIVER_MODESET; 1794 #endif 1795 1796 if (!(driver.driver_features & DRIVER_MODESET)) { 1797 driver.get_vblank_timestamp = NULL; 1798 /* Silently fail loading to not upset userspace. */ 1799 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n"); 1800 return 0; 1801 } 1802 1803 /* 1804 * FIXME: Note that we're lying to the DRM core here so that we can get access 1805 * to the atomic ioctl and the atomic properties. Only plane operations on 1806 * a single CRTC will actually work. 1807 */ 1808 if (driver.driver_features & DRIVER_MODESET) 1809 driver.driver_features |= DRIVER_ATOMIC; 1810 1811 #if 0 1812 return drm_pci_init(&driver, &i915_pci_driver); 1813 #else 1814 return 1; 1815 #endif 1816 } 1817 1818 #if 0 1819 static void __exit i915_exit(void) 1820 { 1821 if (!(driver.driver_features & DRIVER_MODESET)) 1822 return; /* Never loaded a driver. */ 1823 1824 drm_pci_exit(&driver, &i915_pci_driver); 1825 } 1826 #endif 1827 1828 DRIVER_MODULE_ORDERED(i915, vgapci, i915_driver, drm_devclass, NULL, NULL, SI_ORDER_ANY); 1829 MODULE_DEPEND(i915, drm, 1, 1, 1); 1830 MODULE_DEPEND(i915, iicbus, 1, 1, 1); 1831 MODULE_DEPEND(i915, iic, 1, 1, 1); 1832 MODULE_DEPEND(i915, iicbb, 1, 1, 1); 1833 #ifdef CONFIG_ACPI 1834 MODULE_DEPEND(i915, acpi, 1, 1, 1); 1835 #endif 1836