1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 29 */ 30 31 #ifndef _I915_DRV_H_ 32 #define _I915_DRV_H_ 33 34 #include <sys/eventhandler.h> 35 36 #include <dev/agp/agp_i810.h> 37 #include "i915_reg.h" 38 #include "intel_bios.h" 39 #include "intel_ringbuffer.h" 40 #include <linux/completion.h> 41 #include <linux/workqueue.h> 42 43 /* General customization: 44 */ 45 46 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 47 48 #define DRIVER_NAME "i915" 49 #define DRIVER_DESC "Intel Graphics" 50 #define DRIVER_DATE "20080730" 51 52 MALLOC_DECLARE(DRM_I915_GEM); 53 54 enum i915_pipe { 55 PIPE_A = 0, 56 PIPE_B, 57 PIPE_C, 58 I915_MAX_PIPES 59 }; 60 #define pipe_name(p) ((p) + 'A') 61 #define I915_NUM_PIPE 2 62 63 enum transcoder { 64 TRANSCODER_A = 0, 65 TRANSCODER_B, 66 TRANSCODER_C, 67 TRANSCODER_EDP = 0xF, 68 }; 69 #define transcoder_name(t) ((t) + 'A') 70 71 enum plane { 72 PLANE_A = 0, 73 PLANE_B, 74 PLANE_C, 75 }; 76 #define plane_name(p) ((p) + 'A') 77 78 enum port { 79 PORT_A = 0, 80 PORT_B, 81 PORT_C, 82 PORT_D, 83 PORT_E, 84 I915_MAX_PORTS 85 }; 86 #define port_name(p) ((p) + 'A') 87 88 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 89 90 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 91 92 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 93 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 94 if ((intel_encoder)->base.crtc == (__crtc)) 95 96 struct intel_pch_pll { 97 int refcount; /* count of number of CRTCs sharing this PLL */ 98 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 99 bool on; /* is the PLL actually active? Disabled during modeset */ 100 int pll_reg; 101 int fp0_reg; 102 int fp1_reg; 103 }; 104 #define I915_NUM_PLLS 2 105 106 struct intel_ddi_plls { 107 int spll_refcount; 108 int wrpll1_refcount; 109 int wrpll2_refcount; 110 }; 111 112 /* Interface history: 113 * 114 * 1.1: Original. 115 * 1.2: Add Power Management 116 * 1.3: Add vblank support 117 * 1.4: Fix cmdbuffer path, add heap destroy 118 * 1.5: Add vblank pipe configuration 119 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 120 * - Support vertical blank on secondary display pipe 121 */ 122 #define DRIVER_MAJOR 1 123 #define DRIVER_MINOR 6 124 #define DRIVER_PATCHLEVEL 0 125 126 #define WATCH_COHERENCY 0 127 #define WATCH_LISTS 0 128 #define WATCH_GTT 0 129 130 #define I915_GEM_PHYS_CURSOR_0 1 131 #define I915_GEM_PHYS_CURSOR_1 2 132 #define I915_GEM_PHYS_OVERLAY_REGS 3 133 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 134 135 struct drm_i915_gem_phys_object { 136 int id; 137 drm_dma_handle_t *handle; 138 struct drm_i915_gem_object *cur_obj; 139 }; 140 141 struct opregion_header; 142 struct opregion_acpi; 143 struct opregion_swsci; 144 struct opregion_asle; 145 struct drm_i915_private; 146 147 struct intel_opregion { 148 struct opregion_header __iomem *header; 149 struct opregion_acpi __iomem *acpi; 150 struct opregion_swsci __iomem *swsci; 151 struct opregion_asle __iomem *asle; 152 void __iomem *vbt; 153 u32 __iomem *lid_state; 154 }; 155 #define OPREGION_SIZE (8*1024) 156 157 struct intel_overlay; 158 struct intel_overlay_error_state; 159 160 struct drm_i915_master_private { 161 drm_local_map_t *sarea; 162 struct _drm_i915_sarea *sarea_priv; 163 }; 164 #define I915_FENCE_REG_NONE -1 165 #define I915_MAX_NUM_FENCES 16 166 /* 16 fences + sign bit for FENCE_REG_NONE */ 167 #define I915_MAX_NUM_FENCE_BITS 5 168 169 struct drm_i915_fence_reg { 170 struct list_head lru_list; 171 struct drm_i915_gem_object *obj; 172 int pin_count; 173 }; 174 175 struct sdvo_device_mapping { 176 u8 initialized; 177 u8 dvo_port; 178 u8 slave_addr; 179 u8 dvo_wiring; 180 u8 i2c_pin; 181 u8 ddc_pin; 182 }; 183 184 struct drm_i915_error_state { 185 u32 eir; 186 u32 pgtbl_er; 187 u32 ier; 188 bool waiting[I915_NUM_RINGS]; 189 u32 pipestat[I915_MAX_PIPES]; 190 u32 tail[I915_NUM_RINGS]; 191 u32 head[I915_NUM_RINGS]; 192 u32 ipeir[I915_NUM_RINGS]; 193 u32 ipehr[I915_NUM_RINGS]; 194 u32 instdone[I915_NUM_RINGS]; 195 u32 acthd[I915_NUM_RINGS]; 196 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 197 /* our own tracking of ring head and tail */ 198 u32 cpu_ring_head[I915_NUM_RINGS]; 199 u32 cpu_ring_tail[I915_NUM_RINGS]; 200 u32 error; /* gen6+ */ 201 u32 instpm[I915_NUM_RINGS]; 202 u32 instps[I915_NUM_RINGS]; 203 u32 instdone1; 204 u32 seqno[I915_NUM_RINGS]; 205 u64 bbaddr; 206 u32 fault_reg[I915_NUM_RINGS]; 207 u32 done_reg; 208 u32 faddr[I915_NUM_RINGS]; 209 u64 fence[I915_MAX_NUM_FENCES]; 210 struct timeval time; 211 struct drm_i915_error_ring { 212 struct drm_i915_error_object { 213 int page_count; 214 u32 gtt_offset; 215 u32 *pages[0]; 216 } *ringbuffer, *batchbuffer; 217 struct drm_i915_error_request { 218 long jiffies; 219 u32 seqno; 220 u32 tail; 221 } *requests; 222 int num_requests; 223 } ring[I915_NUM_RINGS]; 224 struct drm_i915_error_buffer { 225 u32 size; 226 u32 name; 227 u32 rseqno, wseqno; 228 u32 gtt_offset; 229 u32 read_domains; 230 u32 write_domain; 231 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 232 s32 pinned:2; 233 u32 tiling:2; 234 u32 dirty:1; 235 u32 purgeable:1; 236 s32 ring:4; 237 u32 cache_level:2; 238 } *active_bo, *pinned_bo; 239 u32 active_bo_count, pinned_bo_count; 240 struct intel_overlay_error_state *overlay; 241 struct intel_display_error_state *display; 242 }; 243 244 struct drm_i915_display_funcs { 245 void (*dpms)(struct drm_crtc *crtc, int mode); 246 bool (*fbc_enabled)(struct drm_device *dev); 247 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 248 void (*disable_fbc)(struct drm_device *dev); 249 int (*get_display_clock_speed)(struct drm_device *dev); 250 int (*get_fifo_size)(struct drm_device *dev, int plane); 251 void (*update_wm)(struct drm_device *dev); 252 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 253 uint32_t sprite_width, int pixel_size); 254 void (*update_linetime_wm)(struct drm_device *dev, int pipe, 255 struct drm_display_mode *mode); 256 int (*crtc_mode_set)(struct drm_crtc *crtc, 257 struct drm_display_mode *mode, 258 struct drm_display_mode *adjusted_mode, 259 int x, int y, 260 struct drm_framebuffer *old_fb); 261 void (*write_eld)(struct drm_connector *connector, 262 struct drm_crtc *crtc); 263 void (*fdi_link_train)(struct drm_crtc *crtc); 264 void (*init_clock_gating)(struct drm_device *dev); 265 void (*init_pch_clock_gating)(struct drm_device *dev); 266 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 267 struct drm_framebuffer *fb, 268 struct drm_i915_gem_object *obj); 269 void (*force_wake_get)(struct drm_i915_private *dev_priv); 270 void (*force_wake_put)(struct drm_i915_private *dev_priv); 271 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 272 int x, int y); 273 /* clock updates for mode set */ 274 /* cursor updates */ 275 /* render clock increase/decrease */ 276 /* display clock increase/decrease */ 277 /* pll clock increase/decrease */ 278 }; 279 280 struct drm_i915_gt_funcs { 281 void (*force_wake_get)(struct drm_i915_private *dev_priv); 282 void (*force_wake_put)(struct drm_i915_private *dev_priv); 283 }; 284 285 #define DEV_INFO_FLAGS \ 286 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ 287 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ 288 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ 289 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ 290 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ 291 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ 292 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ 293 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ 294 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ 295 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ 296 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ 297 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ 298 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ 299 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ 300 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ 301 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ 302 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ 303 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ 304 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ 305 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ 306 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ 307 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ 308 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ 309 DEV_INFO_FLAG(has_llc) 310 311 struct intel_device_info { 312 u8 gen; 313 u8 is_mobile:1; 314 u8 is_i85x:1; 315 u8 is_i915g:1; 316 u8 is_i945gm:1; 317 u8 is_g33:1; 318 u8 need_gfx_hws:1; 319 u8 is_g4x:1; 320 u8 is_pineview:1; 321 u8 is_broadwater:1; 322 u8 is_crestline:1; 323 u8 is_ivybridge:1; 324 u8 is_valleyview:1; 325 u8 has_force_wake:1; 326 u8 is_haswell:1; 327 u8 has_fbc:1; 328 u8 has_pipe_cxsr:1; 329 u8 has_hotplug:1; 330 u8 cursor_needs_physical:1; 331 u8 has_overlay:1; 332 u8 overlay_needs_physical:1; 333 u8 supports_tv:1; 334 u8 has_bsd_ring:1; 335 u8 has_blt_ring:1; 336 u8 has_llc:1; 337 }; 338 339 #define I915_PPGTT_PD_ENTRIES 512 340 #define I915_PPGTT_PT_ENTRIES 1024 341 struct i915_hw_ppgtt { 342 unsigned num_pd_entries; 343 vm_page_t *pt_pages; 344 uint32_t pd_offset; 345 vm_paddr_t *pt_dma_addr; 346 vm_paddr_t scratch_page_dma_addr; 347 }; 348 349 enum no_fbc_reason { 350 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 351 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 352 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 353 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 354 FBC_BAD_PLANE, /* fbc not supported on plane */ 355 FBC_NOT_TILED, /* buffer not tiled */ 356 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 357 FBC_MODULE_PARAM, 358 }; 359 360 /* defined intel_pm.c */ 361 extern struct lock mchdev_lock; 362 363 struct mem_block { 364 struct mem_block *next; 365 struct mem_block *prev; 366 int start; 367 int size; 368 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 369 }; 370 371 struct opregion_header; 372 struct opregion_acpi; 373 struct opregion_swsci; 374 struct opregion_asle; 375 376 #define I915_FENCE_REG_NONE -1 377 #define I915_MAX_NUM_FENCES 16 378 /* 16 fences + sign bit for FENCE_REG_NONE */ 379 #define I915_MAX_NUM_FENCE_BITS 5 380 381 enum intel_pch { 382 PCH_NONE = 0, /* No PCH present */ 383 PCH_IBX, /* Ibexpeak PCH */ 384 PCH_CPT, /* Cougarpoint PCH */ 385 PCH_LPT, /* Lynxpoint PCH */ 386 }; 387 388 enum intel_sbi_destination { 389 SBI_ICLK, 390 SBI_MPHY, 391 }; 392 393 #define QUIRK_PIPEA_FORCE (1<<0) 394 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 395 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 396 397 struct intel_fbdev; 398 struct intel_fbc_work; 399 400 struct intel_gmbus { 401 u32 force_bit; 402 u32 reg0; 403 u32 gpio_reg; 404 struct drm_i915_private *dev_priv; 405 }; 406 407 struct i915_suspend_saved_registers { 408 u8 saveLBB; 409 u32 saveDSPACNTR; 410 u32 saveDSPBCNTR; 411 u32 saveDSPARB; 412 u32 savePIPEACONF; 413 u32 savePIPEBCONF; 414 u32 savePIPEASRC; 415 u32 savePIPEBSRC; 416 u32 saveFPA0; 417 u32 saveFPA1; 418 u32 saveDPLL_A; 419 u32 saveDPLL_A_MD; 420 u32 saveHTOTAL_A; 421 u32 saveHBLANK_A; 422 u32 saveHSYNC_A; 423 u32 saveVTOTAL_A; 424 u32 saveVBLANK_A; 425 u32 saveVSYNC_A; 426 u32 saveBCLRPAT_A; 427 u32 saveTRANSACONF; 428 u32 saveTRANS_HTOTAL_A; 429 u32 saveTRANS_HBLANK_A; 430 u32 saveTRANS_HSYNC_A; 431 u32 saveTRANS_VTOTAL_A; 432 u32 saveTRANS_VBLANK_A; 433 u32 saveTRANS_VSYNC_A; 434 u32 savePIPEASTAT; 435 u32 saveDSPASTRIDE; 436 u32 saveDSPASIZE; 437 u32 saveDSPAPOS; 438 u32 saveDSPAADDR; 439 u32 saveDSPASURF; 440 u32 saveDSPATILEOFF; 441 u32 savePFIT_PGM_RATIOS; 442 u32 saveBLC_HIST_CTL; 443 u32 saveBLC_PWM_CTL; 444 u32 saveBLC_PWM_CTL2; 445 u32 saveBLC_CPU_PWM_CTL; 446 u32 saveBLC_CPU_PWM_CTL2; 447 u32 saveFPB0; 448 u32 saveFPB1; 449 u32 saveDPLL_B; 450 u32 saveDPLL_B_MD; 451 u32 saveHTOTAL_B; 452 u32 saveHBLANK_B; 453 u32 saveHSYNC_B; 454 u32 saveVTOTAL_B; 455 u32 saveVBLANK_B; 456 u32 saveVSYNC_B; 457 u32 saveBCLRPAT_B; 458 u32 saveTRANSBCONF; 459 u32 saveTRANS_HTOTAL_B; 460 u32 saveTRANS_HBLANK_B; 461 u32 saveTRANS_HSYNC_B; 462 u32 saveTRANS_VTOTAL_B; 463 u32 saveTRANS_VBLANK_B; 464 u32 saveTRANS_VSYNC_B; 465 u32 savePIPEBSTAT; 466 u32 saveDSPBSTRIDE; 467 u32 saveDSPBSIZE; 468 u32 saveDSPBPOS; 469 u32 saveDSPBADDR; 470 u32 saveDSPBSURF; 471 u32 saveDSPBTILEOFF; 472 u32 saveVGA0; 473 u32 saveVGA1; 474 u32 saveVGA_PD; 475 u32 saveVGACNTRL; 476 u32 saveADPA; 477 u32 saveLVDS; 478 u32 savePP_ON_DELAYS; 479 u32 savePP_OFF_DELAYS; 480 u32 saveDVOA; 481 u32 saveDVOB; 482 u32 saveDVOC; 483 u32 savePP_ON; 484 u32 savePP_OFF; 485 u32 savePP_CONTROL; 486 u32 savePP_DIVISOR; 487 u32 savePFIT_CONTROL; 488 u32 save_palette_a[256]; 489 u32 save_palette_b[256]; 490 u32 saveDPFC_CB_BASE; 491 u32 saveFBC_CFB_BASE; 492 u32 saveFBC_LL_BASE; 493 u32 saveFBC_CONTROL; 494 u32 saveFBC_CONTROL2; 495 u32 saveIER; 496 u32 saveIIR; 497 u32 saveIMR; 498 u32 saveDEIER; 499 u32 saveDEIMR; 500 u32 saveGTIER; 501 u32 saveGTIMR; 502 u32 saveFDI_RXA_IMR; 503 u32 saveFDI_RXB_IMR; 504 u32 saveCACHE_MODE_0; 505 u32 saveMI_ARB_STATE; 506 u32 saveSWF0[16]; 507 u32 saveSWF1[16]; 508 u32 saveSWF2[3]; 509 u8 saveMSR; 510 u8 saveSR[8]; 511 u8 saveGR[25]; 512 u8 saveAR_INDEX; 513 u8 saveAR[21]; 514 u8 saveDACMASK; 515 u8 saveCR[37]; 516 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 517 u32 saveCURACNTR; 518 u32 saveCURAPOS; 519 u32 saveCURABASE; 520 u32 saveCURBCNTR; 521 u32 saveCURBPOS; 522 u32 saveCURBBASE; 523 u32 saveCURSIZE; 524 u32 saveDP_B; 525 u32 saveDP_C; 526 u32 saveDP_D; 527 u32 savePIPEA_GMCH_DATA_M; 528 u32 savePIPEB_GMCH_DATA_M; 529 u32 savePIPEA_GMCH_DATA_N; 530 u32 savePIPEB_GMCH_DATA_N; 531 u32 savePIPEA_DP_LINK_M; 532 u32 savePIPEB_DP_LINK_M; 533 u32 savePIPEA_DP_LINK_N; 534 u32 savePIPEB_DP_LINK_N; 535 u32 saveFDI_RXA_CTL; 536 u32 saveFDI_TXA_CTL; 537 u32 saveFDI_RXB_CTL; 538 u32 saveFDI_TXB_CTL; 539 u32 savePFA_CTL_1; 540 u32 savePFB_CTL_1; 541 u32 savePFA_WIN_SZ; 542 u32 savePFB_WIN_SZ; 543 u32 savePFA_WIN_POS; 544 u32 savePFB_WIN_POS; 545 u32 savePCH_DREF_CONTROL; 546 u32 saveDISP_ARB_CTL; 547 u32 savePIPEA_DATA_M1; 548 u32 savePIPEA_DATA_N1; 549 u32 savePIPEA_LINK_M1; 550 u32 savePIPEA_LINK_N1; 551 u32 savePIPEB_DATA_M1; 552 u32 savePIPEB_DATA_N1; 553 u32 savePIPEB_LINK_M1; 554 u32 savePIPEB_LINK_N1; 555 u32 saveMCHBAR_RENDER_STANDBY; 556 u32 savePCH_PORT_HOTPLUG; 557 }; 558 559 struct intel_gen6_power_mgmt { 560 struct work_struct work; 561 u32 pm_iir; 562 /* lock - irqsave spinlock that protectects the work_struct and 563 * pm_iir. */ 564 struct spinlock lock; 565 566 /* The below variables an all the rps hw state are protected by 567 * dev->struct mutext. */ 568 u8 cur_delay; 569 u8 min_delay; 570 u8 max_delay; 571 572 struct delayed_work delayed_resume_work; 573 574 /* 575 * Protects RPS/RC6 register access and PCU communication. 576 * Must be taken after struct_mutex if nested. 577 */ 578 struct lock hw_lock; 579 }; 580 581 struct intel_ilk_power_mgmt { 582 u8 cur_delay; 583 u8 min_delay; 584 u8 max_delay; 585 u8 fmax; 586 u8 fstart; 587 588 u64 last_count1; 589 unsigned long last_time1; 590 unsigned long chipset_power; 591 u64 last_count2; 592 struct timespec last_time2; 593 unsigned long gfx_power; 594 u8 corr; 595 596 int c_m; 597 int r_t; 598 599 struct drm_i915_gem_object *pwrctx; 600 struct drm_i915_gem_object *renderctx; 601 }; 602 603 struct i915_dri1_state { 604 unsigned allow_batchbuffer : 1; 605 u32 __iomem *gfx_hws_cpu_addr; 606 607 unsigned int cpp; 608 int back_offset; 609 int front_offset; 610 int current_page; 611 int page_flipping; 612 613 uint32_t counter; 614 }; 615 616 struct intel_l3_parity { 617 u32 *remap_info; 618 struct work_struct error_work; 619 }; 620 621 typedef struct drm_i915_private { 622 struct drm_device *dev; 623 624 const struct intel_device_info *info; 625 626 device_t *gmbus_bridge; 627 device_t *bbbus_bridge; 628 device_t *gmbus; 629 device_t *bbbus; 630 631 /** gmbus_sx protects against concurrent usage of the single hw gmbus 632 * controller on different i2c buses. */ 633 struct lock gmbus_lock; 634 635 int relative_constants_mode; 636 637 drm_local_map_t *sarea; 638 drm_local_map_t *mmio_map; 639 640 struct drm_i915_gt_funcs gt; 641 /** gt_fifo_count and the subsequent register write are synchronized 642 * with dev->struct_mutex. */ 643 unsigned gt_fifo_count; 644 /** forcewake_count is protected by gt_lock */ 645 unsigned forcewake_count; 646 /** gt_lock is also taken in irq contexts. */ 647 struct lock gt_lock; 648 649 drm_i915_sarea_t *sarea_priv; 650 struct intel_ring_buffer ring[I915_NUM_RINGS]; 651 uint32_t next_seqno; 652 653 drm_dma_handle_t *status_page_dmah; 654 struct resource *mch_res; 655 656 void *hw_status_page; 657 dma_addr_t dma_status_page; 658 uint32_t counter; 659 unsigned int status_gfx_addr; 660 drm_local_map_t hws_map; 661 struct drm_gem_object *hws_obj; 662 663 struct drm_i915_gem_object *pwrctx; 664 struct drm_i915_gem_object *renderctx; 665 666 unsigned int cpp; 667 int back_offset; 668 int front_offset; 669 int current_page; 670 int page_flipping; 671 672 atomic_t irq_received; 673 u32 trace_irq_seqno; 674 675 /** Cached value of IER to avoid reads in updating the bitfield */ 676 u32 pipestat[2]; 677 u32 irq_mask; 678 u32 gt_irq_mask; 679 u32 pch_irq_mask; 680 struct lock irq_lock; 681 682 u32 hotplug_supported_mask; 683 struct work_struct hotplug_work; 684 685 int tex_lru_log_granularity; 686 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 687 int vblank_pipe; 688 689 int num_pipe; 690 int num_pch_pll; 691 692 /* For hangcheck timer */ 693 #define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 694 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 695 struct timer_list hangcheck_timer; 696 int hangcheck_count; 697 uint32_t last_acthd[I915_NUM_RINGS]; 698 uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; 699 700 uint32_t last_acthd_bsd; 701 uint32_t last_acthd_blt; 702 uint32_t last_instdone; 703 uint32_t last_instdone1; 704 705 unsigned int stop_rings; 706 707 struct intel_opregion opregion; 708 709 /* overlay */ 710 struct intel_overlay *overlay; 711 bool sprite_scaling_enabled; 712 713 /* LVDS info */ 714 int backlight_level; /* restore backlight to this value */ 715 bool backlight_enabled; 716 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 717 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 718 719 /* Feature bits from the VBIOS */ 720 unsigned int int_tv_support:1; 721 unsigned int lvds_dither:1; 722 unsigned int lvds_vbt:1; 723 unsigned int int_crt_support:1; 724 unsigned int lvds_use_ssc:1; 725 unsigned int display_clock_mode:1; 726 unsigned int fdi_rx_polarity_inverted:1; 727 int lvds_ssc_freq; 728 struct { 729 int rate; 730 int lanes; 731 int preemphasis; 732 int vswing; 733 734 bool initialized; 735 bool support; 736 int bpp; 737 struct edp_power_seq pps; 738 } edp; 739 bool no_aux_handshake; 740 741 int crt_ddc_pin; 742 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 743 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 744 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 745 746 unsigned int fsb_freq, mem_freq, is_ddr3; 747 748 /* Display functions */ 749 struct drm_i915_display_funcs display; 750 751 /* PCH chipset type */ 752 enum intel_pch pch_type; 753 unsigned short pch_id; 754 755 unsigned long quirks; 756 757 /* Register state */ 758 bool modeset_on_lid; 759 760 struct { 761 /** Bridge to intel-gtt-ko */ 762 const struct intel_gtt *gtt; 763 /** Memory allocator for GTT stolen memory */ 764 struct drm_mm stolen; 765 /** Memory allocator for GTT */ 766 struct drm_mm gtt_space; 767 /** List of all objects in gtt_space. Used to restore gtt 768 * mappings on resume */ 769 struct list_head gtt_list; 770 771 /** Usable portion of the GTT for GEM */ 772 unsigned long gtt_start; 773 unsigned long gtt_mappable_end; 774 unsigned long gtt_end; 775 776 /** PPGTT used for aliasing the PPGTT with the GTT */ 777 struct i915_hw_ppgtt *aliasing_ppgtt; 778 779 /** 780 * List of objects currently involved in rendering from the 781 * ringbuffer. 782 * 783 * Includes buffers having the contents of their GPU caches 784 * flushed, not necessarily primitives. last_rendering_seqno 785 * represents when the rendering involved will be completed. 786 * 787 * A reference is held on the buffer while on this list. 788 */ 789 struct list_head active_list; 790 791 /** 792 * LRU list of objects which are not in the ringbuffer and 793 * are ready to unbind, but are still in the GTT. 794 * 795 * last_rendering_seqno is 0 while an object is in this list. 796 * 797 * A reference is not held on the buffer while on this list, 798 * as merely being GTT-bound shouldn't prevent its being 799 * freed, and we'll pull it off the list in the free path. 800 */ 801 struct list_head inactive_list; 802 803 /** LRU list of objects with fence regs on them. */ 804 struct list_head fence_list; 805 806 /** 807 * We leave the user IRQ off as much as possible, 808 * but this means that requests will finish and never 809 * be retired once the system goes idle. Set a timer to 810 * fire periodically while the ring is running. When it 811 * fires, go retire requests. 812 */ 813 struct delayed_work retire_work; 814 815 /** 816 * Are we in a non-interruptible section of code like 817 * modesetting? 818 */ 819 bool interruptible; 820 821 uint32_t next_gem_seqno; 822 823 /** 824 * Waiting sequence number, if any 825 */ 826 uint32_t waiting_gem_seqno; 827 828 /** 829 * Last seq seen at irq time 830 */ 831 uint32_t irq_gem_seqno; 832 833 /** 834 * Flag if the X Server, and thus DRM, is not currently in 835 * control of the device. 836 * 837 * This is set between LeaveVT and EnterVT. It needs to be 838 * replaced with a semaphore. It also needs to be 839 * transitioned away from for kernel modesetting. 840 */ 841 int suspended; 842 843 /** 844 * Flag if the hardware appears to be wedged. 845 * 846 * This is set when attempts to idle the device timeout. 847 * It prevents command submission from occuring and makes 848 * every pending request fail 849 */ 850 atomic_t wedged; 851 852 /** Bit 6 swizzling required for X tiling */ 853 uint32_t bit_6_swizzle_x; 854 /** Bit 6 swizzling required for Y tiling */ 855 uint32_t bit_6_swizzle_y; 856 857 /* storage for physical objects */ 858 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 859 860 /* accounting, useful for userland debugging */ 861 size_t gtt_total; 862 size_t mappable_gtt_total; 863 size_t object_memory; 864 u32 object_count; 865 866 eventhandler_tag i915_lowmem; 867 } mm; 868 869 /* Kernel Modesetting */ 870 871 struct sdvo_device_mapping sdvo_mappings[2]; 872 /* indicate whether the LVDS_BORDER should be enabled or not */ 873 unsigned int lvds_border_bits; 874 /* Panel fitter placement and size for Ironlake+ */ 875 u32 pch_pf_pos, pch_pf_size; 876 877 struct drm_crtc *plane_to_crtc_mapping[3]; 878 struct drm_crtc *pipe_to_crtc_mapping[3]; 879 wait_queue_head_t pending_flip_queue; 880 881 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 882 struct intel_ddi_plls ddi_plls; 883 884 /* Reclocking support */ 885 bool render_reclock_avail; 886 bool lvds_downclock_avail; 887 /* indicates the reduced downclock for LVDS*/ 888 int lvds_downclock; 889 struct task idle_task; 890 struct callout idle_callout; 891 bool busy; 892 u16 orig_clock; 893 int child_dev_num; 894 struct child_device_config *child_dev; 895 struct drm_connector *int_lvds_connector; 896 struct drm_connector *int_edp_connector; 897 898 device_t bridge_dev; 899 bool mchbar_need_disable; 900 901 struct intel_l3_parity l3_parity; 902 903 int mch_res_rid; 904 905 /* gen6+ rps state */ 906 struct intel_gen6_power_mgmt rps; 907 908 /* ilk-only ips/rps state. Everything in here is protected by the global 909 * mchdev_lock in intel_pm.c */ 910 struct intel_ilk_power_mgmt ips; 911 912 enum no_fbc_reason no_fbc_reason; 913 914 struct lock *mchdev_lock; 915 916 unsigned long cfb_size; 917 unsigned int cfb_fb; 918 int cfb_plane; 919 int cfb_y; 920 struct intel_fbc_work *fbc_work; 921 922 struct lock error_lock; 923 /* Protected by dev->error_lock. */ 924 struct drm_i915_error_state *first_error; 925 struct work_struct error_work; 926 struct completion error_completion; 927 struct workqueue_struct *wq; 928 929 unsigned long last_gpu_reset; 930 931 struct intel_fbdev *fbdev; 932 933 struct drm_property *broadcast_rgb_property; 934 struct drm_property *force_audio_property; 935 936 struct i915_suspend_saved_registers regfile; 937 938 /* Old dri1 support infrastructure, beware the dragons ya fools entering 939 * here! */ 940 struct i915_dri1_state dri1; 941 } drm_i915_private_t; 942 943 /* Iterate over initialised rings */ 944 #define for_each_ring(ring__, dev_priv__, i__) \ 945 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 946 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 947 948 enum hdmi_force_audio { 949 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 950 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 951 HDMI_AUDIO_AUTO, /* trust EDID */ 952 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 953 }; 954 955 enum i915_cache_level { 956 I915_CACHE_NONE, 957 I915_CACHE_LLC, 958 I915_CACHE_LLC_MLC, /* gen6+ */ 959 }; 960 961 enum intel_chip_family { 962 CHIP_I8XX = 0x01, 963 CHIP_I9XX = 0x02, 964 CHIP_I915 = 0x04, 965 CHIP_I965 = 0x08, 966 }; 967 968 /** driver private structure attached to each drm_gem_object */ 969 struct drm_i915_gem_object { 970 struct drm_gem_object base; 971 972 /** Current space allocated to this object in the GTT, if any. */ 973 struct drm_mm_node *gtt_space; 974 struct list_head gtt_list; 975 /** This object's place on the active/inactive lists */ 976 struct list_head ring_list; 977 struct list_head mm_list; 978 /** This object's place on GPU write list */ 979 struct list_head gpu_write_list; 980 /** This object's place in the batchbuffer or on the eviction list */ 981 struct list_head exec_list; 982 983 /** 984 * This is set if the object is on the active lists (has pending 985 * rendering and so a non-zero seqno), and is not set if it i s on 986 * inactive (ready to be unbound) list. 987 */ 988 unsigned int active:1; 989 990 /** 991 * This is set if the object has been written to since last bound 992 * to the GTT 993 */ 994 unsigned int dirty:1; 995 996 /** 997 * Fence register bits (if any) for this object. Will be set 998 * as needed when mapped into the GTT. 999 * Protected by dev->struct_mutex. 1000 */ 1001 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1002 1003 /** 1004 * Advice: are the backing pages purgeable? 1005 */ 1006 unsigned int madv:2; 1007 1008 /** 1009 * Current tiling mode for the object. 1010 */ 1011 unsigned int tiling_mode:2; 1012 /** 1013 * Whether the tiling parameters for the currently associated fence 1014 * register have changed. Note that for the purposes of tracking 1015 * tiling changes we also treat the unfenced register, the register 1016 * slot that the object occupies whilst it executes a fenced 1017 * command (such as BLT on gen2/3), as a "fence". 1018 */ 1019 unsigned int fence_dirty:1; 1020 1021 /** How many users have pinned this object in GTT space. The following 1022 * users can each hold at most one reference: pwrite/pread, pin_ioctl 1023 * (via user_pin_count), execbuffer (objects are not allowed multiple 1024 * times for the same batchbuffer), and the framebuffer code. When 1025 * switching/pageflipping, the framebuffer code has at most two buffers 1026 * pinned per crtc. 1027 * 1028 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1029 * bits with absolutely no headroom. So use 4 bits. */ 1030 unsigned int pin_count:4; 1031 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1032 1033 /** 1034 * Is the object at the current location in the gtt mappable and 1035 * fenceable? Used to avoid costly recalculations. 1036 */ 1037 unsigned int map_and_fenceable:1; 1038 1039 /** 1040 * Whether the current gtt mapping needs to be mappable (and isn't just 1041 * mappable by accident). Track pin and fault separate for a more 1042 * accurate mappable working set. 1043 */ 1044 unsigned int fault_mappable:1; 1045 unsigned int pin_mappable:1; 1046 1047 /* 1048 * Is the GPU currently using a fence to access this buffer, 1049 */ 1050 unsigned int pending_fenced_gpu_access:1; 1051 unsigned int fenced_gpu_access:1; 1052 1053 unsigned int cache_level:2; 1054 1055 unsigned int has_aliasing_ppgtt_mapping:1; 1056 unsigned int has_global_gtt_mapping:1; 1057 1058 vm_page_t *pages; 1059 1060 /** 1061 * Used for performing relocations during execbuffer insertion. 1062 */ 1063 struct hlist_node exec_node; 1064 unsigned long exec_handle; 1065 struct drm_i915_gem_exec_object2 *exec_entry; 1066 1067 /** 1068 * Current offset of the object in GTT space. 1069 * 1070 * This is the same as gtt_space->start 1071 */ 1072 uint32_t gtt_offset; 1073 1074 struct intel_ring_buffer *ring; 1075 1076 /** Breadcrumb of last rendering to the buffer. */ 1077 uint32_t last_read_seqno; 1078 uint32_t last_write_seqno; 1079 1080 /** Breadcrumb of last fenced GPU access to the buffer. */ 1081 uint32_t last_fenced_seqno; 1082 1083 /** Current tiling stride for the object, if it's tiled. */ 1084 uint32_t stride; 1085 1086 /** Record of address bit 17 of each page at last unbind. */ 1087 unsigned long *bit_17; 1088 1089 /** User space pin count and filp owning the pin */ 1090 uint32_t user_pin_count; 1091 struct drm_file *pin_filp; 1092 1093 /** for phy allocated objects */ 1094 struct drm_i915_gem_phys_object *phys_obj; 1095 1096 /** 1097 * Number of crtcs where this object is currently the fb, but 1098 * will be page flipped away on the next vblank. When it 1099 * reaches 0, dev_priv->pending_flip_queue will be woken up. 1100 */ 1101 atomic_t pending_flip; 1102 }; 1103 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) 1104 1105 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1106 1107 /** 1108 * Request queue structure. 1109 * 1110 * The request queue allows us to note sequence numbers that have been emitted 1111 * and may be associated with active buffers to be retired. 1112 * 1113 * By keeping this list, we can avoid having to do questionable 1114 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1115 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1116 */ 1117 struct drm_i915_gem_request { 1118 /** On Which ring this request was generated */ 1119 struct intel_ring_buffer *ring; 1120 1121 /** GEM sequence number associated with this request. */ 1122 uint32_t seqno; 1123 1124 /** Postion in the ringbuffer of the end of the request */ 1125 u32 tail; 1126 1127 /** Time at which this request was emitted, in jiffies. */ 1128 unsigned long emitted_jiffies; 1129 1130 /** global list entry for this request */ 1131 struct list_head list; 1132 1133 struct drm_i915_file_private *file_priv; 1134 /** file_priv list entry for this request */ 1135 struct list_head client_list; 1136 }; 1137 1138 struct drm_i915_file_private { 1139 struct { 1140 struct spinlock lock; 1141 struct list_head request_list; 1142 } mm; 1143 }; 1144 1145 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1146 1147 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1148 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1149 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1150 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1151 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1152 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1153 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1154 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1155 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1156 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1157 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1158 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1159 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1160 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1161 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1162 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1163 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1164 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1165 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1166 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1167 (dev)->pci_device == 0x0152 || \ 1168 (dev)->pci_device == 0x015a) 1169 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1170 (dev)->pci_device == 0x0106 || \ 1171 (dev)->pci_device == 0x010A) 1172 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1173 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1174 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1175 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1176 ((dev)->pci_device & 0xFF00) == 0x0A00) 1177 1178 /* 1179 * The genX designation typically refers to the render engine, so render 1180 * capability related checks should use IS_GEN, while display and other checks 1181 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1182 * chips, etc.). 1183 */ 1184 1185 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1186 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1187 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1188 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1189 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1190 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1191 1192 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1193 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1194 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1195 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1196 1197 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1198 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1199 1200 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1201 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1202 1203 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1204 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1205 1206 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1207 * rows, which changed the alignment requirements and fence programming. 1208 */ 1209 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1210 IS_I915GM(dev))) 1211 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1212 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1213 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1214 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1215 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1216 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1217 /* dsparb controlled by hw only */ 1218 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1219 1220 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1221 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1222 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1223 1224 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1225 1226 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 1227 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1228 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1229 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1230 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1231 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1232 1233 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1234 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1235 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1236 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1237 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1238 1239 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) 1240 1241 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1242 1243 #define GT_FREQUENCY_MULTIPLIER 50 1244 1245 /** 1246 * RC6 is a special power stage which allows the GPU to enter an very 1247 * low-voltage mode when idle, using down to 0V while at this stage. This 1248 * stage is entered automatically when the GPU is idle when RC6 support is 1249 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1250 * 1251 * There are different RC6 modes available in Intel GPU, which differentiate 1252 * among each other with the latency required to enter and leave RC6 and 1253 * voltage consumed by the GPU in different states. 1254 * 1255 * The combination of the following flags define which states GPU is allowed 1256 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1257 * RC6pp is deepest RC6. Their support by hardware varies according to the 1258 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1259 * which brings the most power savings; deeper states save more power, but 1260 * require higher latency to switch to and wake up. 1261 */ 1262 #define INTEL_RC6_ENABLE (1<<0) 1263 #define INTEL_RC6p_ENABLE (1<<1) 1264 #define INTEL_RC6pp_ENABLE (1<<2) 1265 1266 extern int intel_iommu_enabled; 1267 extern struct drm_ioctl_desc i915_ioctls[]; 1268 extern struct drm_driver i915_driver_info; 1269 extern struct cdev_pager_ops i915_gem_pager_ops; 1270 extern int i915_panel_ignore_lid; 1271 extern unsigned int i915_powersave; 1272 extern int i915_semaphores; 1273 extern unsigned int i915_lvds_downclock; 1274 extern int i915_panel_use_ssc; 1275 extern int i915_vbt_sdvo_panel_type; 1276 extern int i915_enable_rc6; 1277 extern int i915_enable_fbc; 1278 extern int i915_enable_ppgtt; 1279 extern int i915_enable_hangcheck; 1280 1281 void i915_sysctl_cleanup(struct drm_device *dev); 1282 1283 /* i915_dma.c */ 1284 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1285 extern void i915_kernel_lost_context(struct drm_device * dev); 1286 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1287 extern int i915_driver_unload(struct drm_device *); 1288 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1289 extern void i915_driver_lastclose(struct drm_device * dev); 1290 extern void i915_driver_preclose(struct drm_device *dev, 1291 struct drm_file *file_priv); 1292 extern void i915_driver_postclose(struct drm_device *dev, 1293 struct drm_file *file_priv); 1294 extern int i915_driver_device_is_agp(struct drm_device * dev); 1295 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1296 unsigned long arg); 1297 extern int i915_emit_box(struct drm_device *dev, 1298 struct drm_clip_rect __user *boxes, 1299 int i, int DR1, int DR4); 1300 int i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 1301 int DR1, int DR4); 1302 extern int intel_gpu_reset(struct drm_device *dev); 1303 extern int i915_reset(struct drm_device *dev); 1304 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1305 unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1306 void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1307 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1308 1309 /* i915_irq.c */ 1310 extern int i915_irq_emit(struct drm_device *dev, void *data, 1311 struct drm_file *file_priv); 1312 extern int i915_irq_wait(struct drm_device *dev, void *data, 1313 struct drm_file *file_priv); 1314 1315 extern void intel_irq_init(struct drm_device *dev); 1316 extern void intel_gt_init(struct drm_device *dev); 1317 extern void intel_gt_reset(struct drm_device *dev); 1318 1319 void intel_enable_asle(struct drm_device *dev); 1320 void i915_hangcheck_elapsed(unsigned long data); 1321 void i915_handle_error(struct drm_device *dev, bool wedged); 1322 1323 void i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1324 void i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1325 1326 #ifdef CONFIG_DEBUG_FS 1327 extern void i915_destroy_error_state(struct drm_device *dev); 1328 #else 1329 #define i915_destroy_error_state(x) 1330 #endif 1331 1332 /* i915_gem.c */ 1333 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1334 struct drm_file *file_priv); 1335 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1336 struct drm_file *file_priv); 1337 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1338 struct drm_file *file_priv); 1339 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1340 struct drm_file *file_priv); 1341 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1342 struct drm_file *file_priv); 1343 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1344 struct drm_file *file_priv); 1345 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1346 struct drm_file *file_priv); 1347 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1348 struct drm_file *file_priv); 1349 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1350 struct drm_file *file_priv); 1351 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1352 struct drm_file *file_priv); 1353 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1354 struct drm_file *file_priv); 1355 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1356 struct drm_file *file_priv); 1357 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1358 struct drm_file *file_priv); 1359 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1360 struct drm_file *file_priv); 1361 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1362 struct drm_file *file_priv); 1363 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1364 struct drm_file *file_priv); 1365 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1366 struct drm_file *file_priv); 1367 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1368 struct drm_file *file_priv); 1369 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1370 struct drm_file *file_priv); 1371 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1372 struct drm_file *file_priv); 1373 void i915_gem_load(struct drm_device *dev); 1374 void i915_gem_unload(struct drm_device *dev); 1375 int i915_gem_init_object(struct drm_gem_object *obj); 1376 void i915_gem_free_object(struct drm_gem_object *obj); 1377 int i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1378 bool map_and_fenceable); 1379 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1380 int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1381 void i915_gem_lastclose(struct drm_device *dev); 1382 uint32_t i915_get_gem_seqno(struct drm_device *dev); 1383 1384 static inline void 1385 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1386 { 1387 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1388 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1389 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1390 } 1391 } 1392 1393 static inline void 1394 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1395 { 1396 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1397 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1398 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1399 } 1400 } 1401 1402 void i915_gem_retire_requests(struct drm_device *dev); 1403 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1404 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv, 1405 bool interruptible); 1406 1407 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1408 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1409 size_t size); 1410 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 1411 unsigned long mappable_end, unsigned long end); 1412 uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1413 uint32_t size, int tiling_mode); 1414 int i915_mutex_lock_interruptible(struct drm_device *dev); 1415 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 1416 struct intel_ring_buffer *to); 1417 1418 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1419 bool write); 1420 int __must_check 1421 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 1422 int __must_check 1423 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1424 u32 alignment, 1425 struct intel_ring_buffer *pipelined); 1426 int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1427 int __must_check i915_gem_init(struct drm_device *dev); 1428 int i915_gem_flush_ring(struct intel_ring_buffer *ring, 1429 uint32_t invalidate_domains, uint32_t flush_domains); 1430 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1431 int i915_gem_idle(struct drm_device *dev); 1432 int i915_gem_init_hw(struct drm_device *dev); 1433 void i915_gem_l3_remap(struct drm_device *dev); 1434 void i915_gem_init_swizzling(struct drm_device *dev); 1435 void i915_gem_init_ppgtt(struct drm_device *dev); 1436 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1437 int __must_check i915_gpu_idle(struct drm_device *dev); 1438 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1439 struct intel_ring_buffer *ring); 1440 int i915_add_request(struct intel_ring_buffer *ring, 1441 struct drm_file *file, 1442 u32 *seqno); 1443 int i915_wait_seqno(struct intel_ring_buffer *ring, 1444 uint32_t seqno); 1445 void i915_gem_reset(struct drm_device *dev); 1446 int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1447 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1448 uint64_t *phys); 1449 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1450 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1451 enum i915_cache_level cache_level); 1452 1453 void i915_gem_free_all_phys_object(struct drm_device *dev); 1454 void i915_gem_detach_phys_object(struct drm_device *dev, 1455 struct drm_i915_gem_object *obj); 1456 int i915_gem_attach_phys_object(struct drm_device *dev, 1457 struct drm_i915_gem_object *obj, int id, int align); 1458 1459 int i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1460 struct drm_mode_create_dumb *args); 1461 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1462 uint32_t handle, uint64_t *offset); 1463 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1464 uint32_t handle); 1465 1466 /* i915_gem_tiling.c */ 1467 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1468 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1469 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1470 1471 /* i915_gem_debug.c */ 1472 #if WATCH_LISTS 1473 int i915_verify_lists(struct drm_device *dev); 1474 #else 1475 #define i915_verify_lists(dev) 0 1476 #endif 1477 1478 /* i915_gem_evict.c */ 1479 int i915_gem_evict_something(struct drm_device *dev, int min_size, 1480 unsigned alignment, bool mappable); 1481 int i915_gem_evict_everything(struct drm_device *dev); 1482 1483 /* i915_suspend.c */ 1484 extern int i915_save_state(struct drm_device *dev); 1485 extern int i915_restore_state(struct drm_device *dev); 1486 1487 /* intel_iic.c */ 1488 extern int intel_setup_gmbus(struct drm_device *dev); 1489 extern void intel_teardown_gmbus(struct drm_device *dev); 1490 extern void intel_gmbus_set_speed(device_t idev, int speed); 1491 extern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1492 extern void intel_iic_reset(struct drm_device *dev); 1493 1494 /* i915_gem_context.c */ 1495 void i915_gem_context_init(struct drm_device *dev); 1496 1497 /* i915_gem_gtt.c */ 1498 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1499 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1500 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1501 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1502 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1503 struct drm_i915_gem_object *obj); 1504 1505 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1506 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1507 enum i915_cache_level cache_level); 1508 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1509 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 1510 1511 /* intel_opregion.c */ 1512 extern int intel_opregion_setup(struct drm_device *dev); 1513 #ifdef CONFIG_ACPI 1514 extern void intel_opregion_init(struct drm_device *dev); 1515 extern void intel_opregion_fini(struct drm_device *dev); 1516 extern void intel_opregion_asle_intr(struct drm_device *dev); 1517 extern void intel_opregion_gse_intr(struct drm_device *dev); 1518 extern void intel_opregion_enable_asle(struct drm_device *dev); 1519 #else 1520 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1521 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1522 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1523 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1524 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1525 #endif 1526 1527 /* modesetting */ 1528 extern void intel_modeset_init_hw(struct drm_device *dev); 1529 extern void intel_modeset_init(struct drm_device *dev); 1530 extern void intel_modeset_gem_init(struct drm_device *dev); 1531 extern void intel_modeset_cleanup(struct drm_device *dev); 1532 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1533 extern void intel_disable_fbc(struct drm_device *dev); 1534 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1535 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1536 extern void ironlake_enable_rc6(struct drm_device *dev); 1537 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1538 extern void intel_detect_pch(struct drm_device *dev); 1539 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1540 extern int intel_enable_rc6(const struct drm_device *dev); 1541 1542 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 1543 1544 extern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1545 struct drm_device *dev); 1546 extern void intel_overlay_print_error_state(struct sbuf *m, 1547 struct intel_overlay_error_state *error); 1548 extern struct intel_display_error_state *intel_display_capture_error_state( 1549 struct drm_device *dev); 1550 extern void intel_display_print_error_state(struct sbuf *m, 1551 struct drm_device *dev, struct intel_display_error_state *error); 1552 1553 static inline void 1554 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1555 { 1556 return; 1557 } 1558 1559 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) 1560 1561 #define BEGIN_LP_RING(n) \ 1562 intel_ring_begin(LP_RING(dev_priv), (n)) 1563 1564 #define OUT_RING(x) \ 1565 intel_ring_emit(LP_RING(dev_priv), x) 1566 1567 #define ADVANCE_LP_RING() \ 1568 intel_ring_advance(LP_RING(dev_priv)) 1569 1570 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1571 if (LP_RING(dev->dev_private)->obj == NULL) \ 1572 LOCK_TEST_WITH_RETURN(dev, file); \ 1573 } while (0) 1574 1575 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 1576 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1577 #define I915_GEM_HWS_INDEX 0x20 1578 #define I915_BREADCRUMB_INDEX 0x21 1579 1580 const struct intel_device_info *i915_get_device_id(int device); 1581 1582 /* i915_debug.c */ 1583 int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1584 struct sysctl_oid *top); 1585 1586 static inline bool 1587 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1588 { 1589 1590 return ((int32_t)(seq1 - seq2) >= 0); 1591 } 1592 1593 extern int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 1594 1595 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 1596 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1597 1598 /* On SNB platform, before reading ring registers forcewake bit 1599 * must be set to prevent GT core from power down and stale values being 1600 * returned. 1601 */ 1602 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1603 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1604 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1605 1606 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 1607 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 1608 1609 #define __i915_read(x, y) \ 1610 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1611 1612 __i915_read(8, 8) 1613 __i915_read(16, 16) 1614 __i915_read(32, 32) 1615 __i915_read(64, 64) 1616 #undef __i915_read 1617 1618 #define __i915_write(x, y) \ 1619 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1620 1621 __i915_write(8, 8) 1622 __i915_write(16, 16) 1623 __i915_write(32, 32) 1624 __i915_write(64, 64) 1625 #undef __i915_write 1626 1627 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1628 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1629 1630 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1631 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1632 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1633 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1634 1635 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1636 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1637 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1638 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1639 1640 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1641 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1642 1643 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1644 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1645 1646 1647 #endif 1648