1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 29 */ 30 31 #ifndef _I915_DRV_H_ 32 #define _I915_DRV_H_ 33 34 #include <sys/eventhandler.h> 35 36 #include <dev/agp/agp_i810.h> 37 #include "i915_reg.h" 38 #include "intel_bios.h" 39 #include "intel_ringbuffer.h" 40 41 /* General customization: 42 */ 43 44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 45 46 #define DRIVER_NAME "i915" 47 #define DRIVER_DESC "Intel Graphics" 48 #define DRIVER_DATE "20080730" 49 50 MALLOC_DECLARE(DRM_I915_GEM); 51 52 enum i915_pipe { 53 PIPE_A = 0, 54 PIPE_B, 55 PIPE_C, 56 I915_MAX_PIPES 57 }; 58 #define pipe_name(p) ((p) + 'A') 59 #define I915_NUM_PIPE 2 60 61 enum plane { 62 PLANE_A = 0, 63 PLANE_B, 64 PLANE_C, 65 }; 66 #define plane_name(p) ((p) + 'A') 67 68 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 69 70 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 71 72 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 73 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 74 if ((intel_encoder)->base.crtc == (__crtc)) 75 76 struct intel_pch_pll { 77 int refcount; /* count of number of CRTCs sharing this PLL */ 78 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 79 bool on; /* is the PLL actually active? Disabled during modeset */ 80 int pll_reg; 81 int fp0_reg; 82 int fp1_reg; 83 }; 84 #define I915_NUM_PLLS 2 85 86 struct intel_ddi_plls { 87 int spll_refcount; 88 int wrpll1_refcount; 89 int wrpll2_refcount; 90 }; 91 92 /* Interface history: 93 * 94 * 1.1: Original. 95 * 1.2: Add Power Management 96 * 1.3: Add vblank support 97 * 1.4: Fix cmdbuffer path, add heap destroy 98 * 1.5: Add vblank pipe configuration 99 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 100 * - Support vertical blank on secondary display pipe 101 */ 102 #define DRIVER_MAJOR 1 103 #define DRIVER_MINOR 6 104 #define DRIVER_PATCHLEVEL 0 105 106 #define WATCH_COHERENCY 0 107 #define WATCH_BUF 0 108 #define WATCH_EXEC 0 109 #define WATCH_LRU 0 110 #define WATCH_RELOC 0 111 #define WATCH_INACTIVE 0 112 #define WATCH_PWRITE 0 113 114 #define I915_GEM_PHYS_CURSOR_0 1 115 #define I915_GEM_PHYS_CURSOR_1 2 116 #define I915_GEM_PHYS_OVERLAY_REGS 3 117 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 118 119 struct drm_i915_gem_phys_object { 120 int id; 121 drm_dma_handle_t *handle; 122 struct drm_i915_gem_object *cur_obj; 123 }; 124 125 struct drm_i915_private; 126 127 struct drm_i915_display_funcs { 128 void (*dpms)(struct drm_crtc *crtc, int mode); 129 bool (*fbc_enabled)(struct drm_device *dev); 130 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 131 void (*disable_fbc)(struct drm_device *dev); 132 int (*get_display_clock_speed)(struct drm_device *dev); 133 int (*get_fifo_size)(struct drm_device *dev, int plane); 134 void (*update_wm)(struct drm_device *dev); 135 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 136 uint32_t sprite_width, int pixel_size); 137 int (*crtc_mode_set)(struct drm_crtc *crtc, 138 struct drm_display_mode *mode, 139 struct drm_display_mode *adjusted_mode, 140 int x, int y, 141 struct drm_framebuffer *old_fb); 142 void (*write_eld)(struct drm_connector *connector, 143 struct drm_crtc *crtc); 144 void (*fdi_link_train)(struct drm_crtc *crtc); 145 void (*init_clock_gating)(struct drm_device *dev); 146 void (*init_pch_clock_gating)(struct drm_device *dev); 147 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 148 struct drm_framebuffer *fb, 149 struct drm_i915_gem_object *obj); 150 void (*force_wake_get)(struct drm_i915_private *dev_priv); 151 void (*force_wake_put)(struct drm_i915_private *dev_priv); 152 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 153 int x, int y); 154 /* clock updates for mode set */ 155 /* cursor updates */ 156 /* render clock increase/decrease */ 157 /* display clock increase/decrease */ 158 /* pll clock increase/decrease */ 159 }; 160 161 struct intel_device_info { 162 u8 gen; 163 u8 is_mobile:1; 164 u8 is_i85x:1; 165 u8 is_i915g:1; 166 u8 is_i945gm:1; 167 u8 is_g33:1; 168 u8 need_gfx_hws:1; 169 u8 is_g4x:1; 170 u8 is_pineview:1; 171 u8 is_broadwater:1; 172 u8 is_crestline:1; 173 u8 is_ivybridge:1; 174 u8 is_valleyview:1; 175 u8 has_force_wake:1; 176 u8 is_haswell:1; 177 u8 has_fbc:1; 178 u8 has_pipe_cxsr:1; 179 u8 has_hotplug:1; 180 u8 cursor_needs_physical:1; 181 u8 has_overlay:1; 182 u8 overlay_needs_physical:1; 183 u8 supports_tv:1; 184 u8 has_bsd_ring:1; 185 u8 has_blt_ring:1; 186 u8 has_llc:1; 187 }; 188 189 #define I915_PPGTT_PD_ENTRIES 512 190 #define I915_PPGTT_PT_ENTRIES 1024 191 struct i915_hw_ppgtt { 192 unsigned num_pd_entries; 193 vm_page_t *pt_pages; 194 uint32_t pd_offset; 195 vm_paddr_t *pt_dma_addr; 196 vm_paddr_t scratch_page_dma_addr; 197 }; 198 199 enum no_fbc_reason { 200 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 201 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 202 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 203 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 204 FBC_BAD_PLANE, /* fbc not supported on plane */ 205 FBC_NOT_TILED, /* buffer not tiled */ 206 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 207 FBC_MODULE_PARAM, 208 }; 209 210 /* defined intel_pm.c */ 211 extern struct lock mchdev_lock; 212 213 struct mem_block { 214 struct mem_block *next; 215 struct mem_block *prev; 216 int start; 217 int size; 218 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 219 }; 220 221 struct opregion_header; 222 struct opregion_acpi; 223 struct opregion_swsci; 224 struct opregion_asle; 225 226 struct intel_opregion { 227 struct opregion_header *header; 228 struct opregion_acpi *acpi; 229 struct opregion_swsci *swsci; 230 struct opregion_asle *asle; 231 void *vbt; 232 u32 *lid_state; 233 }; 234 #define OPREGION_SIZE (8*1024) 235 236 #define I915_FENCE_REG_NONE -1 237 #define I915_MAX_NUM_FENCES 16 238 /* 16 fences + sign bit for FENCE_REG_NONE */ 239 #define I915_MAX_NUM_FENCE_BITS 5 240 241 struct drm_i915_fence_reg { 242 struct list_head lru_list; 243 struct drm_i915_gem_object *obj; 244 uint32_t setup_seqno; 245 int pin_count; 246 }; 247 248 struct sdvo_device_mapping { 249 u8 initialized; 250 u8 dvo_port; 251 u8 slave_addr; 252 u8 dvo_wiring; 253 u8 i2c_pin; 254 u8 ddc_pin; 255 }; 256 257 enum intel_pch { 258 PCH_IBX, /* Ibexpeak PCH */ 259 PCH_CPT, /* Cougarpoint PCH */ 260 }; 261 262 #define QUIRK_PIPEA_FORCE (1<<0) 263 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 264 265 struct intel_fbdev; 266 struct intel_fbc_work; 267 268 typedef struct drm_i915_private { 269 struct drm_device *dev; 270 271 device_t *gmbus_bridge; 272 device_t *bbbus_bridge; 273 device_t *gmbus; 274 device_t *bbbus; 275 /** gmbus_sx protects against concurrent usage of the single hw gmbus 276 * controller on different i2c buses. */ 277 struct lock gmbus_lock; 278 279 int has_gem; 280 int relative_constants_mode; 281 282 drm_local_map_t *sarea; 283 drm_local_map_t *mmio_map; 284 285 /** gt_fifo_count and the subsequent register write are synchronized 286 * with dev->struct_mutex. */ 287 unsigned gt_fifo_count; 288 /** forcewake_count is protected by gt_lock */ 289 unsigned forcewake_count; 290 /** gt_lock is also taken in irq contexts. */ 291 struct lock gt_lock; 292 293 drm_i915_sarea_t *sarea_priv; 294 struct intel_ring_buffer ring[I915_NUM_RINGS]; 295 uint32_t next_seqno; 296 297 drm_dma_handle_t *status_page_dmah; 298 void *hw_status_page; 299 dma_addr_t dma_status_page; 300 uint32_t counter; 301 unsigned int status_gfx_addr; 302 drm_local_map_t hws_map; 303 struct drm_gem_object *hws_obj; 304 305 struct drm_i915_gem_object *pwrctx; 306 struct drm_i915_gem_object *renderctx; 307 308 unsigned int cpp; 309 int back_offset; 310 int front_offset; 311 int current_page; 312 int page_flipping; 313 314 atomic_t irq_received; 315 u32 trace_irq_seqno; 316 317 /** Cached value of IER to avoid reads in updating the bitfield */ 318 u32 pipestat[2]; 319 u32 irq_mask; 320 u32 gt_irq_mask; 321 u32 pch_irq_mask; 322 struct lock irq_lock; 323 324 u32 hotplug_supported_mask; 325 326 int tex_lru_log_granularity; 327 int allow_batchbuffer; 328 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 329 int vblank_pipe; 330 331 int num_pipe; 332 int num_pch_pll; 333 334 /* For hangcheck timer */ 335 #define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 336 int hangcheck_count; 337 uint32_t last_acthd; 338 uint32_t last_acthd_bsd; 339 uint32_t last_acthd_blt; 340 uint32_t last_instdone; 341 uint32_t last_instdone1; 342 343 struct intel_opregion opregion; 344 345 346 /* overlay */ 347 struct intel_overlay *overlay; 348 bool sprite_scaling_enabled; 349 350 /* LVDS info */ 351 int backlight_level; /* restore backlight to this value */ 352 bool backlight_enabled; 353 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 354 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 355 356 /* Feature bits from the VBIOS */ 357 unsigned int int_tv_support:1; 358 unsigned int lvds_dither:1; 359 unsigned int lvds_vbt:1; 360 unsigned int int_crt_support:1; 361 unsigned int lvds_use_ssc:1; 362 unsigned int display_clock_mode:1; 363 int lvds_ssc_freq; 364 struct { 365 int rate; 366 int lanes; 367 int preemphasis; 368 int vswing; 369 370 bool initialized; 371 bool support; 372 int bpp; 373 struct edp_power_seq pps; 374 } edp; 375 bool no_aux_handshake; 376 377 int crt_ddc_pin; 378 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 379 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 380 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 381 382 /* PCH chipset type */ 383 enum intel_pch pch_type; 384 385 /* Display functions */ 386 struct drm_i915_display_funcs display; 387 388 unsigned long quirks; 389 390 /* Register state */ 391 bool modeset_on_lid; 392 u8 saveLBB; 393 u32 saveDSPACNTR; 394 u32 saveDSPBCNTR; 395 u32 saveDSPARB; 396 u32 saveHWS; 397 u32 savePIPEACONF; 398 u32 savePIPEBCONF; 399 u32 savePIPEASRC; 400 u32 savePIPEBSRC; 401 u32 saveFPA0; 402 u32 saveFPA1; 403 u32 saveDPLL_A; 404 u32 saveDPLL_A_MD; 405 u32 saveHTOTAL_A; 406 u32 saveHBLANK_A; 407 u32 saveHSYNC_A; 408 u32 saveVTOTAL_A; 409 u32 saveVBLANK_A; 410 u32 saveVSYNC_A; 411 u32 saveBCLRPAT_A; 412 u32 saveTRANSACONF; 413 u32 saveTRANS_HTOTAL_A; 414 u32 saveTRANS_HBLANK_A; 415 u32 saveTRANS_HSYNC_A; 416 u32 saveTRANS_VTOTAL_A; 417 u32 saveTRANS_VBLANK_A; 418 u32 saveTRANS_VSYNC_A; 419 u32 savePIPEASTAT; 420 u32 saveDSPASTRIDE; 421 u32 saveDSPASIZE; 422 u32 saveDSPAPOS; 423 u32 saveDSPAADDR; 424 u32 saveDSPASURF; 425 u32 saveDSPATILEOFF; 426 u32 savePFIT_PGM_RATIOS; 427 u32 saveBLC_HIST_CTL; 428 u32 saveBLC_PWM_CTL; 429 u32 saveBLC_PWM_CTL2; 430 u32 saveBLC_CPU_PWM_CTL; 431 u32 saveBLC_CPU_PWM_CTL2; 432 u32 saveFPB0; 433 u32 saveFPB1; 434 u32 saveDPLL_B; 435 u32 saveDPLL_B_MD; 436 u32 saveHTOTAL_B; 437 u32 saveHBLANK_B; 438 u32 saveHSYNC_B; 439 u32 saveVTOTAL_B; 440 u32 saveVBLANK_B; 441 u32 saveVSYNC_B; 442 u32 saveBCLRPAT_B; 443 u32 saveTRANSBCONF; 444 u32 saveTRANS_HTOTAL_B; 445 u32 saveTRANS_HBLANK_B; 446 u32 saveTRANS_HSYNC_B; 447 u32 saveTRANS_VTOTAL_B; 448 u32 saveTRANS_VBLANK_B; 449 u32 saveTRANS_VSYNC_B; 450 u32 savePIPEBSTAT; 451 u32 saveDSPBSTRIDE; 452 u32 saveDSPBSIZE; 453 u32 saveDSPBPOS; 454 u32 saveDSPBADDR; 455 u32 saveDSPBSURF; 456 u32 saveDSPBTILEOFF; 457 u32 saveVGA0; 458 u32 saveVGA1; 459 u32 saveVGA_PD; 460 u32 saveVGACNTRL; 461 u32 saveADPA; 462 u32 saveLVDS; 463 u32 savePP_ON_DELAYS; 464 u32 savePP_OFF_DELAYS; 465 u32 saveDVOA; 466 u32 saveDVOB; 467 u32 saveDVOC; 468 u32 savePP_ON; 469 u32 savePP_OFF; 470 u32 savePP_CONTROL; 471 u32 savePP_DIVISOR; 472 u32 savePFIT_CONTROL; 473 u32 save_palette_a[256]; 474 u32 save_palette_b[256]; 475 u32 saveDPFC_CB_BASE; 476 u32 saveFBC_CFB_BASE; 477 u32 saveFBC_LL_BASE; 478 u32 saveFBC_CONTROL; 479 u32 saveFBC_CONTROL2; 480 u32 saveIER; 481 u32 saveIIR; 482 u32 saveIMR; 483 u32 saveDEIER; 484 u32 saveDEIMR; 485 u32 saveGTIER; 486 u32 saveGTIMR; 487 u32 saveFDI_RXA_IMR; 488 u32 saveFDI_RXB_IMR; 489 u32 saveCACHE_MODE_0; 490 u32 saveMI_ARB_STATE; 491 u32 saveSWF0[16]; 492 u32 saveSWF1[16]; 493 u32 saveSWF2[3]; 494 u8 saveMSR; 495 u8 saveSR[8]; 496 u8 saveGR[25]; 497 u8 saveAR_INDEX; 498 u8 saveAR[21]; 499 u8 saveDACMASK; 500 u8 saveCR[37]; 501 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 502 u32 saveCURACNTR; 503 u32 saveCURAPOS; 504 u32 saveCURABASE; 505 u32 saveCURBCNTR; 506 u32 saveCURBPOS; 507 u32 saveCURBBASE; 508 u32 saveCURSIZE; 509 u32 saveDP_B; 510 u32 saveDP_C; 511 u32 saveDP_D; 512 u32 savePIPEA_GMCH_DATA_M; 513 u32 savePIPEB_GMCH_DATA_M; 514 u32 savePIPEA_GMCH_DATA_N; 515 u32 savePIPEB_GMCH_DATA_N; 516 u32 savePIPEA_DP_LINK_M; 517 u32 savePIPEB_DP_LINK_M; 518 u32 savePIPEA_DP_LINK_N; 519 u32 savePIPEB_DP_LINK_N; 520 u32 saveFDI_RXA_CTL; 521 u32 saveFDI_TXA_CTL; 522 u32 saveFDI_RXB_CTL; 523 u32 saveFDI_TXB_CTL; 524 u32 savePFA_CTL_1; 525 u32 savePFB_CTL_1; 526 u32 savePFA_WIN_SZ; 527 u32 savePFB_WIN_SZ; 528 u32 savePFA_WIN_POS; 529 u32 savePFB_WIN_POS; 530 u32 savePCH_DREF_CONTROL; 531 u32 saveDISP_ARB_CTL; 532 u32 savePIPEA_DATA_M1; 533 u32 savePIPEA_DATA_N1; 534 u32 savePIPEA_LINK_M1; 535 u32 savePIPEA_LINK_N1; 536 u32 savePIPEB_DATA_M1; 537 u32 savePIPEB_DATA_N1; 538 u32 savePIPEB_LINK_M1; 539 u32 savePIPEB_LINK_N1; 540 u32 saveMCHBAR_RENDER_STANDBY; 541 u32 savePCH_PORT_HOTPLUG; 542 543 struct { 544 /** Bridge to intel-gtt-ko */ 545 const struct intel_gtt *gtt; 546 /** Memory allocator for GTT stolen memory */ 547 struct drm_mm stolen; 548 /** Memory allocator for GTT */ 549 struct drm_mm gtt_space; 550 /** List of all objects in gtt_space. Used to restore gtt 551 * mappings on resume */ 552 struct list_head gtt_list; 553 554 /** Usable portion of the GTT for GEM */ 555 unsigned long gtt_start; 556 unsigned long gtt_mappable_end; 557 unsigned long gtt_end; 558 559 /** PPGTT used for aliasing the PPGTT with the GTT */ 560 struct i915_hw_ppgtt *aliasing_ppgtt; 561 562 /** 563 * List of objects currently involved in rendering from the 564 * ringbuffer. 565 * 566 * Includes buffers having the contents of their GPU caches 567 * flushed, not necessarily primitives. last_rendering_seqno 568 * represents when the rendering involved will be completed. 569 * 570 * A reference is held on the buffer while on this list. 571 */ 572 struct list_head active_list; 573 574 /** 575 * List of objects which are not in the ringbuffer but which 576 * still have a write_domain which needs to be flushed before 577 * unbinding. 578 * 579 * A reference is held on the buffer while on this list. 580 */ 581 struct list_head flushing_list; 582 583 /** 584 * LRU list of objects which are not in the ringbuffer and 585 * are ready to unbind, but are still in the GTT. 586 * 587 * last_rendering_seqno is 0 while an object is in this list. 588 * 589 * A reference is not held on the buffer while on this list, 590 * as merely being GTT-bound shouldn't prevent its being 591 * freed, and we'll pull it off the list in the free path. 592 */ 593 struct list_head inactive_list; 594 595 /** 596 * LRU list of objects which are not in the ringbuffer but 597 * are still pinned in the GTT. 598 */ 599 struct list_head pinned_list; 600 601 /** LRU list of objects with fence regs on them. */ 602 struct list_head fence_list; 603 604 /** 605 * List of objects currently pending being freed. 606 * 607 * These objects are no longer in use, but due to a signal 608 * we were prevented from freeing them at the appointed time. 609 */ 610 struct list_head deferred_free_list; 611 612 /** 613 * We leave the user IRQ off as much as possible, 614 * but this means that requests will finish and never 615 * be retired once the system goes idle. Set a timer to 616 * fire periodically while the ring is running. When it 617 * fires, go retire requests. 618 */ 619 struct timeout_task retire_task; 620 621 /** 622 * Are we in a non-interruptible section of code like 623 * modesetting? 624 */ 625 bool interruptible; 626 627 uint32_t next_gem_seqno; 628 629 /** 630 * Waiting sequence number, if any 631 */ 632 uint32_t waiting_gem_seqno; 633 634 /** 635 * Last seq seen at irq time 636 */ 637 uint32_t irq_gem_seqno; 638 639 /** 640 * Flag if the X Server, and thus DRM, is not currently in 641 * control of the device. 642 * 643 * This is set between LeaveVT and EnterVT. It needs to be 644 * replaced with a semaphore. It also needs to be 645 * transitioned away from for kernel modesetting. 646 */ 647 int suspended; 648 649 /** 650 * Flag if the hardware appears to be wedged. 651 * 652 * This is set when attempts to idle the device timeout. 653 * It prevents command submission from occuring and makes 654 * every pending request fail 655 */ 656 atomic_t wedged; 657 658 /** Bit 6 swizzling required for X tiling */ 659 uint32_t bit_6_swizzle_x; 660 /** Bit 6 swizzling required for Y tiling */ 661 uint32_t bit_6_swizzle_y; 662 663 /* storage for physical objects */ 664 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 665 666 /* accounting, useful for userland debugging */ 667 size_t gtt_total; 668 size_t mappable_gtt_total; 669 size_t object_memory; 670 u32 object_count; 671 672 eventhandler_tag i915_lowmem; 673 } mm; 674 675 const struct intel_device_info *info; 676 677 struct sdvo_device_mapping sdvo_mappings[2]; 678 /* indicate whether the LVDS_BORDER should be enabled or not */ 679 unsigned int lvds_border_bits; 680 /* Panel fitter placement and size for Ironlake+ */ 681 u32 pch_pf_pos, pch_pf_size; 682 683 struct drm_crtc *plane_to_crtc_mapping[3]; 684 struct drm_crtc *pipe_to_crtc_mapping[3]; 685 /* wait_queue_head_t pending_flip_queue; XXXKIB */ 686 bool flip_pending_is_done; 687 688 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 689 struct intel_ddi_plls ddi_plls; 690 691 /* Reclocking support */ 692 bool render_reclock_avail; 693 bool lvds_downclock_avail; 694 /* indicates the reduced downclock for LVDS*/ 695 int lvds_downclock; 696 struct task idle_task; 697 struct callout idle_callout; 698 bool busy; 699 u16 orig_clock; 700 int child_dev_num; 701 struct child_device_config *child_dev; 702 struct drm_connector *int_lvds_connector; 703 struct drm_connector *int_edp_connector; 704 705 device_t bridge_dev; 706 bool mchbar_need_disable; 707 int mch_res_rid; 708 struct resource *mch_res; 709 710 struct lock rps_lock; 711 u32 pm_iir; 712 struct task rps_task; 713 714 u8 cur_delay; 715 u8 min_delay; 716 u8 max_delay; 717 u8 fmax; 718 u8 fstart; 719 720 u64 last_count1; 721 unsigned long last_time1; 722 unsigned long chipset_power; 723 u64 last_count2; 724 struct timespec last_time2; 725 unsigned long gfx_power; 726 int c_m; 727 int r_t; 728 u8 corr; 729 struct lock *mchdev_lock; 730 731 enum no_fbc_reason no_fbc_reason; 732 733 unsigned long cfb_size; 734 unsigned int cfb_fb; 735 int cfb_plane; 736 int cfb_y; 737 struct intel_fbc_work *fbc_work; 738 739 unsigned int fsb_freq, mem_freq, is_ddr3; 740 741 struct taskqueue *tq; 742 struct task error_task; 743 struct task hotplug_task; 744 int error_completion; 745 struct lock error_completion_lock; 746 struct drm_i915_error_state *first_error; 747 struct lock error_lock; 748 struct callout hangcheck_timer; 749 750 unsigned long last_gpu_reset; 751 752 struct intel_fbdev *fbdev; 753 754 struct drm_property *broadcast_rgb_property; 755 struct drm_property *force_audio_property; 756 } drm_i915_private_t; 757 758 /* Iterate over initialised rings */ 759 #define for_each_ring(ring__, dev_priv__, i__) \ 760 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 761 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 762 763 enum hdmi_force_audio { 764 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 765 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 766 HDMI_AUDIO_AUTO, /* trust EDID */ 767 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 768 }; 769 770 enum i915_cache_level { 771 I915_CACHE_NONE, 772 I915_CACHE_LLC, 773 I915_CACHE_LLC_MLC, /* gen6+ */ 774 }; 775 776 enum intel_chip_family { 777 CHIP_I8XX = 0x01, 778 CHIP_I9XX = 0x02, 779 CHIP_I915 = 0x04, 780 CHIP_I965 = 0x08, 781 }; 782 783 /** driver private structure attached to each drm_gem_object */ 784 struct drm_i915_gem_object { 785 struct drm_gem_object base; 786 787 /** Current space allocated to this object in the GTT, if any. */ 788 struct drm_mm_node *gtt_space; 789 struct list_head gtt_list; 790 /** This object's place on the active/flushing/inactive lists */ 791 struct list_head ring_list; 792 struct list_head mm_list; 793 /** This object's place on GPU write list */ 794 struct list_head gpu_write_list; 795 /** This object's place in the batchbuffer or on the eviction list */ 796 struct list_head exec_list; 797 798 /** 799 * This is set if the object is on the active or flushing lists 800 * (has pending rendering), and is not set if it's on inactive (ready 801 * to be unbound). 802 */ 803 unsigned int active:1; 804 805 /** 806 * This is set if the object has been written to since last bound 807 * to the GTT 808 */ 809 unsigned int dirty:1; 810 811 /** 812 * This is set if the object has been written to since the last 813 * GPU flush. 814 */ 815 unsigned int pending_gpu_write:1; 816 817 /** 818 * Fence register bits (if any) for this object. Will be set 819 * as needed when mapped into the GTT. 820 * Protected by dev->struct_mutex. 821 */ 822 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 823 824 /** 825 * Advice: are the backing pages purgeable? 826 */ 827 unsigned int madv:2; 828 829 /** 830 * Current tiling mode for the object. 831 */ 832 unsigned int tiling_mode:2; 833 unsigned int tiling_changed:1; 834 835 /** How many users have pinned this object in GTT space. The following 836 * users can each hold at most one reference: pwrite/pread, pin_ioctl 837 * (via user_pin_count), execbuffer (objects are not allowed multiple 838 * times for the same batchbuffer), and the framebuffer code. When 839 * switching/pageflipping, the framebuffer code has at most two buffers 840 * pinned per crtc. 841 * 842 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 843 * bits with absolutely no headroom. So use 4 bits. */ 844 unsigned int pin_count:4; 845 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 846 847 /** 848 * Is the object at the current location in the gtt mappable and 849 * fenceable? Used to avoid costly recalculations. 850 */ 851 unsigned int map_and_fenceable:1; 852 853 /** 854 * Whether the current gtt mapping needs to be mappable (and isn't just 855 * mappable by accident). Track pin and fault separate for a more 856 * accurate mappable working set. 857 */ 858 unsigned int fault_mappable:1; 859 unsigned int pin_mappable:1; 860 861 /* 862 * Is the GPU currently using a fence to access this buffer, 863 */ 864 unsigned int pending_fenced_gpu_access:1; 865 unsigned int fenced_gpu_access:1; 866 867 unsigned int cache_level:2; 868 869 unsigned int has_aliasing_ppgtt_mapping:1; 870 871 vm_page_t *pages; 872 873 /** 874 * DMAR support 875 */ 876 struct sglist *sg_list; 877 878 /** 879 * Used for performing relocations during execbuffer insertion. 880 */ 881 struct hlist_node exec_node; 882 unsigned long exec_handle; 883 struct drm_i915_gem_exec_object2 *exec_entry; 884 885 /** 886 * Current offset of the object in GTT space. 887 * 888 * This is the same as gtt_space->start 889 */ 890 uint32_t gtt_offset; 891 892 /** Breadcrumb of last rendering to the buffer. */ 893 uint32_t last_rendering_seqno; 894 struct intel_ring_buffer *ring; 895 896 /** Breadcrumb of last fenced GPU access to the buffer. */ 897 uint32_t last_fenced_seqno; 898 struct intel_ring_buffer *last_fenced_ring; 899 900 /** Current tiling stride for the object, if it's tiled. */ 901 uint32_t stride; 902 903 /** Record of address bit 17 of each page at last unbind. */ 904 unsigned long *bit_17; 905 906 /** 907 * If present, while GEM_DOMAIN_CPU is in the read domain this array 908 * flags which individual pages are valid. 909 */ 910 uint8_t *page_cpu_valid; 911 912 /** User space pin count and filp owning the pin */ 913 uint32_t user_pin_count; 914 struct drm_file *pin_filp; 915 916 /** for phy allocated objects */ 917 struct drm_i915_gem_phys_object *phys_obj; 918 919 /** 920 * Number of crtcs where this object is currently the fb, but 921 * will be page flipped away on the next vblank. When it 922 * reaches 0, dev_priv->pending_flip_queue will be woken up. 923 */ 924 atomic_t pending_flip; 925 }; 926 927 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 928 929 /** 930 * Request queue structure. 931 * 932 * The request queue allows us to note sequence numbers that have been emitted 933 * and may be associated with active buffers to be retired. 934 * 935 * By keeping this list, we can avoid having to do questionable 936 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 937 * an emission time with seqnos for tracking how far ahead of the GPU we are. 938 */ 939 struct drm_i915_gem_request { 940 /** On Which ring this request was generated */ 941 struct intel_ring_buffer *ring; 942 943 /** GEM sequence number associated with this request. */ 944 uint32_t seqno; 945 946 /** Postion in the ringbuffer of the end of the request */ 947 u32 tail; 948 949 /** Time at which this request was emitted, in jiffies. */ 950 unsigned long emitted_jiffies; 951 952 /** global list entry for this request */ 953 struct list_head list; 954 955 struct drm_i915_file_private *file_priv; 956 /** file_priv list entry for this request */ 957 struct list_head client_list; 958 }; 959 960 struct drm_i915_file_private { 961 struct { 962 struct spinlock lock; 963 struct list_head request_list; 964 } mm; 965 }; 966 967 struct drm_i915_error_state { 968 u32 eir; 969 u32 pgtbl_er; 970 u32 pipestat[I915_MAX_PIPES]; 971 u32 tail[I915_NUM_RINGS]; 972 u32 head[I915_NUM_RINGS]; 973 u32 ipeir[I915_NUM_RINGS]; 974 u32 ipehr[I915_NUM_RINGS]; 975 u32 instdone[I915_NUM_RINGS]; 976 u32 acthd[I915_NUM_RINGS]; 977 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 978 /* our own tracking of ring head and tail */ 979 u32 cpu_ring_head[I915_NUM_RINGS]; 980 u32 cpu_ring_tail[I915_NUM_RINGS]; 981 u32 error; /* gen6+ */ 982 u32 instpm[I915_NUM_RINGS]; 983 u32 instps[I915_NUM_RINGS]; 984 u32 instdone1; 985 u32 seqno[I915_NUM_RINGS]; 986 u64 bbaddr; 987 u32 fault_reg[I915_NUM_RINGS]; 988 u32 done_reg; 989 u32 faddr[I915_NUM_RINGS]; 990 u64 fence[I915_MAX_NUM_FENCES]; 991 struct timeval time; 992 struct drm_i915_error_ring { 993 struct drm_i915_error_object { 994 int page_count; 995 u32 gtt_offset; 996 u32 *pages[0]; 997 } *ringbuffer, *batchbuffer; 998 struct drm_i915_error_request { 999 long jiffies; 1000 u32 seqno; 1001 u32 tail; 1002 } *requests; 1003 int num_requests; 1004 } ring[I915_NUM_RINGS]; 1005 struct drm_i915_error_buffer { 1006 u32 size; 1007 u32 name; 1008 u32 seqno; 1009 u32 gtt_offset; 1010 u32 read_domains; 1011 u32 write_domain; 1012 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 1013 s32 pinned:2; 1014 u32 tiling:2; 1015 u32 dirty:1; 1016 u32 purgeable:1; 1017 s32 ring:4; 1018 u32 cache_level:2; 1019 } *active_bo, *pinned_bo; 1020 u32 active_bo_count, pinned_bo_count; 1021 struct intel_overlay_error_state *overlay; 1022 struct intel_display_error_state *display; 1023 }; 1024 1025 /** 1026 * RC6 is a special power stage which allows the GPU to enter an very 1027 * low-voltage mode when idle, using down to 0V while at this stage. This 1028 * stage is entered automatically when the GPU is idle when RC6 support is 1029 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1030 * 1031 * There are different RC6 modes available in Intel GPU, which differentiate 1032 * among each other with the latency required to enter and leave RC6 and 1033 * voltage consumed by the GPU in different states. 1034 * 1035 * The combination of the following flags define which states GPU is allowed 1036 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1037 * RC6pp is deepest RC6. Their support by hardware varies according to the 1038 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1039 * which brings the most power savings; deeper states save more power, but 1040 * require higher latency to switch to and wake up. 1041 */ 1042 #define INTEL_RC6_ENABLE (1<<0) 1043 #define INTEL_RC6p_ENABLE (1<<1) 1044 #define INTEL_RC6pp_ENABLE (1<<2) 1045 1046 extern int intel_iommu_enabled; 1047 extern struct drm_ioctl_desc i915_ioctls[]; 1048 extern struct drm_driver i915_driver_info; 1049 extern struct cdev_pager_ops i915_gem_pager_ops; 1050 extern int i915_panel_ignore_lid; 1051 extern unsigned int i915_powersave; 1052 extern int i915_semaphores; 1053 extern unsigned int i915_lvds_downclock; 1054 extern int i915_panel_use_ssc; 1055 extern int i915_vbt_sdvo_panel_type; 1056 extern int i915_enable_rc6; 1057 extern int i915_enable_fbc; 1058 extern int i915_enable_ppgtt; 1059 extern int i915_enable_hangcheck; 1060 1061 const struct intel_device_info *i915_get_device_id(int device); 1062 1063 int i915_reset(struct drm_device *dev, u8 flags); 1064 1065 /* i915_debug.c */ 1066 int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1067 struct sysctl_oid *top); 1068 void i915_sysctl_cleanup(struct drm_device *dev); 1069 1070 /* i915_dma.c */ 1071 extern void i915_kernel_lost_context(struct drm_device * dev); 1072 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1073 extern int i915_driver_unload(struct drm_device *); 1074 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1075 extern void i915_driver_lastclose(struct drm_device * dev); 1076 extern void i915_driver_preclose(struct drm_device *dev, 1077 struct drm_file *file_priv); 1078 extern void i915_driver_postclose(struct drm_device *dev, 1079 struct drm_file *file_priv); 1080 extern int i915_driver_device_is_agp(struct drm_device * dev); 1081 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1082 unsigned long arg); 1083 extern int i915_emit_box(struct drm_device *dev, 1084 struct drm_clip_rect __user *boxes, 1085 int i, int DR1, int DR4); 1086 int i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 1087 int DR1, int DR4); 1088 1089 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1090 unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1091 void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1092 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1093 1094 /* i915_irq.c */ 1095 extern int i915_irq_emit(struct drm_device *dev, void *data, 1096 struct drm_file *file_priv); 1097 extern int i915_irq_wait(struct drm_device *dev, void *data, 1098 struct drm_file *file_priv); 1099 1100 extern void intel_irq_init(struct drm_device *dev); 1101 1102 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1103 struct drm_file *file_priv); 1104 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1105 struct drm_file *file_priv); 1106 extern int i915_vblank_swap(struct drm_device *dev, void *data, 1107 struct drm_file *file_priv); 1108 void intel_enable_asle(struct drm_device *dev); 1109 void i915_hangcheck_elapsed(void *context); 1110 void i915_handle_error(struct drm_device *dev, bool wedged); 1111 1112 void i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1113 void i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1114 1115 void i915_destroy_error_state(struct drm_device *dev); 1116 1117 /* i915_gem.c */ 1118 int i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size, 1119 uint32_t *handle_p); 1120 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1121 struct drm_file *file_priv); 1122 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1123 struct drm_file *file_priv); 1124 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1125 struct drm_file *file_priv); 1126 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1127 struct drm_file *file_priv); 1128 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1129 struct drm_file *file_priv); 1130 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1131 struct drm_file *file_priv); 1132 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1133 struct drm_file *file_priv); 1134 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1135 struct drm_file *file_priv); 1136 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1137 struct drm_file *file_priv); 1138 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1139 struct drm_file *file_priv); 1140 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1141 struct drm_file *file_priv); 1142 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1143 struct drm_file *file_priv); 1144 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1145 struct drm_file *file_priv); 1146 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1147 struct drm_file *file_priv); 1148 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1149 struct drm_file *file_priv); 1150 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1151 struct drm_file *file_priv); 1152 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1153 struct drm_file *file_priv); 1154 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1155 struct drm_file *file_priv); 1156 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1157 struct drm_file *file_priv); 1158 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1159 struct drm_file *file_priv); 1160 void i915_gem_load(struct drm_device *dev); 1161 void i915_gem_unload(struct drm_device *dev); 1162 int i915_gem_init_object(struct drm_gem_object *obj); 1163 void i915_gem_free_object(struct drm_gem_object *obj); 1164 int i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1165 bool map_and_fenceable); 1166 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1167 int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1168 void i915_gem_lastclose(struct drm_device *dev); 1169 uint32_t i915_get_gem_seqno(struct drm_device *dev); 1170 1171 static inline void 1172 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1173 { 1174 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1175 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1176 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1177 } 1178 } 1179 1180 static inline void 1181 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1182 { 1183 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1184 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1185 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1186 } 1187 } 1188 1189 void i915_gem_retire_requests(struct drm_device *dev); 1190 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1191 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1192 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1193 size_t size); 1194 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 1195 unsigned long mappable_end, unsigned long end); 1196 uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1197 uint32_t size, int tiling_mode); 1198 int i915_mutex_lock_interruptible(struct drm_device *dev); 1199 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1200 bool write); 1201 int i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1202 u32 alignment, struct intel_ring_buffer *pipelined); 1203 int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1204 int i915_gem_flush_ring(struct intel_ring_buffer *ring, 1205 uint32_t invalidate_domains, uint32_t flush_domains); 1206 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1207 int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1208 int i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1209 int i915_gem_idle(struct drm_device *dev); 1210 int i915_gem_init_hw(struct drm_device *dev); 1211 void i915_gem_init_swizzling(struct drm_device *dev); 1212 void i915_gem_init_ppgtt(struct drm_device *dev); 1213 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1214 int i915_gpu_idle(struct drm_device *dev, bool do_retire); 1215 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1216 struct intel_ring_buffer *ring, uint32_t seqno); 1217 int i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file, 1218 struct drm_i915_gem_request *request); 1219 int i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1220 struct intel_ring_buffer *pipelined); 1221 void i915_gem_reset(struct drm_device *dev); 1222 int i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, 1223 bool do_retire); 1224 int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1225 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1226 uint64_t *phys); 1227 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1228 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1229 enum i915_cache_level cache_level); 1230 1231 void i915_gem_free_all_phys_object(struct drm_device *dev); 1232 void i915_gem_detach_phys_object(struct drm_device *dev, 1233 struct drm_i915_gem_object *obj); 1234 int i915_gem_attach_phys_object(struct drm_device *dev, 1235 struct drm_i915_gem_object *obj, int id, int align); 1236 1237 int i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1238 struct drm_mode_create_dumb *args); 1239 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1240 uint32_t handle, uint64_t *offset); 1241 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1242 uint32_t handle); 1243 1244 /* i915_gem_tiling.c */ 1245 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1246 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1247 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1248 1249 /* i915_gem_evict.c */ 1250 int i915_gem_evict_something(struct drm_device *dev, int min_size, 1251 unsigned alignment, bool mappable); 1252 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1253 int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only); 1254 1255 /* i915_suspend.c */ 1256 extern int i915_save_state(struct drm_device *dev); 1257 extern int i915_restore_state(struct drm_device *dev); 1258 1259 /* intel_iic.c */ 1260 extern int intel_setup_gmbus(struct drm_device *dev); 1261 extern void intel_teardown_gmbus(struct drm_device *dev); 1262 extern void intel_gmbus_set_speed(device_t idev, int speed); 1263 extern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1264 extern void intel_iic_reset(struct drm_device *dev); 1265 1266 /* intel_opregion.c */ 1267 int intel_opregion_setup(struct drm_device *dev); 1268 extern int intel_opregion_init(struct drm_device *dev); 1269 extern void intel_opregion_fini(struct drm_device *dev); 1270 extern void opregion_asle_intr(struct drm_device *dev); 1271 extern void opregion_enable_asle(struct drm_device *dev); 1272 1273 /* i915_gem_gtt.c */ 1274 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1275 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1276 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1277 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1278 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1279 struct drm_i915_gem_object *obj); 1280 1281 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1282 int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1283 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1284 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1285 enum i915_cache_level cache_level); 1286 1287 /* modesetting */ 1288 extern void intel_modeset_init(struct drm_device *dev); 1289 extern void intel_modeset_gem_init(struct drm_device *dev); 1290 extern void intel_modeset_cleanup(struct drm_device *dev); 1291 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1292 extern void intel_disable_fbc(struct drm_device *dev); 1293 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1294 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1295 extern void ironlake_enable_rc6(struct drm_device *dev); 1296 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1297 extern void intel_detect_pch(struct drm_device *dev); 1298 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1299 1300 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1301 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1302 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1303 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1304 1305 extern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1306 struct drm_device *dev); 1307 extern void intel_overlay_print_error_state(struct sbuf *m, 1308 struct intel_overlay_error_state *error); 1309 extern struct intel_display_error_state *intel_display_capture_error_state( 1310 struct drm_device *dev); 1311 extern void intel_display_print_error_state(struct sbuf *m, 1312 struct drm_device *dev, struct intel_display_error_state *error); 1313 1314 static inline void 1315 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1316 { 1317 return; 1318 } 1319 1320 /* On SNB platform, before reading ring registers forcewake bit 1321 * must be set to prevent GT core from power down and stale values being 1322 * returned. 1323 */ 1324 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1325 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1326 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1327 1328 /* We give fast paths for the really cool registers */ 1329 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1330 (((dev_priv)->info->gen >= 6) && \ 1331 ((reg) < 0x40000) && \ 1332 ((reg) != FORCEWAKE)) 1333 1334 #define __i915_read(x, y) \ 1335 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1336 1337 __i915_read(8, 8) 1338 __i915_read(16, 16) 1339 __i915_read(32, 32) 1340 __i915_read(64, 64) 1341 #undef __i915_read 1342 1343 #define __i915_write(x, y) \ 1344 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1345 1346 __i915_write(8, 8) 1347 __i915_write(16, 16) 1348 __i915_write(32, 32) 1349 __i915_write(64, 64) 1350 #undef __i915_write 1351 1352 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1353 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1354 1355 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1356 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1357 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1358 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1359 1360 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1361 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1362 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1363 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1364 1365 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1366 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1367 1368 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1369 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1370 1371 #define I915_VERBOSE 0 1372 1373 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) 1374 1375 #define BEGIN_LP_RING(n) \ 1376 intel_ring_begin(LP_RING(dev_priv), (n)) 1377 1378 #define OUT_RING(x) \ 1379 intel_ring_emit(LP_RING(dev_priv), x) 1380 1381 #define ADVANCE_LP_RING() \ 1382 intel_ring_advance(LP_RING(dev_priv)) 1383 1384 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1385 if (LP_RING(dev->dev_private)->obj == NULL) \ 1386 LOCK_TEST_WITH_RETURN(dev, file); \ 1387 } while (0) 1388 1389 /** 1390 * Reads a dword out of the status page, which is written to from the command 1391 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1392 * MI_STORE_DATA_IMM. 1393 * 1394 * The following dwords have a reserved meaning: 1395 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1396 * 0x04: ring 0 head pointer 1397 * 0x05: ring 1 head pointer (915-class) 1398 * 0x06: ring 2 head pointer (915-class) 1399 * 0x10-0x1b: Context status DWords (GM45) 1400 * 0x1f: Last written status offset. (GM45) 1401 * 1402 * The area from dword 0x20 to 0x3ff is available for driver usage. 1403 */ 1404 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 1405 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1406 #define I915_GEM_HWS_INDEX 0x20 1407 #define I915_BREADCRUMB_INDEX 0x21 1408 1409 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1410 1411 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1412 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1413 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1414 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1415 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1416 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1417 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1418 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1419 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1420 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1421 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1422 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1423 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1424 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1425 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1426 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1427 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1428 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1429 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1430 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1431 (dev)->pci_device == 0x0152 || \ 1432 (dev)->pci_device == 0x015a) 1433 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1434 (dev)->pci_device == 0x0106 || \ 1435 (dev)->pci_device == 0x010A) 1436 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1437 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1438 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1439 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1440 ((dev)->pci_device & 0xFF00) == 0x0A00) 1441 1442 /* XXXKIB LEGACY */ 1443 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1444 (dev)->pci_device == 0x2982 || \ 1445 (dev)->pci_device == 0x2992 || \ 1446 (dev)->pci_device == 0x29A2 || \ 1447 (dev)->pci_device == 0x2A02 || \ 1448 (dev)->pci_device == 0x2A12 || \ 1449 (dev)->pci_device == 0x2A42 || \ 1450 (dev)->pci_device == 0x2E02 || \ 1451 (dev)->pci_device == 0x2E12 || \ 1452 (dev)->pci_device == 0x2E22 || \ 1453 (dev)->pci_device == 0x2E32) 1454 1455 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1456 1457 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1458 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1459 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1460 1461 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1462 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1463 /* XXXKIB LEGACY END */ 1464 1465 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1466 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1467 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1468 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1469 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1470 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1471 1472 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1473 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1474 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1475 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1476 1477 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1478 1479 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1480 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1481 1482 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1483 * rows, which changed the alignment requirements and fence programming. 1484 */ 1485 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1486 IS_I915GM(dev))) 1487 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1488 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1489 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1490 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1491 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1492 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1493 /* dsparb controlled by hw only */ 1494 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1495 1496 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1497 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1498 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1499 1500 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1501 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1502 1503 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1504 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1505 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1506 1507 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1508 1509 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 1510 1511 static inline bool 1512 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1513 { 1514 1515 return ((int32_t)(seq1 - seq2) >= 0); 1516 } 1517 1518 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1519 1520 #endif 1521