1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi_drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include <linux/io-mapping.h> 39 #include <linux/i2c.h> 40 #include <drm/intel-gtt.h> 41 #include <linux/backlight.h> 42 #include <linux/kref.h> 43 #include <linux/kconfig.h> 44 #include <linux/pm_qos.h> 45 46 #define CONFIG_ACPI 1 47 48 /* General customization: 49 */ 50 51 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 52 53 #define DRIVER_NAME "i915" 54 #define DRIVER_DESC "Intel Graphics" 55 #define DRIVER_DATE "20080730" 56 57 enum i915_pipe { 58 INVALID_PIPE = -1, 59 PIPE_A = 0, 60 PIPE_B, 61 PIPE_C, 62 I915_MAX_PIPES 63 }; 64 #define pipe_name(p) ((p) + 'A') 65 66 enum transcoder { 67 TRANSCODER_A = 0, 68 TRANSCODER_B, 69 TRANSCODER_C, 70 TRANSCODER_EDP = 0xF, 71 }; 72 #define transcoder_name(t) ((t) + 'A') 73 74 enum plane { 75 PLANE_A = 0, 76 PLANE_B, 77 PLANE_C, 78 }; 79 #define plane_name(p) ((p) + 'A') 80 81 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') 82 83 enum port { 84 PORT_A = 0, 85 PORT_B, 86 PORT_C, 87 PORT_D, 88 PORT_E, 89 I915_MAX_PORTS 90 }; 91 #define port_name(p) ((p) + 'A') 92 93 #define I915_NUM_PHYS_VLV 1 94 95 enum dpio_channel { 96 DPIO_CH0, 97 DPIO_CH1 98 }; 99 100 enum dpio_phy { 101 DPIO_PHY0, 102 DPIO_PHY1 103 }; 104 105 enum intel_display_power_domain { 106 POWER_DOMAIN_PIPE_A, 107 POWER_DOMAIN_PIPE_B, 108 POWER_DOMAIN_PIPE_C, 109 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 110 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 111 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 112 POWER_DOMAIN_TRANSCODER_A, 113 POWER_DOMAIN_TRANSCODER_B, 114 POWER_DOMAIN_TRANSCODER_C, 115 POWER_DOMAIN_TRANSCODER_EDP, 116 POWER_DOMAIN_VGA, 117 POWER_DOMAIN_AUDIO, 118 POWER_DOMAIN_INIT, 119 120 POWER_DOMAIN_NUM, 121 }; 122 123 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 124 125 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 126 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 127 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 128 #define POWER_DOMAIN_TRANSCODER(tran) \ 129 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 130 (tran) + POWER_DOMAIN_TRANSCODER_A) 131 132 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 133 BIT(POWER_DOMAIN_PIPE_A) | \ 134 BIT(POWER_DOMAIN_TRANSCODER_EDP)) 135 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 136 BIT(POWER_DOMAIN_PIPE_A) | \ 137 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 138 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 139 140 enum hpd_pin { 141 HPD_NONE = 0, 142 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 143 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 144 HPD_CRT, 145 HPD_SDVO_B, 146 HPD_SDVO_C, 147 HPD_PORT_B, 148 HPD_PORT_C, 149 HPD_PORT_D, 150 HPD_NUM_PINS 151 }; 152 153 #define I915_GEM_GPU_DOMAINS \ 154 (I915_GEM_DOMAIN_RENDER | \ 155 I915_GEM_DOMAIN_SAMPLER | \ 156 I915_GEM_DOMAIN_COMMAND | \ 157 I915_GEM_DOMAIN_INSTRUCTION | \ 158 I915_GEM_DOMAIN_VERTEX) 159 160 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) 161 162 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 163 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 164 if ((intel_encoder)->base.crtc == (__crtc)) 165 166 struct drm_i915_private; 167 168 enum intel_dpll_id { 169 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 170 /* real shared dpll ids must be >= 0 */ 171 DPLL_ID_PCH_PLL_A, 172 DPLL_ID_PCH_PLL_B, 173 }; 174 #define I915_NUM_PLLS 2 175 176 struct intel_dpll_hw_state { 177 uint32_t dpll; 178 uint32_t dpll_md; 179 uint32_t fp0; 180 uint32_t fp1; 181 }; 182 183 struct intel_shared_dpll { 184 int refcount; /* count of number of CRTCs sharing this PLL */ 185 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 186 bool on; /* is the PLL actually active? Disabled during modeset */ 187 const char *name; 188 /* should match the index in the dev_priv->shared_dplls array */ 189 enum intel_dpll_id id; 190 struct intel_dpll_hw_state hw_state; 191 void (*mode_set)(struct drm_i915_private *dev_priv, 192 struct intel_shared_dpll *pll); 193 void (*enable)(struct drm_i915_private *dev_priv, 194 struct intel_shared_dpll *pll); 195 void (*disable)(struct drm_i915_private *dev_priv, 196 struct intel_shared_dpll *pll); 197 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 198 struct intel_shared_dpll *pll, 199 struct intel_dpll_hw_state *hw_state); 200 }; 201 202 /* Used by dp and fdi links */ 203 struct intel_link_m_n { 204 uint32_t tu; 205 uint32_t gmch_m; 206 uint32_t gmch_n; 207 uint32_t link_m; 208 uint32_t link_n; 209 }; 210 211 void intel_link_compute_m_n(int bpp, int nlanes, 212 int pixel_clock, int link_clock, 213 struct intel_link_m_n *m_n); 214 215 struct intel_ddi_plls { 216 int spll_refcount; 217 int wrpll1_refcount; 218 int wrpll2_refcount; 219 }; 220 221 /* Interface history: 222 * 223 * 1.1: Original. 224 * 1.2: Add Power Management 225 * 1.3: Add vblank support 226 * 1.4: Fix cmdbuffer path, add heap destroy 227 * 1.5: Add vblank pipe configuration 228 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 229 * - Support vertical blank on secondary display pipe 230 */ 231 #define DRIVER_MAJOR 1 232 #define DRIVER_MINOR 6 233 #define DRIVER_PATCHLEVEL 0 234 235 #define WATCH_LISTS 0 236 #define WATCH_GTT 0 237 238 #define I915_GEM_PHYS_CURSOR_0 1 239 #define I915_GEM_PHYS_CURSOR_1 2 240 #define I915_GEM_PHYS_OVERLAY_REGS 3 241 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 242 243 struct drm_i915_gem_phys_object { 244 int id; 245 struct vm_page **page_list; 246 drm_dma_handle_t *handle; 247 struct drm_i915_gem_object *cur_obj; 248 }; 249 250 struct opregion_header; 251 struct opregion_acpi; 252 struct opregion_swsci; 253 struct opregion_asle; 254 255 struct intel_opregion { 256 struct opregion_header __iomem *header; 257 struct opregion_acpi __iomem *acpi; 258 struct opregion_swsci __iomem *swsci; 259 u32 swsci_gbda_sub_functions; 260 u32 swsci_sbcb_sub_functions; 261 struct opregion_asle __iomem *asle; 262 void __iomem *vbt; 263 u32 __iomem *lid_state; 264 struct work_struct asle_work; 265 }; 266 #define OPREGION_SIZE (8*1024) 267 268 struct intel_overlay; 269 struct intel_overlay_error_state; 270 271 struct drm_i915_master_private { 272 drm_local_map_t *sarea; 273 struct _drm_i915_sarea *sarea_priv; 274 }; 275 #define I915_FENCE_REG_NONE -1 276 #define I915_MAX_NUM_FENCES 32 277 /* 32 fences + sign bit for FENCE_REG_NONE */ 278 #define I915_MAX_NUM_FENCE_BITS 6 279 280 struct drm_i915_fence_reg { 281 struct list_head lru_list; 282 struct drm_i915_gem_object *obj; 283 int pin_count; 284 }; 285 286 struct sdvo_device_mapping { 287 u8 initialized; 288 u8 dvo_port; 289 u8 slave_addr; 290 u8 dvo_wiring; 291 u8 i2c_pin; 292 u8 ddc_pin; 293 }; 294 295 struct intel_display_error_state; 296 297 struct drm_i915_error_state { 298 struct kref ref; 299 u32 eir; 300 u32 pgtbl_er; 301 u32 ier; 302 u32 ccid; 303 u32 derrmr; 304 u32 forcewake; 305 bool waiting[I915_NUM_RINGS]; 306 u32 pipestat[I915_MAX_PIPES]; 307 u32 tail[I915_NUM_RINGS]; 308 u32 head[I915_NUM_RINGS]; 309 u32 ctl[I915_NUM_RINGS]; 310 u32 ipeir[I915_NUM_RINGS]; 311 u32 ipehr[I915_NUM_RINGS]; 312 u32 instdone[I915_NUM_RINGS]; 313 u32 acthd[I915_NUM_RINGS]; 314 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 315 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 316 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ 317 /* our own tracking of ring head and tail */ 318 u32 cpu_ring_head[I915_NUM_RINGS]; 319 u32 cpu_ring_tail[I915_NUM_RINGS]; 320 u32 error; /* gen6+ */ 321 u32 err_int; /* gen7 */ 322 u32 bbstate[I915_NUM_RINGS]; 323 u32 instpm[I915_NUM_RINGS]; 324 u32 instps[I915_NUM_RINGS]; 325 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 326 u32 seqno[I915_NUM_RINGS]; 327 u64 bbaddr[I915_NUM_RINGS]; 328 u32 fault_reg[I915_NUM_RINGS]; 329 u32 done_reg; 330 u32 faddr[I915_NUM_RINGS]; 331 u64 fence[I915_MAX_NUM_FENCES]; 332 struct timeval time; 333 struct drm_i915_error_ring { 334 bool valid; 335 struct drm_i915_error_object { 336 int page_count; 337 u32 gtt_offset; 338 u32 *pages[0]; 339 } *ringbuffer, *batchbuffer, *ctx; 340 struct drm_i915_error_request { 341 long jiffies; 342 u32 seqno; 343 u32 tail; 344 } *requests; 345 int num_requests; 346 } ring[I915_NUM_RINGS]; 347 struct drm_i915_error_buffer { 348 u32 size; 349 u32 name; 350 u32 rseqno, wseqno; 351 u32 gtt_offset; 352 u32 read_domains; 353 u32 write_domain; 354 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 355 s32 pinned:2; 356 u32 tiling:2; 357 u32 dirty:1; 358 u32 purgeable:1; 359 s32 ring:4; 360 u32 cache_level:3; 361 } **active_bo, **pinned_bo; 362 u32 *active_bo_count, *pinned_bo_count; 363 struct intel_overlay_error_state *overlay; 364 struct intel_display_error_state *display; 365 int hangcheck_score[I915_NUM_RINGS]; 366 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS]; 367 }; 368 369 struct intel_connector; 370 struct intel_crtc_config; 371 struct intel_crtc; 372 struct intel_limit; 373 struct dpll; 374 375 struct drm_i915_display_funcs { 376 bool (*fbc_enabled)(struct drm_device *dev); 377 void (*enable_fbc)(struct drm_crtc *crtc); 378 void (*disable_fbc)(struct drm_device *dev); 379 int (*get_display_clock_speed)(struct drm_device *dev); 380 int (*get_fifo_size)(struct drm_device *dev, int plane); 381 /** 382 * find_dpll() - Find the best values for the PLL 383 * @limit: limits for the PLL 384 * @crtc: current CRTC 385 * @target: target frequency in kHz 386 * @refclk: reference clock frequency in kHz 387 * @match_clock: if provided, @best_clock P divider must 388 * match the P divider from @match_clock 389 * used for LVDS downclocking 390 * @best_clock: best PLL values found 391 * 392 * Returns true on success, false on failure. 393 */ 394 bool (*find_dpll)(const struct intel_limit *limit, 395 struct drm_crtc *crtc, 396 int target, int refclk, 397 struct dpll *match_clock, 398 struct dpll *best_clock); 399 void (*update_wm)(struct drm_crtc *crtc); 400 void (*update_sprite_wm)(struct drm_plane *plane, 401 struct drm_crtc *crtc, 402 uint32_t sprite_width, int pixel_size, 403 bool enable, bool scaled); 404 void (*modeset_global_resources)(struct drm_device *dev); 405 /* Returns the active state of the crtc, and if the crtc is active, 406 * fills out the pipe-config with the hw state. */ 407 bool (*get_pipe_config)(struct intel_crtc *, 408 struct intel_crtc_config *); 409 int (*crtc_mode_set)(struct drm_crtc *crtc, 410 int x, int y, 411 struct drm_framebuffer *old_fb); 412 void (*crtc_enable)(struct drm_crtc *crtc); 413 void (*crtc_disable)(struct drm_crtc *crtc); 414 void (*off)(struct drm_crtc *crtc); 415 void (*write_eld)(struct drm_connector *connector, 416 struct drm_crtc *crtc, 417 struct drm_display_mode *mode); 418 void (*fdi_link_train)(struct drm_crtc *crtc); 419 void (*init_clock_gating)(struct drm_device *dev); 420 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 421 struct drm_framebuffer *fb, 422 struct drm_i915_gem_object *obj, 423 uint32_t flags); 424 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 425 int x, int y); 426 void (*hpd_irq_setup)(struct drm_device *dev); 427 /* clock updates for mode set */ 428 /* cursor updates */ 429 /* render clock increase/decrease */ 430 /* display clock increase/decrease */ 431 /* pll clock increase/decrease */ 432 433 int (*setup_backlight)(struct intel_connector *connector); 434 uint32_t (*get_backlight)(struct intel_connector *connector); 435 void (*set_backlight)(struct intel_connector *connector, 436 uint32_t level); 437 void (*disable_backlight)(struct intel_connector *connector); 438 void (*enable_backlight)(struct intel_connector *connector); 439 }; 440 441 struct intel_uncore_funcs { 442 void (*force_wake_get)(struct drm_i915_private *dev_priv, 443 int fw_engine); 444 void (*force_wake_put)(struct drm_i915_private *dev_priv, 445 int fw_engine); 446 447 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 448 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 449 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 450 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 451 452 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 453 uint8_t val, bool trace); 454 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 455 uint16_t val, bool trace); 456 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 457 uint32_t val, bool trace); 458 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 459 uint64_t val, bool trace); 460 }; 461 462 struct intel_uncore { 463 struct lock lock; /** lock is also taken in irq contexts. */ 464 465 struct intel_uncore_funcs funcs; 466 467 unsigned fifo_count; 468 unsigned forcewake_count; 469 470 unsigned fw_rendercount; 471 unsigned fw_mediacount; 472 473 struct delayed_work force_wake_work; 474 }; 475 476 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 477 func(is_mobile) sep \ 478 func(is_i85x) sep \ 479 func(is_i915g) sep \ 480 func(is_i945gm) sep \ 481 func(is_g33) sep \ 482 func(need_gfx_hws) sep \ 483 func(is_g4x) sep \ 484 func(is_pineview) sep \ 485 func(is_broadwater) sep \ 486 func(is_crestline) sep \ 487 func(is_ivybridge) sep \ 488 func(is_valleyview) sep \ 489 func(is_haswell) sep \ 490 func(is_preliminary) sep \ 491 func(has_fbc) sep \ 492 func(has_pipe_cxsr) sep \ 493 func(has_hotplug) sep \ 494 func(cursor_needs_physical) sep \ 495 func(has_overlay) sep \ 496 func(overlay_needs_physical) sep \ 497 func(supports_tv) sep \ 498 func(has_llc) sep \ 499 func(has_ddi) sep \ 500 func(has_fpga_dbg) 501 502 #define DEFINE_FLAG(name) u8 name:1 503 #define SEP_SEMICOLON ; 504 505 struct intel_device_info { 506 u32 display_mmio_offset; 507 u8 num_pipes:3; 508 u8 gen; 509 u8 ring_mask; /* Rings supported by the HW */ 510 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 511 }; 512 513 #undef DEFINE_FLAG 514 #undef SEP_SEMICOLON 515 516 enum i915_cache_level { 517 I915_CACHE_NONE = 0, 518 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 519 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 520 caches, eg sampler/render caches, and the 521 large Last-Level-Cache. LLC is coherent with 522 the CPU, but L3 is only visible to the GPU. */ 523 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 524 }; 525 526 typedef uint32_t gen6_gtt_pte_t; 527 528 struct i915_address_space { 529 struct drm_mm mm; 530 struct drm_device *dev; 531 struct list_head global_link; 532 unsigned long start; /* Start offset always 0 for dri2 */ 533 size_t total; /* size addr space maps (ex. 2GB for ggtt) */ 534 535 struct { 536 dma_addr_t addr; 537 struct vm_page *page; 538 } scratch; 539 540 /** 541 * List of objects currently involved in rendering. 542 * 543 * Includes buffers having the contents of their GPU caches 544 * flushed, not necessarily primitives. last_rendering_seqno 545 * represents when the rendering involved will be completed. 546 * 547 * A reference is held on the buffer while on this list. 548 */ 549 struct list_head active_list; 550 551 /** 552 * LRU list of objects which are not in the ringbuffer and 553 * are ready to unbind, but are still in the GTT. 554 * 555 * last_rendering_seqno is 0 while an object is in this list. 556 * 557 * A reference is not held on the buffer while on this list, 558 * as merely being GTT-bound shouldn't prevent its being 559 * freed, and we'll pull it off the list in the free path. 560 */ 561 struct list_head inactive_list; 562 563 /* FIXME: Need a more generic return type */ 564 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, 565 enum i915_cache_level level, 566 bool valid); /* Create a valid PTE */ 567 void (*clear_range)(struct i915_address_space *vm, 568 unsigned int first_entry, 569 unsigned int num_entries, 570 bool use_scratch); 571 void (*insert_entries)(struct i915_address_space *vm, 572 vm_page_t *pages, 573 unsigned int first_entry, 574 unsigned int num_entries, 575 enum i915_cache_level cache_level); 576 void (*cleanup)(struct i915_address_space *vm); 577 }; 578 579 /* The Graphics Translation Table is the way in which GEN hardware translates a 580 * Graphics Virtual Address into a Physical Address. In addition to the normal 581 * collateral associated with any va->pa translations GEN hardware also has a 582 * portion of the GTT which can be mapped by the CPU and remain both coherent 583 * and correct (in cases like swizzling). That region is referred to as GMADR in 584 * the spec. 585 */ 586 struct i915_gtt { 587 struct i915_address_space base; 588 size_t stolen_size; /* Total size of stolen memory */ 589 590 unsigned long mappable_end; /* End offset that we can CPU map */ 591 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 592 phys_addr_t mappable_base; /* PA of our GMADR */ 593 594 /** "Graphics Stolen Memory" holds the global PTEs */ 595 void __iomem *gsm; 596 597 bool do_idle_maps; 598 599 int mtrr; 600 601 /* global gtt ops */ 602 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, 603 size_t *stolen, phys_addr_t *mappable_base, 604 unsigned long *mappable_end); 605 }; 606 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) 607 608 struct i915_hw_ppgtt { 609 struct i915_address_space base; 610 unsigned num_pd_entries; 611 union { 612 struct vm_page **pt_pages; 613 struct vm_page *gen8_pt_pages; 614 }; 615 struct vm_page *pd_pages; 616 int num_pd_pages; 617 int num_pt_pages; 618 union { 619 uint32_t pd_offset; 620 dma_addr_t pd_dma_addr[4]; 621 }; 622 union { 623 dma_addr_t *pt_dma_addr; 624 dma_addr_t *gen8_pt_dma_addr[4]; 625 }; 626 int (*enable)(struct drm_device *dev); 627 }; 628 629 /** 630 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 631 * VMA's presence cannot be guaranteed before binding, or after unbinding the 632 * object into/from the address space. 633 * 634 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 635 * will always be <= an objects lifetime. So object refcounting should cover us. 636 */ 637 struct i915_vma { 638 struct drm_mm_node node; 639 struct drm_i915_gem_object *obj; 640 struct i915_address_space *vm; 641 642 /** This object's place on the active/inactive lists */ 643 struct list_head mm_list; 644 645 struct list_head vma_link; /* Link in the object's VMA list */ 646 647 /** This vma's place in the batchbuffer or on the eviction list */ 648 struct list_head exec_list; 649 650 /** 651 * Used for performing relocations during execbuffer insertion. 652 */ 653 struct hlist_node exec_node; 654 unsigned long exec_handle; 655 struct drm_i915_gem_exec_object2 *exec_entry; 656 657 }; 658 659 struct i915_ctx_hang_stats { 660 /* This context had batch pending when hang was declared */ 661 unsigned batch_pending; 662 663 /* This context had batch active when hang was declared */ 664 unsigned batch_active; 665 666 /* Time when this context was last blamed for a GPU reset */ 667 unsigned long guilty_ts; 668 669 /* This context is banned to submit more work */ 670 bool banned; 671 }; 672 673 /* This must match up with the value previously used for execbuf2.rsvd1. */ 674 #define DEFAULT_CONTEXT_ID 0 675 struct i915_hw_context { 676 struct kref ref; 677 int id; 678 bool is_initialized; 679 uint8_t remap_slice; 680 struct drm_i915_file_private *file_priv; 681 struct intel_ring_buffer *ring; 682 struct drm_i915_gem_object *obj; 683 struct i915_ctx_hang_stats hang_stats; 684 685 struct list_head link; 686 }; 687 688 struct i915_fbc { 689 unsigned long size; 690 unsigned int fb_id; 691 enum plane plane; 692 int y; 693 694 struct drm_mm_node *compressed_fb; 695 struct drm_mm_node *compressed_llb; 696 697 struct intel_fbc_work { 698 struct delayed_work work; 699 struct drm_crtc *crtc; 700 struct drm_framebuffer *fb; 701 } *fbc_work; 702 703 enum no_fbc_reason { 704 FBC_OK, /* FBC is enabled */ 705 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 706 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 707 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 708 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 709 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 710 FBC_BAD_PLANE, /* fbc not supported on plane */ 711 FBC_NOT_TILED, /* buffer not tiled */ 712 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 713 FBC_MODULE_PARAM, 714 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 715 } no_fbc_reason; 716 }; 717 718 struct i915_psr { 719 bool sink_support; 720 bool source_ok; 721 }; 722 723 enum intel_pch { 724 PCH_NONE = 0, /* No PCH present */ 725 PCH_IBX, /* Ibexpeak PCH */ 726 PCH_CPT, /* Cougarpoint PCH */ 727 PCH_LPT, /* Lynxpoint PCH */ 728 PCH_NOP, 729 }; 730 731 enum intel_sbi_destination { 732 SBI_ICLK, 733 SBI_MPHY, 734 }; 735 736 #define QUIRK_PIPEA_FORCE (1<<0) 737 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 738 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 739 740 struct intel_fbdev; 741 struct intel_fbc_work; 742 743 struct intel_gmbus { 744 u32 force_bit; 745 u32 reg0; 746 u32 gpio_reg; 747 struct drm_i915_private *dev_priv; 748 }; 749 750 struct intel_iic_softc { 751 struct drm_device *drm_dev; 752 device_t iic_dev; 753 bool force_bit_dev; 754 char name[32]; 755 uint32_t reg; 756 uint32_t reg0; 757 }; 758 759 struct i915_suspend_saved_registers { 760 u8 saveLBB; 761 u32 saveDSPACNTR; 762 u32 saveDSPBCNTR; 763 u32 saveDSPARB; 764 u32 savePIPEACONF; 765 u32 savePIPEBCONF; 766 u32 savePIPEASRC; 767 u32 savePIPEBSRC; 768 u32 saveFPA0; 769 u32 saveFPA1; 770 u32 saveDPLL_A; 771 u32 saveDPLL_A_MD; 772 u32 saveHTOTAL_A; 773 u32 saveHBLANK_A; 774 u32 saveHSYNC_A; 775 u32 saveVTOTAL_A; 776 u32 saveVBLANK_A; 777 u32 saveVSYNC_A; 778 u32 saveBCLRPAT_A; 779 u32 saveTRANSACONF; 780 u32 saveTRANS_HTOTAL_A; 781 u32 saveTRANS_HBLANK_A; 782 u32 saveTRANS_HSYNC_A; 783 u32 saveTRANS_VTOTAL_A; 784 u32 saveTRANS_VBLANK_A; 785 u32 saveTRANS_VSYNC_A; 786 u32 savePIPEASTAT; 787 u32 saveDSPASTRIDE; 788 u32 saveDSPASIZE; 789 u32 saveDSPAPOS; 790 u32 saveDSPAADDR; 791 u32 saveDSPASURF; 792 u32 saveDSPATILEOFF; 793 u32 savePFIT_PGM_RATIOS; 794 u32 saveBLC_HIST_CTL; 795 u32 saveBLC_PWM_CTL; 796 u32 saveBLC_PWM_CTL2; 797 u32 saveBLC_HIST_CTL_B; 798 u32 saveBLC_CPU_PWM_CTL; 799 u32 saveBLC_CPU_PWM_CTL2; 800 u32 saveFPB0; 801 u32 saveFPB1; 802 u32 saveDPLL_B; 803 u32 saveDPLL_B_MD; 804 u32 saveHTOTAL_B; 805 u32 saveHBLANK_B; 806 u32 saveHSYNC_B; 807 u32 saveVTOTAL_B; 808 u32 saveVBLANK_B; 809 u32 saveVSYNC_B; 810 u32 saveBCLRPAT_B; 811 u32 saveTRANSBCONF; 812 u32 saveTRANS_HTOTAL_B; 813 u32 saveTRANS_HBLANK_B; 814 u32 saveTRANS_HSYNC_B; 815 u32 saveTRANS_VTOTAL_B; 816 u32 saveTRANS_VBLANK_B; 817 u32 saveTRANS_VSYNC_B; 818 u32 savePIPEBSTAT; 819 u32 saveDSPBSTRIDE; 820 u32 saveDSPBSIZE; 821 u32 saveDSPBPOS; 822 u32 saveDSPBADDR; 823 u32 saveDSPBSURF; 824 u32 saveDSPBTILEOFF; 825 u32 saveVGA0; 826 u32 saveVGA1; 827 u32 saveVGA_PD; 828 u32 saveVGACNTRL; 829 u32 saveADPA; 830 u32 saveLVDS; 831 u32 savePP_ON_DELAYS; 832 u32 savePP_OFF_DELAYS; 833 u32 saveDVOA; 834 u32 saveDVOB; 835 u32 saveDVOC; 836 u32 savePP_ON; 837 u32 savePP_OFF; 838 u32 savePP_CONTROL; 839 u32 savePP_DIVISOR; 840 u32 savePFIT_CONTROL; 841 u32 save_palette_a[256]; 842 u32 save_palette_b[256]; 843 u32 saveDPFC_CB_BASE; 844 u32 saveFBC_CFB_BASE; 845 u32 saveFBC_LL_BASE; 846 u32 saveFBC_CONTROL; 847 u32 saveFBC_CONTROL2; 848 u32 saveIER; 849 u32 saveIIR; 850 u32 saveIMR; 851 u32 saveDEIER; 852 u32 saveDEIMR; 853 u32 saveGTIER; 854 u32 saveGTIMR; 855 u32 saveFDI_RXA_IMR; 856 u32 saveFDI_RXB_IMR; 857 u32 saveCACHE_MODE_0; 858 u32 saveMI_ARB_STATE; 859 u32 saveSWF0[16]; 860 u32 saveSWF1[16]; 861 u32 saveSWF2[3]; 862 u8 saveMSR; 863 u8 saveSR[8]; 864 u8 saveGR[25]; 865 u8 saveAR_INDEX; 866 u8 saveAR[21]; 867 u8 saveDACMASK; 868 u8 saveCR[37]; 869 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 870 u32 saveCURACNTR; 871 u32 saveCURAPOS; 872 u32 saveCURABASE; 873 u32 saveCURBCNTR; 874 u32 saveCURBPOS; 875 u32 saveCURBBASE; 876 u32 saveCURSIZE; 877 u32 saveDP_B; 878 u32 saveDP_C; 879 u32 saveDP_D; 880 u32 savePIPEA_GMCH_DATA_M; 881 u32 savePIPEB_GMCH_DATA_M; 882 u32 savePIPEA_GMCH_DATA_N; 883 u32 savePIPEB_GMCH_DATA_N; 884 u32 savePIPEA_DP_LINK_M; 885 u32 savePIPEB_DP_LINK_M; 886 u32 savePIPEA_DP_LINK_N; 887 u32 savePIPEB_DP_LINK_N; 888 u32 saveFDI_RXA_CTL; 889 u32 saveFDI_TXA_CTL; 890 u32 saveFDI_RXB_CTL; 891 u32 saveFDI_TXB_CTL; 892 u32 savePFA_CTL_1; 893 u32 savePFB_CTL_1; 894 u32 savePFA_WIN_SZ; 895 u32 savePFB_WIN_SZ; 896 u32 savePFA_WIN_POS; 897 u32 savePFB_WIN_POS; 898 u32 savePCH_DREF_CONTROL; 899 u32 saveDISP_ARB_CTL; 900 u32 savePIPEA_DATA_M1; 901 u32 savePIPEA_DATA_N1; 902 u32 savePIPEA_LINK_M1; 903 u32 savePIPEA_LINK_N1; 904 u32 savePIPEB_DATA_M1; 905 u32 savePIPEB_DATA_N1; 906 u32 savePIPEB_LINK_M1; 907 u32 savePIPEB_LINK_N1; 908 u32 saveMCHBAR_RENDER_STANDBY; 909 u32 savePCH_PORT_HOTPLUG; 910 }; 911 912 struct intel_gen6_power_mgmt { 913 /* work and pm_iir are protected by dev_priv->irq_lock */ 914 struct work_struct work; 915 u32 pm_iir; 916 917 /* The below variables an all the rps hw state are protected by 918 * dev->struct mutext. */ 919 u8 cur_delay; 920 u8 min_delay; 921 u8 max_delay; 922 u8 rpe_delay; 923 u8 rp1_delay; 924 u8 rp0_delay; 925 u8 hw_max; 926 927 int last_adj; 928 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 929 930 bool enabled; 931 struct delayed_work delayed_resume_work; 932 933 /* 934 * Protects RPS/RC6 register access and PCU communication. 935 * Must be taken after struct_mutex if nested. 936 */ 937 struct lock hw_lock; 938 }; 939 940 /* defined intel_pm.c */ 941 extern struct lock mchdev_lock; 942 943 struct intel_ilk_power_mgmt { 944 u8 cur_delay; 945 u8 min_delay; 946 u8 max_delay; 947 u8 fmax; 948 u8 fstart; 949 950 u64 last_count1; 951 unsigned long last_time1; 952 unsigned long chipset_power; 953 u64 last_count2; 954 struct timespec last_time2; 955 unsigned long gfx_power; 956 u8 corr; 957 958 int c_m; 959 int r_t; 960 961 struct drm_i915_gem_object *pwrctx; 962 struct drm_i915_gem_object *renderctx; 963 }; 964 965 /* Power well structure for haswell */ 966 struct i915_power_well { 967 const char *name; 968 bool always_on; 969 /* power well enable/disable usage count */ 970 int count; 971 unsigned long domains; 972 void *data; 973 void (*set)(struct drm_device *dev, struct i915_power_well *power_well, 974 bool enable); 975 bool (*is_enabled)(struct drm_device *dev, 976 struct i915_power_well *power_well); 977 }; 978 979 struct i915_power_domains { 980 /* 981 * Power wells needed for initialization at driver init and suspend 982 * time are on. They are kept on until after the first modeset. 983 */ 984 bool init_power_on; 985 int power_well_count; 986 987 struct lock lock; 988 int domain_use_count[POWER_DOMAIN_NUM]; 989 struct i915_power_well *power_wells; 990 }; 991 992 struct i915_dri1_state { 993 unsigned allow_batchbuffer : 1; 994 u32 __iomem *gfx_hws_cpu_addr; 995 996 unsigned int cpp; 997 int back_offset; 998 int front_offset; 999 int current_page; 1000 int page_flipping; 1001 1002 uint32_t counter; 1003 }; 1004 1005 struct i915_ums_state { 1006 /** 1007 * Flag if the X Server, and thus DRM, is not currently in 1008 * control of the device. 1009 * 1010 * This is set between LeaveVT and EnterVT. It needs to be 1011 * replaced with a semaphore. It also needs to be 1012 * transitioned away from for kernel modesetting. 1013 */ 1014 int mm_suspended; 1015 }; 1016 1017 #define MAX_L3_SLICES 2 1018 struct intel_l3_parity { 1019 u32 *remap_info[MAX_L3_SLICES]; 1020 struct work_struct error_work; 1021 int which_slice; 1022 }; 1023 1024 struct i915_gem_mm { 1025 /** Memory allocator for GTT stolen memory */ 1026 struct drm_mm stolen; 1027 /** List of all objects in gtt_space. Used to restore gtt 1028 * mappings on resume */ 1029 struct list_head bound_list; 1030 /** 1031 * List of objects which are not bound to the GTT (thus 1032 * are idle and not used by the GPU) but still have 1033 * (presumably uncached) pages still attached. 1034 */ 1035 struct list_head unbound_list; 1036 1037 /** Usable portion of the GTT for GEM */ 1038 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1039 1040 /** PPGTT used for aliasing the PPGTT with the GTT */ 1041 struct i915_hw_ppgtt *aliasing_ppgtt; 1042 1043 eventhandler_tag inactive_shrinker; 1044 bool shrinker_no_lock_stealing; 1045 1046 /** LRU list of objects with fence regs on them. */ 1047 struct list_head fence_list; 1048 1049 /** 1050 * We leave the user IRQ off as much as possible, 1051 * but this means that requests will finish and never 1052 * be retired once the system goes idle. Set a timer to 1053 * fire periodically while the ring is running. When it 1054 * fires, go retire requests. 1055 */ 1056 struct delayed_work retire_work; 1057 1058 /** 1059 * When we detect an idle GPU, we want to turn on 1060 * powersaving features. So once we see that there 1061 * are no more requests outstanding and no more 1062 * arrive within a small period of time, we fire 1063 * off the idle_work. 1064 */ 1065 struct delayed_work idle_work; 1066 1067 /** 1068 * Are we in a non-interruptible section of code like 1069 * modesetting? 1070 */ 1071 bool interruptible; 1072 1073 /** Bit 6 swizzling required for X tiling */ 1074 uint32_t bit_6_swizzle_x; 1075 /** Bit 6 swizzling required for Y tiling */ 1076 uint32_t bit_6_swizzle_y; 1077 1078 /* storage for physical objects */ 1079 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 1080 1081 /* accounting, useful for userland debugging */ 1082 struct spinlock object_stat_lock; 1083 size_t object_memory; 1084 u32 object_count; 1085 }; 1086 1087 struct drm_i915_error_state_buf { 1088 unsigned bytes; 1089 unsigned size; 1090 int err; 1091 u8 *buf; 1092 loff_t start; 1093 loff_t pos; 1094 }; 1095 1096 struct i915_error_state_file_priv { 1097 struct drm_device *dev; 1098 struct drm_i915_error_state *error; 1099 }; 1100 1101 struct i915_gpu_error { 1102 /* For hangcheck timer */ 1103 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1104 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1105 /* Hang gpu twice in this window and your context gets banned */ 1106 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1107 1108 struct timer_list hangcheck_timer; 1109 1110 /* For reset and error_state handling. */ 1111 struct lock lock; 1112 /* Protected by the above dev->gpu_error.lock. */ 1113 struct drm_i915_error_state *first_error; 1114 struct work_struct work; 1115 1116 1117 unsigned long missed_irq_rings; 1118 1119 /** 1120 * State variable controlling the reset flow and count 1121 * 1122 * This is a counter which gets incremented when reset is triggered, 1123 * and again when reset has been handled. So odd values (lowest bit set) 1124 * means that reset is in progress and even values that 1125 * (reset_counter >> 1):th reset was successfully completed. 1126 * 1127 * If reset is not completed succesfully, the I915_WEDGE bit is 1128 * set meaning that hardware is terminally sour and there is no 1129 * recovery. All waiters on the reset_queue will be woken when 1130 * that happens. 1131 * 1132 * This counter is used by the wait_seqno code to notice that reset 1133 * event happened and it needs to restart the entire ioctl (since most 1134 * likely the seqno it waited for won't ever signal anytime soon). 1135 * 1136 * This is important for lock-free wait paths, where no contended lock 1137 * naturally enforces the correct ordering between the bail-out of the 1138 * waiter and the gpu reset work code. 1139 */ 1140 atomic_t reset_counter; 1141 1142 #define I915_RESET_IN_PROGRESS_FLAG 1 1143 #define I915_WEDGED (1 << 31) 1144 1145 /** 1146 * Waitqueue to signal when the reset has completed. Used by clients 1147 * that wait for dev_priv->mm.wedged to settle. 1148 */ 1149 wait_queue_head_t reset_queue; 1150 1151 /* For gpu hang simulation. */ 1152 unsigned int stop_rings; 1153 1154 /* For missed irq/seqno simulation. */ 1155 unsigned int test_irq_rings; 1156 }; 1157 1158 enum modeset_restore { 1159 MODESET_ON_LID_OPEN, 1160 MODESET_DONE, 1161 MODESET_SUSPENDED, 1162 }; 1163 1164 struct ddi_vbt_port_info { 1165 uint8_t hdmi_level_shift; 1166 1167 uint8_t supports_dvi:1; 1168 uint8_t supports_hdmi:1; 1169 uint8_t supports_dp:1; 1170 }; 1171 1172 struct intel_vbt_data { 1173 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1174 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1175 1176 /* Feature bits */ 1177 unsigned int int_tv_support:1; 1178 unsigned int lvds_dither:1; 1179 unsigned int lvds_vbt:1; 1180 unsigned int int_crt_support:1; 1181 unsigned int lvds_use_ssc:1; 1182 unsigned int display_clock_mode:1; 1183 unsigned int fdi_rx_polarity_inverted:1; 1184 int lvds_ssc_freq; 1185 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1186 1187 /* eDP */ 1188 int edp_rate; 1189 int edp_lanes; 1190 int edp_preemphasis; 1191 int edp_vswing; 1192 bool edp_initialized; 1193 bool edp_support; 1194 int edp_bpp; 1195 struct edp_power_seq edp_pps; 1196 1197 struct { 1198 u16 pwm_freq_hz; 1199 bool active_low_pwm; 1200 } backlight; 1201 1202 /* MIPI DSI */ 1203 struct { 1204 u16 panel_id; 1205 } dsi; 1206 1207 int crt_ddc_pin; 1208 1209 int child_dev_num; 1210 union child_device_config *child_dev; 1211 1212 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1213 }; 1214 1215 enum intel_ddb_partitioning { 1216 INTEL_DDB_PART_1_2, 1217 INTEL_DDB_PART_5_6, /* IVB+ */ 1218 }; 1219 1220 struct intel_wm_level { 1221 bool enable; 1222 uint32_t pri_val; 1223 uint32_t spr_val; 1224 uint32_t cur_val; 1225 uint32_t fbc_val; 1226 }; 1227 1228 struct ilk_wm_values { 1229 uint32_t wm_pipe[3]; 1230 uint32_t wm_lp[3]; 1231 uint32_t wm_lp_spr[3]; 1232 uint32_t wm_linetime[3]; 1233 bool enable_fbc_wm; 1234 enum intel_ddb_partitioning partitioning; 1235 }; 1236 1237 /* 1238 * This struct tracks the state needed for the Package C8+ feature. 1239 * 1240 * Package states C8 and deeper are really deep PC states that can only be 1241 * reached when all the devices on the system allow it, so even if the graphics 1242 * device allows PC8+, it doesn't mean the system will actually get to these 1243 * states. 1244 * 1245 * Our driver only allows PC8+ when all the outputs are disabled, the power well 1246 * is disabled and the GPU is idle. When these conditions are met, we manually 1247 * do the other conditions: disable the interrupts, clocks and switch LCPLL 1248 * refclk to Fclk. 1249 * 1250 * When we really reach PC8 or deeper states (not just when we allow it) we lose 1251 * the state of some registers, so when we come back from PC8+ we need to 1252 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't 1253 * need to take care of the registers kept by RC6. 1254 * 1255 * The interrupt disabling is part of the requirements. We can only leave the 1256 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we 1257 * can lock the machine. 1258 * 1259 * Ideally every piece of our code that needs PC8+ disabled would call 1260 * hsw_disable_package_c8, which would increment disable_count and prevent the 1261 * system from reaching PC8+. But we don't have a symmetric way to do this for 1262 * everything, so we have the requirements_met and gpu_idle variables. When we 1263 * switch requirements_met or gpu_idle to true we decrease disable_count, and 1264 * increase it in the opposite case. The requirements_met variable is true when 1265 * all the CRTCs, encoders and the power well are disabled. The gpu_idle 1266 * variable is true when the GPU is idle. 1267 * 1268 * In addition to everything, we only actually enable PC8+ if disable_count 1269 * stays at zero for at least some seconds. This is implemented with the 1270 * enable_work variable. We do this so we don't enable/disable PC8 dozens of 1271 * consecutive times when all screens are disabled and some background app 1272 * queries the state of our connectors, or we have some application constantly 1273 * waking up to use the GPU. Only after the enable_work function actually 1274 * enables PC8+ the "enable" variable will become true, which means that it can 1275 * be false even if disable_count is 0. 1276 * 1277 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1278 * goes back to false exactly before we reenable the IRQs. We use this variable 1279 * to check if someone is trying to enable/disable IRQs while they're supposed 1280 * to be disabled. This shouldn't happen and we'll print some error messages in 1281 * case it happens, but if it actually happens we'll also update the variables 1282 * inside struct regsave so when we restore the IRQs they will contain the 1283 * latest expected values. 1284 * 1285 * For more, read "Display Sequences for Package C8" on our documentation. 1286 */ 1287 struct i915_package_c8 { 1288 bool requirements_met; 1289 bool gpu_idle; 1290 bool irqs_disabled; 1291 /* Only true after the delayed work task actually enables it. */ 1292 bool enabled; 1293 int disable_count; 1294 struct lock lock; 1295 struct delayed_work enable_work; 1296 1297 struct { 1298 uint32_t deimr; 1299 uint32_t sdeimr; 1300 uint32_t gtimr; 1301 uint32_t gtier; 1302 uint32_t gen6_pmimr; 1303 } regsave; 1304 }; 1305 1306 struct i915_runtime_pm { 1307 bool suspended; 1308 }; 1309 1310 enum intel_pipe_crc_source { 1311 INTEL_PIPE_CRC_SOURCE_NONE, 1312 INTEL_PIPE_CRC_SOURCE_PLANE1, 1313 INTEL_PIPE_CRC_SOURCE_PLANE2, 1314 INTEL_PIPE_CRC_SOURCE_PF, 1315 INTEL_PIPE_CRC_SOURCE_PIPE, 1316 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1317 INTEL_PIPE_CRC_SOURCE_TV, 1318 INTEL_PIPE_CRC_SOURCE_DP_B, 1319 INTEL_PIPE_CRC_SOURCE_DP_C, 1320 INTEL_PIPE_CRC_SOURCE_DP_D, 1321 INTEL_PIPE_CRC_SOURCE_AUTO, 1322 INTEL_PIPE_CRC_SOURCE_MAX, 1323 }; 1324 1325 struct intel_pipe_crc_entry { 1326 uint32_t frame; 1327 uint32_t crc[5]; 1328 }; 1329 1330 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1331 struct intel_pipe_crc { 1332 struct spinlock lock; 1333 bool opened; /* exclusive access to the result file */ 1334 struct intel_pipe_crc_entry *entries; 1335 enum intel_pipe_crc_source source; 1336 int head, tail; 1337 wait_queue_head_t wq; 1338 }; 1339 1340 typedef struct drm_i915_private { 1341 struct drm_device *dev; 1342 struct kmem_cache *slab; 1343 1344 const struct intel_device_info *info; 1345 1346 int relative_constants_mode; 1347 1348 device_t *gmbus_bridge; 1349 device_t *bbbus_bridge; 1350 device_t *bbbus; 1351 1352 drm_local_map_t *sarea; 1353 drm_local_map_t *mmio_map; 1354 char __iomem *regs; 1355 1356 struct intel_uncore uncore; 1357 1358 device_t *gmbus; 1359 1360 1361 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1362 * controller on different i2c buses. */ 1363 struct lock gmbus_mutex; 1364 1365 struct _drm_i915_sarea *sarea_priv; 1366 /** 1367 * Base address of the gmbus and gpio block. 1368 */ 1369 uint32_t gpio_mmio_base; 1370 1371 wait_queue_head_t gmbus_wait_queue; 1372 1373 struct pci_dev *bridge_dev; 1374 struct intel_ring_buffer ring[I915_NUM_RINGS]; 1375 uint32_t last_seqno, next_seqno; 1376 1377 drm_dma_handle_t *status_page_dmah; 1378 struct resource *mch_res; 1379 int mch_res_rid; 1380 1381 atomic_t irq_received; 1382 1383 /* protects the irq masks */ 1384 struct lock irq_lock; 1385 1386 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1387 struct pm_qos_request pm_qos; 1388 1389 /* DPIO indirect register protection */ 1390 struct lock dpio_lock; 1391 1392 /** Cached value of IMR to avoid reads in updating the bitfield */ 1393 union { 1394 u32 irq_mask; 1395 u32 de_irq_mask[I915_MAX_PIPES]; 1396 }; 1397 u32 gt_irq_mask; 1398 u32 pm_irq_mask; 1399 1400 struct work_struct hotplug_work; 1401 bool enable_hotplug_processing; 1402 struct { 1403 unsigned long hpd_last_jiffies; 1404 int hpd_cnt; 1405 enum { 1406 HPD_ENABLED = 0, 1407 HPD_DISABLED = 1, 1408 HPD_MARK_DISABLED = 2 1409 } hpd_mark; 1410 } hpd_stats[HPD_NUM_PINS]; 1411 u32 hpd_event_bits; 1412 struct timer_list hotplug_reenable_timer; 1413 1414 int num_plane; 1415 1416 struct i915_fbc fbc; 1417 struct intel_opregion opregion; 1418 struct intel_vbt_data vbt; 1419 1420 /* overlay */ 1421 struct intel_overlay *overlay; 1422 1423 /* backlight registers and fields in struct intel_panel */ 1424 struct spinlock backlight_lock; 1425 1426 /* LVDS info */ 1427 bool no_aux_handshake; 1428 1429 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1430 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1431 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1432 1433 unsigned int fsb_freq, mem_freq, is_ddr3; 1434 1435 /** 1436 * wq - Driver workqueue for GEM. 1437 * 1438 * NOTE: Work items scheduled here are not allowed to grab any modeset 1439 * locks, for otherwise the flushing done in the pageflip code will 1440 * result in deadlocks. 1441 */ 1442 struct workqueue_struct *wq; 1443 1444 /* Display functions */ 1445 struct drm_i915_display_funcs display; 1446 1447 /* PCH chipset type */ 1448 enum intel_pch pch_type; 1449 unsigned short pch_id; 1450 1451 unsigned long quirks; 1452 1453 enum modeset_restore modeset_restore; 1454 struct lock modeset_restore_lock; 1455 1456 struct list_head vm_list; /* Global list of all address spaces */ 1457 struct i915_gtt gtt; /* VMA representing the global address space */ 1458 1459 struct i915_gem_mm mm; 1460 1461 /* Kernel Modesetting */ 1462 1463 struct sdvo_device_mapping sdvo_mappings[2]; 1464 1465 struct drm_crtc *plane_to_crtc_mapping[3]; 1466 struct drm_crtc *pipe_to_crtc_mapping[3]; 1467 wait_queue_head_t pending_flip_queue; 1468 1469 #ifdef CONFIG_DEBUG_FS 1470 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1471 #endif 1472 1473 int num_shared_dpll; 1474 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1475 struct intel_ddi_plls ddi_plls; 1476 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1477 1478 /* Reclocking support */ 1479 bool render_reclock_avail; 1480 bool lvds_downclock_avail; 1481 /* indicates the reduced downclock for LVDS*/ 1482 int lvds_downclock; 1483 u16 orig_clock; 1484 1485 bool mchbar_need_disable; 1486 1487 struct intel_l3_parity l3_parity; 1488 1489 /* Cannot be determined by PCIID. You must always read a register. */ 1490 size_t ellc_size; 1491 1492 /* gen6+ rps state */ 1493 struct intel_gen6_power_mgmt rps; 1494 1495 /* ilk-only ips/rps state. Everything in here is protected by the global 1496 * mchdev_lock in intel_pm.c */ 1497 struct intel_ilk_power_mgmt ips; 1498 1499 struct i915_power_domains power_domains; 1500 1501 struct i915_psr psr; 1502 1503 struct i915_gpu_error gpu_error; 1504 1505 struct drm_i915_gem_object *vlv_pctx; 1506 1507 #ifdef CONFIG_DRM_I915_FBDEV 1508 /* list of fbdev register on this device */ 1509 struct intel_fbdev *fbdev; 1510 #endif 1511 1512 /* 1513 * The console may be contended at resume, but we don't 1514 * want it to block on it. 1515 */ 1516 struct work_struct console_resume_work; 1517 1518 struct drm_property *broadcast_rgb_property; 1519 struct drm_property *force_audio_property; 1520 1521 uint32_t hw_context_size; 1522 struct list_head context_list; 1523 1524 u32 fdi_rx_config; 1525 1526 struct i915_suspend_saved_registers regfile; 1527 1528 struct { 1529 /* 1530 * Raw watermark latency values: 1531 * in 0.1us units for WM0, 1532 * in 0.5us units for WM1+. 1533 */ 1534 /* primary */ 1535 uint16_t pri_latency[5]; 1536 /* sprite */ 1537 uint16_t spr_latency[5]; 1538 /* cursor */ 1539 uint16_t cur_latency[5]; 1540 1541 /* current hardware state */ 1542 struct ilk_wm_values hw; 1543 } wm; 1544 1545 struct i915_package_c8 pc8; 1546 1547 struct i915_runtime_pm pm; 1548 1549 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1550 * here! */ 1551 struct i915_dri1_state dri1; 1552 /* Old ums support infrastructure, same warning applies. */ 1553 struct i915_ums_state ums; 1554 } drm_i915_private_t; 1555 1556 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1557 { 1558 return dev->dev_private; 1559 } 1560 1561 /* Iterate over initialised rings */ 1562 #define for_each_ring(ring__, dev_priv__, i__) \ 1563 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1564 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1565 1566 enum hdmi_force_audio { 1567 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1568 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1569 HDMI_AUDIO_AUTO, /* trust EDID */ 1570 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1571 }; 1572 1573 #define I915_GTT_OFFSET_NONE ((u32)-1) 1574 1575 struct drm_i915_gem_object_ops { 1576 /* Interface between the GEM object and its backing storage. 1577 * get_pages() is called once prior to the use of the associated set 1578 * of pages before to binding them into the GTT, and put_pages() is 1579 * called after we no longer need them. As we expect there to be 1580 * associated cost with migrating pages between the backing storage 1581 * and making them available for the GPU (e.g. clflush), we may hold 1582 * onto the pages after they are no longer referenced by the GPU 1583 * in case they may be used again shortly (for example migrating the 1584 * pages to a different memory domain within the GTT). put_pages() 1585 * will therefore most likely be called when the object itself is 1586 * being released or under memory pressure (where we attempt to 1587 * reap pages for the shrinker). 1588 */ 1589 int (*get_pages)(struct drm_i915_gem_object *); 1590 void (*put_pages)(struct drm_i915_gem_object *); 1591 }; 1592 1593 struct drm_i915_gem_object { 1594 struct drm_gem_object base; 1595 1596 const struct drm_i915_gem_object_ops *ops; 1597 1598 /** List of VMAs backed by this object */ 1599 struct list_head vma_list; 1600 1601 /** Stolen memory for this object, instead of being backed by shmem. */ 1602 struct drm_mm_node *stolen; 1603 struct list_head global_list; 1604 1605 struct list_head ring_list; 1606 /** Used in execbuf to temporarily hold a ref */ 1607 struct list_head obj_exec_link; 1608 1609 /** 1610 * This is set if the object is on the active lists (has pending 1611 * rendering and so a non-zero seqno), and is not set if it i s on 1612 * inactive (ready to be unbound) list. 1613 */ 1614 unsigned int active:1; 1615 1616 /** 1617 * This is set if the object has been written to since last bound 1618 * to the GTT 1619 */ 1620 unsigned int dirty:1; 1621 1622 /** 1623 * Fence register bits (if any) for this object. Will be set 1624 * as needed when mapped into the GTT. 1625 * Protected by dev->struct_mutex. 1626 */ 1627 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1628 1629 /** 1630 * Advice: are the backing pages purgeable? 1631 */ 1632 unsigned int madv:2; 1633 1634 /** 1635 * Current tiling mode for the object. 1636 */ 1637 unsigned int tiling_mode:2; 1638 /** 1639 * Whether the tiling parameters for the currently associated fence 1640 * register have changed. Note that for the purposes of tracking 1641 * tiling changes we also treat the unfenced register, the register 1642 * slot that the object occupies whilst it executes a fenced 1643 * command (such as BLT on gen2/3), as a "fence". 1644 */ 1645 unsigned int fence_dirty:1; 1646 1647 /** How many users have pinned this object in GTT space. The following 1648 * users can each hold at most one reference: pwrite/pread, pin_ioctl 1649 * (via user_pin_count), execbuffer (objects are not allowed multiple 1650 * times for the same batchbuffer), and the framebuffer code. When 1651 * switching/pageflipping, the framebuffer code has at most two buffers 1652 * pinned per crtc. 1653 * 1654 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1655 * bits with absolutely no headroom. So use 4 bits. */ 1656 unsigned int pin_count:4; 1657 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1658 1659 /** 1660 * Is the object at the current location in the gtt mappable and 1661 * fenceable? Used to avoid costly recalculations. 1662 */ 1663 unsigned int map_and_fenceable:1; 1664 1665 /** 1666 * Whether the current gtt mapping needs to be mappable (and isn't just 1667 * mappable by accident). Track pin and fault separate for a more 1668 * accurate mappable working set. 1669 */ 1670 unsigned int fault_mappable:1; 1671 unsigned int pin_mappable:1; 1672 unsigned int pin_display:1; 1673 1674 /* 1675 * Is the GPU currently using a fence to access this buffer, 1676 */ 1677 unsigned int pending_fenced_gpu_access:1; 1678 unsigned int fenced_gpu_access:1; 1679 1680 unsigned int cache_level:3; 1681 1682 unsigned int has_aliasing_ppgtt_mapping:1; 1683 unsigned int has_global_gtt_mapping:1; 1684 unsigned int has_dma_mapping:1; 1685 1686 vm_page_t *pages; 1687 int pages_pin_count; 1688 1689 /* prime dma-buf support */ 1690 void *dma_buf_vmapping; 1691 int vmapping_count; 1692 1693 struct intel_ring_buffer *ring; 1694 1695 /** Breadcrumb of last rendering to the buffer. */ 1696 uint32_t last_read_seqno; 1697 uint32_t last_write_seqno; 1698 /** Breadcrumb of last fenced GPU access to the buffer. */ 1699 uint32_t last_fenced_seqno; 1700 1701 /** Current tiling stride for the object, if it's tiled. */ 1702 uint32_t stride; 1703 1704 /** References from framebuffers, locks out tiling changes. */ 1705 unsigned long framebuffer_references; 1706 1707 /** Record of address bit 17 of each page at last unbind. */ 1708 unsigned long *bit_17; 1709 1710 /** User space pin count and filp owning the pin */ 1711 unsigned long user_pin_count; 1712 struct drm_file *pin_filp; 1713 1714 /** for phy allocated objects */ 1715 struct drm_i915_gem_phys_object *phys_obj; 1716 }; 1717 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) 1718 1719 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1720 1721 /** 1722 * Request queue structure. 1723 * 1724 * The request queue allows us to note sequence numbers that have been emitted 1725 * and may be associated with active buffers to be retired. 1726 * 1727 * By keeping this list, we can avoid having to do questionable 1728 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1729 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1730 */ 1731 struct drm_i915_gem_request { 1732 /** On Which ring this request was generated */ 1733 struct intel_ring_buffer *ring; 1734 1735 /** GEM sequence number associated with this request. */ 1736 uint32_t seqno; 1737 1738 /** Position in the ringbuffer of the start of the request */ 1739 u32 head; 1740 1741 /** Position in the ringbuffer of the end of the request */ 1742 u32 tail; 1743 1744 /** Context related to this request */ 1745 struct i915_hw_context *ctx; 1746 1747 /** Batch buffer related to this request if any */ 1748 struct drm_i915_gem_object *batch_obj; 1749 1750 /** Time at which this request was emitted, in jiffies. */ 1751 unsigned long emitted_jiffies; 1752 1753 /** global list entry for this request */ 1754 struct list_head list; 1755 1756 struct drm_i915_file_private *file_priv; 1757 /** file_priv list entry for this request */ 1758 struct list_head client_list; 1759 }; 1760 1761 struct drm_i915_file_private { 1762 struct drm_i915_private *dev_priv; 1763 1764 struct { 1765 struct spinlock lock; 1766 struct list_head request_list; 1767 struct delayed_work idle_work; 1768 } mm; 1769 struct idr context_idr; 1770 1771 struct i915_ctx_hang_stats hang_stats; 1772 atomic_t rps_wait_boost; 1773 }; 1774 1775 #define INTEL_INFO(dev) (to_i915(dev)->info) 1776 1777 #define IS_I830(dev) ((dev)->pdev->device == 0x3577) 1778 #define IS_845G(dev) ((dev)->pdev->device == 0x2562) 1779 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1780 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) 1781 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1782 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) 1783 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) 1784 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1785 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1786 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1787 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) 1788 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1789 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) 1790 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) 1791 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1792 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1793 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) 1794 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1795 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ 1796 (dev)->pdev->device == 0x0152 || \ 1797 (dev)->pdev->device == 0x015a) 1798 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ 1799 (dev)->pdev->device == 0x0106 || \ 1800 (dev)->pdev->device == 0x010A) 1801 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1802 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1803 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8) 1804 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1805 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 1806 ((dev)->pdev->device & 0xFF00) == 0x0C00) 1807 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 1808 (((dev)->pdev->device & 0xf) == 0x2 || \ 1809 ((dev)->pdev->device & 0xf) == 0x6 || \ 1810 ((dev)->pdev->device & 0xf) == 0xe)) 1811 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 1812 ((dev)->pdev->device & 0xFF00) == 0x0A00) 1813 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) 1814 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 1815 ((dev)->pdev->device & 0x00F0) == 0x0020) 1816 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 1817 1818 /* 1819 * The genX designation typically refers to the render engine, so render 1820 * capability related checks should use IS_GEN, while display and other checks 1821 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1822 * chips, etc.). 1823 */ 1824 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1825 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1826 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1827 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1828 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1829 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1830 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 1831 1832 #define RENDER_RING (1<<RCS) 1833 #define BSD_RING (1<<VCS) 1834 #define BLT_RING (1<<BCS) 1835 #define VEBOX_RING (1<<VECS) 1836 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 1837 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 1838 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 1839 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1840 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) 1841 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1842 1843 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1844 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) 1845 1846 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1847 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1848 1849 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1850 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1851 /* 1852 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 1853 * even when in MSI mode. This results in spurious interrupt warnings if the 1854 * legacy irq no. is shared with another device. The kernel then disables that 1855 * interrupt source and so prevents the other device from working properly. 1856 */ 1857 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 1858 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 1859 1860 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1861 * rows, which changed the alignment requirements and fence programming. 1862 */ 1863 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1864 IS_I915GM(dev))) 1865 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1866 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1867 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1868 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1869 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1870 1871 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1872 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1873 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1874 1875 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) 1876 1877 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 1878 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 1879 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 1880 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */ 1881 #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev)) 1882 1883 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 1884 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1885 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1886 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1887 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1888 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1889 1890 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) 1891 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1892 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1893 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1894 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 1895 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 1896 1897 /* DPF == dynamic parity feature */ 1898 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1899 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 1900 1901 #define GT_FREQUENCY_MULTIPLIER 50 1902 1903 #include "i915_trace.h" 1904 1905 extern struct drm_ioctl_desc i915_ioctls[]; 1906 extern int i915_max_ioctl; 1907 extern unsigned int i915_fbpercrtc __always_unused; 1908 extern int i915_panel_ignore_lid __read_mostly; 1909 extern unsigned int i915_powersave __read_mostly; 1910 extern int i915_semaphores __read_mostly; 1911 extern unsigned int i915_lvds_downclock __read_mostly; 1912 extern int i915_lvds_channel_mode __read_mostly; 1913 extern int i915_panel_use_ssc __read_mostly; 1914 extern int i915_vbt_sdvo_panel_type __read_mostly; 1915 extern int i915_enable_rc6 __read_mostly; 1916 extern int i915_enable_fbc __read_mostly; 1917 extern bool i915_enable_hangcheck __read_mostly; 1918 extern int i915_enable_ppgtt __read_mostly; 1919 extern int i915_enable_psr __read_mostly; 1920 extern unsigned int i915_preliminary_hw_support __read_mostly; 1921 extern int i915_disable_power_well __read_mostly; 1922 extern int i915_enable_ips __read_mostly; 1923 extern bool i915_fastboot __read_mostly; 1924 extern int i915_enable_pc8 __read_mostly; 1925 extern int i915_pc8_timeout __read_mostly; 1926 extern bool i915_prefault_disable __read_mostly; 1927 1928 extern int i915_suspend(device_t kdev); 1929 extern int i915_resume(struct drm_device *dev); 1930 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 1931 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 1932 1933 /* i915_dma.c */ 1934 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1935 extern void i915_kernel_lost_context(struct drm_device * dev); 1936 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1937 extern int i915_driver_unload(struct drm_device *); 1938 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1939 extern void i915_driver_lastclose(struct drm_device * dev); 1940 extern void i915_driver_preclose(struct drm_device *dev, 1941 struct drm_file *file_priv); 1942 extern void i915_driver_postclose(struct drm_device *dev, 1943 struct drm_file *file_priv); 1944 extern int i915_driver_device_is_agp(struct drm_device * dev); 1945 #ifdef CONFIG_COMPAT 1946 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1947 unsigned long arg); 1948 #endif 1949 extern int i915_emit_box(struct drm_device *dev, 1950 struct drm_clip_rect *box, 1951 int DR1, int DR4); 1952 extern int intel_gpu_reset(struct drm_device *dev); 1953 extern int i915_reset(struct drm_device *dev); 1954 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1955 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1956 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1957 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1958 1959 extern void intel_console_resume(struct work_struct *work); 1960 1961 /* i915_irq.c */ 1962 void i915_queue_hangcheck(struct drm_device *dev); 1963 void i915_handle_error(struct drm_device *dev, bool wedged); 1964 1965 extern void intel_irq_init(struct drm_device *dev); 1966 extern void intel_hpd_init(struct drm_device *dev); 1967 1968 extern void intel_uncore_sanitize(struct drm_device *dev); 1969 extern void intel_uncore_early_sanitize(struct drm_device *dev); 1970 extern void intel_uncore_init(struct drm_device *dev); 1971 extern void intel_uncore_check_errors(struct drm_device *dev); 1972 extern void intel_uncore_fini(struct drm_device *dev); 1973 1974 void 1975 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum i915_pipe pipe, u32 mask); 1976 1977 void 1978 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum i915_pipe pipe, u32 mask); 1979 1980 /* i915_gem.c */ 1981 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1982 struct drm_file *file_priv); 1983 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1984 struct drm_file *file_priv); 1985 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1986 struct drm_file *file_priv); 1987 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1988 struct drm_file *file_priv); 1989 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1990 struct drm_file *file_priv); 1991 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1992 struct drm_file *file_priv); 1993 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1994 struct drm_file *file_priv); 1995 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1996 struct drm_file *file_priv); 1997 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1998 struct drm_file *file_priv); 1999 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 2000 struct drm_file *file_priv); 2001 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 2002 struct drm_file *file_priv); 2003 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 2004 struct drm_file *file_priv); 2005 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2006 struct drm_file *file_priv); 2007 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2008 struct drm_file *file); 2009 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2010 struct drm_file *file); 2011 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2012 struct drm_file *file_priv); 2013 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2014 struct drm_file *file_priv); 2015 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 2016 struct drm_file *file_priv); 2017 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 2018 struct drm_file *file_priv); 2019 int i915_gem_set_tiling(struct drm_device *dev, void *data, 2020 struct drm_file *file_priv); 2021 int i915_gem_get_tiling(struct drm_device *dev, void *data, 2022 struct drm_file *file_priv); 2023 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2024 struct drm_file *file_priv); 2025 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2026 struct drm_file *file_priv); 2027 void i915_gem_load(struct drm_device *dev); 2028 void *i915_gem_object_alloc(struct drm_device *dev); 2029 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2030 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2031 const struct drm_i915_gem_object_ops *ops); 2032 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2033 size_t size); 2034 void i915_gem_free_object(struct drm_gem_object *obj); 2035 void i915_gem_vma_destroy(struct i915_vma *vma); 2036 2037 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 2038 struct i915_address_space *vm, 2039 uint32_t alignment, 2040 bool map_and_fenceable, 2041 bool nonblocking); 2042 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 2043 int __must_check i915_vma_unbind(struct i915_vma *vma); 2044 int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); 2045 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2046 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2047 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2048 void i915_gem_lastclose(struct drm_device *dev); 2049 2050 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2051 static inline struct vm_page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2052 { 2053 return obj->pages[n]; 2054 } 2055 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2056 { 2057 BUG_ON(obj->pages == NULL); 2058 obj->pages_pin_count++; 2059 } 2060 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2061 { 2062 BUG_ON(obj->pages_pin_count == 0); 2063 obj->pages_pin_count--; 2064 } 2065 2066 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2067 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2068 struct intel_ring_buffer *to); 2069 void i915_vma_move_to_active(struct i915_vma *vma, 2070 struct intel_ring_buffer *ring); 2071 int i915_gem_dumb_create(struct drm_file *file_priv, 2072 struct drm_device *dev, 2073 struct drm_mode_create_dumb *args); 2074 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2075 uint32_t handle, uint64_t *offset); 2076 /** 2077 * Returns true if seq1 is later than seq2. 2078 */ 2079 static inline bool 2080 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2081 { 2082 return (int32_t)(seq1 - seq2) >= 0; 2083 } 2084 2085 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2086 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2087 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 2088 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 2089 2090 static inline bool 2091 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 2092 { 2093 if (obj->fence_reg != I915_FENCE_REG_NONE) { 2094 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2095 dev_priv->fence_regs[obj->fence_reg].pin_count++; 2096 return true; 2097 } else 2098 return false; 2099 } 2100 2101 static inline void 2102 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 2103 { 2104 if (obj->fence_reg != I915_FENCE_REG_NONE) { 2105 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2106 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); 2107 dev_priv->fence_regs[obj->fence_reg].pin_count--; 2108 } 2109 } 2110 2111 bool i915_gem_retire_requests(struct drm_device *dev); 2112 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 2113 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2114 bool interruptible); 2115 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2116 { 2117 return unlikely(atomic_read(&error->reset_counter) 2118 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2119 } 2120 2121 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2122 { 2123 return atomic_read(&error->reset_counter) & I915_WEDGED; 2124 } 2125 2126 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2127 { 2128 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2129 } 2130 2131 void i915_gem_reset(struct drm_device *dev); 2132 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 2133 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 2134 int __must_check i915_gem_init(struct drm_device *dev); 2135 int __must_check i915_gem_init_hw(struct drm_device *dev); 2136 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice); 2137 void i915_gem_init_swizzling(struct drm_device *dev); 2138 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 2139 int __must_check i915_gpu_idle(struct drm_device *dev); 2140 int __must_check i915_gem_suspend(struct drm_device *dev); 2141 int __i915_add_request(struct intel_ring_buffer *ring, 2142 struct drm_file *file, 2143 struct drm_i915_gem_object *batch_obj, 2144 u32 *seqno); 2145 #define i915_add_request(ring, seqno) \ 2146 __i915_add_request(ring, NULL, NULL, seqno) 2147 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, 2148 uint32_t seqno); 2149 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres); 2150 int __must_check 2151 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 2152 bool write); 2153 int __must_check 2154 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 2155 int __must_check 2156 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 2157 u32 alignment, 2158 struct intel_ring_buffer *pipelined); 2159 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 2160 int i915_gem_attach_phys_object(struct drm_device *dev, 2161 struct drm_i915_gem_object *obj, 2162 int id, 2163 int align); 2164 void i915_gem_detach_phys_object(struct drm_device *dev, 2165 struct drm_i915_gem_object *obj); 2166 void i915_gem_free_all_phys_object(struct drm_device *dev); 2167 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 2168 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2169 2170 uint32_t 2171 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 2172 uint32_t 2173 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2174 int tiling_mode, bool fenced); 2175 2176 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2177 enum i915_cache_level cache_level); 2178 2179 #if 0 2180 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2181 struct dma_buf *dma_buf); 2182 2183 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 2184 struct drm_gem_object *gem_obj, int flags); 2185 #endif 2186 2187 void i915_gem_restore_fences(struct drm_device *dev); 2188 2189 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, 2190 struct i915_address_space *vm); 2191 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 2192 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 2193 struct i915_address_space *vm); 2194 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 2195 struct i915_address_space *vm); 2196 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 2197 struct i915_address_space *vm); 2198 struct i915_vma * 2199 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2200 struct i915_address_space *vm); 2201 2202 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); 2203 2204 /* Some GGTT VM helpers */ 2205 #define obj_to_ggtt(obj) \ 2206 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 2207 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2208 { 2209 struct i915_address_space *ggtt = 2210 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2211 return vm == ggtt; 2212 } 2213 2214 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2215 { 2216 return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); 2217 } 2218 2219 static inline unsigned long 2220 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) 2221 { 2222 return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); 2223 } 2224 2225 static inline unsigned long 2226 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2227 { 2228 return i915_gem_obj_size(obj, obj_to_ggtt(obj)); 2229 } 2230 2231 static inline int __must_check 2232 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2233 uint32_t alignment, 2234 bool map_and_fenceable, 2235 bool nonblocking) 2236 { 2237 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, 2238 map_and_fenceable, nonblocking); 2239 } 2240 2241 /* i915_gem_context.c */ 2242 int __must_check i915_gem_context_init(struct drm_device *dev); 2243 void i915_gem_context_fini(struct drm_device *dev); 2244 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2245 int i915_switch_context(struct intel_ring_buffer *ring, 2246 struct drm_file *file, int to_id); 2247 void i915_gem_context_free(struct kref *ctx_ref); 2248 static inline void i915_gem_context_reference(struct i915_hw_context *ctx) 2249 { 2250 kref_get(&ctx->ref); 2251 } 2252 2253 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) 2254 { 2255 kref_put(&ctx->ref, i915_gem_context_free); 2256 } 2257 2258 struct i915_ctx_hang_stats * __must_check 2259 i915_gem_context_get_hang_stats(struct drm_device *dev, 2260 struct drm_file *file, 2261 u32 id); 2262 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2263 struct drm_file *file); 2264 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2265 struct drm_file *file); 2266 2267 /* i915_gem_gtt.c */ 2268 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 2269 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 2270 struct drm_i915_gem_object *obj, 2271 enum i915_cache_level cache_level); 2272 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 2273 struct drm_i915_gem_object *obj); 2274 2275 void i915_check_and_clear_faults(struct drm_device *dev); 2276 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 2277 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 2278 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 2279 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 2280 enum i915_cache_level cache_level); 2281 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 2282 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 2283 void i915_gem_init_global_gtt(struct drm_device *dev); 2284 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, 2285 unsigned long mappable_end, unsigned long end); 2286 int i915_gem_gtt_init(struct drm_device *dev); 2287 static inline void i915_gem_chipset_flush(struct drm_device *dev) 2288 { 2289 if (INTEL_INFO(dev)->gen < 6) 2290 intel_gtt_chipset_flush(); 2291 } 2292 2293 2294 /* i915_gem_evict.c */ 2295 int __must_check i915_gem_evict_something(struct drm_device *dev, 2296 struct i915_address_space *vm, 2297 int min_size, 2298 unsigned alignment, 2299 unsigned cache_level, 2300 bool mappable, 2301 bool nonblock); 2302 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 2303 int i915_gem_evict_everything(struct drm_device *dev); 2304 2305 /* i915_gem_stolen.c */ 2306 int i915_gem_init_stolen(struct drm_device *dev); 2307 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); 2308 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 2309 void i915_gem_cleanup_stolen(struct drm_device *dev); 2310 struct drm_i915_gem_object * 2311 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 2312 struct drm_i915_gem_object * 2313 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 2314 u32 stolen_offset, 2315 u32 gtt_offset, 2316 u32 size); 2317 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); 2318 2319 /* i915_gem_tiling.c */ 2320 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2321 { 2322 drm_i915_private_t *dev_priv = obj->base.dev->dev_private; 2323 2324 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2325 obj->tiling_mode != I915_TILING_NONE; 2326 } 2327 2328 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 2329 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 2330 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 2331 2332 /* i915_gem_debug.c */ 2333 #if WATCH_LISTS 2334 int i915_verify_lists(struct drm_device *dev); 2335 #else 2336 #define i915_verify_lists(dev) 0 2337 #endif 2338 2339 /* i915_debugfs.c */ 2340 int i915_debugfs_init(struct drm_minor *minor); 2341 void i915_debugfs_cleanup(struct drm_minor *minor); 2342 #ifdef CONFIG_DEBUG_FS 2343 void intel_display_crc_init(struct drm_device *dev); 2344 #else 2345 static inline void intel_display_crc_init(struct drm_device *dev) {} 2346 #endif 2347 2348 /* i915_gpu_error.c */ 2349 __printf(2, 3) 2350 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 2351 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 2352 const struct i915_error_state_file_priv *error); 2353 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 2354 size_t count, loff_t pos); 2355 static inline void i915_error_state_buf_release( 2356 struct drm_i915_error_state_buf *eb) 2357 { 2358 kfree(eb->buf); 2359 } 2360 void i915_capture_error_state(struct drm_device *dev); 2361 void i915_error_state_get(struct drm_device *dev, 2362 struct i915_error_state_file_priv *error_priv); 2363 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 2364 void i915_destroy_error_state(struct drm_device *dev); 2365 2366 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 2367 const char *i915_cache_level_str(int type); 2368 2369 /* i915_suspend.c */ 2370 extern int i915_save_state(struct drm_device *dev); 2371 extern int i915_restore_state(struct drm_device *dev); 2372 2373 /* i915_ums.c */ 2374 void i915_save_display_reg(struct drm_device *dev); 2375 void i915_restore_display_reg(struct drm_device *dev); 2376 2377 /* i915_sysfs.c */ 2378 void i915_setup_sysfs(struct drm_device *dev_priv); 2379 void i915_teardown_sysfs(struct drm_device *dev_priv); 2380 2381 /* intel_i2c.c */ 2382 extern int intel_setup_gmbus(struct drm_device *dev); 2383 extern void intel_teardown_gmbus(struct drm_device *dev); 2384 static inline bool intel_gmbus_is_port_valid(unsigned port) 2385 { 2386 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 2387 } 2388 2389 extern struct device *intel_gmbus_get_adapter( 2390 struct drm_i915_private *dev_priv, unsigned port); 2391 extern void intel_gmbus_set_speed(struct device *adapter, int speed); 2392 extern void intel_gmbus_force_bit(struct device *adapter, bool force_bit); 2393 static inline bool intel_gmbus_is_forced_bit(struct device *adapter) 2394 { 2395 struct intel_iic_softc *sc; 2396 sc = device_get_softc(device_get_parent(adapter)); 2397 2398 return sc->force_bit_dev; 2399 } 2400 extern void intel_i2c_reset(struct drm_device *dev); 2401 2402 /* intel_opregion.c */ 2403 struct intel_encoder; 2404 #ifdef CONFIG_ACPI 2405 extern int intel_opregion_setup(struct drm_device *dev); 2406 extern void intel_opregion_init(struct drm_device *dev); 2407 extern void intel_opregion_fini(struct drm_device *dev); 2408 extern void intel_opregion_asle_intr(struct drm_device *dev); 2409 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 2410 bool enable); 2411 extern int intel_opregion_notify_adapter(struct drm_device *dev, 2412 pci_power_t state); 2413 #else 2414 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } 2415 static inline void intel_opregion_init(struct drm_device *dev) { return; } 2416 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 2417 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 2418 static inline int 2419 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 2420 { 2421 return 0; 2422 } 2423 static inline int 2424 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 2425 { 2426 return 0; 2427 } 2428 #endif 2429 2430 /* intel_acpi.c */ 2431 #ifdef CONFIG_ACPI 2432 extern void intel_register_dsm_handler(void); 2433 extern void intel_unregister_dsm_handler(void); 2434 #else 2435 static inline void intel_register_dsm_handler(void) { return; } 2436 static inline void intel_unregister_dsm_handler(void) { return; } 2437 #endif /* CONFIG_ACPI */ 2438 2439 /* modesetting */ 2440 extern void intel_modeset_init_hw(struct drm_device *dev); 2441 extern void intel_modeset_suspend_hw(struct drm_device *dev); 2442 extern void intel_modeset_init(struct drm_device *dev); 2443 extern void intel_modeset_gem_init(struct drm_device *dev); 2444 extern void intel_modeset_cleanup(struct drm_device *dev); 2445 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 2446 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 2447 bool force_restore); 2448 extern void i915_redisable_vga(struct drm_device *dev); 2449 extern void intel_disable_fbc(struct drm_device *dev); 2450 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2451 extern void intel_init_pch_refclk(struct drm_device *dev); 2452 extern void gen6_set_rps(struct drm_device *dev, u8 val); 2453 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2454 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); 2455 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); 2456 extern void intel_detect_pch(struct drm_device *dev); 2457 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 2458 extern int intel_enable_rc6(const struct drm_device *dev); 2459 2460 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 2461 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2462 struct drm_file *file); 2463 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 2464 struct drm_file *file); 2465 2466 const struct intel_device_info *i915_get_device_id(int device); 2467 2468 /* overlay */ 2469 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2470 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 2471 struct intel_overlay_error_state *error); 2472 2473 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 2474 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2475 struct drm_device *dev, 2476 struct intel_display_error_state *error); 2477 2478 /* On SNB platform, before reading ring registers forcewake bit 2479 * must be set to prevent GT core from power down and stale values being 2480 * returned. 2481 */ 2482 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); 2483 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); 2484 2485 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 2486 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 2487 2488 /* intel_sideband.c */ 2489 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 2490 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 2491 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 2492 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 2493 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2494 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 2495 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2496 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 2497 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2498 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 2499 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2500 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 2501 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2502 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg); 2503 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val); 2504 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 2505 enum intel_sbi_destination destination); 2506 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2507 enum intel_sbi_destination destination); 2508 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 2509 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2510 2511 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); 2512 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); 2513 2514 void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); 2515 void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); 2516 2517 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ 2518 (((reg) >= 0x2000 && (reg) < 0x4000) ||\ 2519 ((reg) >= 0x5000 && (reg) < 0x8000) ||\ 2520 ((reg) >= 0xB000 && (reg) < 0x12000) ||\ 2521 ((reg) >= 0x2E000 && (reg) < 0x30000)) 2522 2523 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\ 2524 (((reg) >= 0x12000 && (reg) < 0x14000) ||\ 2525 ((reg) >= 0x22000 && (reg) < 0x24000) ||\ 2526 ((reg) >= 0x30000 && (reg) < 0x40000)) 2527 2528 #define FORCEWAKE_RENDER (1 << 0) 2529 #define FORCEWAKE_MEDIA (1 << 1) 2530 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) 2531 2532 2533 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 2534 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 2535 2536 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 2537 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 2538 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 2539 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 2540 2541 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 2542 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 2543 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 2544 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 2545 2546 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 2547 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 2548 2549 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 2550 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 2551 2552 /* "Broadcast RGB" property */ 2553 #define INTEL_BROADCAST_RGB_AUTO 0 2554 #define INTEL_BROADCAST_RGB_FULL 1 2555 #define INTEL_BROADCAST_RGB_LIMITED 2 2556 2557 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 2558 { 2559 if (HAS_PCH_SPLIT(dev)) 2560 return CPU_VGACNTRL; 2561 else if (IS_VALLEYVIEW(dev)) 2562 return VLV_VGACNTRL; 2563 else 2564 return VGACNTRL; 2565 } 2566 2567 static inline void __user *to_user_ptr(u64 address) 2568 { 2569 return (void __user *)(uintptr_t)address; 2570 } 2571 2572 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 2573 { 2574 unsigned long j = msecs_to_jiffies(m); 2575 2576 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2577 } 2578 2579 static inline unsigned long 2580 timespec_to_jiffies_timeout(const struct timespec *value) 2581 { 2582 unsigned long j = timespec_to_jiffies(value); 2583 2584 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2585 } 2586 2587 #endif 2588