1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi_drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include "intel_lrc.h" 39 #include "i915_gem_gtt.h" 40 #include "i915_gem_render_state.h" 41 #include <linux/io-mapping.h> 42 #include <linux/i2c.h> 43 #include <drm/intel-gtt.h> 44 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 45 #include <drm/drm_gem.h> 46 #include <linux/backlight.h> 47 #include <linux/hashtable.h> 48 #include <linux/kref.h> 49 #include <linux/kconfig.h> 50 #include <linux/pm_qos.h> 51 #include <linux/seq_file.h> 52 #include <linux/delay.h> 53 54 #define CONFIG_DRM_I915_FBDEV 1 55 #define CONFIG_DRM_I915_KMS 1 56 #define CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT 1 57 #define CONFIG_ACPI 1 58 #define CONFIG_X86 1 59 60 /* General customization: 61 */ 62 63 #define DRIVER_NAME "i915" 64 #define DRIVER_DESC "Intel Graphics" 65 #define DRIVER_DATE "20140905" 66 67 enum i915_pipe { 68 INVALID_PIPE = -1, 69 PIPE_A = 0, 70 PIPE_B, 71 PIPE_C, 72 _PIPE_EDP, 73 I915_MAX_PIPES = _PIPE_EDP 74 }; 75 #define pipe_name(p) ((p) + 'A') 76 77 enum transcoder { 78 TRANSCODER_A = 0, 79 TRANSCODER_B, 80 TRANSCODER_C, 81 TRANSCODER_EDP, 82 I915_MAX_TRANSCODERS 83 }; 84 #define transcoder_name(t) ((t) + 'A') 85 86 enum plane { 87 PLANE_A = 0, 88 PLANE_B, 89 PLANE_C, 90 }; 91 #define plane_name(p) ((p) + 'A') 92 93 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') 94 95 enum port { 96 PORT_A = 0, 97 PORT_B, 98 PORT_C, 99 PORT_D, 100 PORT_E, 101 I915_MAX_PORTS 102 }; 103 #define port_name(p) ((p) + 'A') 104 105 #define I915_NUM_PHYS_VLV 2 106 107 enum dpio_channel { 108 DPIO_CH0, 109 DPIO_CH1 110 }; 111 112 enum dpio_phy { 113 DPIO_PHY0, 114 DPIO_PHY1 115 }; 116 117 enum intel_display_power_domain { 118 POWER_DOMAIN_PIPE_A, 119 POWER_DOMAIN_PIPE_B, 120 POWER_DOMAIN_PIPE_C, 121 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 122 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 123 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 124 POWER_DOMAIN_TRANSCODER_A, 125 POWER_DOMAIN_TRANSCODER_B, 126 POWER_DOMAIN_TRANSCODER_C, 127 POWER_DOMAIN_TRANSCODER_EDP, 128 POWER_DOMAIN_PORT_DDI_A_2_LANES, 129 POWER_DOMAIN_PORT_DDI_A_4_LANES, 130 POWER_DOMAIN_PORT_DDI_B_2_LANES, 131 POWER_DOMAIN_PORT_DDI_B_4_LANES, 132 POWER_DOMAIN_PORT_DDI_C_2_LANES, 133 POWER_DOMAIN_PORT_DDI_C_4_LANES, 134 POWER_DOMAIN_PORT_DDI_D_2_LANES, 135 POWER_DOMAIN_PORT_DDI_D_4_LANES, 136 POWER_DOMAIN_PORT_DSI, 137 POWER_DOMAIN_PORT_CRT, 138 POWER_DOMAIN_PORT_OTHER, 139 POWER_DOMAIN_VGA, 140 POWER_DOMAIN_AUDIO, 141 POWER_DOMAIN_PLLS, 142 POWER_DOMAIN_INIT, 143 144 POWER_DOMAIN_NUM, 145 }; 146 147 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 148 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 149 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 150 #define POWER_DOMAIN_TRANSCODER(tran) \ 151 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 152 (tran) + POWER_DOMAIN_TRANSCODER_A) 153 154 enum hpd_pin { 155 HPD_NONE = 0, 156 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 157 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 158 HPD_CRT, 159 HPD_SDVO_B, 160 HPD_SDVO_C, 161 HPD_PORT_B, 162 HPD_PORT_C, 163 HPD_PORT_D, 164 HPD_NUM_PINS 165 }; 166 167 #define I915_GEM_GPU_DOMAINS \ 168 (I915_GEM_DOMAIN_RENDER | \ 169 I915_GEM_DOMAIN_SAMPLER | \ 170 I915_GEM_DOMAIN_COMMAND | \ 171 I915_GEM_DOMAIN_INSTRUCTION | \ 172 I915_GEM_DOMAIN_VERTEX) 173 174 #define for_each_pipe(__dev_priv, __p) \ 175 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 176 #define for_each_plane(pipe, p) \ 177 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++) 178 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) 179 180 #define for_each_crtc(dev, crtc) \ 181 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 182 183 #define for_each_intel_crtc(dev, intel_crtc) \ 184 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) 185 186 #define for_each_intel_encoder(dev, intel_encoder) \ 187 list_for_each_entry(intel_encoder, \ 188 &(dev)->mode_config.encoder_list, \ 189 base.head) 190 191 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 192 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 193 if ((intel_encoder)->base.crtc == (__crtc)) 194 195 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 196 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 197 if ((intel_connector)->base.encoder == (__encoder)) 198 199 #define for_each_power_domain(domain, mask) \ 200 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 201 if ((1 << (domain)) & (mask)) 202 203 struct drm_i915_private; 204 struct i915_mmu_object; 205 206 enum intel_dpll_id { 207 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 208 /* real shared dpll ids must be >= 0 */ 209 DPLL_ID_PCH_PLL_A = 0, 210 DPLL_ID_PCH_PLL_B = 1, 211 DPLL_ID_WRPLL1 = 0, 212 DPLL_ID_WRPLL2 = 1, 213 }; 214 #define I915_NUM_PLLS 2 215 216 struct intel_dpll_hw_state { 217 /* i9xx, pch plls */ 218 uint32_t dpll; 219 uint32_t dpll_md; 220 uint32_t fp0; 221 uint32_t fp1; 222 223 /* hsw, bdw */ 224 uint32_t wrpll; 225 }; 226 227 struct intel_shared_dpll { 228 int refcount; /* count of number of CRTCs sharing this PLL */ 229 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 230 bool on; /* is the PLL actually active? Disabled during modeset */ 231 const char *name; 232 /* should match the index in the dev_priv->shared_dplls array */ 233 enum intel_dpll_id id; 234 struct intel_dpll_hw_state hw_state; 235 /* The mode_set hook is optional and should be used together with the 236 * intel_prepare_shared_dpll function. */ 237 void (*mode_set)(struct drm_i915_private *dev_priv, 238 struct intel_shared_dpll *pll); 239 void (*enable)(struct drm_i915_private *dev_priv, 240 struct intel_shared_dpll *pll); 241 void (*disable)(struct drm_i915_private *dev_priv, 242 struct intel_shared_dpll *pll); 243 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 244 struct intel_shared_dpll *pll, 245 struct intel_dpll_hw_state *hw_state); 246 }; 247 248 /* Used by dp and fdi links */ 249 struct intel_link_m_n { 250 uint32_t tu; 251 uint32_t gmch_m; 252 uint32_t gmch_n; 253 uint32_t link_m; 254 uint32_t link_n; 255 }; 256 257 void intel_link_compute_m_n(int bpp, int nlanes, 258 int pixel_clock, int link_clock, 259 struct intel_link_m_n *m_n); 260 261 /* Interface history: 262 * 263 * 1.1: Original. 264 * 1.2: Add Power Management 265 * 1.3: Add vblank support 266 * 1.4: Fix cmdbuffer path, add heap destroy 267 * 1.5: Add vblank pipe configuration 268 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 269 * - Support vertical blank on secondary display pipe 270 */ 271 #define DRIVER_MAJOR 1 272 #define DRIVER_MINOR 6 273 #define DRIVER_PATCHLEVEL 0 274 275 #define WATCH_LISTS 0 276 #define WATCH_GTT 0 277 278 struct opregion_header; 279 struct opregion_acpi; 280 struct opregion_swsci; 281 struct opregion_asle; 282 283 struct intel_opregion { 284 struct opregion_header __iomem *header; 285 struct opregion_acpi __iomem *acpi; 286 struct opregion_swsci __iomem *swsci; 287 u32 swsci_gbda_sub_functions; 288 u32 swsci_sbcb_sub_functions; 289 struct opregion_asle __iomem *asle; 290 void __iomem *vbt; 291 u32 __iomem *lid_state; 292 struct work_struct asle_work; 293 }; 294 #define OPREGION_SIZE (8*1024) 295 296 struct intel_overlay; 297 struct intel_overlay_error_state; 298 299 struct drm_i915_master_private { 300 struct drm_local_map *sarea; 301 struct _drm_i915_sarea *sarea_priv; 302 }; 303 #define I915_FENCE_REG_NONE -1 304 #define I915_MAX_NUM_FENCES 32 305 /* 32 fences + sign bit for FENCE_REG_NONE */ 306 #define I915_MAX_NUM_FENCE_BITS 6 307 308 struct drm_i915_fence_reg { 309 struct list_head lru_list; 310 struct drm_i915_gem_object *obj; 311 int pin_count; 312 }; 313 314 struct sdvo_device_mapping { 315 u8 initialized; 316 u8 dvo_port; 317 u8 slave_addr; 318 u8 dvo_wiring; 319 u8 i2c_pin; 320 u8 ddc_pin; 321 }; 322 323 struct intel_display_error_state; 324 325 struct drm_i915_error_state { 326 struct kref ref; 327 struct timeval time; 328 329 char error_msg[128]; 330 u32 reset_count; 331 u32 suspend_count; 332 333 /* Generic register state */ 334 u32 eir; 335 u32 pgtbl_er; 336 u32 ier; 337 u32 gtier[4]; 338 u32 ccid; 339 u32 derrmr; 340 u32 forcewake; 341 u32 error; /* gen6+ */ 342 u32 err_int; /* gen7 */ 343 u32 done_reg; 344 u32 gac_eco; 345 u32 gam_ecochk; 346 u32 gab_ctl; 347 u32 gfx_mode; 348 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 349 u64 fence[I915_MAX_NUM_FENCES]; 350 struct intel_overlay_error_state *overlay; 351 struct intel_display_error_state *display; 352 struct drm_i915_error_object *semaphore_obj; 353 354 struct drm_i915_error_ring { 355 bool valid; 356 /* Software tracked state */ 357 bool waiting; 358 int hangcheck_score; 359 enum intel_ring_hangcheck_action hangcheck_action; 360 int num_requests; 361 362 /* our own tracking of ring head and tail */ 363 u32 cpu_ring_head; 364 u32 cpu_ring_tail; 365 366 u32 semaphore_seqno[I915_NUM_RINGS - 1]; 367 368 /* Register state */ 369 u32 tail; 370 u32 head; 371 u32 ctl; 372 u32 hws; 373 u32 ipeir; 374 u32 ipehr; 375 u32 instdone; 376 u32 bbstate; 377 u32 instpm; 378 u32 instps; 379 u32 seqno; 380 u64 bbaddr; 381 u64 acthd; 382 u32 fault_reg; 383 u64 faddr; 384 u32 rc_psmi; /* sleep state */ 385 u32 semaphore_mboxes[I915_NUM_RINGS - 1]; 386 387 struct drm_i915_error_object { 388 int page_count; 389 u32 gtt_offset; 390 u32 *pages[0]; 391 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 392 393 struct drm_i915_error_request { 394 long jiffies; 395 u32 seqno; 396 u32 tail; 397 } *requests; 398 399 struct { 400 u32 gfx_mode; 401 union { 402 u64 pdp[4]; 403 u32 pp_dir_base; 404 }; 405 } vm_info; 406 407 pid_t pid; 408 char comm[TASK_COMM_LEN]; 409 } ring[I915_NUM_RINGS]; 410 411 struct drm_i915_error_buffer { 412 u32 size; 413 u32 name; 414 u32 rseqno, wseqno; 415 u32 gtt_offset; 416 u32 read_domains; 417 u32 write_domain; 418 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 419 s32 pinned:2; 420 u32 tiling:2; 421 u32 dirty:1; 422 u32 purgeable:1; 423 u32 userptr:1; 424 s32 ring:4; 425 u32 cache_level:3; 426 } **active_bo, **pinned_bo; 427 428 u32 *active_bo_count, *pinned_bo_count; 429 u32 vm_count; 430 }; 431 432 struct intel_connector; 433 struct intel_crtc_config; 434 struct intel_plane_config; 435 struct intel_crtc; 436 struct intel_limit; 437 struct dpll; 438 439 struct drm_i915_display_funcs { 440 bool (*fbc_enabled)(struct drm_device *dev); 441 void (*enable_fbc)(struct drm_crtc *crtc); 442 void (*disable_fbc)(struct drm_device *dev); 443 int (*get_display_clock_speed)(struct drm_device *dev); 444 int (*get_fifo_size)(struct drm_device *dev, int plane); 445 /** 446 * find_dpll() - Find the best values for the PLL 447 * @limit: limits for the PLL 448 * @crtc: current CRTC 449 * @target: target frequency in kHz 450 * @refclk: reference clock frequency in kHz 451 * @match_clock: if provided, @best_clock P divider must 452 * match the P divider from @match_clock 453 * used for LVDS downclocking 454 * @best_clock: best PLL values found 455 * 456 * Returns true on success, false on failure. 457 */ 458 bool (*find_dpll)(const struct intel_limit *limit, 459 struct drm_crtc *crtc, 460 int target, int refclk, 461 struct dpll *match_clock, 462 struct dpll *best_clock); 463 void (*update_wm)(struct drm_crtc *crtc); 464 void (*update_sprite_wm)(struct drm_plane *plane, 465 struct drm_crtc *crtc, 466 uint32_t sprite_width, uint32_t sprite_height, 467 int pixel_size, bool enable, bool scaled); 468 void (*modeset_global_resources)(struct drm_device *dev); 469 /* Returns the active state of the crtc, and if the crtc is active, 470 * fills out the pipe-config with the hw state. */ 471 bool (*get_pipe_config)(struct intel_crtc *, 472 struct intel_crtc_config *); 473 void (*get_plane_config)(struct intel_crtc *, 474 struct intel_plane_config *); 475 int (*crtc_mode_set)(struct drm_crtc *crtc, 476 int x, int y, 477 struct drm_framebuffer *old_fb); 478 void (*crtc_enable)(struct drm_crtc *crtc); 479 void (*crtc_disable)(struct drm_crtc *crtc); 480 void (*off)(struct drm_crtc *crtc); 481 void (*write_eld)(struct drm_connector *connector, 482 struct drm_crtc *crtc, 483 struct drm_display_mode *mode); 484 void (*fdi_link_train)(struct drm_crtc *crtc); 485 void (*init_clock_gating)(struct drm_device *dev); 486 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 487 struct drm_framebuffer *fb, 488 struct drm_i915_gem_object *obj, 489 struct intel_engine_cs *ring, 490 uint32_t flags); 491 void (*update_primary_plane)(struct drm_crtc *crtc, 492 struct drm_framebuffer *fb, 493 int x, int y); 494 void (*hpd_irq_setup)(struct drm_device *dev); 495 /* clock updates for mode set */ 496 /* cursor updates */ 497 /* render clock increase/decrease */ 498 /* display clock increase/decrease */ 499 /* pll clock increase/decrease */ 500 501 int (*setup_backlight)(struct intel_connector *connector); 502 uint32_t (*get_backlight)(struct intel_connector *connector); 503 void (*set_backlight)(struct intel_connector *connector, 504 uint32_t level); 505 void (*disable_backlight)(struct intel_connector *connector); 506 void (*enable_backlight)(struct intel_connector *connector); 507 }; 508 509 struct intel_uncore_funcs { 510 void (*force_wake_get)(struct drm_i915_private *dev_priv, 511 int fw_engine); 512 void (*force_wake_put)(struct drm_i915_private *dev_priv, 513 int fw_engine); 514 515 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 516 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 517 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 518 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 519 520 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 521 uint8_t val, bool trace); 522 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 523 uint16_t val, bool trace); 524 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 525 uint32_t val, bool trace); 526 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 527 uint64_t val, bool trace); 528 }; 529 530 struct intel_uncore { 531 struct lock lock; /** lock is also taken in irq contexts. */ 532 533 struct intel_uncore_funcs funcs; 534 535 unsigned fifo_count; 536 unsigned forcewake_count; 537 538 unsigned fw_rendercount; 539 unsigned fw_mediacount; 540 541 struct timer_list force_wake_timer; 542 }; 543 544 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 545 func(is_mobile) sep \ 546 func(is_i85x) sep \ 547 func(is_i915g) sep \ 548 func(is_i945gm) sep \ 549 func(is_g33) sep \ 550 func(need_gfx_hws) sep \ 551 func(is_g4x) sep \ 552 func(is_pineview) sep \ 553 func(is_broadwater) sep \ 554 func(is_crestline) sep \ 555 func(is_ivybridge) sep \ 556 func(is_valleyview) sep \ 557 func(is_haswell) sep \ 558 func(is_preliminary) sep \ 559 func(has_fbc) sep \ 560 func(has_pipe_cxsr) sep \ 561 func(has_hotplug) sep \ 562 func(cursor_needs_physical) sep \ 563 func(has_overlay) sep \ 564 func(overlay_needs_physical) sep \ 565 func(supports_tv) sep \ 566 func(has_llc) sep \ 567 func(has_ddi) sep \ 568 func(has_fpga_dbg) 569 570 #define DEFINE_FLAG(name) u8 name:1 571 #define SEP_SEMICOLON ; 572 573 struct intel_device_info { 574 u32 display_mmio_offset; 575 u16 device_id; 576 u8 num_pipes:3; 577 u8 num_sprites[I915_MAX_PIPES]; 578 u8 gen; 579 u8 ring_mask; /* Rings supported by the HW */ 580 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 581 /* Register offsets for the various display pipes and transcoders */ 582 int pipe_offsets[I915_MAX_TRANSCODERS]; 583 int trans_offsets[I915_MAX_TRANSCODERS]; 584 int palette_offsets[I915_MAX_PIPES]; 585 int cursor_offsets[I915_MAX_PIPES]; 586 }; 587 588 #undef DEFINE_FLAG 589 #undef SEP_SEMICOLON 590 591 enum i915_cache_level { 592 I915_CACHE_NONE = 0, 593 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 594 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 595 caches, eg sampler/render caches, and the 596 large Last-Level-Cache. LLC is coherent with 597 the CPU, but L3 is only visible to the GPU. */ 598 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 599 }; 600 601 struct i915_ctx_hang_stats { 602 /* This context had batch pending when hang was declared */ 603 unsigned batch_pending; 604 605 /* This context had batch active when hang was declared */ 606 unsigned batch_active; 607 608 /* Time when this context was last blamed for a GPU reset */ 609 unsigned long guilty_ts; 610 611 /* This context is banned to submit more work */ 612 bool banned; 613 }; 614 615 /* This must match up with the value previously used for execbuf2.rsvd1. */ 616 #define DEFAULT_CONTEXT_HANDLE 0 617 /** 618 * struct intel_context - as the name implies, represents a context. 619 * @ref: reference count. 620 * @user_handle: userspace tracking identity for this context. 621 * @remap_slice: l3 row remapping information. 622 * @file_priv: filp associated with this context (NULL for global default 623 * context). 624 * @hang_stats: information about the role of this context in possible GPU 625 * hangs. 626 * @vm: virtual memory space used by this context. 627 * @legacy_hw_ctx: render context backing object and whether it is correctly 628 * initialized (legacy ring submission mechanism only). 629 * @link: link in the global list of contexts. 630 * 631 * Contexts are memory images used by the hardware to store copies of their 632 * internal state. 633 */ 634 struct intel_context { 635 struct kref ref; 636 int user_handle; 637 uint8_t remap_slice; 638 struct drm_i915_file_private *file_priv; 639 struct i915_ctx_hang_stats hang_stats; 640 struct i915_hw_ppgtt *ppgtt; 641 642 /* Legacy ring buffer submission */ 643 struct { 644 struct drm_i915_gem_object *rcs_state; 645 bool initialized; 646 } legacy_hw_ctx; 647 648 /* Execlists */ 649 bool rcs_initialized; 650 struct { 651 struct drm_i915_gem_object *state; 652 struct intel_ringbuffer *ringbuf; 653 } engine[I915_NUM_RINGS]; 654 655 struct list_head link; 656 }; 657 658 struct i915_fbc { 659 unsigned long size; 660 unsigned threshold; 661 unsigned int fb_id; 662 enum plane plane; 663 int y; 664 665 struct drm_mm_node compressed_fb; 666 struct drm_mm_node *compressed_llb; 667 668 bool false_color; 669 670 struct intel_fbc_work { 671 struct delayed_work work; 672 struct drm_crtc *crtc; 673 struct drm_framebuffer *fb; 674 } *fbc_work; 675 676 enum no_fbc_reason { 677 FBC_OK, /* FBC is enabled */ 678 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 679 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 680 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 681 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 682 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 683 FBC_BAD_PLANE, /* fbc not supported on plane */ 684 FBC_NOT_TILED, /* buffer not tiled */ 685 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 686 FBC_MODULE_PARAM, 687 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 688 } no_fbc_reason; 689 }; 690 691 struct i915_drrs { 692 struct intel_connector *connector; 693 }; 694 695 struct intel_dp; 696 struct i915_psr { 697 struct lock lock; 698 bool sink_support; 699 bool source_ok; 700 struct intel_dp *enabled; 701 bool active; 702 struct delayed_work work; 703 unsigned busy_frontbuffer_bits; 704 }; 705 706 enum intel_pch { 707 PCH_NONE = 0, /* No PCH present */ 708 PCH_IBX, /* Ibexpeak PCH */ 709 PCH_CPT, /* Cougarpoint PCH */ 710 PCH_LPT, /* Lynxpoint PCH */ 711 PCH_NOP, 712 }; 713 714 enum intel_sbi_destination { 715 SBI_ICLK, 716 SBI_MPHY, 717 }; 718 719 #define QUIRK_PIPEA_FORCE (1<<0) 720 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 721 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 722 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 723 #define QUIRK_PIPEB_FORCE (1<<4) 724 725 struct intel_fbdev; 726 struct intel_fbc_work; 727 728 struct intel_gmbus { 729 u32 force_bit; 730 u32 reg0; 731 u32 gpio_reg; 732 struct drm_i915_private *dev_priv; 733 }; 734 735 struct intel_iic_softc { 736 struct drm_device *drm_dev; 737 device_t iic_dev; 738 bool force_bit_dev; 739 char name[32]; 740 uint32_t reg; 741 uint32_t reg0; 742 }; 743 744 struct i915_suspend_saved_registers { 745 u8 saveLBB; 746 u32 saveDSPACNTR; 747 u32 saveDSPBCNTR; 748 u32 saveDSPARB; 749 u32 savePIPEACONF; 750 u32 savePIPEBCONF; 751 u32 savePIPEASRC; 752 u32 savePIPEBSRC; 753 u32 saveFPA0; 754 u32 saveFPA1; 755 u32 saveDPLL_A; 756 u32 saveDPLL_A_MD; 757 u32 saveHTOTAL_A; 758 u32 saveHBLANK_A; 759 u32 saveHSYNC_A; 760 u32 saveVTOTAL_A; 761 u32 saveVBLANK_A; 762 u32 saveVSYNC_A; 763 u32 saveBCLRPAT_A; 764 u32 saveTRANSACONF; 765 u32 saveTRANS_HTOTAL_A; 766 u32 saveTRANS_HBLANK_A; 767 u32 saveTRANS_HSYNC_A; 768 u32 saveTRANS_VTOTAL_A; 769 u32 saveTRANS_VBLANK_A; 770 u32 saveTRANS_VSYNC_A; 771 u32 savePIPEASTAT; 772 u32 saveDSPASTRIDE; 773 u32 saveDSPASIZE; 774 u32 saveDSPAPOS; 775 u32 saveDSPAADDR; 776 u32 saveDSPASURF; 777 u32 saveDSPATILEOFF; 778 u32 savePFIT_PGM_RATIOS; 779 u32 saveBLC_HIST_CTL; 780 u32 saveBLC_PWM_CTL; 781 u32 saveBLC_PWM_CTL2; 782 u32 saveBLC_HIST_CTL_B; 783 u32 saveBLC_CPU_PWM_CTL; 784 u32 saveBLC_CPU_PWM_CTL2; 785 u32 saveFPB0; 786 u32 saveFPB1; 787 u32 saveDPLL_B; 788 u32 saveDPLL_B_MD; 789 u32 saveHTOTAL_B; 790 u32 saveHBLANK_B; 791 u32 saveHSYNC_B; 792 u32 saveVTOTAL_B; 793 u32 saveVBLANK_B; 794 u32 saveVSYNC_B; 795 u32 saveBCLRPAT_B; 796 u32 saveTRANSBCONF; 797 u32 saveTRANS_HTOTAL_B; 798 u32 saveTRANS_HBLANK_B; 799 u32 saveTRANS_HSYNC_B; 800 u32 saveTRANS_VTOTAL_B; 801 u32 saveTRANS_VBLANK_B; 802 u32 saveTRANS_VSYNC_B; 803 u32 savePIPEBSTAT; 804 u32 saveDSPBSTRIDE; 805 u32 saveDSPBSIZE; 806 u32 saveDSPBPOS; 807 u32 saveDSPBADDR; 808 u32 saveDSPBSURF; 809 u32 saveDSPBTILEOFF; 810 u32 saveVGA0; 811 u32 saveVGA1; 812 u32 saveVGA_PD; 813 u32 saveVGACNTRL; 814 u32 saveADPA; 815 u32 saveLVDS; 816 u32 savePP_ON_DELAYS; 817 u32 savePP_OFF_DELAYS; 818 u32 saveDVOA; 819 u32 saveDVOB; 820 u32 saveDVOC; 821 u32 savePP_ON; 822 u32 savePP_OFF; 823 u32 savePP_CONTROL; 824 u32 savePP_DIVISOR; 825 u32 savePFIT_CONTROL; 826 u32 save_palette_a[256]; 827 u32 save_palette_b[256]; 828 u32 saveFBC_CONTROL; 829 u32 saveIER; 830 u32 saveIIR; 831 u32 saveIMR; 832 u32 saveDEIER; 833 u32 saveDEIMR; 834 u32 saveGTIER; 835 u32 saveGTIMR; 836 u32 saveFDI_RXA_IMR; 837 u32 saveFDI_RXB_IMR; 838 u32 saveCACHE_MODE_0; 839 u32 saveMI_ARB_STATE; 840 u32 saveSWF0[16]; 841 u32 saveSWF1[16]; 842 u32 saveSWF2[3]; 843 u8 saveMSR; 844 u8 saveSR[8]; 845 u8 saveGR[25]; 846 u8 saveAR_INDEX; 847 u8 saveAR[21]; 848 u8 saveDACMASK; 849 u8 saveCR[37]; 850 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 851 u32 saveCURACNTR; 852 u32 saveCURAPOS; 853 u32 saveCURABASE; 854 u32 saveCURBCNTR; 855 u32 saveCURBPOS; 856 u32 saveCURBBASE; 857 u32 saveCURSIZE; 858 u32 saveDP_B; 859 u32 saveDP_C; 860 u32 saveDP_D; 861 u32 savePIPEA_GMCH_DATA_M; 862 u32 savePIPEB_GMCH_DATA_M; 863 u32 savePIPEA_GMCH_DATA_N; 864 u32 savePIPEB_GMCH_DATA_N; 865 u32 savePIPEA_DP_LINK_M; 866 u32 savePIPEB_DP_LINK_M; 867 u32 savePIPEA_DP_LINK_N; 868 u32 savePIPEB_DP_LINK_N; 869 u32 saveFDI_RXA_CTL; 870 u32 saveFDI_TXA_CTL; 871 u32 saveFDI_RXB_CTL; 872 u32 saveFDI_TXB_CTL; 873 u32 savePFA_CTL_1; 874 u32 savePFB_CTL_1; 875 u32 savePFA_WIN_SZ; 876 u32 savePFB_WIN_SZ; 877 u32 savePFA_WIN_POS; 878 u32 savePFB_WIN_POS; 879 u32 savePCH_DREF_CONTROL; 880 u32 saveDISP_ARB_CTL; 881 u32 savePIPEA_DATA_M1; 882 u32 savePIPEA_DATA_N1; 883 u32 savePIPEA_LINK_M1; 884 u32 savePIPEA_LINK_N1; 885 u32 savePIPEB_DATA_M1; 886 u32 savePIPEB_DATA_N1; 887 u32 savePIPEB_LINK_M1; 888 u32 savePIPEB_LINK_N1; 889 u32 saveMCHBAR_RENDER_STANDBY; 890 u32 savePCH_PORT_HOTPLUG; 891 }; 892 893 struct vlv_s0ix_state { 894 /* GAM */ 895 u32 wr_watermark; 896 u32 gfx_prio_ctrl; 897 u32 arb_mode; 898 u32 gfx_pend_tlb0; 899 u32 gfx_pend_tlb1; 900 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 901 u32 media_max_req_count; 902 u32 gfx_max_req_count; 903 u32 render_hwsp; 904 u32 ecochk; 905 u32 bsd_hwsp; 906 u32 blt_hwsp; 907 u32 tlb_rd_addr; 908 909 /* MBC */ 910 u32 g3dctl; 911 u32 gsckgctl; 912 u32 mbctl; 913 914 /* GCP */ 915 u32 ucgctl1; 916 u32 ucgctl3; 917 u32 rcgctl1; 918 u32 rcgctl2; 919 u32 rstctl; 920 u32 misccpctl; 921 922 /* GPM */ 923 u32 gfxpause; 924 u32 rpdeuhwtc; 925 u32 rpdeuc; 926 u32 ecobus; 927 u32 pwrdwnupctl; 928 u32 rp_down_timeout; 929 u32 rp_deucsw; 930 u32 rcubmabdtmr; 931 u32 rcedata; 932 u32 spare2gh; 933 934 /* Display 1 CZ domain */ 935 u32 gt_imr; 936 u32 gt_ier; 937 u32 pm_imr; 938 u32 pm_ier; 939 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 940 941 /* GT SA CZ domain */ 942 u32 tilectl; 943 u32 gt_fifoctl; 944 u32 gtlc_wake_ctrl; 945 u32 gtlc_survive; 946 u32 pmwgicz; 947 948 /* Display 2 CZ domain */ 949 u32 gu_ctl0; 950 u32 gu_ctl1; 951 u32 clock_gate_dis2; 952 }; 953 954 struct intel_rps_ei { 955 u32 cz_clock; 956 u32 render_c0; 957 u32 media_c0; 958 }; 959 960 struct intel_gen6_power_mgmt { 961 /* work and pm_iir are protected by dev_priv->irq_lock */ 962 struct work_struct work; 963 u32 pm_iir; 964 965 /* Frequencies are stored in potentially platform dependent multiples. 966 * In other words, *_freq needs to be multiplied by X to be interesting. 967 * Soft limits are those which are used for the dynamic reclocking done 968 * by the driver (raise frequencies under heavy loads, and lower for 969 * lighter loads). Hard limits are those imposed by the hardware. 970 * 971 * A distinction is made for overclocking, which is never enabled by 972 * default, and is considered to be above the hard limit if it's 973 * possible at all. 974 */ 975 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 976 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 977 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 978 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 979 u8 min_freq; /* AKA RPn. Minimum frequency */ 980 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 981 u8 rp1_freq; /* "less than" RP0 power/freqency */ 982 u8 rp0_freq; /* Non-overclocked max frequency. */ 983 u32 cz_freq; 984 985 u32 ei_interrupt_count; 986 987 int last_adj; 988 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 989 990 bool enabled; 991 struct delayed_work delayed_resume_work; 992 993 /* manual wa residency calculations */ 994 struct intel_rps_ei up_ei, down_ei; 995 996 /* 997 * Protects RPS/RC6 register access and PCU communication. 998 * Must be taken after struct_mutex if nested. 999 */ 1000 struct lock hw_lock; 1001 }; 1002 1003 /* defined intel_pm.c */ 1004 extern struct lock mchdev_lock; 1005 1006 struct intel_ilk_power_mgmt { 1007 u8 cur_delay; 1008 u8 min_delay; 1009 u8 max_delay; 1010 u8 fmax; 1011 u8 fstart; 1012 1013 u64 last_count1; 1014 unsigned long last_time1; 1015 unsigned long chipset_power; 1016 u64 last_count2; 1017 struct timespec last_time2; 1018 unsigned long gfx_power; 1019 u8 corr; 1020 1021 int c_m; 1022 int r_t; 1023 1024 struct drm_i915_gem_object *pwrctx; 1025 struct drm_i915_gem_object *renderctx; 1026 }; 1027 1028 struct drm_i915_private; 1029 struct i915_power_well; 1030 1031 struct i915_power_well_ops { 1032 /* 1033 * Synchronize the well's hw state to match the current sw state, for 1034 * example enable/disable it based on the current refcount. Called 1035 * during driver init and resume time, possibly after first calling 1036 * the enable/disable handlers. 1037 */ 1038 void (*sync_hw)(struct drm_i915_private *dev_priv, 1039 struct i915_power_well *power_well); 1040 /* 1041 * Enable the well and resources that depend on it (for example 1042 * interrupts located on the well). Called after the 0->1 refcount 1043 * transition. 1044 */ 1045 void (*enable)(struct drm_i915_private *dev_priv, 1046 struct i915_power_well *power_well); 1047 /* 1048 * Disable the well and resources that depend on it. Called after 1049 * the 1->0 refcount transition. 1050 */ 1051 void (*disable)(struct drm_i915_private *dev_priv, 1052 struct i915_power_well *power_well); 1053 /* Returns the hw enabled state. */ 1054 bool (*is_enabled)(struct drm_i915_private *dev_priv, 1055 struct i915_power_well *power_well); 1056 }; 1057 1058 /* Power well structure for haswell */ 1059 struct i915_power_well { 1060 const char *name; 1061 bool always_on; 1062 /* power well enable/disable usage count */ 1063 int count; 1064 /* cached hw enabled state */ 1065 bool hw_enabled; 1066 unsigned long domains; 1067 unsigned long data; 1068 const struct i915_power_well_ops *ops; 1069 }; 1070 1071 struct i915_power_domains { 1072 /* 1073 * Power wells needed for initialization at driver init and suspend 1074 * time are on. They are kept on until after the first modeset. 1075 */ 1076 bool init_power_on; 1077 bool initializing; 1078 int power_well_count; 1079 1080 struct lock lock; 1081 int domain_use_count[POWER_DOMAIN_NUM]; 1082 struct i915_power_well *power_wells; 1083 }; 1084 1085 struct i915_dri1_state { 1086 unsigned allow_batchbuffer : 1; 1087 u32 __iomem *gfx_hws_cpu_addr; 1088 1089 unsigned int cpp; 1090 int back_offset; 1091 int front_offset; 1092 int current_page; 1093 int page_flipping; 1094 1095 uint32_t counter; 1096 }; 1097 1098 struct i915_ums_state { 1099 /** 1100 * Flag if the X Server, and thus DRM, is not currently in 1101 * control of the device. 1102 * 1103 * This is set between LeaveVT and EnterVT. It needs to be 1104 * replaced with a semaphore. It also needs to be 1105 * transitioned away from for kernel modesetting. 1106 */ 1107 int mm_suspended; 1108 }; 1109 1110 #define MAX_L3_SLICES 2 1111 struct intel_l3_parity { 1112 u32 *remap_info[MAX_L3_SLICES]; 1113 struct work_struct error_work; 1114 int which_slice; 1115 }; 1116 1117 struct i915_gem_mm { 1118 /** Memory allocator for GTT stolen memory */ 1119 struct drm_mm stolen; 1120 /** List of all objects in gtt_space. Used to restore gtt 1121 * mappings on resume */ 1122 struct list_head bound_list; 1123 /** 1124 * List of objects which are not bound to the GTT (thus 1125 * are idle and not used by the GPU) but still have 1126 * (presumably uncached) pages still attached. 1127 */ 1128 struct list_head unbound_list; 1129 1130 /** Usable portion of the GTT for GEM */ 1131 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1132 1133 /** PPGTT used for aliasing the PPGTT with the GTT */ 1134 struct i915_hw_ppgtt *aliasing_ppgtt; 1135 1136 eventhandler_tag inactive_shrinker; 1137 bool shrinker_no_lock_stealing; 1138 1139 /** LRU list of objects with fence regs on them. */ 1140 struct list_head fence_list; 1141 1142 /** 1143 * We leave the user IRQ off as much as possible, 1144 * but this means that requests will finish and never 1145 * be retired once the system goes idle. Set a timer to 1146 * fire periodically while the ring is running. When it 1147 * fires, go retire requests. 1148 */ 1149 struct delayed_work retire_work; 1150 1151 /** 1152 * When we detect an idle GPU, we want to turn on 1153 * powersaving features. So once we see that there 1154 * are no more requests outstanding and no more 1155 * arrive within a small period of time, we fire 1156 * off the idle_work. 1157 */ 1158 struct delayed_work idle_work; 1159 1160 /** 1161 * Are we in a non-interruptible section of code like 1162 * modesetting? 1163 */ 1164 bool interruptible; 1165 1166 /** 1167 * Is the GPU currently considered idle, or busy executing userspace 1168 * requests? Whilst idle, we attempt to power down the hardware and 1169 * display clocks. In order to reduce the effect on performance, there 1170 * is a slight delay before we do so. 1171 */ 1172 bool busy; 1173 1174 /* the indicator for dispatch video commands on two BSD rings */ 1175 int bsd_ring_dispatch_index; 1176 1177 /** Bit 6 swizzling required for X tiling */ 1178 uint32_t bit_6_swizzle_x; 1179 /** Bit 6 swizzling required for Y tiling */ 1180 uint32_t bit_6_swizzle_y; 1181 1182 /* accounting, useful for userland debugging */ 1183 struct spinlock object_stat_lock; 1184 size_t object_memory; 1185 u32 object_count; 1186 }; 1187 1188 struct drm_i915_error_state_buf { 1189 struct drm_i915_private *i915; 1190 unsigned bytes; 1191 unsigned size; 1192 int err; 1193 u8 *buf; 1194 loff_t start; 1195 loff_t pos; 1196 }; 1197 1198 struct i915_error_state_file_priv { 1199 struct drm_device *dev; 1200 struct drm_i915_error_state *error; 1201 }; 1202 1203 struct i915_gpu_error { 1204 /* For hangcheck timer */ 1205 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1206 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1207 /* Hang gpu twice in this window and your context gets banned */ 1208 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1209 1210 struct timer_list hangcheck_timer; 1211 1212 /* For reset and error_state handling. */ 1213 struct lock lock; 1214 /* Protected by the above dev->gpu_error.lock. */ 1215 struct drm_i915_error_state *first_error; 1216 struct work_struct work; 1217 1218 1219 unsigned long missed_irq_rings; 1220 1221 /** 1222 * State variable controlling the reset flow and count 1223 * 1224 * This is a counter which gets incremented when reset is triggered, 1225 * and again when reset has been handled. So odd values (lowest bit set) 1226 * means that reset is in progress and even values that 1227 * (reset_counter >> 1):th reset was successfully completed. 1228 * 1229 * If reset is not completed succesfully, the I915_WEDGE bit is 1230 * set meaning that hardware is terminally sour and there is no 1231 * recovery. All waiters on the reset_queue will be woken when 1232 * that happens. 1233 * 1234 * This counter is used by the wait_seqno code to notice that reset 1235 * event happened and it needs to restart the entire ioctl (since most 1236 * likely the seqno it waited for won't ever signal anytime soon). 1237 * 1238 * This is important for lock-free wait paths, where no contended lock 1239 * naturally enforces the correct ordering between the bail-out of the 1240 * waiter and the gpu reset work code. 1241 */ 1242 atomic_t reset_counter; 1243 1244 #define I915_RESET_IN_PROGRESS_FLAG 1 1245 #define I915_WEDGED (1 << 31) 1246 1247 /** 1248 * Waitqueue to signal when the reset has completed. Used by clients 1249 * that wait for dev_priv->mm.wedged to settle. 1250 */ 1251 wait_queue_head_t reset_queue; 1252 1253 /* Userspace knobs for gpu hang simulation; 1254 * combines both a ring mask, and extra flags 1255 */ 1256 u32 stop_rings; 1257 #define I915_STOP_RING_ALLOW_BAN (1 << 31) 1258 #define I915_STOP_RING_ALLOW_WARN (1 << 30) 1259 1260 /* For missed irq/seqno simulation. */ 1261 unsigned int test_irq_rings; 1262 1263 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ 1264 bool reload_in_reset; 1265 }; 1266 1267 enum modeset_restore { 1268 MODESET_ON_LID_OPEN, 1269 MODESET_DONE, 1270 MODESET_SUSPENDED, 1271 }; 1272 1273 struct ddi_vbt_port_info { 1274 /* 1275 * This is an index in the HDMI/DVI DDI buffer translation table. 1276 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 1277 * populate this field. 1278 */ 1279 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 1280 uint8_t hdmi_level_shift; 1281 1282 uint8_t supports_dvi:1; 1283 uint8_t supports_hdmi:1; 1284 uint8_t supports_dp:1; 1285 }; 1286 1287 enum drrs_support_type { 1288 DRRS_NOT_SUPPORTED = 0, 1289 STATIC_DRRS_SUPPORT = 1, 1290 SEAMLESS_DRRS_SUPPORT = 2 1291 }; 1292 1293 struct intel_vbt_data { 1294 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1295 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1296 1297 /* Feature bits */ 1298 unsigned int int_tv_support:1; 1299 unsigned int lvds_dither:1; 1300 unsigned int lvds_vbt:1; 1301 unsigned int int_crt_support:1; 1302 unsigned int lvds_use_ssc:1; 1303 unsigned int display_clock_mode:1; 1304 unsigned int fdi_rx_polarity_inverted:1; 1305 unsigned int has_mipi:1; 1306 int lvds_ssc_freq; 1307 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1308 1309 enum drrs_support_type drrs_type; 1310 1311 /* eDP */ 1312 int edp_rate; 1313 int edp_lanes; 1314 int edp_preemphasis; 1315 int edp_vswing; 1316 bool edp_initialized; 1317 bool edp_support; 1318 int edp_bpp; 1319 struct edp_power_seq edp_pps; 1320 1321 struct { 1322 u16 pwm_freq_hz; 1323 bool present; 1324 bool active_low_pwm; 1325 u8 min_brightness; /* min_brightness/255 of max */ 1326 } backlight; 1327 1328 /* MIPI DSI */ 1329 struct { 1330 u16 port; 1331 u16 panel_id; 1332 struct mipi_config *config; 1333 struct mipi_pps_data *pps; 1334 u8 seq_version; 1335 u32 size; 1336 u8 *data; 1337 u8 *sequence[MIPI_SEQ_MAX]; 1338 } dsi; 1339 1340 int crt_ddc_pin; 1341 1342 int child_dev_num; 1343 union child_device_config *child_dev; 1344 1345 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1346 }; 1347 1348 enum intel_ddb_partitioning { 1349 INTEL_DDB_PART_1_2, 1350 INTEL_DDB_PART_5_6, /* IVB+ */ 1351 }; 1352 1353 struct intel_wm_level { 1354 bool enable; 1355 uint32_t pri_val; 1356 uint32_t spr_val; 1357 uint32_t cur_val; 1358 uint32_t fbc_val; 1359 }; 1360 1361 struct ilk_wm_values { 1362 uint32_t wm_pipe[3]; 1363 uint32_t wm_lp[3]; 1364 uint32_t wm_lp_spr[3]; 1365 uint32_t wm_linetime[3]; 1366 bool enable_fbc_wm; 1367 enum intel_ddb_partitioning partitioning; 1368 }; 1369 1370 /* 1371 * This struct helps tracking the state needed for runtime PM, which puts the 1372 * device in PCI D3 state. Notice that when this happens, nothing on the 1373 * graphics device works, even register access, so we don't get interrupts nor 1374 * anything else. 1375 * 1376 * Every piece of our code that needs to actually touch the hardware needs to 1377 * either call intel_runtime_pm_get or call intel_display_power_get with the 1378 * appropriate power domain. 1379 * 1380 * Our driver uses the autosuspend delay feature, which means we'll only really 1381 * suspend if we stay with zero refcount for a certain amount of time. The 1382 * default value is currently very conservative (see intel_init_runtime_pm), but 1383 * it can be changed with the standard runtime PM files from sysfs. 1384 * 1385 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1386 * goes back to false exactly before we reenable the IRQs. We use this variable 1387 * to check if someone is trying to enable/disable IRQs while they're supposed 1388 * to be disabled. This shouldn't happen and we'll print some error messages in 1389 * case it happens. 1390 * 1391 * For more, read the Documentation/power/runtime_pm.txt. 1392 */ 1393 struct i915_runtime_pm { 1394 bool suspended; 1395 bool _irqs_disabled; 1396 }; 1397 1398 enum intel_pipe_crc_source { 1399 INTEL_PIPE_CRC_SOURCE_NONE, 1400 INTEL_PIPE_CRC_SOURCE_PLANE1, 1401 INTEL_PIPE_CRC_SOURCE_PLANE2, 1402 INTEL_PIPE_CRC_SOURCE_PF, 1403 INTEL_PIPE_CRC_SOURCE_PIPE, 1404 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1405 INTEL_PIPE_CRC_SOURCE_TV, 1406 INTEL_PIPE_CRC_SOURCE_DP_B, 1407 INTEL_PIPE_CRC_SOURCE_DP_C, 1408 INTEL_PIPE_CRC_SOURCE_DP_D, 1409 INTEL_PIPE_CRC_SOURCE_AUTO, 1410 INTEL_PIPE_CRC_SOURCE_MAX, 1411 }; 1412 1413 struct intel_pipe_crc_entry { 1414 uint32_t frame; 1415 uint32_t crc[5]; 1416 }; 1417 1418 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1419 struct intel_pipe_crc { 1420 struct spinlock lock; 1421 bool opened; /* exclusive access to the result file */ 1422 struct intel_pipe_crc_entry *entries; 1423 enum intel_pipe_crc_source source; 1424 int head, tail; 1425 wait_queue_head_t wq; 1426 }; 1427 1428 struct i915_frontbuffer_tracking { 1429 struct lock lock; 1430 1431 /* 1432 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 1433 * scheduled flips. 1434 */ 1435 unsigned busy_bits; 1436 unsigned flip_bits; 1437 }; 1438 1439 struct drm_i915_private { 1440 struct drm_device *dev; 1441 struct kmem_cache *slab; 1442 1443 struct intel_device_info info; 1444 1445 int relative_constants_mode; 1446 1447 device_t *gmbus_bridge; 1448 device_t *bbbus_bridge; 1449 device_t *bbbus; 1450 1451 drm_local_map_t *sarea; 1452 drm_local_map_t *mmio_map; 1453 char __iomem *regs; 1454 1455 struct intel_uncore uncore; 1456 1457 device_t *gmbus; 1458 1459 1460 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1461 * controller on different i2c buses. */ 1462 struct lock gmbus_mutex; 1463 1464 struct _drm_i915_sarea *sarea_priv; 1465 /** 1466 * Base address of the gmbus and gpio block. 1467 */ 1468 uint32_t gpio_mmio_base; 1469 1470 /* MMIO base address for MIPI regs */ 1471 uint32_t mipi_mmio_base; 1472 1473 wait_queue_head_t gmbus_wait_queue; 1474 1475 struct pci_dev *bridge_dev; 1476 struct intel_engine_cs ring[I915_NUM_RINGS]; 1477 struct drm_i915_gem_object *semaphore_obj; 1478 uint32_t last_seqno, next_seqno; 1479 1480 drm_dma_handle_t *status_page_dmah; 1481 struct resource *mch_res; 1482 int mch_res_rid; 1483 1484 /* protects the irq masks */ 1485 struct lock irq_lock; 1486 1487 /* protects the mmio flip data */ 1488 struct spinlock mmio_flip_lock; 1489 1490 bool display_irqs_enabled; 1491 1492 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1493 struct pm_qos_request pm_qos; 1494 1495 /* DPIO indirect register protection */ 1496 struct lock dpio_lock; 1497 1498 /** Cached value of IMR to avoid reads in updating the bitfield */ 1499 union { 1500 u32 irq_mask; 1501 u32 de_irq_mask[I915_MAX_PIPES]; 1502 }; 1503 u32 gt_irq_mask; 1504 u32 pm_irq_mask; 1505 u32 pm_rps_events; 1506 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1507 1508 struct work_struct hotplug_work; 1509 struct { 1510 unsigned long hpd_last_jiffies; 1511 int hpd_cnt; 1512 enum { 1513 HPD_ENABLED = 0, 1514 HPD_DISABLED = 1, 1515 HPD_MARK_DISABLED = 2 1516 } hpd_mark; 1517 } hpd_stats[HPD_NUM_PINS]; 1518 u32 hpd_event_bits; 1519 struct delayed_work hotplug_reenable_work; 1520 1521 struct i915_fbc fbc; 1522 struct i915_drrs drrs; 1523 struct intel_opregion opregion; 1524 struct intel_vbt_data vbt; 1525 1526 /* overlay */ 1527 struct intel_overlay *overlay; 1528 1529 /* backlight registers and fields in struct intel_panel */ 1530 struct spinlock backlight_lock; 1531 1532 /* LVDS info */ 1533 bool no_aux_handshake; 1534 1535 /* protects panel power sequencer state */ 1536 struct lock pps_mutex; 1537 1538 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1539 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1540 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1541 1542 unsigned int fsb_freq, mem_freq, is_ddr3; 1543 unsigned int vlv_cdclk_freq; 1544 1545 /** 1546 * wq - Driver workqueue for GEM. 1547 * 1548 * NOTE: Work items scheduled here are not allowed to grab any modeset 1549 * locks, for otherwise the flushing done in the pageflip code will 1550 * result in deadlocks. 1551 */ 1552 struct workqueue_struct *wq; 1553 1554 /* Display functions */ 1555 struct drm_i915_display_funcs display; 1556 1557 /* PCH chipset type */ 1558 enum intel_pch pch_type; 1559 unsigned short pch_id; 1560 1561 unsigned long quirks; 1562 1563 enum modeset_restore modeset_restore; 1564 struct lock modeset_restore_lock; 1565 1566 struct list_head vm_list; /* Global list of all address spaces */ 1567 struct i915_gtt gtt; /* VM representing the global address space */ 1568 1569 struct i915_gem_mm mm; 1570 #if defined(CONFIG_MMU_NOTIFIER) 1571 DECLARE_HASHTABLE(mmu_notifiers, 7); 1572 #endif 1573 1574 /* Kernel Modesetting */ 1575 1576 struct sdvo_device_mapping sdvo_mappings[2]; 1577 1578 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1579 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1580 wait_queue_head_t pending_flip_queue; 1581 1582 #ifdef CONFIG_DEBUG_FS 1583 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1584 #endif 1585 1586 int num_shared_dpll; 1587 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1588 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1589 1590 /* 1591 * workarounds are currently applied at different places and 1592 * changes are being done to consolidate them so exact count is 1593 * not clear at this point, use a max value for now. 1594 */ 1595 #define I915_MAX_WA_REGS 16 1596 struct { 1597 u32 addr; 1598 u32 value; 1599 /* bitmask representing WA bits */ 1600 u32 mask; 1601 } intel_wa_regs[I915_MAX_WA_REGS]; 1602 u32 num_wa_regs; 1603 1604 /* Reclocking support */ 1605 bool render_reclock_avail; 1606 bool lvds_downclock_avail; 1607 /* indicates the reduced downclock for LVDS*/ 1608 int lvds_downclock; 1609 1610 struct i915_frontbuffer_tracking fb_tracking; 1611 1612 u16 orig_clock; 1613 1614 bool mchbar_need_disable; 1615 1616 struct intel_l3_parity l3_parity; 1617 1618 /* Cannot be determined by PCIID. You must always read a register. */ 1619 size_t ellc_size; 1620 1621 /* gen6+ rps state */ 1622 struct intel_gen6_power_mgmt rps; 1623 1624 /* ilk-only ips/rps state. Everything in here is protected by the global 1625 * mchdev_lock in intel_pm.c */ 1626 struct intel_ilk_power_mgmt ips; 1627 1628 struct i915_power_domains power_domains; 1629 1630 struct i915_psr psr; 1631 1632 struct i915_gpu_error gpu_error; 1633 1634 struct drm_i915_gem_object *vlv_pctx; 1635 1636 #ifdef CONFIG_DRM_I915_FBDEV 1637 /* list of fbdev register on this device */ 1638 struct intel_fbdev *fbdev; 1639 struct work_struct fbdev_suspend_work; 1640 #endif 1641 1642 struct drm_property *broadcast_rgb_property; 1643 struct drm_property *force_audio_property; 1644 1645 uint32_t hw_context_size; 1646 struct list_head context_list; 1647 1648 u32 fdi_rx_config; 1649 1650 u32 suspend_count; 1651 struct i915_suspend_saved_registers regfile; 1652 struct vlv_s0ix_state vlv_s0ix_state; 1653 1654 struct { 1655 /* 1656 * Raw watermark latency values: 1657 * in 0.1us units for WM0, 1658 * in 0.5us units for WM1+. 1659 */ 1660 /* primary */ 1661 uint16_t pri_latency[5]; 1662 /* sprite */ 1663 uint16_t spr_latency[5]; 1664 /* cursor */ 1665 uint16_t cur_latency[5]; 1666 1667 /* current hardware state */ 1668 struct ilk_wm_values hw; 1669 } wm; 1670 1671 struct i915_runtime_pm pm; 1672 1673 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; 1674 u32 long_hpd_port_mask; 1675 u32 short_hpd_port_mask; 1676 struct work_struct dig_port_work; 1677 1678 /* 1679 * if we get a HPD irq from DP and a HPD irq from non-DP 1680 * the non-DP HPD could block the workqueue on a mode config 1681 * mutex getting, that userspace may have taken. However 1682 * userspace is waiting on the DP workqueue to run which is 1683 * blocked behind the non-DP one. 1684 */ 1685 struct workqueue_struct *dp_wq; 1686 1687 uint32_t bios_vgacntr; 1688 1689 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1690 * here! */ 1691 struct i915_dri1_state dri1; 1692 /* Old ums support infrastructure, same warning applies. */ 1693 struct i915_ums_state ums; 1694 1695 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1696 struct { 1697 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, 1698 struct intel_engine_cs *ring, 1699 struct intel_context *ctx, 1700 struct drm_i915_gem_execbuffer2 *args, 1701 struct list_head *vmas, 1702 struct drm_i915_gem_object *batch_obj, 1703 u64 exec_start, u32 flags); 1704 int (*init_rings)(struct drm_device *dev); 1705 void (*cleanup_ring)(struct intel_engine_cs *ring); 1706 void (*stop_ring)(struct intel_engine_cs *ring); 1707 } gt; 1708 1709 /* 1710 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1711 * will be rejected. Instead look for a better place. 1712 */ 1713 }; 1714 1715 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1716 { 1717 return dev->dev_private; 1718 } 1719 1720 /* Iterate over initialised rings */ 1721 #define for_each_ring(ring__, dev_priv__, i__) \ 1722 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1723 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1724 1725 enum hdmi_force_audio { 1726 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1727 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1728 HDMI_AUDIO_AUTO, /* trust EDID */ 1729 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1730 }; 1731 1732 #define I915_GTT_OFFSET_NONE ((u32)-1) 1733 1734 struct drm_i915_gem_object_ops { 1735 /* Interface between the GEM object and its backing storage. 1736 * get_pages() is called once prior to the use of the associated set 1737 * of pages before to binding them into the GTT, and put_pages() is 1738 * called after we no longer need them. As we expect there to be 1739 * associated cost with migrating pages between the backing storage 1740 * and making them available for the GPU (e.g. clflush), we may hold 1741 * onto the pages after they are no longer referenced by the GPU 1742 * in case they may be used again shortly (for example migrating the 1743 * pages to a different memory domain within the GTT). put_pages() 1744 * will therefore most likely be called when the object itself is 1745 * being released or under memory pressure (where we attempt to 1746 * reap pages for the shrinker). 1747 */ 1748 int (*get_pages)(struct drm_i915_gem_object *); 1749 void (*put_pages)(struct drm_i915_gem_object *); 1750 int (*dmabuf_export)(struct drm_i915_gem_object *); 1751 void (*release)(struct drm_i915_gem_object *); 1752 }; 1753 1754 /* 1755 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1756 * considered to be the frontbuffer for the given plane interface-vise. This 1757 * doesn't mean that the hw necessarily already scans it out, but that any 1758 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1759 * 1760 * We have one bit per pipe and per scanout plane type. 1761 */ 1762 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 1763 #define INTEL_FRONTBUFFER_BITS \ 1764 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) 1765 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ 1766 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1767 #define INTEL_FRONTBUFFER_CURSOR(pipe) \ 1768 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1769 #define INTEL_FRONTBUFFER_SPRITE(pipe) \ 1770 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1771 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1772 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1773 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1774 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1775 1776 struct drm_i915_gem_object { 1777 struct drm_gem_object base; 1778 1779 const struct drm_i915_gem_object_ops *ops; 1780 1781 /** List of VMAs backed by this object */ 1782 struct list_head vma_list; 1783 1784 /** Stolen memory for this object, instead of being backed by shmem. */ 1785 struct drm_mm_node *stolen; 1786 struct list_head global_list; 1787 1788 struct list_head ring_list; 1789 /** Used in execbuf to temporarily hold a ref */ 1790 struct list_head obj_exec_link; 1791 1792 /** 1793 * This is set if the object is on the active lists (has pending 1794 * rendering and so a non-zero seqno), and is not set if it i s on 1795 * inactive (ready to be unbound) list. 1796 */ 1797 unsigned int active:1; 1798 1799 /** 1800 * This is set if the object has been written to since last bound 1801 * to the GTT 1802 */ 1803 unsigned int dirty:1; 1804 1805 /** 1806 * Fence register bits (if any) for this object. Will be set 1807 * as needed when mapped into the GTT. 1808 * Protected by dev->struct_mutex. 1809 */ 1810 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1811 1812 /** 1813 * Advice: are the backing pages purgeable? 1814 */ 1815 unsigned int madv:2; 1816 1817 /** 1818 * Current tiling mode for the object. 1819 */ 1820 unsigned int tiling_mode:2; 1821 /** 1822 * Whether the tiling parameters for the currently associated fence 1823 * register have changed. Note that for the purposes of tracking 1824 * tiling changes we also treat the unfenced register, the register 1825 * slot that the object occupies whilst it executes a fenced 1826 * command (such as BLT on gen2/3), as a "fence". 1827 */ 1828 unsigned int fence_dirty:1; 1829 1830 /** 1831 * Is the object at the current location in the gtt mappable and 1832 * fenceable? Used to avoid costly recalculations. 1833 */ 1834 unsigned int map_and_fenceable:1; 1835 1836 /** 1837 * Whether the current gtt mapping needs to be mappable (and isn't just 1838 * mappable by accident). Track pin and fault separate for a more 1839 * accurate mappable working set. 1840 */ 1841 unsigned int fault_mappable:1; 1842 unsigned int pin_mappable:1; 1843 unsigned int pin_display:1; 1844 1845 /* 1846 * Is the object to be mapped as read-only to the GPU 1847 * Only honoured if hardware has relevant pte bit 1848 */ 1849 unsigned long gt_ro:1; 1850 unsigned int cache_level:3; 1851 1852 unsigned int has_aliasing_ppgtt_mapping:1; 1853 unsigned int has_global_gtt_mapping:1; 1854 unsigned int has_dma_mapping:1; 1855 1856 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; 1857 1858 vm_page_t *pages; 1859 int pages_pin_count; 1860 1861 /* prime dma-buf support */ 1862 void *dma_buf_vmapping; 1863 int vmapping_count; 1864 1865 struct intel_engine_cs *ring; 1866 1867 /** Breadcrumb of last rendering to the buffer. */ 1868 uint32_t last_read_seqno; 1869 uint32_t last_write_seqno; 1870 /** Breadcrumb of last fenced GPU access to the buffer. */ 1871 uint32_t last_fenced_seqno; 1872 1873 /** Current tiling stride for the object, if it's tiled. */ 1874 uint32_t stride; 1875 1876 /** References from framebuffers, locks out tiling changes. */ 1877 unsigned long framebuffer_references; 1878 1879 /** Record of address bit 17 of each page at last unbind. */ 1880 unsigned long *bit_17; 1881 1882 /** User space pin count and filp owning the pin */ 1883 unsigned long user_pin_count; 1884 struct drm_file *pin_filp; 1885 1886 /** for phy allocated objects */ 1887 struct drm_dma_handle *phys_handle; 1888 1889 union { 1890 struct i915_gem_userptr { 1891 uintptr_t ptr; 1892 unsigned read_only :1; 1893 unsigned workers :4; 1894 #define I915_GEM_USERPTR_MAX_WORKERS 15 1895 1896 struct mm_struct *mm; 1897 struct i915_mmu_object *mn; 1898 struct work_struct *work; 1899 } userptr; 1900 }; 1901 }; 1902 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1903 1904 void i915_gem_track_fb(struct drm_i915_gem_object *old, 1905 struct drm_i915_gem_object *new, 1906 unsigned frontbuffer_bits); 1907 1908 /** 1909 * Request queue structure. 1910 * 1911 * The request queue allows us to note sequence numbers that have been emitted 1912 * and may be associated with active buffers to be retired. 1913 * 1914 * By keeping this list, we can avoid having to do questionable 1915 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1916 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1917 */ 1918 struct drm_i915_gem_request { 1919 /** On Which ring this request was generated */ 1920 struct intel_engine_cs *ring; 1921 1922 /** GEM sequence number associated with this request. */ 1923 uint32_t seqno; 1924 1925 /** Position in the ringbuffer of the start of the request */ 1926 u32 head; 1927 1928 /** Position in the ringbuffer of the end of the request */ 1929 u32 tail; 1930 1931 /** Context related to this request */ 1932 struct intel_context *ctx; 1933 1934 /** Batch buffer related to this request if any */ 1935 struct drm_i915_gem_object *batch_obj; 1936 1937 /** Time at which this request was emitted, in jiffies. */ 1938 unsigned long emitted_jiffies; 1939 1940 /** global list entry for this request */ 1941 struct list_head list; 1942 1943 struct drm_i915_file_private *file_priv; 1944 /** file_priv list entry for this request */ 1945 struct list_head client_list; 1946 }; 1947 1948 struct drm_i915_file_private { 1949 struct drm_i915_private *dev_priv; 1950 struct drm_file *file; 1951 1952 struct { 1953 struct spinlock lock; 1954 struct list_head request_list; 1955 struct delayed_work idle_work; 1956 } mm; 1957 struct idr context_idr; 1958 1959 atomic_t rps_wait_boost; 1960 struct intel_engine_cs *bsd_ring; 1961 }; 1962 1963 /* 1964 * A command that requires special handling by the command parser. 1965 */ 1966 struct drm_i915_cmd_descriptor { 1967 /* 1968 * Flags describing how the command parser processes the command. 1969 * 1970 * CMD_DESC_FIXED: The command has a fixed length if this is set, 1971 * a length mask if not set 1972 * CMD_DESC_SKIP: The command is allowed but does not follow the 1973 * standard length encoding for the opcode range in 1974 * which it falls 1975 * CMD_DESC_REJECT: The command is never allowed 1976 * CMD_DESC_REGISTER: The command should be checked against the 1977 * register whitelist for the appropriate ring 1978 * CMD_DESC_MASTER: The command is allowed if the submitting process 1979 * is the DRM master 1980 */ 1981 u32 flags; 1982 #define CMD_DESC_FIXED (1<<0) 1983 #define CMD_DESC_SKIP (1<<1) 1984 #define CMD_DESC_REJECT (1<<2) 1985 #define CMD_DESC_REGISTER (1<<3) 1986 #define CMD_DESC_BITMASK (1<<4) 1987 #define CMD_DESC_MASTER (1<<5) 1988 1989 /* 1990 * The command's unique identification bits and the bitmask to get them. 1991 * This isn't strictly the opcode field as defined in the spec and may 1992 * also include type, subtype, and/or subop fields. 1993 */ 1994 struct { 1995 u32 value; 1996 u32 mask; 1997 } cmd; 1998 1999 /* 2000 * The command's length. The command is either fixed length (i.e. does 2001 * not include a length field) or has a length field mask. The flag 2002 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 2003 * a length mask. All command entries in a command table must include 2004 * length information. 2005 */ 2006 union { 2007 u32 fixed; 2008 u32 mask; 2009 } length; 2010 2011 /* 2012 * Describes where to find a register address in the command to check 2013 * against the ring's register whitelist. Only valid if flags has the 2014 * CMD_DESC_REGISTER bit set. 2015 */ 2016 struct { 2017 u32 offset; 2018 u32 mask; 2019 } reg; 2020 2021 #define MAX_CMD_DESC_BITMASKS 3 2022 /* 2023 * Describes command checks where a particular dword is masked and 2024 * compared against an expected value. If the command does not match 2025 * the expected value, the parser rejects it. Only valid if flags has 2026 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 2027 * are valid. 2028 * 2029 * If the check specifies a non-zero condition_mask then the parser 2030 * only performs the check when the bits specified by condition_mask 2031 * are non-zero. 2032 */ 2033 struct { 2034 u32 offset; 2035 u32 mask; 2036 u32 expected; 2037 u32 condition_offset; 2038 u32 condition_mask; 2039 } bits[MAX_CMD_DESC_BITMASKS]; 2040 }; 2041 2042 /* 2043 * A table of commands requiring special handling by the command parser. 2044 * 2045 * Each ring has an array of tables. Each table consists of an array of command 2046 * descriptors, which must be sorted with command opcodes in ascending order. 2047 */ 2048 struct drm_i915_cmd_table { 2049 const struct drm_i915_cmd_descriptor *table; 2050 int count; 2051 }; 2052 2053 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ 2054 #define __I915__(p) ({ \ 2055 const struct drm_i915_private *__p; \ 2056 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ 2057 __p = (const struct drm_i915_private *)p; \ 2058 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ 2059 __p = to_i915((const struct drm_device *)p); \ 2060 __p; \ 2061 }) 2062 2063 #define INTEL_INFO(p) (&__I915__(p)->info) 2064 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) 2065 2066 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) 2067 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) 2068 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 2069 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) 2070 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 2071 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) 2072 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) 2073 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 2074 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 2075 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 2076 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) 2077 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 2078 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) 2079 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) 2080 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 2081 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 2082 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) 2083 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 2084 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ 2085 INTEL_DEVID(dev) == 0x0152 || \ 2086 INTEL_DEVID(dev) == 0x015a) 2087 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \ 2088 INTEL_DEVID(dev) == 0x0106 || \ 2089 INTEL_DEVID(dev) == 0x010A) 2090 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 2091 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2092 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 2093 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2094 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 2095 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 2096 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) 2097 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2098 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \ 2099 (INTEL_DEVID(dev) & 0xf) == 0x6 || \ 2100 (INTEL_DEVID(dev) & 0xf) == 0xe)) 2101 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 2102 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) 2103 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) 2104 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 2105 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2106 /* ULX machines are also considered ULT. */ 2107 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ 2108 INTEL_DEVID(dev) == 0x0A1E) 2109 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 2110 2111 /* 2112 * The genX designation typically refers to the render engine, so render 2113 * capability related checks should use IS_GEN, while display and other checks 2114 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 2115 * chips, etc.). 2116 */ 2117 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 2118 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 2119 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 2120 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 2121 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 2122 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 2123 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 2124 2125 #define RENDER_RING (1<<RCS) 2126 #define BSD_RING (1<<VCS) 2127 #define BLT_RING (1<<BCS) 2128 #define VEBOX_RING (1<<VECS) 2129 #define BSD2_RING (1<<VCS2) 2130 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 2131 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) 2132 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 2133 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 2134 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 2135 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 2136 to_i915(dev)->ellc_size) 2137 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 2138 2139 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 2140 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) 2141 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6) 2142 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev)) 2143 #define USES_PPGTT(dev) (i915.enable_ppgtt) 2144 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) 2145 2146 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 2147 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 2148 2149 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2150 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 2151 /* 2152 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 2153 * even when in MSI mode. This results in spurious interrupt warnings if the 2154 * legacy irq no. is shared with another device. The kernel then disables that 2155 * interrupt source and so prevents the other device from working properly. 2156 */ 2157 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2158 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2159 2160 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2161 * rows, which changed the alignment requirements and fence programming. 2162 */ 2163 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 2164 IS_I915GM(dev))) 2165 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 2166 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2167 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2168 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 2169 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 2170 2171 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 2172 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 2173 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 2174 2175 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) 2176 2177 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 2178 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2179 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2180 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ 2181 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) 2182 2183 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 2184 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2185 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2186 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2187 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2188 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2189 2190 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) 2191 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 2192 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 2193 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 2194 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 2195 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 2196 2197 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) 2198 2199 /* DPF == dynamic parity feature */ 2200 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 2201 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 2202 2203 #define GT_FREQUENCY_MULTIPLIER 50 2204 2205 #include "i915_trace.h" 2206 2207 extern const struct drm_ioctl_desc i915_ioctls[]; 2208 extern int i915_max_ioctl; 2209 2210 extern int i915_suspend(device_t kdev); 2211 extern int i915_resume(struct drm_device *dev); 2212 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 2213 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 2214 2215 /* i915_params.c */ 2216 struct i915_params { 2217 int modeset; 2218 int panel_ignore_lid; 2219 unsigned int powersave; 2220 int semaphores; 2221 unsigned int lvds_downclock; 2222 int lvds_channel_mode; 2223 int panel_use_ssc; 2224 int vbt_sdvo_panel_type; 2225 int enable_rc6; 2226 int enable_fbc; 2227 int enable_ppgtt; 2228 int enable_execlists; 2229 int enable_psr; 2230 unsigned int preliminary_hw_support; 2231 int disable_power_well; 2232 int enable_ips; 2233 int invert_brightness; 2234 int enable_cmd_parser; 2235 /* leave bools at the end to not create holes */ 2236 bool enable_hangcheck; 2237 bool fastboot; 2238 bool prefault_disable; 2239 int reset; 2240 bool disable_display; 2241 bool disable_vtd_wa; 2242 int use_mmio_flip; 2243 bool mmio_debug; 2244 }; 2245 extern struct i915_params i915 __read_mostly; 2246 2247 /* i915_dma.c */ 2248 void i915_update_dri1_breadcrumb(struct drm_device *dev); 2249 extern void i915_kernel_lost_context(struct drm_device * dev); 2250 extern int i915_driver_load(struct drm_device *, unsigned long flags); 2251 extern int i915_driver_unload(struct drm_device *); 2252 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); 2253 extern void i915_driver_lastclose(struct drm_device * dev); 2254 extern void i915_driver_preclose(struct drm_device *dev, 2255 struct drm_file *file); 2256 extern void i915_driver_postclose(struct drm_device *dev, 2257 struct drm_file *file); 2258 extern int i915_driver_device_is_agp(struct drm_device * dev); 2259 #ifdef CONFIG_COMPAT 2260 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2261 unsigned long arg); 2262 #endif 2263 extern int i915_emit_box(struct drm_device *dev, 2264 struct drm_clip_rect *box, 2265 int DR1, int DR4); 2266 extern int intel_gpu_reset(struct drm_device *dev); 2267 extern int i915_reset(struct drm_device *dev); 2268 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2269 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2270 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2271 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2272 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2273 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); 2274 2275 /* i915_irq.c */ 2276 void i915_queue_hangcheck(struct drm_device *dev); 2277 __printf(3, 4) 2278 void i915_handle_error(struct drm_device *dev, bool wedged, 2279 const char *fmt, ...); 2280 2281 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir, 2282 int new_delay); 2283 extern void intel_irq_init(struct drm_device *dev); 2284 extern void intel_hpd_init(struct drm_device *dev); 2285 2286 extern void intel_uncore_sanitize(struct drm_device *dev); 2287 extern void intel_uncore_early_sanitize(struct drm_device *dev, 2288 bool restore_forcewake); 2289 extern void intel_uncore_init(struct drm_device *dev); 2290 extern void intel_uncore_check_errors(struct drm_device *dev); 2291 extern void intel_uncore_fini(struct drm_device *dev); 2292 2293 void 2294 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 2295 u32 status_mask); 2296 2297 void 2298 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 2299 u32 status_mask); 2300 2301 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2302 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2303 2304 /* i915_gem.c */ 2305 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 2306 struct drm_file *file_priv); 2307 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 2308 struct drm_file *file_priv); 2309 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 2310 struct drm_file *file_priv); 2311 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2312 struct drm_file *file_priv); 2313 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 2314 struct drm_file *file_priv); 2315 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2316 struct drm_file *file_priv); 2317 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2318 struct drm_file *file_priv); 2319 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 2320 struct drm_file *file_priv); 2321 void i915_gem_execbuffer_move_to_active(struct list_head *vmas, 2322 struct intel_engine_cs *ring); 2323 void i915_gem_execbuffer_retire_commands(struct drm_device *dev, 2324 struct drm_file *file, 2325 struct intel_engine_cs *ring, 2326 struct drm_i915_gem_object *obj); 2327 int i915_gem_ringbuffer_submission(struct drm_device *dev, 2328 struct drm_file *file, 2329 struct intel_engine_cs *ring, 2330 struct intel_context *ctx, 2331 struct drm_i915_gem_execbuffer2 *args, 2332 struct list_head *vmas, 2333 struct drm_i915_gem_object *batch_obj, 2334 u64 exec_start, u32 flags); 2335 int i915_gem_execbuffer(struct drm_device *dev, void *data, 2336 struct drm_file *file_priv); 2337 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 2338 struct drm_file *file_priv); 2339 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 2340 struct drm_file *file_priv); 2341 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 2342 struct drm_file *file_priv); 2343 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2344 struct drm_file *file_priv); 2345 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2346 struct drm_file *file); 2347 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2348 struct drm_file *file); 2349 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2350 struct drm_file *file_priv); 2351 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2352 struct drm_file *file_priv); 2353 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 2354 struct drm_file *file_priv); 2355 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 2356 struct drm_file *file_priv); 2357 int i915_gem_set_tiling(struct drm_device *dev, void *data, 2358 struct drm_file *file_priv); 2359 int i915_gem_get_tiling(struct drm_device *dev, void *data, 2360 struct drm_file *file_priv); 2361 int i915_gem_init_userptr(struct drm_device *dev); 2362 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 2363 struct drm_file *file); 2364 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2365 struct drm_file *file_priv); 2366 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2367 struct drm_file *file_priv); 2368 void i915_gem_load(struct drm_device *dev); 2369 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, 2370 long target, 2371 unsigned flags); 2372 #define I915_SHRINK_PURGEABLE 0x1 2373 #define I915_SHRINK_UNBOUND 0x2 2374 #define I915_SHRINK_BOUND 0x4 2375 void *i915_gem_object_alloc(struct drm_device *dev); 2376 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2377 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2378 const struct drm_i915_gem_object_ops *ops); 2379 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2380 size_t size); 2381 void i915_init_vm(struct drm_i915_private *dev_priv, 2382 struct i915_address_space *vm); 2383 void i915_gem_free_object(struct drm_gem_object *obj); 2384 void i915_gem_vma_destroy(struct i915_vma *vma); 2385 2386 #define PIN_MAPPABLE 0x1 2387 #define PIN_NONBLOCK 0x2 2388 #define PIN_GLOBAL 0x4 2389 #define PIN_OFFSET_BIAS 0x8 2390 #define PIN_OFFSET_MASK (~4095) 2391 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 2392 struct i915_address_space *vm, 2393 uint32_t alignment, 2394 uint64_t flags); 2395 int __must_check i915_vma_unbind(struct i915_vma *vma); 2396 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2397 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2398 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2399 void i915_gem_lastclose(struct drm_device *dev); 2400 2401 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 2402 int *needs_clflush); 2403 2404 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2405 static inline struct vm_page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2406 { 2407 return obj->pages[n]; 2408 } 2409 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2410 { 2411 BUG_ON(obj->pages == NULL); 2412 obj->pages_pin_count++; 2413 } 2414 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2415 { 2416 BUG_ON(obj->pages_pin_count == 0); 2417 obj->pages_pin_count--; 2418 } 2419 2420 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2421 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2422 struct intel_engine_cs *to); 2423 void i915_vma_move_to_active(struct i915_vma *vma, 2424 struct intel_engine_cs *ring); 2425 int i915_gem_dumb_create(struct drm_file *file_priv, 2426 struct drm_device *dev, 2427 struct drm_mode_create_dumb *args); 2428 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2429 uint32_t handle, uint64_t *offset); 2430 /** 2431 * Returns true if seq1 is later than seq2. 2432 */ 2433 static inline bool 2434 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2435 { 2436 return (int32_t)(seq1 - seq2) >= 0; 2437 } 2438 2439 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2440 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2441 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 2442 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 2443 2444 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); 2445 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); 2446 2447 struct drm_i915_gem_request * 2448 i915_gem_find_active_request(struct intel_engine_cs *ring); 2449 2450 bool i915_gem_retire_requests(struct drm_device *dev); 2451 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); 2452 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2453 bool interruptible); 2454 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno); 2455 2456 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2457 { 2458 return unlikely(atomic_read(&error->reset_counter) 2459 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2460 } 2461 2462 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2463 { 2464 return atomic_read(&error->reset_counter) & I915_WEDGED; 2465 } 2466 2467 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2468 { 2469 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2470 } 2471 2472 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) 2473 { 2474 return dev_priv->gpu_error.stop_rings == 0 || 2475 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; 2476 } 2477 2478 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) 2479 { 2480 return dev_priv->gpu_error.stop_rings == 0 || 2481 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; 2482 } 2483 2484 void i915_gem_reset(struct drm_device *dev); 2485 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 2486 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 2487 int __must_check i915_gem_init(struct drm_device *dev); 2488 int i915_gem_init_rings(struct drm_device *dev); 2489 int __must_check i915_gem_init_hw(struct drm_device *dev); 2490 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); 2491 void i915_gem_init_swizzling(struct drm_device *dev); 2492 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 2493 int __must_check i915_gpu_idle(struct drm_device *dev); 2494 int __must_check i915_gem_suspend(struct drm_device *dev); 2495 int __i915_add_request(struct intel_engine_cs *ring, 2496 struct drm_file *file, 2497 struct drm_i915_gem_object *batch_obj, 2498 u32 *seqno); 2499 #define i915_add_request(ring, seqno) \ 2500 __i915_add_request(ring, NULL, NULL, seqno) 2501 int __must_check i915_wait_seqno(struct intel_engine_cs *ring, 2502 uint32_t seqno); 2503 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres); 2504 int __must_check 2505 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 2506 bool write); 2507 int __must_check 2508 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 2509 int __must_check 2510 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 2511 u32 alignment, 2512 struct intel_engine_cs *pipelined); 2513 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 2514 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 2515 int align); 2516 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 2517 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2518 2519 uint32_t 2520 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 2521 uint32_t 2522 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2523 int tiling_mode, bool fenced); 2524 2525 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2526 enum i915_cache_level cache_level); 2527 2528 #if 0 2529 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2530 struct dma_buf *dma_buf); 2531 2532 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 2533 struct drm_gem_object *gem_obj, int flags); 2534 #endif 2535 2536 void i915_gem_restore_fences(struct drm_device *dev); 2537 2538 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, 2539 struct i915_address_space *vm); 2540 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 2541 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 2542 struct i915_address_space *vm); 2543 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 2544 struct i915_address_space *vm); 2545 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 2546 struct i915_address_space *vm); 2547 struct i915_vma * 2548 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2549 struct i915_address_space *vm); 2550 2551 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); 2552 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { 2553 struct i915_vma *vma; 2554 list_for_each_entry(vma, &obj->vma_list, vma_link) 2555 if (vma->pin_count > 0) 2556 return true; 2557 return false; 2558 } 2559 2560 /* Some GGTT VM helpers */ 2561 #define i915_obj_to_ggtt(obj) \ 2562 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 2563 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2564 { 2565 struct i915_address_space *ggtt = 2566 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2567 return vm == ggtt; 2568 } 2569 2570 static inline struct i915_hw_ppgtt * 2571 i915_vm_to_ppgtt(struct i915_address_space *vm) 2572 { 2573 WARN_ON(i915_is_ggtt(vm)); 2574 2575 return container_of(vm, struct i915_hw_ppgtt, base); 2576 } 2577 2578 2579 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2580 { 2581 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj)); 2582 } 2583 2584 static inline unsigned long 2585 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) 2586 { 2587 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj)); 2588 } 2589 2590 static inline unsigned long 2591 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2592 { 2593 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); 2594 } 2595 2596 static inline int __must_check 2597 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2598 uint32_t alignment, 2599 unsigned flags) 2600 { 2601 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), 2602 alignment, flags | PIN_GLOBAL); 2603 } 2604 2605 static inline int 2606 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) 2607 { 2608 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); 2609 } 2610 2611 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); 2612 2613 /* i915_gem_context.c */ 2614 int __must_check i915_gem_context_init(struct drm_device *dev); 2615 void i915_gem_context_fini(struct drm_device *dev); 2616 void i915_gem_context_reset(struct drm_device *dev); 2617 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); 2618 int i915_gem_context_enable(struct drm_i915_private *dev_priv); 2619 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2620 int i915_switch_context(struct intel_engine_cs *ring, 2621 struct intel_context *to); 2622 struct intel_context * 2623 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 2624 void i915_gem_context_free(struct kref *ctx_ref); 2625 struct drm_i915_gem_object * 2626 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); 2627 static inline void i915_gem_context_reference(struct intel_context *ctx) 2628 { 2629 kref_get(&ctx->ref); 2630 } 2631 2632 static inline void i915_gem_context_unreference(struct intel_context *ctx) 2633 { 2634 kref_put(&ctx->ref, i915_gem_context_free); 2635 } 2636 2637 static inline bool i915_gem_context_is_default(const struct intel_context *c) 2638 { 2639 return c->user_handle == DEFAULT_CONTEXT_HANDLE; 2640 } 2641 2642 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2643 struct drm_file *file); 2644 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2645 struct drm_file *file); 2646 2647 /* i915_gem_evict.c */ 2648 int __must_check i915_gem_evict_something(struct drm_device *dev, 2649 struct i915_address_space *vm, 2650 int min_size, 2651 unsigned alignment, 2652 unsigned cache_level, 2653 unsigned long start, 2654 unsigned long end, 2655 unsigned flags); 2656 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 2657 int i915_gem_evict_everything(struct drm_device *dev); 2658 2659 /* belongs in i915_gem_gtt.h */ 2660 static inline void i915_gem_chipset_flush(struct drm_device *dev) 2661 { 2662 if (INTEL_INFO(dev)->gen < 6) 2663 intel_gtt_chipset_flush(); 2664 } 2665 2666 /* i915_gem_stolen.c */ 2667 int i915_gem_init_stolen(struct drm_device *dev); 2668 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); 2669 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 2670 void i915_gem_cleanup_stolen(struct drm_device *dev); 2671 struct drm_i915_gem_object * 2672 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 2673 struct drm_i915_gem_object * 2674 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 2675 u32 stolen_offset, 2676 u32 gtt_offset, 2677 u32 size); 2678 2679 /* i915_gem_tiling.c */ 2680 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2681 { 2682 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2683 2684 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2685 obj->tiling_mode != I915_TILING_NONE; 2686 } 2687 2688 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 2689 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 2690 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 2691 2692 /* i915_gem_debug.c */ 2693 #if WATCH_LISTS 2694 int i915_verify_lists(struct drm_device *dev); 2695 #else 2696 #define i915_verify_lists(dev) 0 2697 #endif 2698 2699 /* i915_debugfs.c */ 2700 int i915_debugfs_init(struct drm_minor *minor); 2701 void i915_debugfs_cleanup(struct drm_minor *minor); 2702 #ifdef CONFIG_DEBUG_FS 2703 void intel_display_crc_init(struct drm_device *dev); 2704 #else 2705 static inline void intel_display_crc_init(struct drm_device *dev) {} 2706 #endif 2707 2708 /* i915_gpu_error.c */ 2709 __printf(2, 3) 2710 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 2711 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 2712 const struct i915_error_state_file_priv *error); 2713 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 2714 struct drm_i915_private *i915, 2715 size_t count, loff_t pos); 2716 static inline void i915_error_state_buf_release( 2717 struct drm_i915_error_state_buf *eb) 2718 { 2719 kfree(eb->buf); 2720 } 2721 void i915_capture_error_state(struct drm_device *dev, bool wedge, 2722 const char *error_msg); 2723 void i915_error_state_get(struct drm_device *dev, 2724 struct i915_error_state_file_priv *error_priv); 2725 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 2726 void i915_destroy_error_state(struct drm_device *dev); 2727 2728 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 2729 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 2730 2731 /* i915_cmd_parser.c */ 2732 int i915_cmd_parser_get_version(void); 2733 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); 2734 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); 2735 bool i915_needs_cmd_parser(struct intel_engine_cs *ring); 2736 int i915_parse_cmds(struct intel_engine_cs *ring, 2737 struct drm_i915_gem_object *batch_obj, 2738 u32 batch_start_offset, 2739 bool is_master); 2740 2741 /* i915_suspend.c */ 2742 extern int i915_save_state(struct drm_device *dev); 2743 extern int i915_restore_state(struct drm_device *dev); 2744 2745 /* i915_ums.c */ 2746 void i915_save_display_reg(struct drm_device *dev); 2747 void i915_restore_display_reg(struct drm_device *dev); 2748 2749 /* i915_sysfs.c */ 2750 void i915_setup_sysfs(struct drm_device *dev_priv); 2751 void i915_teardown_sysfs(struct drm_device *dev_priv); 2752 2753 /* intel_i2c.c */ 2754 extern int intel_setup_gmbus(struct drm_device *dev); 2755 extern void intel_teardown_gmbus(struct drm_device *dev); 2756 static inline bool intel_gmbus_is_port_valid(unsigned port) 2757 { 2758 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 2759 } 2760 2761 extern struct device *intel_gmbus_get_adapter( 2762 struct drm_i915_private *dev_priv, unsigned port); 2763 extern void intel_gmbus_set_speed(struct device *adapter, int speed); 2764 extern void intel_gmbus_force_bit(struct device *adapter, bool force_bit); 2765 static inline bool intel_gmbus_is_forced_bit(struct device *adapter) 2766 { 2767 struct intel_iic_softc *sc; 2768 sc = device_get_softc(device_get_parent(adapter)); 2769 2770 return sc->force_bit_dev; 2771 } 2772 extern void intel_i2c_reset(struct drm_device *dev); 2773 2774 /* intel_opregion.c */ 2775 struct intel_encoder; 2776 #ifdef CONFIG_ACPI 2777 extern int intel_opregion_setup(struct drm_device *dev); 2778 extern void intel_opregion_init(struct drm_device *dev); 2779 extern void intel_opregion_fini(struct drm_device *dev); 2780 extern void intel_opregion_asle_intr(struct drm_device *dev); 2781 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 2782 bool enable); 2783 extern int intel_opregion_notify_adapter(struct drm_device *dev, 2784 pci_power_t state); 2785 #else 2786 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } 2787 static inline void intel_opregion_init(struct drm_device *dev) { return; } 2788 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 2789 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 2790 static inline int 2791 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 2792 { 2793 return 0; 2794 } 2795 static inline int 2796 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 2797 { 2798 return 0; 2799 } 2800 #endif 2801 2802 /* intel_acpi.c */ 2803 #ifdef CONFIG_ACPI 2804 extern void intel_register_dsm_handler(void); 2805 extern void intel_unregister_dsm_handler(void); 2806 #else 2807 static inline void intel_register_dsm_handler(void) { return; } 2808 static inline void intel_unregister_dsm_handler(void) { return; } 2809 #endif /* CONFIG_ACPI */ 2810 2811 /* modesetting */ 2812 extern void intel_modeset_init_hw(struct drm_device *dev); 2813 extern void intel_modeset_suspend_hw(struct drm_device *dev); 2814 extern void intel_modeset_init(struct drm_device *dev); 2815 extern void intel_modeset_gem_init(struct drm_device *dev); 2816 extern void intel_modeset_cleanup(struct drm_device *dev); 2817 extern void intel_connector_unregister(struct intel_connector *); 2818 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 2819 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 2820 bool force_restore); 2821 extern void i915_redisable_vga(struct drm_device *dev); 2822 extern void i915_redisable_vga_power_on(struct drm_device *dev); 2823 extern void gen8_fbc_sw_flush(struct drm_device *dev, u32 value); 2824 extern void intel_disable_fbc(struct drm_device *dev); 2825 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2826 extern void intel_init_pch_refclk(struct drm_device *dev); 2827 extern void gen6_set_rps(struct drm_device *dev, u8 val); 2828 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2829 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 2830 bool enable); 2831 extern void intel_detect_pch(struct drm_device *dev); 2832 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 2833 extern int intel_enable_rc6(const struct drm_device *dev); 2834 2835 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 2836 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2837 struct drm_file *file); 2838 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 2839 struct drm_file *file); 2840 2841 struct intel_device_info *i915_get_device_id(int device); 2842 2843 void intel_notify_mmio_flip(struct intel_engine_cs *ring); 2844 2845 /* overlay */ 2846 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2847 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 2848 struct intel_overlay_error_state *error); 2849 2850 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 2851 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2852 struct drm_device *dev, 2853 struct intel_display_error_state *error); 2854 2855 /* On SNB platform, before reading ring registers forcewake bit 2856 * must be set to prevent GT core from power down and stale values being 2857 * returned. 2858 */ 2859 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); 2860 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); 2861 void assert_force_wake_inactive(struct drm_i915_private *dev_priv); 2862 2863 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 2864 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 2865 2866 /* intel_sideband.c */ 2867 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 2868 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 2869 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 2870 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 2871 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2872 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 2873 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2874 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 2875 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2876 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 2877 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2878 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 2879 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2880 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg); 2881 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val); 2882 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 2883 enum intel_sbi_destination destination); 2884 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2885 enum intel_sbi_destination destination); 2886 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 2887 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2888 2889 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); 2890 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); 2891 2892 #define FORCEWAKE_RENDER (1 << 0) 2893 #define FORCEWAKE_MEDIA (1 << 1) 2894 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) 2895 2896 2897 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 2898 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 2899 2900 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 2901 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 2902 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 2903 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 2904 2905 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 2906 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 2907 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 2908 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 2909 2910 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 2911 * will be implemented using 2 32-bit writes in an arbitrary order with 2912 * an arbitrary delay between them. This can cause the hardware to 2913 * act upon the intermediate value, possibly leading to corruption and 2914 * machine death. You have been warned. 2915 */ 2916 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 2917 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 2918 2919 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 2920 u32 upper = I915_READ(upper_reg); \ 2921 u32 lower = I915_READ(lower_reg); \ 2922 u32 tmp = I915_READ(upper_reg); \ 2923 if (upper != tmp) { \ 2924 upper = tmp; \ 2925 lower = I915_READ(lower_reg); \ 2926 WARN_ON(I915_READ(upper_reg) != upper); \ 2927 } \ 2928 (u64)upper << 32 | lower; }) 2929 2930 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 2931 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 2932 2933 /* "Broadcast RGB" property */ 2934 #define INTEL_BROADCAST_RGB_AUTO 0 2935 #define INTEL_BROADCAST_RGB_FULL 1 2936 #define INTEL_BROADCAST_RGB_LIMITED 2 2937 2938 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 2939 { 2940 if (IS_VALLEYVIEW(dev)) 2941 return VLV_VGACNTRL; 2942 else if (INTEL_INFO(dev)->gen >= 5) 2943 return CPU_VGACNTRL; 2944 else 2945 return VGACNTRL; 2946 } 2947 2948 static inline void __user *to_user_ptr(u64 address) 2949 { 2950 return (void __user *)(uintptr_t)address; 2951 } 2952 2953 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 2954 { 2955 unsigned long j = msecs_to_jiffies(m); 2956 2957 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2958 } 2959 2960 static inline unsigned long 2961 timespec_to_jiffies_timeout(const struct timespec *value) 2962 { 2963 unsigned long j = timespec_to_jiffies(value); 2964 2965 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2966 } 2967 2968 /* 2969 * If you need to wait X milliseconds between events A and B, but event B 2970 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 2971 * when event A happened, then just before event B you call this function and 2972 * pass the timestamp as the first argument, and X as the second argument. 2973 */ 2974 static inline void 2975 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 2976 { 2977 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 2978 2979 /* 2980 * Don't re-read the value of "jiffies" every time since it may change 2981 * behind our back and break the math. 2982 */ 2983 tmp_jiffies = jiffies; 2984 target_jiffies = timestamp_jiffies + 2985 msecs_to_jiffies_timeout(to_wait_ms); 2986 2987 if (time_after(target_jiffies, tmp_jiffies)) { 2988 remaining_jiffies = target_jiffies - tmp_jiffies; 2989 2990 #if 0 2991 while (remaining_jiffies) 2992 remaining_jiffies = 2993 schedule_timeout_uninterruptible(remaining_jiffies); 2994 #else 2995 msleep(jiffies_to_msecs(remaining_jiffies)); 2996 #endif 2997 } 2998 } 2999 3000 #endif 3001