1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 29 */ 30 31 #ifndef _I915_DRV_H_ 32 #define _I915_DRV_H_ 33 34 #include <sys/eventhandler.h> 35 36 #include <dev/agp/agp_i810.h> 37 #include "i915_reg.h" 38 #include "intel_bios.h" 39 #include "intel_ringbuffer.h" 40 41 /* General customization: 42 */ 43 44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 45 46 #define DRIVER_NAME "i915" 47 #define DRIVER_DESC "Intel Graphics" 48 #define DRIVER_DATE "20080730" 49 50 MALLOC_DECLARE(DRM_I915_GEM); 51 52 enum i915_pipe { 53 PIPE_A = 0, 54 PIPE_B, 55 PIPE_C, 56 I915_MAX_PIPES 57 }; 58 #define pipe_name(p) ((p) + 'A') 59 #define I915_NUM_PIPE 2 60 61 enum transcoder { 62 TRANSCODER_A = 0, 63 TRANSCODER_B, 64 TRANSCODER_C, 65 TRANSCODER_EDP = 0xF, 66 }; 67 #define transcoder_name(t) ((t) + 'A') 68 69 enum plane { 70 PLANE_A = 0, 71 PLANE_B, 72 PLANE_C, 73 }; 74 #define plane_name(p) ((p) + 'A') 75 76 enum port { 77 PORT_A = 0, 78 PORT_B, 79 PORT_C, 80 PORT_D, 81 PORT_E, 82 I915_MAX_PORTS 83 }; 84 #define port_name(p) ((p) + 'A') 85 86 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 87 88 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 89 90 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 91 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 92 if ((intel_encoder)->base.crtc == (__crtc)) 93 94 struct intel_pch_pll { 95 int refcount; /* count of number of CRTCs sharing this PLL */ 96 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 97 bool on; /* is the PLL actually active? Disabled during modeset */ 98 int pll_reg; 99 int fp0_reg; 100 int fp1_reg; 101 }; 102 #define I915_NUM_PLLS 2 103 104 struct intel_ddi_plls { 105 int spll_refcount; 106 int wrpll1_refcount; 107 int wrpll2_refcount; 108 }; 109 110 /* Interface history: 111 * 112 * 1.1: Original. 113 * 1.2: Add Power Management 114 * 1.3: Add vblank support 115 * 1.4: Fix cmdbuffer path, add heap destroy 116 * 1.5: Add vblank pipe configuration 117 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 118 * - Support vertical blank on secondary display pipe 119 */ 120 #define DRIVER_MAJOR 1 121 #define DRIVER_MINOR 6 122 #define DRIVER_PATCHLEVEL 0 123 124 #define WATCH_COHERENCY 0 125 #define WATCH_LISTS 0 126 #define WATCH_GTT 0 127 128 #define I915_GEM_PHYS_CURSOR_0 1 129 #define I915_GEM_PHYS_CURSOR_1 2 130 #define I915_GEM_PHYS_OVERLAY_REGS 3 131 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 132 133 struct drm_i915_gem_phys_object { 134 int id; 135 drm_dma_handle_t *handle; 136 struct drm_i915_gem_object *cur_obj; 137 }; 138 139 struct opregion_header; 140 struct opregion_acpi; 141 struct opregion_swsci; 142 struct opregion_asle; 143 struct drm_i915_private; 144 145 struct intel_opregion { 146 struct opregion_header __iomem *header; 147 struct opregion_acpi __iomem *acpi; 148 struct opregion_swsci __iomem *swsci; 149 struct opregion_asle __iomem *asle; 150 void __iomem *vbt; 151 u32 __iomem *lid_state; 152 }; 153 #define OPREGION_SIZE (8*1024) 154 155 struct intel_overlay; 156 struct intel_overlay_error_state; 157 158 struct drm_i915_master_private { 159 drm_local_map_t *sarea; 160 struct _drm_i915_sarea *sarea_priv; 161 }; 162 #define I915_FENCE_REG_NONE -1 163 #define I915_MAX_NUM_FENCES 16 164 /* 16 fences + sign bit for FENCE_REG_NONE */ 165 #define I915_MAX_NUM_FENCE_BITS 5 166 167 struct drm_i915_fence_reg { 168 struct list_head lru_list; 169 struct drm_i915_gem_object *obj; 170 uint32_t setup_seqno; 171 int pin_count; 172 }; 173 174 struct sdvo_device_mapping { 175 u8 initialized; 176 u8 dvo_port; 177 u8 slave_addr; 178 u8 dvo_wiring; 179 u8 i2c_pin; 180 u8 ddc_pin; 181 }; 182 183 struct drm_i915_error_state { 184 u32 eir; 185 u32 pgtbl_er; 186 u32 pipestat[I915_MAX_PIPES]; 187 u32 tail[I915_NUM_RINGS]; 188 u32 head[I915_NUM_RINGS]; 189 u32 ipeir[I915_NUM_RINGS]; 190 u32 ipehr[I915_NUM_RINGS]; 191 u32 instdone[I915_NUM_RINGS]; 192 u32 acthd[I915_NUM_RINGS]; 193 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 194 /* our own tracking of ring head and tail */ 195 u32 cpu_ring_head[I915_NUM_RINGS]; 196 u32 cpu_ring_tail[I915_NUM_RINGS]; 197 u32 error; /* gen6+ */ 198 u32 instpm[I915_NUM_RINGS]; 199 u32 instps[I915_NUM_RINGS]; 200 u32 instdone1; 201 u32 seqno[I915_NUM_RINGS]; 202 u64 bbaddr; 203 u32 fault_reg[I915_NUM_RINGS]; 204 u32 done_reg; 205 u32 faddr[I915_NUM_RINGS]; 206 u64 fence[I915_MAX_NUM_FENCES]; 207 struct timeval time; 208 struct drm_i915_error_ring { 209 struct drm_i915_error_object { 210 int page_count; 211 u32 gtt_offset; 212 u32 *pages[0]; 213 } *ringbuffer, *batchbuffer; 214 struct drm_i915_error_request { 215 long jiffies; 216 u32 seqno; 217 u32 tail; 218 } *requests; 219 int num_requests; 220 } ring[I915_NUM_RINGS]; 221 struct drm_i915_error_buffer { 222 u32 size; 223 u32 name; 224 u32 seqno; 225 u32 gtt_offset; 226 u32 read_domains; 227 u32 write_domain; 228 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 229 s32 pinned:2; 230 u32 tiling:2; 231 u32 dirty:1; 232 u32 purgeable:1; 233 s32 ring:4; 234 u32 cache_level:2; 235 } *active_bo, *pinned_bo; 236 u32 active_bo_count, pinned_bo_count; 237 struct intel_overlay_error_state *overlay; 238 struct intel_display_error_state *display; 239 }; 240 241 struct drm_i915_display_funcs { 242 void (*dpms)(struct drm_crtc *crtc, int mode); 243 bool (*fbc_enabled)(struct drm_device *dev); 244 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 245 void (*disable_fbc)(struct drm_device *dev); 246 int (*get_display_clock_speed)(struct drm_device *dev); 247 int (*get_fifo_size)(struct drm_device *dev, int plane); 248 void (*update_wm)(struct drm_device *dev); 249 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 250 uint32_t sprite_width, int pixel_size); 251 int (*crtc_mode_set)(struct drm_crtc *crtc, 252 struct drm_display_mode *mode, 253 struct drm_display_mode *adjusted_mode, 254 int x, int y, 255 struct drm_framebuffer *old_fb); 256 void (*write_eld)(struct drm_connector *connector, 257 struct drm_crtc *crtc); 258 void (*fdi_link_train)(struct drm_crtc *crtc); 259 void (*init_clock_gating)(struct drm_device *dev); 260 void (*init_pch_clock_gating)(struct drm_device *dev); 261 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 262 struct drm_framebuffer *fb, 263 struct drm_i915_gem_object *obj); 264 void (*force_wake_get)(struct drm_i915_private *dev_priv); 265 void (*force_wake_put)(struct drm_i915_private *dev_priv); 266 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 267 int x, int y); 268 /* clock updates for mode set */ 269 /* cursor updates */ 270 /* render clock increase/decrease */ 271 /* display clock increase/decrease */ 272 /* pll clock increase/decrease */ 273 }; 274 275 struct drm_i915_gt_funcs { 276 void (*force_wake_get)(struct drm_i915_private *dev_priv); 277 void (*force_wake_put)(struct drm_i915_private *dev_priv); 278 }; 279 280 #define DEV_INFO_FLAGS \ 281 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ 282 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ 283 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ 284 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ 285 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ 286 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ 287 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ 288 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ 289 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ 290 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ 291 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ 292 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ 293 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ 294 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ 295 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ 296 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ 297 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ 298 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ 299 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ 300 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ 301 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ 302 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ 303 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ 304 DEV_INFO_FLAG(has_llc) 305 306 struct intel_device_info { 307 u8 gen; 308 u8 is_mobile:1; 309 u8 is_i85x:1; 310 u8 is_i915g:1; 311 u8 is_i945gm:1; 312 u8 is_g33:1; 313 u8 need_gfx_hws:1; 314 u8 is_g4x:1; 315 u8 is_pineview:1; 316 u8 is_broadwater:1; 317 u8 is_crestline:1; 318 u8 is_ivybridge:1; 319 u8 is_valleyview:1; 320 u8 has_force_wake:1; 321 u8 is_haswell:1; 322 u8 has_fbc:1; 323 u8 has_pipe_cxsr:1; 324 u8 has_hotplug:1; 325 u8 cursor_needs_physical:1; 326 u8 has_overlay:1; 327 u8 overlay_needs_physical:1; 328 u8 supports_tv:1; 329 u8 has_bsd_ring:1; 330 u8 has_blt_ring:1; 331 u8 has_llc:1; 332 }; 333 334 #define I915_PPGTT_PD_ENTRIES 512 335 #define I915_PPGTT_PT_ENTRIES 1024 336 struct i915_hw_ppgtt { 337 unsigned num_pd_entries; 338 vm_page_t *pt_pages; 339 uint32_t pd_offset; 340 vm_paddr_t *pt_dma_addr; 341 vm_paddr_t scratch_page_dma_addr; 342 }; 343 344 enum no_fbc_reason { 345 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 346 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 347 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 348 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 349 FBC_BAD_PLANE, /* fbc not supported on plane */ 350 FBC_NOT_TILED, /* buffer not tiled */ 351 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 352 FBC_MODULE_PARAM, 353 }; 354 355 /* defined intel_pm.c */ 356 extern struct lock mchdev_lock; 357 358 struct mem_block { 359 struct mem_block *next; 360 struct mem_block *prev; 361 int start; 362 int size; 363 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 364 }; 365 366 struct opregion_header; 367 struct opregion_acpi; 368 struct opregion_swsci; 369 struct opregion_asle; 370 371 #define I915_FENCE_REG_NONE -1 372 #define I915_MAX_NUM_FENCES 16 373 /* 16 fences + sign bit for FENCE_REG_NONE */ 374 #define I915_MAX_NUM_FENCE_BITS 5 375 376 enum intel_pch { 377 PCH_IBX, /* Ibexpeak PCH */ 378 PCH_CPT, /* Cougarpoint PCH */ 379 }; 380 381 #define QUIRK_PIPEA_FORCE (1<<0) 382 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 383 384 struct intel_fbdev; 385 struct intel_fbc_work; 386 387 typedef struct drm_i915_private { 388 struct drm_device *dev; 389 390 device_t *gmbus_bridge; 391 device_t *bbbus_bridge; 392 device_t *gmbus; 393 device_t *bbbus; 394 /** gmbus_sx protects against concurrent usage of the single hw gmbus 395 * controller on different i2c buses. */ 396 struct lock gmbus_lock; 397 398 int has_gem; 399 int relative_constants_mode; 400 401 drm_local_map_t *sarea; 402 drm_local_map_t *mmio_map; 403 404 /** gt_fifo_count and the subsequent register write are synchronized 405 * with dev->struct_mutex. */ 406 unsigned gt_fifo_count; 407 /** forcewake_count is protected by gt_lock */ 408 unsigned forcewake_count; 409 /** gt_lock is also taken in irq contexts. */ 410 struct lock gt_lock; 411 412 drm_i915_sarea_t *sarea_priv; 413 struct intel_ring_buffer ring[I915_NUM_RINGS]; 414 uint32_t next_seqno; 415 416 drm_dma_handle_t *status_page_dmah; 417 void *hw_status_page; 418 dma_addr_t dma_status_page; 419 uint32_t counter; 420 unsigned int status_gfx_addr; 421 drm_local_map_t hws_map; 422 struct drm_gem_object *hws_obj; 423 424 struct drm_i915_gem_object *pwrctx; 425 struct drm_i915_gem_object *renderctx; 426 427 unsigned int cpp; 428 int back_offset; 429 int front_offset; 430 int current_page; 431 int page_flipping; 432 433 atomic_t irq_received; 434 u32 trace_irq_seqno; 435 436 /** Cached value of IER to avoid reads in updating the bitfield */ 437 u32 pipestat[2]; 438 u32 irq_mask; 439 u32 gt_irq_mask; 440 u32 pch_irq_mask; 441 struct lock irq_lock; 442 443 u32 hotplug_supported_mask; 444 445 int tex_lru_log_granularity; 446 int allow_batchbuffer; 447 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 448 int vblank_pipe; 449 450 int num_pipe; 451 int num_pch_pll; 452 453 /* For hangcheck timer */ 454 #define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 455 int hangcheck_count; 456 uint32_t last_acthd; 457 uint32_t last_acthd_bsd; 458 uint32_t last_acthd_blt; 459 uint32_t last_instdone; 460 uint32_t last_instdone1; 461 462 struct intel_opregion opregion; 463 464 465 /* overlay */ 466 struct intel_overlay *overlay; 467 bool sprite_scaling_enabled; 468 469 /* LVDS info */ 470 int backlight_level; /* restore backlight to this value */ 471 bool backlight_enabled; 472 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 473 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 474 475 /* Feature bits from the VBIOS */ 476 unsigned int int_tv_support:1; 477 unsigned int lvds_dither:1; 478 unsigned int lvds_vbt:1; 479 unsigned int int_crt_support:1; 480 unsigned int lvds_use_ssc:1; 481 unsigned int display_clock_mode:1; 482 int lvds_ssc_freq; 483 struct { 484 int rate; 485 int lanes; 486 int preemphasis; 487 int vswing; 488 489 bool initialized; 490 bool support; 491 int bpp; 492 struct edp_power_seq pps; 493 } edp; 494 bool no_aux_handshake; 495 496 int crt_ddc_pin; 497 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 498 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 499 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 500 501 /* PCH chipset type */ 502 enum intel_pch pch_type; 503 504 /* Display functions */ 505 struct drm_i915_display_funcs display; 506 507 unsigned long quirks; 508 509 /* Register state */ 510 bool modeset_on_lid; 511 u8 saveLBB; 512 u32 saveDSPACNTR; 513 u32 saveDSPBCNTR; 514 u32 saveDSPARB; 515 u32 saveHWS; 516 u32 savePIPEACONF; 517 u32 savePIPEBCONF; 518 u32 savePIPEASRC; 519 u32 savePIPEBSRC; 520 u32 saveFPA0; 521 u32 saveFPA1; 522 u32 saveDPLL_A; 523 u32 saveDPLL_A_MD; 524 u32 saveHTOTAL_A; 525 u32 saveHBLANK_A; 526 u32 saveHSYNC_A; 527 u32 saveVTOTAL_A; 528 u32 saveVBLANK_A; 529 u32 saveVSYNC_A; 530 u32 saveBCLRPAT_A; 531 u32 saveTRANSACONF; 532 u32 saveTRANS_HTOTAL_A; 533 u32 saveTRANS_HBLANK_A; 534 u32 saveTRANS_HSYNC_A; 535 u32 saveTRANS_VTOTAL_A; 536 u32 saveTRANS_VBLANK_A; 537 u32 saveTRANS_VSYNC_A; 538 u32 savePIPEASTAT; 539 u32 saveDSPASTRIDE; 540 u32 saveDSPASIZE; 541 u32 saveDSPAPOS; 542 u32 saveDSPAADDR; 543 u32 saveDSPASURF; 544 u32 saveDSPATILEOFF; 545 u32 savePFIT_PGM_RATIOS; 546 u32 saveBLC_HIST_CTL; 547 u32 saveBLC_PWM_CTL; 548 u32 saveBLC_PWM_CTL2; 549 u32 saveBLC_CPU_PWM_CTL; 550 u32 saveBLC_CPU_PWM_CTL2; 551 u32 saveFPB0; 552 u32 saveFPB1; 553 u32 saveDPLL_B; 554 u32 saveDPLL_B_MD; 555 u32 saveHTOTAL_B; 556 u32 saveHBLANK_B; 557 u32 saveHSYNC_B; 558 u32 saveVTOTAL_B; 559 u32 saveVBLANK_B; 560 u32 saveVSYNC_B; 561 u32 saveBCLRPAT_B; 562 u32 saveTRANSBCONF; 563 u32 saveTRANS_HTOTAL_B; 564 u32 saveTRANS_HBLANK_B; 565 u32 saveTRANS_HSYNC_B; 566 u32 saveTRANS_VTOTAL_B; 567 u32 saveTRANS_VBLANK_B; 568 u32 saveTRANS_VSYNC_B; 569 u32 savePIPEBSTAT; 570 u32 saveDSPBSTRIDE; 571 u32 saveDSPBSIZE; 572 u32 saveDSPBPOS; 573 u32 saveDSPBADDR; 574 u32 saveDSPBSURF; 575 u32 saveDSPBTILEOFF; 576 u32 saveVGA0; 577 u32 saveVGA1; 578 u32 saveVGA_PD; 579 u32 saveVGACNTRL; 580 u32 saveADPA; 581 u32 saveLVDS; 582 u32 savePP_ON_DELAYS; 583 u32 savePP_OFF_DELAYS; 584 u32 saveDVOA; 585 u32 saveDVOB; 586 u32 saveDVOC; 587 u32 savePP_ON; 588 u32 savePP_OFF; 589 u32 savePP_CONTROL; 590 u32 savePP_DIVISOR; 591 u32 savePFIT_CONTROL; 592 u32 save_palette_a[256]; 593 u32 save_palette_b[256]; 594 u32 saveDPFC_CB_BASE; 595 u32 saveFBC_CFB_BASE; 596 u32 saveFBC_LL_BASE; 597 u32 saveFBC_CONTROL; 598 u32 saveFBC_CONTROL2; 599 u32 saveIER; 600 u32 saveIIR; 601 u32 saveIMR; 602 u32 saveDEIER; 603 u32 saveDEIMR; 604 u32 saveGTIER; 605 u32 saveGTIMR; 606 u32 saveFDI_RXA_IMR; 607 u32 saveFDI_RXB_IMR; 608 u32 saveCACHE_MODE_0; 609 u32 saveMI_ARB_STATE; 610 u32 saveSWF0[16]; 611 u32 saveSWF1[16]; 612 u32 saveSWF2[3]; 613 u8 saveMSR; 614 u8 saveSR[8]; 615 u8 saveGR[25]; 616 u8 saveAR_INDEX; 617 u8 saveAR[21]; 618 u8 saveDACMASK; 619 u8 saveCR[37]; 620 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 621 u32 saveCURACNTR; 622 u32 saveCURAPOS; 623 u32 saveCURABASE; 624 u32 saveCURBCNTR; 625 u32 saveCURBPOS; 626 u32 saveCURBBASE; 627 u32 saveCURSIZE; 628 u32 saveDP_B; 629 u32 saveDP_C; 630 u32 saveDP_D; 631 u32 savePIPEA_GMCH_DATA_M; 632 u32 savePIPEB_GMCH_DATA_M; 633 u32 savePIPEA_GMCH_DATA_N; 634 u32 savePIPEB_GMCH_DATA_N; 635 u32 savePIPEA_DP_LINK_M; 636 u32 savePIPEB_DP_LINK_M; 637 u32 savePIPEA_DP_LINK_N; 638 u32 savePIPEB_DP_LINK_N; 639 u32 saveFDI_RXA_CTL; 640 u32 saveFDI_TXA_CTL; 641 u32 saveFDI_RXB_CTL; 642 u32 saveFDI_TXB_CTL; 643 u32 savePFA_CTL_1; 644 u32 savePFB_CTL_1; 645 u32 savePFA_WIN_SZ; 646 u32 savePFB_WIN_SZ; 647 u32 savePFA_WIN_POS; 648 u32 savePFB_WIN_POS; 649 u32 savePCH_DREF_CONTROL; 650 u32 saveDISP_ARB_CTL; 651 u32 savePIPEA_DATA_M1; 652 u32 savePIPEA_DATA_N1; 653 u32 savePIPEA_LINK_M1; 654 u32 savePIPEA_LINK_N1; 655 u32 savePIPEB_DATA_M1; 656 u32 savePIPEB_DATA_N1; 657 u32 savePIPEB_LINK_M1; 658 u32 savePIPEB_LINK_N1; 659 u32 saveMCHBAR_RENDER_STANDBY; 660 u32 savePCH_PORT_HOTPLUG; 661 662 struct { 663 /** Bridge to intel-gtt-ko */ 664 const struct intel_gtt *gtt; 665 /** Memory allocator for GTT stolen memory */ 666 struct drm_mm stolen; 667 /** Memory allocator for GTT */ 668 struct drm_mm gtt_space; 669 /** List of all objects in gtt_space. Used to restore gtt 670 * mappings on resume */ 671 struct list_head gtt_list; 672 673 /** Usable portion of the GTT for GEM */ 674 unsigned long gtt_start; 675 unsigned long gtt_mappable_end; 676 unsigned long gtt_end; 677 678 /** PPGTT used for aliasing the PPGTT with the GTT */ 679 struct i915_hw_ppgtt *aliasing_ppgtt; 680 681 /** 682 * List of objects currently involved in rendering from the 683 * ringbuffer. 684 * 685 * Includes buffers having the contents of their GPU caches 686 * flushed, not necessarily primitives. last_rendering_seqno 687 * represents when the rendering involved will be completed. 688 * 689 * A reference is held on the buffer while on this list. 690 */ 691 struct list_head active_list; 692 693 /** 694 * List of objects which are not in the ringbuffer but which 695 * still have a write_domain which needs to be flushed before 696 * unbinding. 697 * 698 * A reference is held on the buffer while on this list. 699 */ 700 struct list_head flushing_list; 701 702 /** 703 * LRU list of objects which are not in the ringbuffer and 704 * are ready to unbind, but are still in the GTT. 705 * 706 * last_rendering_seqno is 0 while an object is in this list. 707 * 708 * A reference is not held on the buffer while on this list, 709 * as merely being GTT-bound shouldn't prevent its being 710 * freed, and we'll pull it off the list in the free path. 711 */ 712 struct list_head inactive_list; 713 714 /** 715 * LRU list of objects which are not in the ringbuffer but 716 * are still pinned in the GTT. 717 */ 718 struct list_head pinned_list; 719 720 /** LRU list of objects with fence regs on them. */ 721 struct list_head fence_list; 722 723 /** 724 * List of objects currently pending being freed. 725 * 726 * These objects are no longer in use, but due to a signal 727 * we were prevented from freeing them at the appointed time. 728 */ 729 struct list_head deferred_free_list; 730 731 /** 732 * We leave the user IRQ off as much as possible, 733 * but this means that requests will finish and never 734 * be retired once the system goes idle. Set a timer to 735 * fire periodically while the ring is running. When it 736 * fires, go retire requests. 737 */ 738 struct timeout_task retire_task; 739 740 /** 741 * Are we in a non-interruptible section of code like 742 * modesetting? 743 */ 744 bool interruptible; 745 746 uint32_t next_gem_seqno; 747 748 /** 749 * Waiting sequence number, if any 750 */ 751 uint32_t waiting_gem_seqno; 752 753 /** 754 * Last seq seen at irq time 755 */ 756 uint32_t irq_gem_seqno; 757 758 /** 759 * Flag if the X Server, and thus DRM, is not currently in 760 * control of the device. 761 * 762 * This is set between LeaveVT and EnterVT. It needs to be 763 * replaced with a semaphore. It also needs to be 764 * transitioned away from for kernel modesetting. 765 */ 766 int suspended; 767 768 /** 769 * Flag if the hardware appears to be wedged. 770 * 771 * This is set when attempts to idle the device timeout. 772 * It prevents command submission from occuring and makes 773 * every pending request fail 774 */ 775 atomic_t wedged; 776 777 /** Bit 6 swizzling required for X tiling */ 778 uint32_t bit_6_swizzle_x; 779 /** Bit 6 swizzling required for Y tiling */ 780 uint32_t bit_6_swizzle_y; 781 782 /* storage for physical objects */ 783 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 784 785 /* accounting, useful for userland debugging */ 786 size_t gtt_total; 787 size_t mappable_gtt_total; 788 size_t object_memory; 789 u32 object_count; 790 791 eventhandler_tag i915_lowmem; 792 } mm; 793 794 const struct intel_device_info *info; 795 796 struct sdvo_device_mapping sdvo_mappings[2]; 797 /* indicate whether the LVDS_BORDER should be enabled or not */ 798 unsigned int lvds_border_bits; 799 /* Panel fitter placement and size for Ironlake+ */ 800 u32 pch_pf_pos, pch_pf_size; 801 802 struct drm_crtc *plane_to_crtc_mapping[3]; 803 struct drm_crtc *pipe_to_crtc_mapping[3]; 804 /* wait_queue_head_t pending_flip_queue; XXXKIB */ 805 bool flip_pending_is_done; 806 807 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 808 struct intel_ddi_plls ddi_plls; 809 810 /* Reclocking support */ 811 bool render_reclock_avail; 812 bool lvds_downclock_avail; 813 /* indicates the reduced downclock for LVDS*/ 814 int lvds_downclock; 815 struct task idle_task; 816 struct callout idle_callout; 817 bool busy; 818 u16 orig_clock; 819 int child_dev_num; 820 struct child_device_config *child_dev; 821 struct drm_connector *int_lvds_connector; 822 struct drm_connector *int_edp_connector; 823 824 device_t bridge_dev; 825 bool mchbar_need_disable; 826 int mch_res_rid; 827 struct resource *mch_res; 828 829 struct lock rps_lock; 830 u32 pm_iir; 831 struct task rps_task; 832 833 u8 cur_delay; 834 u8 min_delay; 835 u8 max_delay; 836 u8 fmax; 837 u8 fstart; 838 839 u64 last_count1; 840 unsigned long last_time1; 841 unsigned long chipset_power; 842 u64 last_count2; 843 struct timespec last_time2; 844 unsigned long gfx_power; 845 int c_m; 846 int r_t; 847 u8 corr; 848 struct lock *mchdev_lock; 849 850 enum no_fbc_reason no_fbc_reason; 851 852 unsigned long cfb_size; 853 unsigned int cfb_fb; 854 int cfb_plane; 855 int cfb_y; 856 struct intel_fbc_work *fbc_work; 857 858 unsigned int fsb_freq, mem_freq, is_ddr3; 859 860 struct taskqueue *tq; 861 struct task error_task; 862 struct task hotplug_task; 863 int error_completion; 864 struct lock error_completion_lock; 865 struct drm_i915_error_state *first_error; 866 struct lock error_lock; 867 struct callout hangcheck_timer; 868 869 unsigned long last_gpu_reset; 870 871 struct intel_fbdev *fbdev; 872 873 struct drm_property *broadcast_rgb_property; 874 struct drm_property *force_audio_property; 875 } drm_i915_private_t; 876 877 /* Iterate over initialised rings */ 878 #define for_each_ring(ring__, dev_priv__, i__) \ 879 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 880 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 881 882 enum hdmi_force_audio { 883 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 884 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 885 HDMI_AUDIO_AUTO, /* trust EDID */ 886 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 887 }; 888 889 enum i915_cache_level { 890 I915_CACHE_NONE, 891 I915_CACHE_LLC, 892 I915_CACHE_LLC_MLC, /* gen6+ */ 893 }; 894 895 enum intel_chip_family { 896 CHIP_I8XX = 0x01, 897 CHIP_I9XX = 0x02, 898 CHIP_I915 = 0x04, 899 CHIP_I965 = 0x08, 900 }; 901 902 /** driver private structure attached to each drm_gem_object */ 903 struct drm_i915_gem_object { 904 struct drm_gem_object base; 905 906 /** Current space allocated to this object in the GTT, if any. */ 907 struct drm_mm_node *gtt_space; 908 struct list_head gtt_list; 909 /** This object's place on the active/flushing/inactive lists */ 910 struct list_head ring_list; 911 struct list_head mm_list; 912 /** This object's place on GPU write list */ 913 struct list_head gpu_write_list; 914 /** This object's place in the batchbuffer or on the eviction list */ 915 struct list_head exec_list; 916 917 /** 918 * This is set if the object is on the active or flushing lists 919 * (has pending rendering), and is not set if it's on inactive (ready 920 * to be unbound). 921 */ 922 unsigned int active:1; 923 924 /** 925 * This is set if the object has been written to since last bound 926 * to the GTT 927 */ 928 unsigned int dirty:1; 929 930 /** 931 * This is set if the object has been written to since the last 932 * GPU flush. 933 */ 934 unsigned int pending_gpu_write:1; 935 936 /** 937 * Fence register bits (if any) for this object. Will be set 938 * as needed when mapped into the GTT. 939 * Protected by dev->struct_mutex. 940 */ 941 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 942 943 /** 944 * Advice: are the backing pages purgeable? 945 */ 946 unsigned int madv:2; 947 948 /** 949 * Current tiling mode for the object. 950 */ 951 unsigned int tiling_mode:2; 952 unsigned int tiling_changed:1; 953 954 /** How many users have pinned this object in GTT space. The following 955 * users can each hold at most one reference: pwrite/pread, pin_ioctl 956 * (via user_pin_count), execbuffer (objects are not allowed multiple 957 * times for the same batchbuffer), and the framebuffer code. When 958 * switching/pageflipping, the framebuffer code has at most two buffers 959 * pinned per crtc. 960 * 961 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 962 * bits with absolutely no headroom. So use 4 bits. */ 963 unsigned int pin_count:4; 964 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 965 966 /** 967 * Is the object at the current location in the gtt mappable and 968 * fenceable? Used to avoid costly recalculations. 969 */ 970 unsigned int map_and_fenceable:1; 971 972 /** 973 * Whether the current gtt mapping needs to be mappable (and isn't just 974 * mappable by accident). Track pin and fault separate for a more 975 * accurate mappable working set. 976 */ 977 unsigned int fault_mappable:1; 978 unsigned int pin_mappable:1; 979 980 /* 981 * Is the GPU currently using a fence to access this buffer, 982 */ 983 unsigned int pending_fenced_gpu_access:1; 984 unsigned int fenced_gpu_access:1; 985 986 unsigned int cache_level:2; 987 988 unsigned int has_aliasing_ppgtt_mapping:1; 989 990 vm_page_t *pages; 991 992 /** 993 * DMAR support 994 */ 995 struct sglist *sg_list; 996 997 /** 998 * Used for performing relocations during execbuffer insertion. 999 */ 1000 struct hlist_node exec_node; 1001 unsigned long exec_handle; 1002 struct drm_i915_gem_exec_object2 *exec_entry; 1003 1004 /** 1005 * Current offset of the object in GTT space. 1006 * 1007 * This is the same as gtt_space->start 1008 */ 1009 uint32_t gtt_offset; 1010 1011 /** Breadcrumb of last rendering to the buffer. */ 1012 uint32_t last_rendering_seqno; 1013 struct intel_ring_buffer *ring; 1014 1015 /** Breadcrumb of last fenced GPU access to the buffer. */ 1016 uint32_t last_fenced_seqno; 1017 struct intel_ring_buffer *last_fenced_ring; 1018 1019 /** Current tiling stride for the object, if it's tiled. */ 1020 uint32_t stride; 1021 1022 /** Record of address bit 17 of each page at last unbind. */ 1023 unsigned long *bit_17; 1024 1025 /** 1026 * If present, while GEM_DOMAIN_CPU is in the read domain this array 1027 * flags which individual pages are valid. 1028 */ 1029 uint8_t *page_cpu_valid; 1030 1031 /** User space pin count and filp owning the pin */ 1032 uint32_t user_pin_count; 1033 struct drm_file *pin_filp; 1034 1035 /** for phy allocated objects */ 1036 struct drm_i915_gem_phys_object *phys_obj; 1037 1038 /** 1039 * Number of crtcs where this object is currently the fb, but 1040 * will be page flipped away on the next vblank. When it 1041 * reaches 0, dev_priv->pending_flip_queue will be woken up. 1042 */ 1043 atomic_t pending_flip; 1044 }; 1045 1046 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1047 1048 /** 1049 * Request queue structure. 1050 * 1051 * The request queue allows us to note sequence numbers that have been emitted 1052 * and may be associated with active buffers to be retired. 1053 * 1054 * By keeping this list, we can avoid having to do questionable 1055 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1056 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1057 */ 1058 struct drm_i915_gem_request { 1059 /** On Which ring this request was generated */ 1060 struct intel_ring_buffer *ring; 1061 1062 /** GEM sequence number associated with this request. */ 1063 uint32_t seqno; 1064 1065 /** Postion in the ringbuffer of the end of the request */ 1066 u32 tail; 1067 1068 /** Time at which this request was emitted, in jiffies. */ 1069 unsigned long emitted_jiffies; 1070 1071 /** global list entry for this request */ 1072 struct list_head list; 1073 1074 struct drm_i915_file_private *file_priv; 1075 /** file_priv list entry for this request */ 1076 struct list_head client_list; 1077 }; 1078 1079 struct drm_i915_file_private { 1080 struct { 1081 struct spinlock lock; 1082 struct list_head request_list; 1083 } mm; 1084 }; 1085 1086 /** 1087 * RC6 is a special power stage which allows the GPU to enter an very 1088 * low-voltage mode when idle, using down to 0V while at this stage. This 1089 * stage is entered automatically when the GPU is idle when RC6 support is 1090 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1091 * 1092 * There are different RC6 modes available in Intel GPU, which differentiate 1093 * among each other with the latency required to enter and leave RC6 and 1094 * voltage consumed by the GPU in different states. 1095 * 1096 * The combination of the following flags define which states GPU is allowed 1097 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1098 * RC6pp is deepest RC6. Their support by hardware varies according to the 1099 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1100 * which brings the most power savings; deeper states save more power, but 1101 * require higher latency to switch to and wake up. 1102 */ 1103 #define INTEL_RC6_ENABLE (1<<0) 1104 #define INTEL_RC6p_ENABLE (1<<1) 1105 #define INTEL_RC6pp_ENABLE (1<<2) 1106 1107 extern int intel_iommu_enabled; 1108 extern struct drm_ioctl_desc i915_ioctls[]; 1109 extern struct drm_driver i915_driver_info; 1110 extern struct cdev_pager_ops i915_gem_pager_ops; 1111 extern int i915_panel_ignore_lid; 1112 extern unsigned int i915_powersave; 1113 extern int i915_semaphores; 1114 extern unsigned int i915_lvds_downclock; 1115 extern int i915_panel_use_ssc; 1116 extern int i915_vbt_sdvo_panel_type; 1117 extern int i915_enable_rc6; 1118 extern int i915_enable_fbc; 1119 extern int i915_enable_ppgtt; 1120 extern int i915_enable_hangcheck; 1121 1122 const struct intel_device_info *i915_get_device_id(int device); 1123 1124 int i915_reset(struct drm_device *dev, u8 flags); 1125 1126 /* i915_debug.c */ 1127 int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1128 struct sysctl_oid *top); 1129 void i915_sysctl_cleanup(struct drm_device *dev); 1130 1131 /* i915_dma.c */ 1132 extern void i915_kernel_lost_context(struct drm_device * dev); 1133 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1134 extern int i915_driver_unload(struct drm_device *); 1135 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1136 extern void i915_driver_lastclose(struct drm_device * dev); 1137 extern void i915_driver_preclose(struct drm_device *dev, 1138 struct drm_file *file_priv); 1139 extern void i915_driver_postclose(struct drm_device *dev, 1140 struct drm_file *file_priv); 1141 extern int i915_driver_device_is_agp(struct drm_device * dev); 1142 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1143 unsigned long arg); 1144 extern int i915_emit_box(struct drm_device *dev, 1145 struct drm_clip_rect __user *boxes, 1146 int i, int DR1, int DR4); 1147 int i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 1148 int DR1, int DR4); 1149 1150 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1151 unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1152 void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1153 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1154 1155 /* i915_irq.c */ 1156 extern int i915_irq_emit(struct drm_device *dev, void *data, 1157 struct drm_file *file_priv); 1158 extern int i915_irq_wait(struct drm_device *dev, void *data, 1159 struct drm_file *file_priv); 1160 1161 extern void intel_irq_init(struct drm_device *dev); 1162 1163 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1164 struct drm_file *file_priv); 1165 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1166 struct drm_file *file_priv); 1167 extern int i915_vblank_swap(struct drm_device *dev, void *data, 1168 struct drm_file *file_priv); 1169 void intel_enable_asle(struct drm_device *dev); 1170 void i915_hangcheck_elapsed(void *context); 1171 void i915_handle_error(struct drm_device *dev, bool wedged); 1172 1173 void i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1174 void i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1175 1176 void i915_destroy_error_state(struct drm_device *dev); 1177 1178 /* i915_gem.c */ 1179 int i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size, 1180 uint32_t *handle_p); 1181 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1182 struct drm_file *file_priv); 1183 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1184 struct drm_file *file_priv); 1185 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1186 struct drm_file *file_priv); 1187 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1188 struct drm_file *file_priv); 1189 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1190 struct drm_file *file_priv); 1191 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1192 struct drm_file *file_priv); 1193 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1194 struct drm_file *file_priv); 1195 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1196 struct drm_file *file_priv); 1197 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1198 struct drm_file *file_priv); 1199 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1200 struct drm_file *file_priv); 1201 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1202 struct drm_file *file_priv); 1203 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1204 struct drm_file *file_priv); 1205 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1206 struct drm_file *file_priv); 1207 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1208 struct drm_file *file_priv); 1209 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1210 struct drm_file *file_priv); 1211 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1212 struct drm_file *file_priv); 1213 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1214 struct drm_file *file_priv); 1215 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1216 struct drm_file *file_priv); 1217 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1218 struct drm_file *file_priv); 1219 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1220 struct drm_file *file_priv); 1221 void i915_gem_load(struct drm_device *dev); 1222 void i915_gem_unload(struct drm_device *dev); 1223 int i915_gem_init_object(struct drm_gem_object *obj); 1224 void i915_gem_free_object(struct drm_gem_object *obj); 1225 int i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1226 bool map_and_fenceable); 1227 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1228 int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1229 void i915_gem_lastclose(struct drm_device *dev); 1230 uint32_t i915_get_gem_seqno(struct drm_device *dev); 1231 1232 static inline void 1233 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1234 { 1235 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1236 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1237 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1238 } 1239 } 1240 1241 static inline void 1242 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1243 { 1244 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1245 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1246 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1247 } 1248 } 1249 1250 void i915_gem_retire_requests(struct drm_device *dev); 1251 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1252 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1253 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1254 size_t size); 1255 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 1256 unsigned long mappable_end, unsigned long end); 1257 uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1258 uint32_t size, int tiling_mode); 1259 int i915_mutex_lock_interruptible(struct drm_device *dev); 1260 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1261 bool write); 1262 int i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1263 u32 alignment, struct intel_ring_buffer *pipelined); 1264 int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1265 int i915_gem_flush_ring(struct intel_ring_buffer *ring, 1266 uint32_t invalidate_domains, uint32_t flush_domains); 1267 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1268 int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1269 int i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1270 int i915_gem_idle(struct drm_device *dev); 1271 int i915_gem_init_hw(struct drm_device *dev); 1272 void i915_gem_init_swizzling(struct drm_device *dev); 1273 void i915_gem_init_ppgtt(struct drm_device *dev); 1274 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1275 int i915_gpu_idle(struct drm_device *dev, bool do_retire); 1276 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1277 struct intel_ring_buffer *ring, uint32_t seqno); 1278 int i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file, 1279 struct drm_i915_gem_request *request); 1280 int i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1281 struct intel_ring_buffer *pipelined); 1282 void i915_gem_reset(struct drm_device *dev); 1283 int i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, 1284 bool do_retire); 1285 int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1286 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1287 uint64_t *phys); 1288 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1289 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1290 enum i915_cache_level cache_level); 1291 1292 void i915_gem_free_all_phys_object(struct drm_device *dev); 1293 void i915_gem_detach_phys_object(struct drm_device *dev, 1294 struct drm_i915_gem_object *obj); 1295 int i915_gem_attach_phys_object(struct drm_device *dev, 1296 struct drm_i915_gem_object *obj, int id, int align); 1297 1298 int i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1299 struct drm_mode_create_dumb *args); 1300 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1301 uint32_t handle, uint64_t *offset); 1302 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1303 uint32_t handle); 1304 1305 /* i915_gem_tiling.c */ 1306 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1307 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1308 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1309 1310 /* i915_gem_evict.c */ 1311 int i915_gem_evict_something(struct drm_device *dev, int min_size, 1312 unsigned alignment, bool mappable); 1313 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1314 int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only); 1315 1316 /* i915_suspend.c */ 1317 extern int i915_save_state(struct drm_device *dev); 1318 extern int i915_restore_state(struct drm_device *dev); 1319 1320 /* intel_iic.c */ 1321 extern int intel_setup_gmbus(struct drm_device *dev); 1322 extern void intel_teardown_gmbus(struct drm_device *dev); 1323 extern void intel_gmbus_set_speed(device_t idev, int speed); 1324 extern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1325 extern void intel_iic_reset(struct drm_device *dev); 1326 1327 /* intel_opregion.c */ 1328 int intel_opregion_setup(struct drm_device *dev); 1329 extern int intel_opregion_init(struct drm_device *dev); 1330 extern void intel_opregion_fini(struct drm_device *dev); 1331 extern void opregion_asle_intr(struct drm_device *dev); 1332 extern void opregion_enable_asle(struct drm_device *dev); 1333 1334 /* i915_gem_gtt.c */ 1335 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1336 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1337 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1338 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1339 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1340 struct drm_i915_gem_object *obj); 1341 1342 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1343 int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1344 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1345 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1346 enum i915_cache_level cache_level); 1347 1348 /* modesetting */ 1349 extern void intel_modeset_init(struct drm_device *dev); 1350 extern void intel_modeset_gem_init(struct drm_device *dev); 1351 extern void intel_modeset_cleanup(struct drm_device *dev); 1352 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1353 extern void intel_disable_fbc(struct drm_device *dev); 1354 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1355 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1356 extern void ironlake_enable_rc6(struct drm_device *dev); 1357 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1358 extern void intel_detect_pch(struct drm_device *dev); 1359 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1360 1361 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1362 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1363 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1364 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1365 1366 extern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1367 struct drm_device *dev); 1368 extern void intel_overlay_print_error_state(struct sbuf *m, 1369 struct intel_overlay_error_state *error); 1370 extern struct intel_display_error_state *intel_display_capture_error_state( 1371 struct drm_device *dev); 1372 extern void intel_display_print_error_state(struct sbuf *m, 1373 struct drm_device *dev, struct intel_display_error_state *error); 1374 1375 static inline void 1376 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1377 { 1378 return; 1379 } 1380 1381 /* On SNB platform, before reading ring registers forcewake bit 1382 * must be set to prevent GT core from power down and stale values being 1383 * returned. 1384 */ 1385 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1386 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1387 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1388 1389 /* We give fast paths for the really cool registers */ 1390 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1391 (((dev_priv)->info->gen >= 6) && \ 1392 ((reg) < 0x40000) && \ 1393 ((reg) != FORCEWAKE)) 1394 1395 #define __i915_read(x, y) \ 1396 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1397 1398 __i915_read(8, 8) 1399 __i915_read(16, 16) 1400 __i915_read(32, 32) 1401 __i915_read(64, 64) 1402 #undef __i915_read 1403 1404 #define __i915_write(x, y) \ 1405 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1406 1407 __i915_write(8, 8) 1408 __i915_write(16, 16) 1409 __i915_write(32, 32) 1410 __i915_write(64, 64) 1411 #undef __i915_write 1412 1413 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1414 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1415 1416 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1417 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1418 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1419 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1420 1421 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1422 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1423 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1424 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1425 1426 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1427 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1428 1429 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1430 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1431 1432 #define I915_VERBOSE 0 1433 1434 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) 1435 1436 #define BEGIN_LP_RING(n) \ 1437 intel_ring_begin(LP_RING(dev_priv), (n)) 1438 1439 #define OUT_RING(x) \ 1440 intel_ring_emit(LP_RING(dev_priv), x) 1441 1442 #define ADVANCE_LP_RING() \ 1443 intel_ring_advance(LP_RING(dev_priv)) 1444 1445 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1446 if (LP_RING(dev->dev_private)->obj == NULL) \ 1447 LOCK_TEST_WITH_RETURN(dev, file); \ 1448 } while (0) 1449 1450 /** 1451 * Reads a dword out of the status page, which is written to from the command 1452 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1453 * MI_STORE_DATA_IMM. 1454 * 1455 * The following dwords have a reserved meaning: 1456 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1457 * 0x04: ring 0 head pointer 1458 * 0x05: ring 1 head pointer (915-class) 1459 * 0x06: ring 2 head pointer (915-class) 1460 * 0x10-0x1b: Context status DWords (GM45) 1461 * 0x1f: Last written status offset. (GM45) 1462 * 1463 * The area from dword 0x20 to 0x3ff is available for driver usage. 1464 */ 1465 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 1466 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1467 #define I915_GEM_HWS_INDEX 0x20 1468 #define I915_BREADCRUMB_INDEX 0x21 1469 1470 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1471 1472 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1473 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1474 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1475 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1476 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1477 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1478 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1479 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1480 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1481 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1482 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1483 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1484 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1485 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1486 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1487 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1488 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1489 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1490 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1491 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1492 (dev)->pci_device == 0x0152 || \ 1493 (dev)->pci_device == 0x015a) 1494 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1495 (dev)->pci_device == 0x0106 || \ 1496 (dev)->pci_device == 0x010A) 1497 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1498 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1499 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1500 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1501 ((dev)->pci_device & 0xFF00) == 0x0A00) 1502 1503 /* XXXKIB LEGACY */ 1504 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1505 (dev)->pci_device == 0x2982 || \ 1506 (dev)->pci_device == 0x2992 || \ 1507 (dev)->pci_device == 0x29A2 || \ 1508 (dev)->pci_device == 0x2A02 || \ 1509 (dev)->pci_device == 0x2A12 || \ 1510 (dev)->pci_device == 0x2A42 || \ 1511 (dev)->pci_device == 0x2E02 || \ 1512 (dev)->pci_device == 0x2E12 || \ 1513 (dev)->pci_device == 0x2E22 || \ 1514 (dev)->pci_device == 0x2E32) 1515 1516 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1517 1518 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1519 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1520 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1521 1522 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1523 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1524 /* XXXKIB LEGACY END */ 1525 1526 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1527 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1528 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1529 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1530 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1531 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1532 1533 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1534 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1535 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1536 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1537 1538 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1539 1540 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1541 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1542 1543 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1544 * rows, which changed the alignment requirements and fence programming. 1545 */ 1546 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1547 IS_I915GM(dev))) 1548 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1549 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1550 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1551 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1552 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1553 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1554 /* dsparb controlled by hw only */ 1555 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1556 1557 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1558 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1559 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1560 1561 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1562 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1563 1564 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1565 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1566 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1567 1568 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1569 1570 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 1571 1572 static inline bool 1573 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1574 { 1575 1576 return ((int32_t)(seq1 - seq2) >= 0); 1577 } 1578 1579 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1580 1581 #endif 1582