1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi_drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include "intel_lrc.h" 39 #include "i915_gem_gtt.h" 40 #include "i915_gem_render_state.h" 41 #include <linux/io-mapping.h> 42 #include <linux/i2c.h> 43 #include <drm/intel-gtt.h> 44 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ 45 #include <drm/drm_gem.h> 46 #include <linux/backlight.h> 47 #include <linux/hashtable.h> 48 #include <linux/kref.h> 49 #include <linux/kconfig.h> 50 #include <linux/pm_qos.h> 51 #include <linux/seq_file.h> 52 #include <linux/delay.h> 53 54 #define CONFIG_ACPI 1 55 56 /* General customization: 57 */ 58 59 #define DRIVER_NAME "i915" 60 #define DRIVER_DESC "Intel Graphics" 61 #define DRIVER_DATE "20140905" 62 63 enum i915_pipe { 64 INVALID_PIPE = -1, 65 PIPE_A = 0, 66 PIPE_B, 67 PIPE_C, 68 _PIPE_EDP, 69 I915_MAX_PIPES = _PIPE_EDP 70 }; 71 #define pipe_name(p) ((p) + 'A') 72 73 enum transcoder { 74 TRANSCODER_A = 0, 75 TRANSCODER_B, 76 TRANSCODER_C, 77 TRANSCODER_EDP, 78 I915_MAX_TRANSCODERS 79 }; 80 #define transcoder_name(t) ((t) + 'A') 81 82 enum plane { 83 PLANE_A = 0, 84 PLANE_B, 85 PLANE_C, 86 }; 87 #define plane_name(p) ((p) + 'A') 88 89 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') 90 91 enum port { 92 PORT_A = 0, 93 PORT_B, 94 PORT_C, 95 PORT_D, 96 PORT_E, 97 I915_MAX_PORTS 98 }; 99 #define port_name(p) ((p) + 'A') 100 101 #define I915_NUM_PHYS_VLV 2 102 103 enum dpio_channel { 104 DPIO_CH0, 105 DPIO_CH1 106 }; 107 108 enum dpio_phy { 109 DPIO_PHY0, 110 DPIO_PHY1 111 }; 112 113 enum intel_display_power_domain { 114 POWER_DOMAIN_PIPE_A, 115 POWER_DOMAIN_PIPE_B, 116 POWER_DOMAIN_PIPE_C, 117 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 118 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 119 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 120 POWER_DOMAIN_TRANSCODER_A, 121 POWER_DOMAIN_TRANSCODER_B, 122 POWER_DOMAIN_TRANSCODER_C, 123 POWER_DOMAIN_TRANSCODER_EDP, 124 POWER_DOMAIN_PORT_DDI_A_2_LANES, 125 POWER_DOMAIN_PORT_DDI_A_4_LANES, 126 POWER_DOMAIN_PORT_DDI_B_2_LANES, 127 POWER_DOMAIN_PORT_DDI_B_4_LANES, 128 POWER_DOMAIN_PORT_DDI_C_2_LANES, 129 POWER_DOMAIN_PORT_DDI_C_4_LANES, 130 POWER_DOMAIN_PORT_DDI_D_2_LANES, 131 POWER_DOMAIN_PORT_DDI_D_4_LANES, 132 POWER_DOMAIN_PORT_DSI, 133 POWER_DOMAIN_PORT_CRT, 134 POWER_DOMAIN_PORT_OTHER, 135 POWER_DOMAIN_VGA, 136 POWER_DOMAIN_AUDIO, 137 POWER_DOMAIN_PLLS, 138 POWER_DOMAIN_INIT, 139 140 POWER_DOMAIN_NUM, 141 }; 142 143 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 144 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 145 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 146 #define POWER_DOMAIN_TRANSCODER(tran) \ 147 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 148 (tran) + POWER_DOMAIN_TRANSCODER_A) 149 150 enum hpd_pin { 151 HPD_NONE = 0, 152 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 153 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 154 HPD_CRT, 155 HPD_SDVO_B, 156 HPD_SDVO_C, 157 HPD_PORT_B, 158 HPD_PORT_C, 159 HPD_PORT_D, 160 HPD_NUM_PINS 161 }; 162 163 #define I915_GEM_GPU_DOMAINS \ 164 (I915_GEM_DOMAIN_RENDER | \ 165 I915_GEM_DOMAIN_SAMPLER | \ 166 I915_GEM_DOMAIN_COMMAND | \ 167 I915_GEM_DOMAIN_INSTRUCTION | \ 168 I915_GEM_DOMAIN_VERTEX) 169 170 #define for_each_pipe(__dev_priv, __p) \ 171 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) 172 #define for_each_plane(pipe, p) \ 173 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++) 174 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) 175 176 #define for_each_crtc(dev, crtc) \ 177 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 178 179 #define for_each_intel_crtc(dev, intel_crtc) \ 180 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) 181 182 #define for_each_intel_encoder(dev, intel_encoder) \ 183 list_for_each_entry(intel_encoder, \ 184 &(dev)->mode_config.encoder_list, \ 185 base.head) 186 187 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 188 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 189 if ((intel_encoder)->base.crtc == (__crtc)) 190 191 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 192 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 193 if ((intel_connector)->base.encoder == (__encoder)) 194 195 #define for_each_power_domain(domain, mask) \ 196 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ 197 if ((1 << (domain)) & (mask)) 198 199 struct drm_i915_private; 200 struct i915_mmu_object; 201 202 enum intel_dpll_id { 203 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 204 /* real shared dpll ids must be >= 0 */ 205 DPLL_ID_PCH_PLL_A = 0, 206 DPLL_ID_PCH_PLL_B = 1, 207 DPLL_ID_WRPLL1 = 0, 208 DPLL_ID_WRPLL2 = 1, 209 }; 210 #define I915_NUM_PLLS 2 211 212 struct intel_dpll_hw_state { 213 /* i9xx, pch plls */ 214 uint32_t dpll; 215 uint32_t dpll_md; 216 uint32_t fp0; 217 uint32_t fp1; 218 219 /* hsw, bdw */ 220 uint32_t wrpll; 221 }; 222 223 struct intel_shared_dpll { 224 int refcount; /* count of number of CRTCs sharing this PLL */ 225 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 226 bool on; /* is the PLL actually active? Disabled during modeset */ 227 const char *name; 228 /* should match the index in the dev_priv->shared_dplls array */ 229 enum intel_dpll_id id; 230 struct intel_dpll_hw_state hw_state; 231 /* The mode_set hook is optional and should be used together with the 232 * intel_prepare_shared_dpll function. */ 233 void (*mode_set)(struct drm_i915_private *dev_priv, 234 struct intel_shared_dpll *pll); 235 void (*enable)(struct drm_i915_private *dev_priv, 236 struct intel_shared_dpll *pll); 237 void (*disable)(struct drm_i915_private *dev_priv, 238 struct intel_shared_dpll *pll); 239 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 240 struct intel_shared_dpll *pll, 241 struct intel_dpll_hw_state *hw_state); 242 }; 243 244 /* Used by dp and fdi links */ 245 struct intel_link_m_n { 246 uint32_t tu; 247 uint32_t gmch_m; 248 uint32_t gmch_n; 249 uint32_t link_m; 250 uint32_t link_n; 251 }; 252 253 void intel_link_compute_m_n(int bpp, int nlanes, 254 int pixel_clock, int link_clock, 255 struct intel_link_m_n *m_n); 256 257 /* Interface history: 258 * 259 * 1.1: Original. 260 * 1.2: Add Power Management 261 * 1.3: Add vblank support 262 * 1.4: Fix cmdbuffer path, add heap destroy 263 * 1.5: Add vblank pipe configuration 264 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 265 * - Support vertical blank on secondary display pipe 266 */ 267 #define DRIVER_MAJOR 1 268 #define DRIVER_MINOR 6 269 #define DRIVER_PATCHLEVEL 0 270 271 #define WATCH_LISTS 0 272 #define WATCH_GTT 0 273 274 struct opregion_header; 275 struct opregion_acpi; 276 struct opregion_swsci; 277 struct opregion_asle; 278 279 struct intel_opregion { 280 struct opregion_header __iomem *header; 281 struct opregion_acpi __iomem *acpi; 282 struct opregion_swsci __iomem *swsci; 283 u32 swsci_gbda_sub_functions; 284 u32 swsci_sbcb_sub_functions; 285 struct opregion_asle __iomem *asle; 286 void __iomem *vbt; 287 u32 __iomem *lid_state; 288 struct work_struct asle_work; 289 }; 290 #define OPREGION_SIZE (8*1024) 291 292 struct intel_overlay; 293 struct intel_overlay_error_state; 294 295 struct drm_i915_master_private { 296 struct drm_local_map *sarea; 297 struct _drm_i915_sarea *sarea_priv; 298 }; 299 #define I915_FENCE_REG_NONE -1 300 #define I915_MAX_NUM_FENCES 32 301 /* 32 fences + sign bit for FENCE_REG_NONE */ 302 #define I915_MAX_NUM_FENCE_BITS 6 303 304 struct drm_i915_fence_reg { 305 struct list_head lru_list; 306 struct drm_i915_gem_object *obj; 307 int pin_count; 308 }; 309 310 struct sdvo_device_mapping { 311 u8 initialized; 312 u8 dvo_port; 313 u8 slave_addr; 314 u8 dvo_wiring; 315 u8 i2c_pin; 316 u8 ddc_pin; 317 }; 318 319 struct intel_display_error_state; 320 321 struct drm_i915_error_state { 322 struct kref ref; 323 struct timeval time; 324 325 char error_msg[128]; 326 u32 reset_count; 327 u32 suspend_count; 328 329 /* Generic register state */ 330 u32 eir; 331 u32 pgtbl_er; 332 u32 ier; 333 u32 gtier[4]; 334 u32 ccid; 335 u32 derrmr; 336 u32 forcewake; 337 u32 error; /* gen6+ */ 338 u32 err_int; /* gen7 */ 339 u32 done_reg; 340 u32 gac_eco; 341 u32 gam_ecochk; 342 u32 gab_ctl; 343 u32 gfx_mode; 344 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 345 u64 fence[I915_MAX_NUM_FENCES]; 346 struct intel_overlay_error_state *overlay; 347 struct intel_display_error_state *display; 348 struct drm_i915_error_object *semaphore_obj; 349 350 struct drm_i915_error_ring { 351 bool valid; 352 /* Software tracked state */ 353 bool waiting; 354 int hangcheck_score; 355 enum intel_ring_hangcheck_action hangcheck_action; 356 int num_requests; 357 358 /* our own tracking of ring head and tail */ 359 u32 cpu_ring_head; 360 u32 cpu_ring_tail; 361 362 u32 semaphore_seqno[I915_NUM_RINGS - 1]; 363 364 /* Register state */ 365 u32 tail; 366 u32 head; 367 u32 ctl; 368 u32 hws; 369 u32 ipeir; 370 u32 ipehr; 371 u32 instdone; 372 u32 bbstate; 373 u32 instpm; 374 u32 instps; 375 u32 seqno; 376 u64 bbaddr; 377 u64 acthd; 378 u32 fault_reg; 379 u64 faddr; 380 u32 rc_psmi; /* sleep state */ 381 u32 semaphore_mboxes[I915_NUM_RINGS - 1]; 382 383 struct drm_i915_error_object { 384 int page_count; 385 u32 gtt_offset; 386 u32 *pages[0]; 387 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 388 389 struct drm_i915_error_request { 390 long jiffies; 391 u32 seqno; 392 u32 tail; 393 } *requests; 394 395 struct { 396 u32 gfx_mode; 397 union { 398 u64 pdp[4]; 399 u32 pp_dir_base; 400 }; 401 } vm_info; 402 403 pid_t pid; 404 char comm[TASK_COMM_LEN]; 405 } ring[I915_NUM_RINGS]; 406 407 struct drm_i915_error_buffer { 408 u32 size; 409 u32 name; 410 u32 rseqno, wseqno; 411 u32 gtt_offset; 412 u32 read_domains; 413 u32 write_domain; 414 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 415 s32 pinned:2; 416 u32 tiling:2; 417 u32 dirty:1; 418 u32 purgeable:1; 419 u32 userptr:1; 420 s32 ring:4; 421 u32 cache_level:3; 422 } **active_bo, **pinned_bo; 423 424 u32 *active_bo_count, *pinned_bo_count; 425 u32 vm_count; 426 }; 427 428 struct intel_connector; 429 struct intel_crtc_config; 430 struct intel_plane_config; 431 struct intel_crtc; 432 struct intel_limit; 433 struct dpll; 434 435 struct drm_i915_display_funcs { 436 bool (*fbc_enabled)(struct drm_device *dev); 437 void (*enable_fbc)(struct drm_crtc *crtc); 438 void (*disable_fbc)(struct drm_device *dev); 439 int (*get_display_clock_speed)(struct drm_device *dev); 440 int (*get_fifo_size)(struct drm_device *dev, int plane); 441 /** 442 * find_dpll() - Find the best values for the PLL 443 * @limit: limits for the PLL 444 * @crtc: current CRTC 445 * @target: target frequency in kHz 446 * @refclk: reference clock frequency in kHz 447 * @match_clock: if provided, @best_clock P divider must 448 * match the P divider from @match_clock 449 * used for LVDS downclocking 450 * @best_clock: best PLL values found 451 * 452 * Returns true on success, false on failure. 453 */ 454 bool (*find_dpll)(const struct intel_limit *limit, 455 struct drm_crtc *crtc, 456 int target, int refclk, 457 struct dpll *match_clock, 458 struct dpll *best_clock); 459 void (*update_wm)(struct drm_crtc *crtc); 460 void (*update_sprite_wm)(struct drm_plane *plane, 461 struct drm_crtc *crtc, 462 uint32_t sprite_width, uint32_t sprite_height, 463 int pixel_size, bool enable, bool scaled); 464 void (*modeset_global_resources)(struct drm_device *dev); 465 /* Returns the active state of the crtc, and if the crtc is active, 466 * fills out the pipe-config with the hw state. */ 467 bool (*get_pipe_config)(struct intel_crtc *, 468 struct intel_crtc_config *); 469 void (*get_plane_config)(struct intel_crtc *, 470 struct intel_plane_config *); 471 int (*crtc_mode_set)(struct drm_crtc *crtc, 472 int x, int y, 473 struct drm_framebuffer *old_fb); 474 void (*crtc_enable)(struct drm_crtc *crtc); 475 void (*crtc_disable)(struct drm_crtc *crtc); 476 void (*off)(struct drm_crtc *crtc); 477 void (*write_eld)(struct drm_connector *connector, 478 struct drm_crtc *crtc, 479 struct drm_display_mode *mode); 480 void (*fdi_link_train)(struct drm_crtc *crtc); 481 void (*init_clock_gating)(struct drm_device *dev); 482 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 483 struct drm_framebuffer *fb, 484 struct drm_i915_gem_object *obj, 485 struct intel_engine_cs *ring, 486 uint32_t flags); 487 void (*update_primary_plane)(struct drm_crtc *crtc, 488 struct drm_framebuffer *fb, 489 int x, int y); 490 void (*hpd_irq_setup)(struct drm_device *dev); 491 /* clock updates for mode set */ 492 /* cursor updates */ 493 /* render clock increase/decrease */ 494 /* display clock increase/decrease */ 495 /* pll clock increase/decrease */ 496 497 int (*setup_backlight)(struct intel_connector *connector); 498 uint32_t (*get_backlight)(struct intel_connector *connector); 499 void (*set_backlight)(struct intel_connector *connector, 500 uint32_t level); 501 void (*disable_backlight)(struct intel_connector *connector); 502 void (*enable_backlight)(struct intel_connector *connector); 503 }; 504 505 struct intel_uncore_funcs { 506 void (*force_wake_get)(struct drm_i915_private *dev_priv, 507 int fw_engine); 508 void (*force_wake_put)(struct drm_i915_private *dev_priv, 509 int fw_engine); 510 511 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 512 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 513 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 514 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 515 516 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 517 uint8_t val, bool trace); 518 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 519 uint16_t val, bool trace); 520 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 521 uint32_t val, bool trace); 522 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 523 uint64_t val, bool trace); 524 }; 525 526 struct intel_uncore { 527 struct lock lock; /** lock is also taken in irq contexts. */ 528 529 struct intel_uncore_funcs funcs; 530 531 unsigned fifo_count; 532 unsigned forcewake_count; 533 534 unsigned fw_rendercount; 535 unsigned fw_mediacount; 536 537 struct timer_list force_wake_timer; 538 }; 539 540 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 541 func(is_mobile) sep \ 542 func(is_i85x) sep \ 543 func(is_i915g) sep \ 544 func(is_i945gm) sep \ 545 func(is_g33) sep \ 546 func(need_gfx_hws) sep \ 547 func(is_g4x) sep \ 548 func(is_pineview) sep \ 549 func(is_broadwater) sep \ 550 func(is_crestline) sep \ 551 func(is_ivybridge) sep \ 552 func(is_valleyview) sep \ 553 func(is_haswell) sep \ 554 func(is_preliminary) sep \ 555 func(has_fbc) sep \ 556 func(has_pipe_cxsr) sep \ 557 func(has_hotplug) sep \ 558 func(cursor_needs_physical) sep \ 559 func(has_overlay) sep \ 560 func(overlay_needs_physical) sep \ 561 func(supports_tv) sep \ 562 func(has_llc) sep \ 563 func(has_ddi) sep \ 564 func(has_fpga_dbg) 565 566 #define DEFINE_FLAG(name) u8 name:1 567 #define SEP_SEMICOLON ; 568 569 struct intel_device_info { 570 u32 display_mmio_offset; 571 u16 device_id; 572 u8 num_pipes:3; 573 u8 num_sprites[I915_MAX_PIPES]; 574 u8 gen; 575 u8 ring_mask; /* Rings supported by the HW */ 576 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 577 /* Register offsets for the various display pipes and transcoders */ 578 int pipe_offsets[I915_MAX_TRANSCODERS]; 579 int trans_offsets[I915_MAX_TRANSCODERS]; 580 int palette_offsets[I915_MAX_PIPES]; 581 int cursor_offsets[I915_MAX_PIPES]; 582 }; 583 584 #undef DEFINE_FLAG 585 #undef SEP_SEMICOLON 586 587 enum i915_cache_level { 588 I915_CACHE_NONE = 0, 589 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 590 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 591 caches, eg sampler/render caches, and the 592 large Last-Level-Cache. LLC is coherent with 593 the CPU, but L3 is only visible to the GPU. */ 594 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 595 }; 596 597 struct i915_ctx_hang_stats { 598 /* This context had batch pending when hang was declared */ 599 unsigned batch_pending; 600 601 /* This context had batch active when hang was declared */ 602 unsigned batch_active; 603 604 /* Time when this context was last blamed for a GPU reset */ 605 unsigned long guilty_ts; 606 607 /* This context is banned to submit more work */ 608 bool banned; 609 }; 610 611 /* This must match up with the value previously used for execbuf2.rsvd1. */ 612 #define DEFAULT_CONTEXT_HANDLE 0 613 /** 614 * struct intel_context - as the name implies, represents a context. 615 * @ref: reference count. 616 * @user_handle: userspace tracking identity for this context. 617 * @remap_slice: l3 row remapping information. 618 * @file_priv: filp associated with this context (NULL for global default 619 * context). 620 * @hang_stats: information about the role of this context in possible GPU 621 * hangs. 622 * @vm: virtual memory space used by this context. 623 * @legacy_hw_ctx: render context backing object and whether it is correctly 624 * initialized (legacy ring submission mechanism only). 625 * @link: link in the global list of contexts. 626 * 627 * Contexts are memory images used by the hardware to store copies of their 628 * internal state. 629 */ 630 struct intel_context { 631 struct kref ref; 632 int user_handle; 633 uint8_t remap_slice; 634 struct drm_i915_file_private *file_priv; 635 struct i915_ctx_hang_stats hang_stats; 636 struct i915_hw_ppgtt *ppgtt; 637 638 /* Legacy ring buffer submission */ 639 struct { 640 struct drm_i915_gem_object *rcs_state; 641 bool initialized; 642 } legacy_hw_ctx; 643 644 /* Execlists */ 645 bool rcs_initialized; 646 struct { 647 struct drm_i915_gem_object *state; 648 struct intel_ringbuffer *ringbuf; 649 } engine[I915_NUM_RINGS]; 650 651 struct list_head link; 652 }; 653 654 struct i915_fbc { 655 unsigned long size; 656 unsigned threshold; 657 unsigned int fb_id; 658 enum plane plane; 659 int y; 660 661 struct drm_mm_node compressed_fb; 662 struct drm_mm_node *compressed_llb; 663 664 bool false_color; 665 666 struct intel_fbc_work { 667 struct delayed_work work; 668 struct drm_crtc *crtc; 669 struct drm_framebuffer *fb; 670 } *fbc_work; 671 672 enum no_fbc_reason { 673 FBC_OK, /* FBC is enabled */ 674 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 675 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 676 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 677 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 678 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 679 FBC_BAD_PLANE, /* fbc not supported on plane */ 680 FBC_NOT_TILED, /* buffer not tiled */ 681 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 682 FBC_MODULE_PARAM, 683 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 684 } no_fbc_reason; 685 }; 686 687 struct i915_drrs { 688 struct intel_connector *connector; 689 }; 690 691 struct intel_dp; 692 struct i915_psr { 693 struct lock lock; 694 bool sink_support; 695 bool source_ok; 696 struct intel_dp *enabled; 697 bool active; 698 struct delayed_work work; 699 unsigned busy_frontbuffer_bits; 700 }; 701 702 enum intel_pch { 703 PCH_NONE = 0, /* No PCH present */ 704 PCH_IBX, /* Ibexpeak PCH */ 705 PCH_CPT, /* Cougarpoint PCH */ 706 PCH_LPT, /* Lynxpoint PCH */ 707 PCH_NOP, 708 }; 709 710 enum intel_sbi_destination { 711 SBI_ICLK, 712 SBI_MPHY, 713 }; 714 715 #define QUIRK_PIPEA_FORCE (1<<0) 716 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 717 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 718 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 719 #define QUIRK_PIPEB_FORCE (1<<4) 720 721 struct intel_fbdev; 722 struct intel_fbc_work; 723 724 struct intel_gmbus { 725 u32 force_bit; 726 u32 reg0; 727 u32 gpio_reg; 728 struct drm_i915_private *dev_priv; 729 }; 730 731 struct intel_iic_softc { 732 struct drm_device *drm_dev; 733 device_t iic_dev; 734 bool force_bit_dev; 735 char name[32]; 736 uint32_t reg; 737 uint32_t reg0; 738 }; 739 740 struct i915_suspend_saved_registers { 741 u8 saveLBB; 742 u32 saveDSPACNTR; 743 u32 saveDSPBCNTR; 744 u32 saveDSPARB; 745 u32 savePIPEACONF; 746 u32 savePIPEBCONF; 747 u32 savePIPEASRC; 748 u32 savePIPEBSRC; 749 u32 saveFPA0; 750 u32 saveFPA1; 751 u32 saveDPLL_A; 752 u32 saveDPLL_A_MD; 753 u32 saveHTOTAL_A; 754 u32 saveHBLANK_A; 755 u32 saveHSYNC_A; 756 u32 saveVTOTAL_A; 757 u32 saveVBLANK_A; 758 u32 saveVSYNC_A; 759 u32 saveBCLRPAT_A; 760 u32 saveTRANSACONF; 761 u32 saveTRANS_HTOTAL_A; 762 u32 saveTRANS_HBLANK_A; 763 u32 saveTRANS_HSYNC_A; 764 u32 saveTRANS_VTOTAL_A; 765 u32 saveTRANS_VBLANK_A; 766 u32 saveTRANS_VSYNC_A; 767 u32 savePIPEASTAT; 768 u32 saveDSPASTRIDE; 769 u32 saveDSPASIZE; 770 u32 saveDSPAPOS; 771 u32 saveDSPAADDR; 772 u32 saveDSPASURF; 773 u32 saveDSPATILEOFF; 774 u32 savePFIT_PGM_RATIOS; 775 u32 saveBLC_HIST_CTL; 776 u32 saveBLC_PWM_CTL; 777 u32 saveBLC_PWM_CTL2; 778 u32 saveBLC_HIST_CTL_B; 779 u32 saveBLC_CPU_PWM_CTL; 780 u32 saveBLC_CPU_PWM_CTL2; 781 u32 saveFPB0; 782 u32 saveFPB1; 783 u32 saveDPLL_B; 784 u32 saveDPLL_B_MD; 785 u32 saveHTOTAL_B; 786 u32 saveHBLANK_B; 787 u32 saveHSYNC_B; 788 u32 saveVTOTAL_B; 789 u32 saveVBLANK_B; 790 u32 saveVSYNC_B; 791 u32 saveBCLRPAT_B; 792 u32 saveTRANSBCONF; 793 u32 saveTRANS_HTOTAL_B; 794 u32 saveTRANS_HBLANK_B; 795 u32 saveTRANS_HSYNC_B; 796 u32 saveTRANS_VTOTAL_B; 797 u32 saveTRANS_VBLANK_B; 798 u32 saveTRANS_VSYNC_B; 799 u32 savePIPEBSTAT; 800 u32 saveDSPBSTRIDE; 801 u32 saveDSPBSIZE; 802 u32 saveDSPBPOS; 803 u32 saveDSPBADDR; 804 u32 saveDSPBSURF; 805 u32 saveDSPBTILEOFF; 806 u32 saveVGA0; 807 u32 saveVGA1; 808 u32 saveVGA_PD; 809 u32 saveVGACNTRL; 810 u32 saveADPA; 811 u32 saveLVDS; 812 u32 savePP_ON_DELAYS; 813 u32 savePP_OFF_DELAYS; 814 u32 saveDVOA; 815 u32 saveDVOB; 816 u32 saveDVOC; 817 u32 savePP_ON; 818 u32 savePP_OFF; 819 u32 savePP_CONTROL; 820 u32 savePP_DIVISOR; 821 u32 savePFIT_CONTROL; 822 u32 save_palette_a[256]; 823 u32 save_palette_b[256]; 824 u32 saveFBC_CONTROL; 825 u32 saveIER; 826 u32 saveIIR; 827 u32 saveIMR; 828 u32 saveDEIER; 829 u32 saveDEIMR; 830 u32 saveGTIER; 831 u32 saveGTIMR; 832 u32 saveFDI_RXA_IMR; 833 u32 saveFDI_RXB_IMR; 834 u32 saveCACHE_MODE_0; 835 u32 saveMI_ARB_STATE; 836 u32 saveSWF0[16]; 837 u32 saveSWF1[16]; 838 u32 saveSWF2[3]; 839 u8 saveMSR; 840 u8 saveSR[8]; 841 u8 saveGR[25]; 842 u8 saveAR_INDEX; 843 u8 saveAR[21]; 844 u8 saveDACMASK; 845 u8 saveCR[37]; 846 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 847 u32 saveCURACNTR; 848 u32 saveCURAPOS; 849 u32 saveCURABASE; 850 u32 saveCURBCNTR; 851 u32 saveCURBPOS; 852 u32 saveCURBBASE; 853 u32 saveCURSIZE; 854 u32 saveDP_B; 855 u32 saveDP_C; 856 u32 saveDP_D; 857 u32 savePIPEA_GMCH_DATA_M; 858 u32 savePIPEB_GMCH_DATA_M; 859 u32 savePIPEA_GMCH_DATA_N; 860 u32 savePIPEB_GMCH_DATA_N; 861 u32 savePIPEA_DP_LINK_M; 862 u32 savePIPEB_DP_LINK_M; 863 u32 savePIPEA_DP_LINK_N; 864 u32 savePIPEB_DP_LINK_N; 865 u32 saveFDI_RXA_CTL; 866 u32 saveFDI_TXA_CTL; 867 u32 saveFDI_RXB_CTL; 868 u32 saveFDI_TXB_CTL; 869 u32 savePFA_CTL_1; 870 u32 savePFB_CTL_1; 871 u32 savePFA_WIN_SZ; 872 u32 savePFB_WIN_SZ; 873 u32 savePFA_WIN_POS; 874 u32 savePFB_WIN_POS; 875 u32 savePCH_DREF_CONTROL; 876 u32 saveDISP_ARB_CTL; 877 u32 savePIPEA_DATA_M1; 878 u32 savePIPEA_DATA_N1; 879 u32 savePIPEA_LINK_M1; 880 u32 savePIPEA_LINK_N1; 881 u32 savePIPEB_DATA_M1; 882 u32 savePIPEB_DATA_N1; 883 u32 savePIPEB_LINK_M1; 884 u32 savePIPEB_LINK_N1; 885 u32 saveMCHBAR_RENDER_STANDBY; 886 u32 savePCH_PORT_HOTPLUG; 887 }; 888 889 struct vlv_s0ix_state { 890 /* GAM */ 891 u32 wr_watermark; 892 u32 gfx_prio_ctrl; 893 u32 arb_mode; 894 u32 gfx_pend_tlb0; 895 u32 gfx_pend_tlb1; 896 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 897 u32 media_max_req_count; 898 u32 gfx_max_req_count; 899 u32 render_hwsp; 900 u32 ecochk; 901 u32 bsd_hwsp; 902 u32 blt_hwsp; 903 u32 tlb_rd_addr; 904 905 /* MBC */ 906 u32 g3dctl; 907 u32 gsckgctl; 908 u32 mbctl; 909 910 /* GCP */ 911 u32 ucgctl1; 912 u32 ucgctl3; 913 u32 rcgctl1; 914 u32 rcgctl2; 915 u32 rstctl; 916 u32 misccpctl; 917 918 /* GPM */ 919 u32 gfxpause; 920 u32 rpdeuhwtc; 921 u32 rpdeuc; 922 u32 ecobus; 923 u32 pwrdwnupctl; 924 u32 rp_down_timeout; 925 u32 rp_deucsw; 926 u32 rcubmabdtmr; 927 u32 rcedata; 928 u32 spare2gh; 929 930 /* Display 1 CZ domain */ 931 u32 gt_imr; 932 u32 gt_ier; 933 u32 pm_imr; 934 u32 pm_ier; 935 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 936 937 /* GT SA CZ domain */ 938 u32 tilectl; 939 u32 gt_fifoctl; 940 u32 gtlc_wake_ctrl; 941 u32 gtlc_survive; 942 u32 pmwgicz; 943 944 /* Display 2 CZ domain */ 945 u32 gu_ctl0; 946 u32 gu_ctl1; 947 u32 clock_gate_dis2; 948 }; 949 950 struct intel_rps_ei { 951 u32 cz_clock; 952 u32 render_c0; 953 u32 media_c0; 954 }; 955 956 struct intel_gen6_power_mgmt { 957 /* work and pm_iir are protected by dev_priv->irq_lock */ 958 struct work_struct work; 959 u32 pm_iir; 960 961 /* Frequencies are stored in potentially platform dependent multiples. 962 * In other words, *_freq needs to be multiplied by X to be interesting. 963 * Soft limits are those which are used for the dynamic reclocking done 964 * by the driver (raise frequencies under heavy loads, and lower for 965 * lighter loads). Hard limits are those imposed by the hardware. 966 * 967 * A distinction is made for overclocking, which is never enabled by 968 * default, and is considered to be above the hard limit if it's 969 * possible at all. 970 */ 971 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 972 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 973 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 974 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 975 u8 min_freq; /* AKA RPn. Minimum frequency */ 976 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 977 u8 rp1_freq; /* "less than" RP0 power/freqency */ 978 u8 rp0_freq; /* Non-overclocked max frequency. */ 979 u32 cz_freq; 980 981 u32 ei_interrupt_count; 982 983 int last_adj; 984 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 985 986 bool enabled; 987 struct delayed_work delayed_resume_work; 988 989 /* manual wa residency calculations */ 990 struct intel_rps_ei up_ei, down_ei; 991 992 /* 993 * Protects RPS/RC6 register access and PCU communication. 994 * Must be taken after struct_mutex if nested. 995 */ 996 struct lock hw_lock; 997 }; 998 999 /* defined intel_pm.c */ 1000 extern struct lock mchdev_lock; 1001 1002 struct intel_ilk_power_mgmt { 1003 u8 cur_delay; 1004 u8 min_delay; 1005 u8 max_delay; 1006 u8 fmax; 1007 u8 fstart; 1008 1009 u64 last_count1; 1010 unsigned long last_time1; 1011 unsigned long chipset_power; 1012 u64 last_count2; 1013 struct timespec last_time2; 1014 unsigned long gfx_power; 1015 u8 corr; 1016 1017 int c_m; 1018 int r_t; 1019 1020 struct drm_i915_gem_object *pwrctx; 1021 struct drm_i915_gem_object *renderctx; 1022 }; 1023 1024 struct drm_i915_private; 1025 struct i915_power_well; 1026 1027 struct i915_power_well_ops { 1028 /* 1029 * Synchronize the well's hw state to match the current sw state, for 1030 * example enable/disable it based on the current refcount. Called 1031 * during driver init and resume time, possibly after first calling 1032 * the enable/disable handlers. 1033 */ 1034 void (*sync_hw)(struct drm_i915_private *dev_priv, 1035 struct i915_power_well *power_well); 1036 /* 1037 * Enable the well and resources that depend on it (for example 1038 * interrupts located on the well). Called after the 0->1 refcount 1039 * transition. 1040 */ 1041 void (*enable)(struct drm_i915_private *dev_priv, 1042 struct i915_power_well *power_well); 1043 /* 1044 * Disable the well and resources that depend on it. Called after 1045 * the 1->0 refcount transition. 1046 */ 1047 void (*disable)(struct drm_i915_private *dev_priv, 1048 struct i915_power_well *power_well); 1049 /* Returns the hw enabled state. */ 1050 bool (*is_enabled)(struct drm_i915_private *dev_priv, 1051 struct i915_power_well *power_well); 1052 }; 1053 1054 /* Power well structure for haswell */ 1055 struct i915_power_well { 1056 const char *name; 1057 bool always_on; 1058 /* power well enable/disable usage count */ 1059 int count; 1060 /* cached hw enabled state */ 1061 bool hw_enabled; 1062 unsigned long domains; 1063 unsigned long data; 1064 const struct i915_power_well_ops *ops; 1065 }; 1066 1067 struct i915_power_domains { 1068 /* 1069 * Power wells needed for initialization at driver init and suspend 1070 * time are on. They are kept on until after the first modeset. 1071 */ 1072 bool init_power_on; 1073 bool initializing; 1074 int power_well_count; 1075 1076 struct lock lock; 1077 int domain_use_count[POWER_DOMAIN_NUM]; 1078 struct i915_power_well *power_wells; 1079 }; 1080 1081 struct i915_dri1_state { 1082 unsigned allow_batchbuffer : 1; 1083 u32 __iomem *gfx_hws_cpu_addr; 1084 1085 unsigned int cpp; 1086 int back_offset; 1087 int front_offset; 1088 int current_page; 1089 int page_flipping; 1090 1091 uint32_t counter; 1092 }; 1093 1094 struct i915_ums_state { 1095 /** 1096 * Flag if the X Server, and thus DRM, is not currently in 1097 * control of the device. 1098 * 1099 * This is set between LeaveVT and EnterVT. It needs to be 1100 * replaced with a semaphore. It also needs to be 1101 * transitioned away from for kernel modesetting. 1102 */ 1103 int mm_suspended; 1104 }; 1105 1106 #define MAX_L3_SLICES 2 1107 struct intel_l3_parity { 1108 u32 *remap_info[MAX_L3_SLICES]; 1109 struct work_struct error_work; 1110 int which_slice; 1111 }; 1112 1113 struct i915_gem_mm { 1114 /** Memory allocator for GTT stolen memory */ 1115 struct drm_mm stolen; 1116 /** List of all objects in gtt_space. Used to restore gtt 1117 * mappings on resume */ 1118 struct list_head bound_list; 1119 /** 1120 * List of objects which are not bound to the GTT (thus 1121 * are idle and not used by the GPU) but still have 1122 * (presumably uncached) pages still attached. 1123 */ 1124 struct list_head unbound_list; 1125 1126 /** Usable portion of the GTT for GEM */ 1127 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1128 1129 /** PPGTT used for aliasing the PPGTT with the GTT */ 1130 struct i915_hw_ppgtt *aliasing_ppgtt; 1131 1132 eventhandler_tag inactive_shrinker; 1133 bool shrinker_no_lock_stealing; 1134 1135 /** LRU list of objects with fence regs on them. */ 1136 struct list_head fence_list; 1137 1138 /** 1139 * We leave the user IRQ off as much as possible, 1140 * but this means that requests will finish and never 1141 * be retired once the system goes idle. Set a timer to 1142 * fire periodically while the ring is running. When it 1143 * fires, go retire requests. 1144 */ 1145 struct delayed_work retire_work; 1146 1147 /** 1148 * When we detect an idle GPU, we want to turn on 1149 * powersaving features. So once we see that there 1150 * are no more requests outstanding and no more 1151 * arrive within a small period of time, we fire 1152 * off the idle_work. 1153 */ 1154 struct delayed_work idle_work; 1155 1156 /** 1157 * Are we in a non-interruptible section of code like 1158 * modesetting? 1159 */ 1160 bool interruptible; 1161 1162 /** 1163 * Is the GPU currently considered idle, or busy executing userspace 1164 * requests? Whilst idle, we attempt to power down the hardware and 1165 * display clocks. In order to reduce the effect on performance, there 1166 * is a slight delay before we do so. 1167 */ 1168 bool busy; 1169 1170 /* the indicator for dispatch video commands on two BSD rings */ 1171 int bsd_ring_dispatch_index; 1172 1173 /** Bit 6 swizzling required for X tiling */ 1174 uint32_t bit_6_swizzle_x; 1175 /** Bit 6 swizzling required for Y tiling */ 1176 uint32_t bit_6_swizzle_y; 1177 1178 /* accounting, useful for userland debugging */ 1179 struct spinlock object_stat_lock; 1180 size_t object_memory; 1181 u32 object_count; 1182 }; 1183 1184 struct drm_i915_error_state_buf { 1185 struct drm_i915_private *i915; 1186 unsigned bytes; 1187 unsigned size; 1188 int err; 1189 u8 *buf; 1190 loff_t start; 1191 loff_t pos; 1192 }; 1193 1194 struct i915_error_state_file_priv { 1195 struct drm_device *dev; 1196 struct drm_i915_error_state *error; 1197 }; 1198 1199 struct i915_gpu_error { 1200 /* For hangcheck timer */ 1201 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1202 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1203 /* Hang gpu twice in this window and your context gets banned */ 1204 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1205 1206 struct timer_list hangcheck_timer; 1207 1208 /* For reset and error_state handling. */ 1209 struct lock lock; 1210 /* Protected by the above dev->gpu_error.lock. */ 1211 struct drm_i915_error_state *first_error; 1212 struct work_struct work; 1213 1214 1215 unsigned long missed_irq_rings; 1216 1217 /** 1218 * State variable controlling the reset flow and count 1219 * 1220 * This is a counter which gets incremented when reset is triggered, 1221 * and again when reset has been handled. So odd values (lowest bit set) 1222 * means that reset is in progress and even values that 1223 * (reset_counter >> 1):th reset was successfully completed. 1224 * 1225 * If reset is not completed succesfully, the I915_WEDGE bit is 1226 * set meaning that hardware is terminally sour and there is no 1227 * recovery. All waiters on the reset_queue will be woken when 1228 * that happens. 1229 * 1230 * This counter is used by the wait_seqno code to notice that reset 1231 * event happened and it needs to restart the entire ioctl (since most 1232 * likely the seqno it waited for won't ever signal anytime soon). 1233 * 1234 * This is important for lock-free wait paths, where no contended lock 1235 * naturally enforces the correct ordering between the bail-out of the 1236 * waiter and the gpu reset work code. 1237 */ 1238 atomic_t reset_counter; 1239 1240 #define I915_RESET_IN_PROGRESS_FLAG 1 1241 #define I915_WEDGED (1 << 31) 1242 1243 /** 1244 * Waitqueue to signal when the reset has completed. Used by clients 1245 * that wait for dev_priv->mm.wedged to settle. 1246 */ 1247 wait_queue_head_t reset_queue; 1248 1249 /* Userspace knobs for gpu hang simulation; 1250 * combines both a ring mask, and extra flags 1251 */ 1252 u32 stop_rings; 1253 #define I915_STOP_RING_ALLOW_BAN (1 << 31) 1254 #define I915_STOP_RING_ALLOW_WARN (1 << 30) 1255 1256 /* For missed irq/seqno simulation. */ 1257 unsigned int test_irq_rings; 1258 1259 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ 1260 bool reload_in_reset; 1261 }; 1262 1263 enum modeset_restore { 1264 MODESET_ON_LID_OPEN, 1265 MODESET_DONE, 1266 MODESET_SUSPENDED, 1267 }; 1268 1269 struct ddi_vbt_port_info { 1270 /* 1271 * This is an index in the HDMI/DVI DDI buffer translation table. 1272 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't 1273 * populate this field. 1274 */ 1275 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff 1276 uint8_t hdmi_level_shift; 1277 1278 uint8_t supports_dvi:1; 1279 uint8_t supports_hdmi:1; 1280 uint8_t supports_dp:1; 1281 }; 1282 1283 enum drrs_support_type { 1284 DRRS_NOT_SUPPORTED = 0, 1285 STATIC_DRRS_SUPPORT = 1, 1286 SEAMLESS_DRRS_SUPPORT = 2 1287 }; 1288 1289 struct intel_vbt_data { 1290 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1291 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1292 1293 /* Feature bits */ 1294 unsigned int int_tv_support:1; 1295 unsigned int lvds_dither:1; 1296 unsigned int lvds_vbt:1; 1297 unsigned int int_crt_support:1; 1298 unsigned int lvds_use_ssc:1; 1299 unsigned int display_clock_mode:1; 1300 unsigned int fdi_rx_polarity_inverted:1; 1301 unsigned int has_mipi:1; 1302 int lvds_ssc_freq; 1303 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1304 1305 enum drrs_support_type drrs_type; 1306 1307 /* eDP */ 1308 int edp_rate; 1309 int edp_lanes; 1310 int edp_preemphasis; 1311 int edp_vswing; 1312 bool edp_initialized; 1313 bool edp_support; 1314 int edp_bpp; 1315 struct edp_power_seq edp_pps; 1316 1317 struct { 1318 u16 pwm_freq_hz; 1319 bool present; 1320 bool active_low_pwm; 1321 u8 min_brightness; /* min_brightness/255 of max */ 1322 } backlight; 1323 1324 /* MIPI DSI */ 1325 struct { 1326 u16 port; 1327 u16 panel_id; 1328 struct mipi_config *config; 1329 struct mipi_pps_data *pps; 1330 u8 seq_version; 1331 u32 size; 1332 u8 *data; 1333 u8 *sequence[MIPI_SEQ_MAX]; 1334 } dsi; 1335 1336 int crt_ddc_pin; 1337 1338 int child_dev_num; 1339 union child_device_config *child_dev; 1340 1341 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1342 }; 1343 1344 enum intel_ddb_partitioning { 1345 INTEL_DDB_PART_1_2, 1346 INTEL_DDB_PART_5_6, /* IVB+ */ 1347 }; 1348 1349 struct intel_wm_level { 1350 bool enable; 1351 uint32_t pri_val; 1352 uint32_t spr_val; 1353 uint32_t cur_val; 1354 uint32_t fbc_val; 1355 }; 1356 1357 struct ilk_wm_values { 1358 uint32_t wm_pipe[3]; 1359 uint32_t wm_lp[3]; 1360 uint32_t wm_lp_spr[3]; 1361 uint32_t wm_linetime[3]; 1362 bool enable_fbc_wm; 1363 enum intel_ddb_partitioning partitioning; 1364 }; 1365 1366 /* 1367 * This struct helps tracking the state needed for runtime PM, which puts the 1368 * device in PCI D3 state. Notice that when this happens, nothing on the 1369 * graphics device works, even register access, so we don't get interrupts nor 1370 * anything else. 1371 * 1372 * Every piece of our code that needs to actually touch the hardware needs to 1373 * either call intel_runtime_pm_get or call intel_display_power_get with the 1374 * appropriate power domain. 1375 * 1376 * Our driver uses the autosuspend delay feature, which means we'll only really 1377 * suspend if we stay with zero refcount for a certain amount of time. The 1378 * default value is currently very conservative (see intel_init_runtime_pm), but 1379 * it can be changed with the standard runtime PM files from sysfs. 1380 * 1381 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1382 * goes back to false exactly before we reenable the IRQs. We use this variable 1383 * to check if someone is trying to enable/disable IRQs while they're supposed 1384 * to be disabled. This shouldn't happen and we'll print some error messages in 1385 * case it happens. 1386 * 1387 * For more, read the Documentation/power/runtime_pm.txt. 1388 */ 1389 struct i915_runtime_pm { 1390 bool suspended; 1391 bool _irqs_disabled; 1392 }; 1393 1394 enum intel_pipe_crc_source { 1395 INTEL_PIPE_CRC_SOURCE_NONE, 1396 INTEL_PIPE_CRC_SOURCE_PLANE1, 1397 INTEL_PIPE_CRC_SOURCE_PLANE2, 1398 INTEL_PIPE_CRC_SOURCE_PF, 1399 INTEL_PIPE_CRC_SOURCE_PIPE, 1400 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1401 INTEL_PIPE_CRC_SOURCE_TV, 1402 INTEL_PIPE_CRC_SOURCE_DP_B, 1403 INTEL_PIPE_CRC_SOURCE_DP_C, 1404 INTEL_PIPE_CRC_SOURCE_DP_D, 1405 INTEL_PIPE_CRC_SOURCE_AUTO, 1406 INTEL_PIPE_CRC_SOURCE_MAX, 1407 }; 1408 1409 struct intel_pipe_crc_entry { 1410 uint32_t frame; 1411 uint32_t crc[5]; 1412 }; 1413 1414 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1415 struct intel_pipe_crc { 1416 struct spinlock lock; 1417 bool opened; /* exclusive access to the result file */ 1418 struct intel_pipe_crc_entry *entries; 1419 enum intel_pipe_crc_source source; 1420 int head, tail; 1421 wait_queue_head_t wq; 1422 }; 1423 1424 struct i915_frontbuffer_tracking { 1425 struct lock lock; 1426 1427 /* 1428 * Tracking bits for delayed frontbuffer flushing du to gpu activity or 1429 * scheduled flips. 1430 */ 1431 unsigned busy_bits; 1432 unsigned flip_bits; 1433 }; 1434 1435 struct drm_i915_private { 1436 struct drm_device *dev; 1437 struct kmem_cache *slab; 1438 1439 struct intel_device_info info; 1440 1441 int relative_constants_mode; 1442 1443 device_t *gmbus_bridge; 1444 device_t *bbbus_bridge; 1445 device_t *bbbus; 1446 1447 drm_local_map_t *sarea; 1448 drm_local_map_t *mmio_map; 1449 char __iomem *regs; 1450 1451 struct intel_uncore uncore; 1452 1453 device_t *gmbus; 1454 1455 1456 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1457 * controller on different i2c buses. */ 1458 struct lock gmbus_mutex; 1459 1460 struct _drm_i915_sarea *sarea_priv; 1461 /** 1462 * Base address of the gmbus and gpio block. 1463 */ 1464 uint32_t gpio_mmio_base; 1465 1466 /* MMIO base address for MIPI regs */ 1467 uint32_t mipi_mmio_base; 1468 1469 wait_queue_head_t gmbus_wait_queue; 1470 1471 struct pci_dev *bridge_dev; 1472 struct intel_engine_cs ring[I915_NUM_RINGS]; 1473 struct drm_i915_gem_object *semaphore_obj; 1474 uint32_t last_seqno, next_seqno; 1475 1476 drm_dma_handle_t *status_page_dmah; 1477 struct resource *mch_res; 1478 int mch_res_rid; 1479 1480 /* protects the irq masks */ 1481 struct lock irq_lock; 1482 1483 /* protects the mmio flip data */ 1484 struct spinlock mmio_flip_lock; 1485 1486 bool display_irqs_enabled; 1487 1488 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1489 struct pm_qos_request pm_qos; 1490 1491 /* DPIO indirect register protection */ 1492 struct lock dpio_lock; 1493 1494 /** Cached value of IMR to avoid reads in updating the bitfield */ 1495 union { 1496 u32 irq_mask; 1497 u32 de_irq_mask[I915_MAX_PIPES]; 1498 }; 1499 u32 gt_irq_mask; 1500 u32 pm_irq_mask; 1501 u32 pm_rps_events; 1502 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1503 1504 struct work_struct hotplug_work; 1505 struct { 1506 unsigned long hpd_last_jiffies; 1507 int hpd_cnt; 1508 enum { 1509 HPD_ENABLED = 0, 1510 HPD_DISABLED = 1, 1511 HPD_MARK_DISABLED = 2 1512 } hpd_mark; 1513 } hpd_stats[HPD_NUM_PINS]; 1514 u32 hpd_event_bits; 1515 struct delayed_work hotplug_reenable_work; 1516 1517 struct i915_fbc fbc; 1518 struct i915_drrs drrs; 1519 struct intel_opregion opregion; 1520 struct intel_vbt_data vbt; 1521 1522 /* overlay */ 1523 struct intel_overlay *overlay; 1524 1525 /* backlight registers and fields in struct intel_panel */ 1526 struct spinlock backlight_lock; 1527 1528 /* LVDS info */ 1529 bool no_aux_handshake; 1530 1531 /* protects panel power sequencer state */ 1532 struct lock pps_mutex; 1533 1534 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1535 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1536 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1537 1538 unsigned int fsb_freq, mem_freq, is_ddr3; 1539 unsigned int vlv_cdclk_freq; 1540 1541 /** 1542 * wq - Driver workqueue for GEM. 1543 * 1544 * NOTE: Work items scheduled here are not allowed to grab any modeset 1545 * locks, for otherwise the flushing done in the pageflip code will 1546 * result in deadlocks. 1547 */ 1548 struct workqueue_struct *wq; 1549 1550 /* Display functions */ 1551 struct drm_i915_display_funcs display; 1552 1553 /* PCH chipset type */ 1554 enum intel_pch pch_type; 1555 unsigned short pch_id; 1556 1557 unsigned long quirks; 1558 1559 enum modeset_restore modeset_restore; 1560 struct lock modeset_restore_lock; 1561 1562 struct list_head vm_list; /* Global list of all address spaces */ 1563 struct i915_gtt gtt; /* VM representing the global address space */ 1564 1565 struct i915_gem_mm mm; 1566 #if defined(CONFIG_MMU_NOTIFIER) 1567 DECLARE_HASHTABLE(mmu_notifiers, 7); 1568 #endif 1569 1570 /* Kernel Modesetting */ 1571 1572 struct sdvo_device_mapping sdvo_mappings[2]; 1573 1574 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1575 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1576 wait_queue_head_t pending_flip_queue; 1577 1578 #ifdef CONFIG_DEBUG_FS 1579 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1580 #endif 1581 1582 int num_shared_dpll; 1583 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1584 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1585 1586 /* 1587 * workarounds are currently applied at different places and 1588 * changes are being done to consolidate them so exact count is 1589 * not clear at this point, use a max value for now. 1590 */ 1591 #define I915_MAX_WA_REGS 16 1592 struct { 1593 u32 addr; 1594 u32 value; 1595 /* bitmask representing WA bits */ 1596 u32 mask; 1597 } intel_wa_regs[I915_MAX_WA_REGS]; 1598 u32 num_wa_regs; 1599 1600 /* Reclocking support */ 1601 bool render_reclock_avail; 1602 bool lvds_downclock_avail; 1603 /* indicates the reduced downclock for LVDS*/ 1604 int lvds_downclock; 1605 1606 struct i915_frontbuffer_tracking fb_tracking; 1607 1608 u16 orig_clock; 1609 1610 bool mchbar_need_disable; 1611 1612 struct intel_l3_parity l3_parity; 1613 1614 /* Cannot be determined by PCIID. You must always read a register. */ 1615 size_t ellc_size; 1616 1617 /* gen6+ rps state */ 1618 struct intel_gen6_power_mgmt rps; 1619 1620 /* ilk-only ips/rps state. Everything in here is protected by the global 1621 * mchdev_lock in intel_pm.c */ 1622 struct intel_ilk_power_mgmt ips; 1623 1624 struct i915_power_domains power_domains; 1625 1626 struct i915_psr psr; 1627 1628 struct i915_gpu_error gpu_error; 1629 1630 struct drm_i915_gem_object *vlv_pctx; 1631 1632 #ifdef CONFIG_DRM_I915_FBDEV 1633 /* list of fbdev register on this device */ 1634 struct intel_fbdev *fbdev; 1635 struct work_struct fbdev_suspend_work; 1636 #endif 1637 1638 struct drm_property *broadcast_rgb_property; 1639 struct drm_property *force_audio_property; 1640 1641 uint32_t hw_context_size; 1642 struct list_head context_list; 1643 1644 u32 fdi_rx_config; 1645 1646 u32 suspend_count; 1647 struct i915_suspend_saved_registers regfile; 1648 struct vlv_s0ix_state vlv_s0ix_state; 1649 1650 struct { 1651 /* 1652 * Raw watermark latency values: 1653 * in 0.1us units for WM0, 1654 * in 0.5us units for WM1+. 1655 */ 1656 /* primary */ 1657 uint16_t pri_latency[5]; 1658 /* sprite */ 1659 uint16_t spr_latency[5]; 1660 /* cursor */ 1661 uint16_t cur_latency[5]; 1662 1663 /* current hardware state */ 1664 struct ilk_wm_values hw; 1665 } wm; 1666 1667 struct i915_runtime_pm pm; 1668 1669 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; 1670 u32 long_hpd_port_mask; 1671 u32 short_hpd_port_mask; 1672 struct work_struct dig_port_work; 1673 1674 /* 1675 * if we get a HPD irq from DP and a HPD irq from non-DP 1676 * the non-DP HPD could block the workqueue on a mode config 1677 * mutex getting, that userspace may have taken. However 1678 * userspace is waiting on the DP workqueue to run which is 1679 * blocked behind the non-DP one. 1680 */ 1681 struct workqueue_struct *dp_wq; 1682 1683 uint32_t bios_vgacntr; 1684 1685 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1686 * here! */ 1687 struct i915_dri1_state dri1; 1688 /* Old ums support infrastructure, same warning applies. */ 1689 struct i915_ums_state ums; 1690 1691 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ 1692 struct { 1693 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, 1694 struct intel_engine_cs *ring, 1695 struct intel_context *ctx, 1696 struct drm_i915_gem_execbuffer2 *args, 1697 struct list_head *vmas, 1698 struct drm_i915_gem_object *batch_obj, 1699 u64 exec_start, u32 flags); 1700 int (*init_rings)(struct drm_device *dev); 1701 void (*cleanup_ring)(struct intel_engine_cs *ring); 1702 void (*stop_ring)(struct intel_engine_cs *ring); 1703 } gt; 1704 1705 /* 1706 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1707 * will be rejected. Instead look for a better place. 1708 */ 1709 }; 1710 1711 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1712 { 1713 return dev->dev_private; 1714 } 1715 1716 /* Iterate over initialised rings */ 1717 #define for_each_ring(ring__, dev_priv__, i__) \ 1718 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1719 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1720 1721 enum hdmi_force_audio { 1722 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1723 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1724 HDMI_AUDIO_AUTO, /* trust EDID */ 1725 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1726 }; 1727 1728 #define I915_GTT_OFFSET_NONE ((u32)-1) 1729 1730 struct drm_i915_gem_object_ops { 1731 /* Interface between the GEM object and its backing storage. 1732 * get_pages() is called once prior to the use of the associated set 1733 * of pages before to binding them into the GTT, and put_pages() is 1734 * called after we no longer need them. As we expect there to be 1735 * associated cost with migrating pages between the backing storage 1736 * and making them available for the GPU (e.g. clflush), we may hold 1737 * onto the pages after they are no longer referenced by the GPU 1738 * in case they may be used again shortly (for example migrating the 1739 * pages to a different memory domain within the GTT). put_pages() 1740 * will therefore most likely be called when the object itself is 1741 * being released or under memory pressure (where we attempt to 1742 * reap pages for the shrinker). 1743 */ 1744 int (*get_pages)(struct drm_i915_gem_object *); 1745 void (*put_pages)(struct drm_i915_gem_object *); 1746 int (*dmabuf_export)(struct drm_i915_gem_object *); 1747 void (*release)(struct drm_i915_gem_object *); 1748 }; 1749 1750 /* 1751 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is 1752 * considered to be the frontbuffer for the given plane interface-vise. This 1753 * doesn't mean that the hw necessarily already scans it out, but that any 1754 * rendering (by the cpu or gpu) will land in the frontbuffer eventually. 1755 * 1756 * We have one bit per pipe and per scanout plane type. 1757 */ 1758 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 1759 #define INTEL_FRONTBUFFER_BITS \ 1760 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) 1761 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ 1762 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1763 #define INTEL_FRONTBUFFER_CURSOR(pipe) \ 1764 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1765 #define INTEL_FRONTBUFFER_SPRITE(pipe) \ 1766 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1767 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ 1768 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) 1769 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ 1770 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) 1771 1772 struct drm_i915_gem_object { 1773 struct drm_gem_object base; 1774 1775 const struct drm_i915_gem_object_ops *ops; 1776 1777 /** List of VMAs backed by this object */ 1778 struct list_head vma_list; 1779 1780 /** Stolen memory for this object, instead of being backed by shmem. */ 1781 struct drm_mm_node *stolen; 1782 struct list_head global_list; 1783 1784 struct list_head ring_list; 1785 /** Used in execbuf to temporarily hold a ref */ 1786 struct list_head obj_exec_link; 1787 1788 /** 1789 * This is set if the object is on the active lists (has pending 1790 * rendering and so a non-zero seqno), and is not set if it i s on 1791 * inactive (ready to be unbound) list. 1792 */ 1793 unsigned int active:1; 1794 1795 /** 1796 * This is set if the object has been written to since last bound 1797 * to the GTT 1798 */ 1799 unsigned int dirty:1; 1800 1801 /** 1802 * Fence register bits (if any) for this object. Will be set 1803 * as needed when mapped into the GTT. 1804 * Protected by dev->struct_mutex. 1805 */ 1806 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1807 1808 /** 1809 * Advice: are the backing pages purgeable? 1810 */ 1811 unsigned int madv:2; 1812 1813 /** 1814 * Current tiling mode for the object. 1815 */ 1816 unsigned int tiling_mode:2; 1817 /** 1818 * Whether the tiling parameters for the currently associated fence 1819 * register have changed. Note that for the purposes of tracking 1820 * tiling changes we also treat the unfenced register, the register 1821 * slot that the object occupies whilst it executes a fenced 1822 * command (such as BLT on gen2/3), as a "fence". 1823 */ 1824 unsigned int fence_dirty:1; 1825 1826 /** 1827 * Is the object at the current location in the gtt mappable and 1828 * fenceable? Used to avoid costly recalculations. 1829 */ 1830 unsigned int map_and_fenceable:1; 1831 1832 /** 1833 * Whether the current gtt mapping needs to be mappable (and isn't just 1834 * mappable by accident). Track pin and fault separate for a more 1835 * accurate mappable working set. 1836 */ 1837 unsigned int fault_mappable:1; 1838 unsigned int pin_mappable:1; 1839 unsigned int pin_display:1; 1840 1841 /* 1842 * Is the object to be mapped as read-only to the GPU 1843 * Only honoured if hardware has relevant pte bit 1844 */ 1845 unsigned long gt_ro:1; 1846 unsigned int cache_level:3; 1847 1848 unsigned int has_aliasing_ppgtt_mapping:1; 1849 unsigned int has_global_gtt_mapping:1; 1850 unsigned int has_dma_mapping:1; 1851 1852 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; 1853 1854 vm_page_t *pages; 1855 int pages_pin_count; 1856 1857 /* prime dma-buf support */ 1858 void *dma_buf_vmapping; 1859 int vmapping_count; 1860 1861 struct intel_engine_cs *ring; 1862 1863 /** Breadcrumb of last rendering to the buffer. */ 1864 uint32_t last_read_seqno; 1865 uint32_t last_write_seqno; 1866 /** Breadcrumb of last fenced GPU access to the buffer. */ 1867 uint32_t last_fenced_seqno; 1868 1869 /** Current tiling stride for the object, if it's tiled. */ 1870 uint32_t stride; 1871 1872 /** References from framebuffers, locks out tiling changes. */ 1873 unsigned long framebuffer_references; 1874 1875 /** Record of address bit 17 of each page at last unbind. */ 1876 unsigned long *bit_17; 1877 1878 /** User space pin count and filp owning the pin */ 1879 unsigned long user_pin_count; 1880 struct drm_file *pin_filp; 1881 1882 /** for phy allocated objects */ 1883 struct drm_dma_handle *phys_handle; 1884 1885 union { 1886 struct i915_gem_userptr { 1887 uintptr_t ptr; 1888 unsigned read_only :1; 1889 unsigned workers :4; 1890 #define I915_GEM_USERPTR_MAX_WORKERS 15 1891 1892 struct mm_struct *mm; 1893 struct i915_mmu_object *mn; 1894 struct work_struct *work; 1895 } userptr; 1896 }; 1897 }; 1898 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1899 1900 void i915_gem_track_fb(struct drm_i915_gem_object *old, 1901 struct drm_i915_gem_object *new, 1902 unsigned frontbuffer_bits); 1903 1904 /** 1905 * Request queue structure. 1906 * 1907 * The request queue allows us to note sequence numbers that have been emitted 1908 * and may be associated with active buffers to be retired. 1909 * 1910 * By keeping this list, we can avoid having to do questionable 1911 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1912 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1913 */ 1914 struct drm_i915_gem_request { 1915 /** On Which ring this request was generated */ 1916 struct intel_engine_cs *ring; 1917 1918 /** GEM sequence number associated with this request. */ 1919 uint32_t seqno; 1920 1921 /** Position in the ringbuffer of the start of the request */ 1922 u32 head; 1923 1924 /** Position in the ringbuffer of the end of the request */ 1925 u32 tail; 1926 1927 /** Context related to this request */ 1928 struct intel_context *ctx; 1929 1930 /** Batch buffer related to this request if any */ 1931 struct drm_i915_gem_object *batch_obj; 1932 1933 /** Time at which this request was emitted, in jiffies. */ 1934 unsigned long emitted_jiffies; 1935 1936 /** global list entry for this request */ 1937 struct list_head list; 1938 1939 struct drm_i915_file_private *file_priv; 1940 /** file_priv list entry for this request */ 1941 struct list_head client_list; 1942 }; 1943 1944 struct drm_i915_file_private { 1945 struct drm_i915_private *dev_priv; 1946 struct drm_file *file; 1947 1948 struct { 1949 struct spinlock lock; 1950 struct list_head request_list; 1951 struct delayed_work idle_work; 1952 } mm; 1953 struct idr context_idr; 1954 1955 atomic_t rps_wait_boost; 1956 struct intel_engine_cs *bsd_ring; 1957 }; 1958 1959 /* 1960 * A command that requires special handling by the command parser. 1961 */ 1962 struct drm_i915_cmd_descriptor { 1963 /* 1964 * Flags describing how the command parser processes the command. 1965 * 1966 * CMD_DESC_FIXED: The command has a fixed length if this is set, 1967 * a length mask if not set 1968 * CMD_DESC_SKIP: The command is allowed but does not follow the 1969 * standard length encoding for the opcode range in 1970 * which it falls 1971 * CMD_DESC_REJECT: The command is never allowed 1972 * CMD_DESC_REGISTER: The command should be checked against the 1973 * register whitelist for the appropriate ring 1974 * CMD_DESC_MASTER: The command is allowed if the submitting process 1975 * is the DRM master 1976 */ 1977 u32 flags; 1978 #define CMD_DESC_FIXED (1<<0) 1979 #define CMD_DESC_SKIP (1<<1) 1980 #define CMD_DESC_REJECT (1<<2) 1981 #define CMD_DESC_REGISTER (1<<3) 1982 #define CMD_DESC_BITMASK (1<<4) 1983 #define CMD_DESC_MASTER (1<<5) 1984 1985 /* 1986 * The command's unique identification bits and the bitmask to get them. 1987 * This isn't strictly the opcode field as defined in the spec and may 1988 * also include type, subtype, and/or subop fields. 1989 */ 1990 struct { 1991 u32 value; 1992 u32 mask; 1993 } cmd; 1994 1995 /* 1996 * The command's length. The command is either fixed length (i.e. does 1997 * not include a length field) or has a length field mask. The flag 1998 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 1999 * a length mask. All command entries in a command table must include 2000 * length information. 2001 */ 2002 union { 2003 u32 fixed; 2004 u32 mask; 2005 } length; 2006 2007 /* 2008 * Describes where to find a register address in the command to check 2009 * against the ring's register whitelist. Only valid if flags has the 2010 * CMD_DESC_REGISTER bit set. 2011 */ 2012 struct { 2013 u32 offset; 2014 u32 mask; 2015 } reg; 2016 2017 #define MAX_CMD_DESC_BITMASKS 3 2018 /* 2019 * Describes command checks where a particular dword is masked and 2020 * compared against an expected value. If the command does not match 2021 * the expected value, the parser rejects it. Only valid if flags has 2022 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 2023 * are valid. 2024 * 2025 * If the check specifies a non-zero condition_mask then the parser 2026 * only performs the check when the bits specified by condition_mask 2027 * are non-zero. 2028 */ 2029 struct { 2030 u32 offset; 2031 u32 mask; 2032 u32 expected; 2033 u32 condition_offset; 2034 u32 condition_mask; 2035 } bits[MAX_CMD_DESC_BITMASKS]; 2036 }; 2037 2038 /* 2039 * A table of commands requiring special handling by the command parser. 2040 * 2041 * Each ring has an array of tables. Each table consists of an array of command 2042 * descriptors, which must be sorted with command opcodes in ascending order. 2043 */ 2044 struct drm_i915_cmd_table { 2045 const struct drm_i915_cmd_descriptor *table; 2046 int count; 2047 }; 2048 2049 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ 2050 #define __I915__(p) ({ \ 2051 const struct drm_i915_private *__p; \ 2052 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ 2053 __p = (const struct drm_i915_private *)p; \ 2054 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ 2055 __p = to_i915((const struct drm_device *)p); \ 2056 __p; \ 2057 }) 2058 2059 #define INTEL_INFO(p) (&__I915__(p)->info) 2060 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) 2061 2062 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) 2063 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) 2064 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 2065 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) 2066 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 2067 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) 2068 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) 2069 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 2070 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 2071 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 2072 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) 2073 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 2074 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) 2075 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) 2076 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 2077 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 2078 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) 2079 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 2080 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ 2081 INTEL_DEVID(dev) == 0x0152 || \ 2082 INTEL_DEVID(dev) == 0x015a) 2083 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \ 2084 INTEL_DEVID(dev) == 0x0106 || \ 2085 INTEL_DEVID(dev) == 0x010A) 2086 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 2087 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2088 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 2089 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 2090 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 2091 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 2092 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) 2093 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2094 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \ 2095 (INTEL_DEVID(dev) & 0xf) == 0x6 || \ 2096 (INTEL_DEVID(dev) & 0xf) == 0xe)) 2097 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 2098 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) 2099 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) 2100 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 2101 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2102 /* ULX machines are also considered ULT. */ 2103 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ 2104 INTEL_DEVID(dev) == 0x0A1E) 2105 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 2106 2107 /* 2108 * The genX designation typically refers to the render engine, so render 2109 * capability related checks should use IS_GEN, while display and other checks 2110 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 2111 * chips, etc.). 2112 */ 2113 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 2114 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 2115 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 2116 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 2117 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 2118 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 2119 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 2120 2121 #define RENDER_RING (1<<RCS) 2122 #define BSD_RING (1<<VCS) 2123 #define BLT_RING (1<<BCS) 2124 #define VEBOX_RING (1<<VECS) 2125 #define BSD2_RING (1<<VCS2) 2126 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 2127 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) 2128 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 2129 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 2130 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 2131 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 2132 to_i915(dev)->ellc_size) 2133 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 2134 2135 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 2136 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) 2137 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6) 2138 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev)) 2139 #define USES_PPGTT(dev) (i915.enable_ppgtt) 2140 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) 2141 2142 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 2143 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 2144 2145 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 2146 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 2147 /* 2148 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 2149 * even when in MSI mode. This results in spurious interrupt warnings if the 2150 * legacy irq no. is shared with another device. The kernel then disables that 2151 * interrupt source and so prevents the other device from working properly. 2152 */ 2153 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2154 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 2155 2156 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 2157 * rows, which changed the alignment requirements and fence programming. 2158 */ 2159 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 2160 IS_I915GM(dev))) 2161 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 2162 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2163 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 2164 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 2165 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 2166 2167 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 2168 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 2169 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 2170 2171 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) 2172 2173 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 2174 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2175 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2176 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ 2177 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) 2178 2179 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 2180 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2181 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2182 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2183 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2184 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2185 2186 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) 2187 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 2188 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 2189 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 2190 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 2191 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 2192 2193 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) 2194 2195 /* DPF == dynamic parity feature */ 2196 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 2197 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 2198 2199 #define GT_FREQUENCY_MULTIPLIER 50 2200 2201 #include "i915_trace.h" 2202 2203 extern const struct drm_ioctl_desc i915_ioctls[]; 2204 extern int i915_max_ioctl; 2205 2206 extern int i915_suspend(device_t kdev); 2207 extern int i915_resume(struct drm_device *dev); 2208 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 2209 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 2210 2211 /* i915_params.c */ 2212 struct i915_params { 2213 int modeset; 2214 int panel_ignore_lid; 2215 unsigned int powersave; 2216 int semaphores; 2217 unsigned int lvds_downclock; 2218 int lvds_channel_mode; 2219 int panel_use_ssc; 2220 int vbt_sdvo_panel_type; 2221 int enable_rc6; 2222 int enable_fbc; 2223 int enable_ppgtt; 2224 int enable_execlists; 2225 int enable_psr; 2226 unsigned int preliminary_hw_support; 2227 int disable_power_well; 2228 int enable_ips; 2229 int invert_brightness; 2230 int enable_cmd_parser; 2231 /* leave bools at the end to not create holes */ 2232 bool enable_hangcheck; 2233 bool fastboot; 2234 bool prefault_disable; 2235 int reset; 2236 bool disable_display; 2237 bool disable_vtd_wa; 2238 int use_mmio_flip; 2239 bool mmio_debug; 2240 }; 2241 extern struct i915_params i915 __read_mostly; 2242 2243 /* i915_dma.c */ 2244 void i915_update_dri1_breadcrumb(struct drm_device *dev); 2245 extern void i915_kernel_lost_context(struct drm_device * dev); 2246 extern int i915_driver_load(struct drm_device *, unsigned long flags); 2247 extern int i915_driver_unload(struct drm_device *); 2248 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); 2249 extern void i915_driver_lastclose(struct drm_device * dev); 2250 extern void i915_driver_preclose(struct drm_device *dev, 2251 struct drm_file *file); 2252 extern void i915_driver_postclose(struct drm_device *dev, 2253 struct drm_file *file); 2254 extern int i915_driver_device_is_agp(struct drm_device * dev); 2255 #ifdef CONFIG_COMPAT 2256 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2257 unsigned long arg); 2258 #endif 2259 extern int i915_emit_box(struct drm_device *dev, 2260 struct drm_clip_rect *box, 2261 int DR1, int DR4); 2262 extern int intel_gpu_reset(struct drm_device *dev); 2263 extern int i915_reset(struct drm_device *dev); 2264 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2265 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2266 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2267 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2268 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2269 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); 2270 2271 /* i915_irq.c */ 2272 void i915_queue_hangcheck(struct drm_device *dev); 2273 __printf(3, 4) 2274 void i915_handle_error(struct drm_device *dev, bool wedged, 2275 const char *fmt, ...); 2276 2277 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir, 2278 int new_delay); 2279 extern void intel_irq_init(struct drm_device *dev); 2280 extern void intel_hpd_init(struct drm_device *dev); 2281 2282 extern void intel_uncore_sanitize(struct drm_device *dev); 2283 extern void intel_uncore_early_sanitize(struct drm_device *dev, 2284 bool restore_forcewake); 2285 extern void intel_uncore_init(struct drm_device *dev); 2286 extern void intel_uncore_check_errors(struct drm_device *dev); 2287 extern void intel_uncore_fini(struct drm_device *dev); 2288 2289 void 2290 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 2291 u32 status_mask); 2292 2293 void 2294 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 2295 u32 status_mask); 2296 2297 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2298 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2299 2300 /* i915_gem.c */ 2301 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 2302 struct drm_file *file_priv); 2303 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 2304 struct drm_file *file_priv); 2305 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 2306 struct drm_file *file_priv); 2307 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2308 struct drm_file *file_priv); 2309 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 2310 struct drm_file *file_priv); 2311 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2312 struct drm_file *file_priv); 2313 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2314 struct drm_file *file_priv); 2315 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 2316 struct drm_file *file_priv); 2317 void i915_gem_execbuffer_move_to_active(struct list_head *vmas, 2318 struct intel_engine_cs *ring); 2319 void i915_gem_execbuffer_retire_commands(struct drm_device *dev, 2320 struct drm_file *file, 2321 struct intel_engine_cs *ring, 2322 struct drm_i915_gem_object *obj); 2323 int i915_gem_ringbuffer_submission(struct drm_device *dev, 2324 struct drm_file *file, 2325 struct intel_engine_cs *ring, 2326 struct intel_context *ctx, 2327 struct drm_i915_gem_execbuffer2 *args, 2328 struct list_head *vmas, 2329 struct drm_i915_gem_object *batch_obj, 2330 u64 exec_start, u32 flags); 2331 int i915_gem_execbuffer(struct drm_device *dev, void *data, 2332 struct drm_file *file_priv); 2333 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 2334 struct drm_file *file_priv); 2335 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 2336 struct drm_file *file_priv); 2337 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 2338 struct drm_file *file_priv); 2339 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2340 struct drm_file *file_priv); 2341 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2342 struct drm_file *file); 2343 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2344 struct drm_file *file); 2345 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2346 struct drm_file *file_priv); 2347 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2348 struct drm_file *file_priv); 2349 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 2350 struct drm_file *file_priv); 2351 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 2352 struct drm_file *file_priv); 2353 int i915_gem_set_tiling(struct drm_device *dev, void *data, 2354 struct drm_file *file_priv); 2355 int i915_gem_get_tiling(struct drm_device *dev, void *data, 2356 struct drm_file *file_priv); 2357 int i915_gem_init_userptr(struct drm_device *dev); 2358 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 2359 struct drm_file *file); 2360 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2361 struct drm_file *file_priv); 2362 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2363 struct drm_file *file_priv); 2364 void i915_gem_load(struct drm_device *dev); 2365 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, 2366 long target, 2367 unsigned flags); 2368 #define I915_SHRINK_PURGEABLE 0x1 2369 #define I915_SHRINK_UNBOUND 0x2 2370 #define I915_SHRINK_BOUND 0x4 2371 void *i915_gem_object_alloc(struct drm_device *dev); 2372 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2373 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2374 const struct drm_i915_gem_object_ops *ops); 2375 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2376 size_t size); 2377 void i915_init_vm(struct drm_i915_private *dev_priv, 2378 struct i915_address_space *vm); 2379 void i915_gem_free_object(struct drm_gem_object *obj); 2380 void i915_gem_vma_destroy(struct i915_vma *vma); 2381 2382 #define PIN_MAPPABLE 0x1 2383 #define PIN_NONBLOCK 0x2 2384 #define PIN_GLOBAL 0x4 2385 #define PIN_OFFSET_BIAS 0x8 2386 #define PIN_OFFSET_MASK (~4095) 2387 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 2388 struct i915_address_space *vm, 2389 uint32_t alignment, 2390 uint64_t flags); 2391 int __must_check i915_vma_unbind(struct i915_vma *vma); 2392 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2393 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2394 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2395 void i915_gem_lastclose(struct drm_device *dev); 2396 2397 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 2398 int *needs_clflush); 2399 2400 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2401 static inline struct vm_page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2402 { 2403 return obj->pages[n]; 2404 } 2405 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2406 { 2407 BUG_ON(obj->pages == NULL); 2408 obj->pages_pin_count++; 2409 } 2410 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2411 { 2412 BUG_ON(obj->pages_pin_count == 0); 2413 obj->pages_pin_count--; 2414 } 2415 2416 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2417 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2418 struct intel_engine_cs *to); 2419 void i915_vma_move_to_active(struct i915_vma *vma, 2420 struct intel_engine_cs *ring); 2421 int i915_gem_dumb_create(struct drm_file *file_priv, 2422 struct drm_device *dev, 2423 struct drm_mode_create_dumb *args); 2424 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2425 uint32_t handle, uint64_t *offset); 2426 /** 2427 * Returns true if seq1 is later than seq2. 2428 */ 2429 static inline bool 2430 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2431 { 2432 return (int32_t)(seq1 - seq2) >= 0; 2433 } 2434 2435 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2436 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2437 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 2438 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 2439 2440 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); 2441 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); 2442 2443 struct drm_i915_gem_request * 2444 i915_gem_find_active_request(struct intel_engine_cs *ring); 2445 2446 bool i915_gem_retire_requests(struct drm_device *dev); 2447 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); 2448 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2449 bool interruptible); 2450 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno); 2451 2452 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2453 { 2454 return unlikely(atomic_read(&error->reset_counter) 2455 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2456 } 2457 2458 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2459 { 2460 return atomic_read(&error->reset_counter) & I915_WEDGED; 2461 } 2462 2463 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2464 { 2465 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2466 } 2467 2468 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) 2469 { 2470 return dev_priv->gpu_error.stop_rings == 0 || 2471 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; 2472 } 2473 2474 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) 2475 { 2476 return dev_priv->gpu_error.stop_rings == 0 || 2477 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; 2478 } 2479 2480 void i915_gem_reset(struct drm_device *dev); 2481 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 2482 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 2483 int __must_check i915_gem_init(struct drm_device *dev); 2484 int i915_gem_init_rings(struct drm_device *dev); 2485 int __must_check i915_gem_init_hw(struct drm_device *dev); 2486 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); 2487 void i915_gem_init_swizzling(struct drm_device *dev); 2488 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 2489 int __must_check i915_gpu_idle(struct drm_device *dev); 2490 int __must_check i915_gem_suspend(struct drm_device *dev); 2491 int __i915_add_request(struct intel_engine_cs *ring, 2492 struct drm_file *file, 2493 struct drm_i915_gem_object *batch_obj, 2494 u32 *seqno); 2495 #define i915_add_request(ring, seqno) \ 2496 __i915_add_request(ring, NULL, NULL, seqno) 2497 int __must_check i915_wait_seqno(struct intel_engine_cs *ring, 2498 uint32_t seqno); 2499 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres); 2500 int __must_check 2501 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 2502 bool write); 2503 int __must_check 2504 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 2505 int __must_check 2506 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 2507 u32 alignment, 2508 struct intel_engine_cs *pipelined); 2509 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 2510 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 2511 int align); 2512 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 2513 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2514 2515 uint32_t 2516 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 2517 uint32_t 2518 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2519 int tiling_mode, bool fenced); 2520 2521 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2522 enum i915_cache_level cache_level); 2523 2524 #if 0 2525 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2526 struct dma_buf *dma_buf); 2527 2528 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 2529 struct drm_gem_object *gem_obj, int flags); 2530 #endif 2531 2532 void i915_gem_restore_fences(struct drm_device *dev); 2533 2534 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, 2535 struct i915_address_space *vm); 2536 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 2537 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 2538 struct i915_address_space *vm); 2539 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 2540 struct i915_address_space *vm); 2541 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 2542 struct i915_address_space *vm); 2543 struct i915_vma * 2544 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2545 struct i915_address_space *vm); 2546 2547 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); 2548 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { 2549 struct i915_vma *vma; 2550 list_for_each_entry(vma, &obj->vma_list, vma_link) 2551 if (vma->pin_count > 0) 2552 return true; 2553 return false; 2554 } 2555 2556 /* Some GGTT VM helpers */ 2557 #define i915_obj_to_ggtt(obj) \ 2558 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 2559 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2560 { 2561 struct i915_address_space *ggtt = 2562 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2563 return vm == ggtt; 2564 } 2565 2566 static inline struct i915_hw_ppgtt * 2567 i915_vm_to_ppgtt(struct i915_address_space *vm) 2568 { 2569 WARN_ON(i915_is_ggtt(vm)); 2570 2571 return container_of(vm, struct i915_hw_ppgtt, base); 2572 } 2573 2574 2575 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2576 { 2577 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj)); 2578 } 2579 2580 static inline unsigned long 2581 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) 2582 { 2583 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj)); 2584 } 2585 2586 static inline unsigned long 2587 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2588 { 2589 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); 2590 } 2591 2592 static inline int __must_check 2593 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2594 uint32_t alignment, 2595 unsigned flags) 2596 { 2597 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), 2598 alignment, flags | PIN_GLOBAL); 2599 } 2600 2601 static inline int 2602 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) 2603 { 2604 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); 2605 } 2606 2607 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); 2608 2609 /* i915_gem_context.c */ 2610 int __must_check i915_gem_context_init(struct drm_device *dev); 2611 void i915_gem_context_fini(struct drm_device *dev); 2612 void i915_gem_context_reset(struct drm_device *dev); 2613 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); 2614 int i915_gem_context_enable(struct drm_i915_private *dev_priv); 2615 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2616 int i915_switch_context(struct intel_engine_cs *ring, 2617 struct intel_context *to); 2618 struct intel_context * 2619 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 2620 void i915_gem_context_free(struct kref *ctx_ref); 2621 struct drm_i915_gem_object * 2622 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); 2623 static inline void i915_gem_context_reference(struct intel_context *ctx) 2624 { 2625 kref_get(&ctx->ref); 2626 } 2627 2628 static inline void i915_gem_context_unreference(struct intel_context *ctx) 2629 { 2630 kref_put(&ctx->ref, i915_gem_context_free); 2631 } 2632 2633 static inline bool i915_gem_context_is_default(const struct intel_context *c) 2634 { 2635 return c->user_handle == DEFAULT_CONTEXT_HANDLE; 2636 } 2637 2638 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2639 struct drm_file *file); 2640 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2641 struct drm_file *file); 2642 2643 /* i915_gem_evict.c */ 2644 int __must_check i915_gem_evict_something(struct drm_device *dev, 2645 struct i915_address_space *vm, 2646 int min_size, 2647 unsigned alignment, 2648 unsigned cache_level, 2649 unsigned long start, 2650 unsigned long end, 2651 unsigned flags); 2652 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 2653 int i915_gem_evict_everything(struct drm_device *dev); 2654 2655 /* belongs in i915_gem_gtt.h */ 2656 static inline void i915_gem_chipset_flush(struct drm_device *dev) 2657 { 2658 if (INTEL_INFO(dev)->gen < 6) 2659 intel_gtt_chipset_flush(); 2660 } 2661 2662 /* i915_gem_stolen.c */ 2663 int i915_gem_init_stolen(struct drm_device *dev); 2664 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); 2665 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 2666 void i915_gem_cleanup_stolen(struct drm_device *dev); 2667 struct drm_i915_gem_object * 2668 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 2669 struct drm_i915_gem_object * 2670 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 2671 u32 stolen_offset, 2672 u32 gtt_offset, 2673 u32 size); 2674 2675 /* i915_gem_tiling.c */ 2676 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2677 { 2678 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2679 2680 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2681 obj->tiling_mode != I915_TILING_NONE; 2682 } 2683 2684 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 2685 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 2686 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 2687 2688 /* i915_gem_debug.c */ 2689 #if WATCH_LISTS 2690 int i915_verify_lists(struct drm_device *dev); 2691 #else 2692 #define i915_verify_lists(dev) 0 2693 #endif 2694 2695 /* i915_debugfs.c */ 2696 int i915_debugfs_init(struct drm_minor *minor); 2697 void i915_debugfs_cleanup(struct drm_minor *minor); 2698 #ifdef CONFIG_DEBUG_FS 2699 void intel_display_crc_init(struct drm_device *dev); 2700 #else 2701 static inline void intel_display_crc_init(struct drm_device *dev) {} 2702 #endif 2703 2704 /* i915_gpu_error.c */ 2705 __printf(2, 3) 2706 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 2707 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 2708 const struct i915_error_state_file_priv *error); 2709 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 2710 struct drm_i915_private *i915, 2711 size_t count, loff_t pos); 2712 static inline void i915_error_state_buf_release( 2713 struct drm_i915_error_state_buf *eb) 2714 { 2715 kfree(eb->buf); 2716 } 2717 void i915_capture_error_state(struct drm_device *dev, bool wedge, 2718 const char *error_msg); 2719 void i915_error_state_get(struct drm_device *dev, 2720 struct i915_error_state_file_priv *error_priv); 2721 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 2722 void i915_destroy_error_state(struct drm_device *dev); 2723 2724 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 2725 const char *i915_cache_level_str(struct drm_i915_private *i915, int type); 2726 2727 /* i915_cmd_parser.c */ 2728 int i915_cmd_parser_get_version(void); 2729 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); 2730 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); 2731 bool i915_needs_cmd_parser(struct intel_engine_cs *ring); 2732 int i915_parse_cmds(struct intel_engine_cs *ring, 2733 struct drm_i915_gem_object *batch_obj, 2734 u32 batch_start_offset, 2735 bool is_master); 2736 2737 /* i915_suspend.c */ 2738 extern int i915_save_state(struct drm_device *dev); 2739 extern int i915_restore_state(struct drm_device *dev); 2740 2741 /* i915_ums.c */ 2742 void i915_save_display_reg(struct drm_device *dev); 2743 void i915_restore_display_reg(struct drm_device *dev); 2744 2745 /* i915_sysfs.c */ 2746 void i915_setup_sysfs(struct drm_device *dev_priv); 2747 void i915_teardown_sysfs(struct drm_device *dev_priv); 2748 2749 /* intel_i2c.c */ 2750 extern int intel_setup_gmbus(struct drm_device *dev); 2751 extern void intel_teardown_gmbus(struct drm_device *dev); 2752 static inline bool intel_gmbus_is_port_valid(unsigned port) 2753 { 2754 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 2755 } 2756 2757 extern struct device *intel_gmbus_get_adapter( 2758 struct drm_i915_private *dev_priv, unsigned port); 2759 extern void intel_gmbus_set_speed(struct device *adapter, int speed); 2760 extern void intel_gmbus_force_bit(struct device *adapter, bool force_bit); 2761 static inline bool intel_gmbus_is_forced_bit(struct device *adapter) 2762 { 2763 struct intel_iic_softc *sc; 2764 sc = device_get_softc(device_get_parent(adapter)); 2765 2766 return sc->force_bit_dev; 2767 } 2768 extern void intel_i2c_reset(struct drm_device *dev); 2769 2770 /* intel_opregion.c */ 2771 struct intel_encoder; 2772 #ifdef CONFIG_ACPI 2773 extern int intel_opregion_setup(struct drm_device *dev); 2774 extern void intel_opregion_init(struct drm_device *dev); 2775 extern void intel_opregion_fini(struct drm_device *dev); 2776 extern void intel_opregion_asle_intr(struct drm_device *dev); 2777 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 2778 bool enable); 2779 extern int intel_opregion_notify_adapter(struct drm_device *dev, 2780 pci_power_t state); 2781 #else 2782 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } 2783 static inline void intel_opregion_init(struct drm_device *dev) { return; } 2784 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 2785 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 2786 static inline int 2787 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 2788 { 2789 return 0; 2790 } 2791 static inline int 2792 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 2793 { 2794 return 0; 2795 } 2796 #endif 2797 2798 /* intel_acpi.c */ 2799 #ifdef CONFIG_ACPI 2800 extern void intel_register_dsm_handler(void); 2801 extern void intel_unregister_dsm_handler(void); 2802 #else 2803 static inline void intel_register_dsm_handler(void) { return; } 2804 static inline void intel_unregister_dsm_handler(void) { return; } 2805 #endif /* CONFIG_ACPI */ 2806 2807 /* modesetting */ 2808 extern void intel_modeset_init_hw(struct drm_device *dev); 2809 extern void intel_modeset_suspend_hw(struct drm_device *dev); 2810 extern void intel_modeset_init(struct drm_device *dev); 2811 extern void intel_modeset_gem_init(struct drm_device *dev); 2812 extern void intel_modeset_cleanup(struct drm_device *dev); 2813 extern void intel_connector_unregister(struct intel_connector *); 2814 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 2815 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 2816 bool force_restore); 2817 extern void i915_redisable_vga(struct drm_device *dev); 2818 extern void i915_redisable_vga_power_on(struct drm_device *dev); 2819 extern void gen8_fbc_sw_flush(struct drm_device *dev, u32 value); 2820 extern void intel_disable_fbc(struct drm_device *dev); 2821 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2822 extern void intel_init_pch_refclk(struct drm_device *dev); 2823 extern void gen6_set_rps(struct drm_device *dev, u8 val); 2824 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2825 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, 2826 bool enable); 2827 extern void intel_detect_pch(struct drm_device *dev); 2828 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 2829 extern int intel_enable_rc6(const struct drm_device *dev); 2830 2831 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 2832 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2833 struct drm_file *file); 2834 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 2835 struct drm_file *file); 2836 2837 struct intel_device_info *i915_get_device_id(int device); 2838 2839 void intel_notify_mmio_flip(struct intel_engine_cs *ring); 2840 2841 /* overlay */ 2842 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2843 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 2844 struct intel_overlay_error_state *error); 2845 2846 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 2847 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2848 struct drm_device *dev, 2849 struct intel_display_error_state *error); 2850 2851 /* On SNB platform, before reading ring registers forcewake bit 2852 * must be set to prevent GT core from power down and stale values being 2853 * returned. 2854 */ 2855 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); 2856 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); 2857 void assert_force_wake_inactive(struct drm_i915_private *dev_priv); 2858 2859 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 2860 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 2861 2862 /* intel_sideband.c */ 2863 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 2864 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 2865 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 2866 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 2867 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2868 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 2869 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2870 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 2871 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2872 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 2873 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2874 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 2875 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2876 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg); 2877 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val); 2878 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 2879 enum intel_sbi_destination destination); 2880 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2881 enum intel_sbi_destination destination); 2882 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 2883 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2884 2885 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); 2886 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); 2887 2888 #define FORCEWAKE_RENDER (1 << 0) 2889 #define FORCEWAKE_MEDIA (1 << 1) 2890 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) 2891 2892 2893 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 2894 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 2895 2896 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 2897 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 2898 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 2899 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 2900 2901 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 2902 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 2903 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 2904 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 2905 2906 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 2907 * will be implemented using 2 32-bit writes in an arbitrary order with 2908 * an arbitrary delay between them. This can cause the hardware to 2909 * act upon the intermediate value, possibly leading to corruption and 2910 * machine death. You have been warned. 2911 */ 2912 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 2913 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 2914 2915 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 2916 u32 upper = I915_READ(upper_reg); \ 2917 u32 lower = I915_READ(lower_reg); \ 2918 u32 tmp = I915_READ(upper_reg); \ 2919 if (upper != tmp) { \ 2920 upper = tmp; \ 2921 lower = I915_READ(lower_reg); \ 2922 WARN_ON(I915_READ(upper_reg) != upper); \ 2923 } \ 2924 (u64)upper << 32 | lower; }) 2925 2926 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 2927 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 2928 2929 /* "Broadcast RGB" property */ 2930 #define INTEL_BROADCAST_RGB_AUTO 0 2931 #define INTEL_BROADCAST_RGB_FULL 1 2932 #define INTEL_BROADCAST_RGB_LIMITED 2 2933 2934 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 2935 { 2936 if (IS_VALLEYVIEW(dev)) 2937 return VLV_VGACNTRL; 2938 else if (INTEL_INFO(dev)->gen >= 5) 2939 return CPU_VGACNTRL; 2940 else 2941 return VGACNTRL; 2942 } 2943 2944 static inline void __user *to_user_ptr(u64 address) 2945 { 2946 return (void __user *)(uintptr_t)address; 2947 } 2948 2949 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 2950 { 2951 unsigned long j = msecs_to_jiffies(m); 2952 2953 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2954 } 2955 2956 static inline unsigned long 2957 timespec_to_jiffies_timeout(const struct timespec *value) 2958 { 2959 unsigned long j = timespec_to_jiffies(value); 2960 2961 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2962 } 2963 2964 /* 2965 * If you need to wait X milliseconds between events A and B, but event B 2966 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 2967 * when event A happened, then just before event B you call this function and 2968 * pass the timestamp as the first argument, and X as the second argument. 2969 */ 2970 static inline void 2971 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 2972 { 2973 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 2974 2975 /* 2976 * Don't re-read the value of "jiffies" every time since it may change 2977 * behind our back and break the math. 2978 */ 2979 tmp_jiffies = jiffies; 2980 target_jiffies = timestamp_jiffies + 2981 msecs_to_jiffies_timeout(to_wait_ms); 2982 2983 if (time_after(target_jiffies, tmp_jiffies)) { 2984 remaining_jiffies = target_jiffies - tmp_jiffies; 2985 2986 #if 0 2987 while (remaining_jiffies) 2988 remaining_jiffies = 2989 schedule_timeout_uninterruptible(remaining_jiffies); 2990 #else 2991 msleep(jiffies_to_msecs(remaining_jiffies)); 2992 #endif 2993 } 2994 } 2995 2996 #endif 2997