1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 29 */ 30 31 #ifndef _I915_DRV_H_ 32 #define _I915_DRV_H_ 33 34 #include <sys/eventhandler.h> 35 36 #include <dev/agp/agp_i810.h> 37 #include "i915_reg.h" 38 #include "intel_bios.h" 39 #include "intel_ringbuffer.h" 40 41 /* General customization: 42 */ 43 44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 45 46 #define DRIVER_NAME "i915" 47 #define DRIVER_DESC "Intel Graphics" 48 #define DRIVER_DATE "20080730" 49 50 MALLOC_DECLARE(DRM_I915_GEM); 51 52 enum i915_pipe { 53 PIPE_A = 0, 54 PIPE_B, 55 PIPE_C, 56 I915_MAX_PIPES 57 }; 58 #define pipe_name(p) ((p) + 'A') 59 #define I915_NUM_PIPE 2 60 61 enum plane { 62 PLANE_A = 0, 63 PLANE_B, 64 PLANE_C, 65 }; 66 #define plane_name(p) ((p) + 'A') 67 68 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 69 70 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 71 72 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 73 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 74 if ((intel_encoder)->base.crtc == (__crtc)) 75 76 struct intel_pch_pll { 77 int refcount; /* count of number of CRTCs sharing this PLL */ 78 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 79 bool on; /* is the PLL actually active? Disabled during modeset */ 80 int pll_reg; 81 int fp0_reg; 82 int fp1_reg; 83 }; 84 #define I915_NUM_PLLS 2 85 86 struct intel_ddi_plls { 87 int spll_refcount; 88 int wrpll1_refcount; 89 int wrpll2_refcount; 90 }; 91 92 /* Interface history: 93 * 94 * 1.1: Original. 95 * 1.2: Add Power Management 96 * 1.3: Add vblank support 97 * 1.4: Fix cmdbuffer path, add heap destroy 98 * 1.5: Add vblank pipe configuration 99 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 100 * - Support vertical blank on secondary display pipe 101 */ 102 #define DRIVER_MAJOR 1 103 #define DRIVER_MINOR 6 104 #define DRIVER_PATCHLEVEL 0 105 106 #define WATCH_COHERENCY 0 107 #define WATCH_BUF 0 108 #define WATCH_EXEC 0 109 #define WATCH_LRU 0 110 #define WATCH_RELOC 0 111 #define WATCH_INACTIVE 0 112 #define WATCH_PWRITE 0 113 114 #define I915_GEM_PHYS_CURSOR_0 1 115 #define I915_GEM_PHYS_CURSOR_1 2 116 #define I915_GEM_PHYS_OVERLAY_REGS 3 117 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 118 119 struct drm_i915_gem_phys_object { 120 int id; 121 drm_dma_handle_t *handle; 122 struct drm_i915_gem_object *cur_obj; 123 }; 124 125 struct drm_i915_private; 126 127 struct drm_i915_display_funcs { 128 void (*dpms)(struct drm_crtc *crtc, int mode); 129 bool (*fbc_enabled)(struct drm_device *dev); 130 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 131 void (*disable_fbc)(struct drm_device *dev); 132 int (*get_display_clock_speed)(struct drm_device *dev); 133 int (*get_fifo_size)(struct drm_device *dev, int plane); 134 void (*update_wm)(struct drm_device *dev); 135 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 136 uint32_t sprite_width, int pixel_size); 137 int (*crtc_mode_set)(struct drm_crtc *crtc, 138 struct drm_display_mode *mode, 139 struct drm_display_mode *adjusted_mode, 140 int x, int y, 141 struct drm_framebuffer *old_fb); 142 void (*write_eld)(struct drm_connector *connector, 143 struct drm_crtc *crtc); 144 void (*fdi_link_train)(struct drm_crtc *crtc); 145 void (*init_clock_gating)(struct drm_device *dev); 146 void (*init_pch_clock_gating)(struct drm_device *dev); 147 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 148 struct drm_framebuffer *fb, 149 struct drm_i915_gem_object *obj); 150 void (*force_wake_get)(struct drm_i915_private *dev_priv); 151 void (*force_wake_put)(struct drm_i915_private *dev_priv); 152 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 153 int x, int y); 154 /* clock updates for mode set */ 155 /* cursor updates */ 156 /* render clock increase/decrease */ 157 /* display clock increase/decrease */ 158 /* pll clock increase/decrease */ 159 }; 160 161 struct intel_device_info { 162 u8 gen; 163 u8 is_mobile:1; 164 u8 is_i85x:1; 165 u8 is_i915g:1; 166 u8 is_i945gm:1; 167 u8 is_g33:1; 168 u8 need_gfx_hws:1; 169 u8 is_g4x:1; 170 u8 is_pineview:1; 171 u8 is_broadwater:1; 172 u8 is_crestline:1; 173 u8 is_ivybridge:1; 174 u8 is_valleyview:1; 175 u8 has_force_wake:1; 176 u8 is_haswell:1; 177 u8 has_fbc:1; 178 u8 has_pipe_cxsr:1; 179 u8 has_hotplug:1; 180 u8 cursor_needs_physical:1; 181 u8 has_overlay:1; 182 u8 overlay_needs_physical:1; 183 u8 supports_tv:1; 184 u8 has_bsd_ring:1; 185 u8 has_blt_ring:1; 186 u8 has_llc:1; 187 }; 188 189 #define I915_PPGTT_PD_ENTRIES 512 190 #define I915_PPGTT_PT_ENTRIES 1024 191 struct i915_hw_ppgtt { 192 unsigned num_pd_entries; 193 vm_page_t *pt_pages; 194 uint32_t pd_offset; 195 vm_paddr_t *pt_dma_addr; 196 vm_paddr_t scratch_page_dma_addr; 197 }; 198 199 enum no_fbc_reason { 200 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 201 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 202 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 203 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 204 FBC_BAD_PLANE, /* fbc not supported on plane */ 205 FBC_NOT_TILED, /* buffer not tiled */ 206 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 207 FBC_MODULE_PARAM, 208 }; 209 210 /* defined intel_pm.c */ 211 extern struct lock mchdev_lock; 212 213 struct mem_block { 214 struct mem_block *next; 215 struct mem_block *prev; 216 int start; 217 int size; 218 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 219 }; 220 221 struct opregion_header; 222 struct opregion_acpi; 223 struct opregion_swsci; 224 struct opregion_asle; 225 226 struct intel_opregion { 227 struct opregion_header *header; 228 struct opregion_acpi *acpi; 229 struct opregion_swsci *swsci; 230 struct opregion_asle *asle; 231 void *vbt; 232 u32 *lid_state; 233 }; 234 #define OPREGION_SIZE (8*1024) 235 236 #define I915_FENCE_REG_NONE -1 237 #define I915_MAX_NUM_FENCES 16 238 /* 16 fences + sign bit for FENCE_REG_NONE */ 239 #define I915_MAX_NUM_FENCE_BITS 5 240 241 struct drm_i915_fence_reg { 242 struct list_head lru_list; 243 struct drm_i915_gem_object *obj; 244 uint32_t setup_seqno; 245 int pin_count; 246 }; 247 248 struct sdvo_device_mapping { 249 u8 initialized; 250 u8 dvo_port; 251 u8 slave_addr; 252 u8 dvo_wiring; 253 u8 i2c_pin; 254 u8 ddc_pin; 255 }; 256 257 enum intel_pch { 258 PCH_IBX, /* Ibexpeak PCH */ 259 PCH_CPT, /* Cougarpoint PCH */ 260 }; 261 262 #define QUIRK_PIPEA_FORCE (1<<0) 263 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 264 265 struct intel_fbdev; 266 struct intel_fbc_work; 267 268 typedef struct drm_i915_private { 269 struct drm_device *dev; 270 271 device_t *gmbus_bridge; 272 device_t *bbbus_bridge; 273 device_t *gmbus; 274 device_t *bbbus; 275 /** gmbus_sx protects against concurrent usage of the single hw gmbus 276 * controller on different i2c buses. */ 277 struct lock gmbus_lock; 278 279 int has_gem; 280 int relative_constants_mode; 281 282 drm_local_map_t *sarea; 283 drm_local_map_t *mmio_map; 284 285 /** gt_fifo_count and the subsequent register write are synchronized 286 * with dev->struct_mutex. */ 287 unsigned gt_fifo_count; 288 /** forcewake_count is protected by gt_lock */ 289 unsigned forcewake_count; 290 /** gt_lock is also taken in irq contexts. */ 291 struct lock gt_lock; 292 293 drm_i915_sarea_t *sarea_priv; 294 /* drm_i915_ring_buffer_t ring; */ 295 struct intel_ring_buffer rings[I915_NUM_RINGS]; 296 uint32_t next_seqno; 297 298 drm_dma_handle_t *status_page_dmah; 299 void *hw_status_page; 300 dma_addr_t dma_status_page; 301 uint32_t counter; 302 unsigned int status_gfx_addr; 303 drm_local_map_t hws_map; 304 struct drm_gem_object *hws_obj; 305 306 struct drm_i915_gem_object *pwrctx; 307 struct drm_i915_gem_object *renderctx; 308 309 unsigned int cpp; 310 int back_offset; 311 int front_offset; 312 int current_page; 313 int page_flipping; 314 315 atomic_t irq_received; 316 u32 trace_irq_seqno; 317 318 /** Cached value of IER to avoid reads in updating the bitfield */ 319 u32 pipestat[2]; 320 u32 irq_mask; 321 u32 gt_irq_mask; 322 u32 pch_irq_mask; 323 struct lock irq_lock; 324 325 u32 hotplug_supported_mask; 326 327 int tex_lru_log_granularity; 328 int allow_batchbuffer; 329 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 330 int vblank_pipe; 331 332 int num_pipe; 333 int num_pch_pll; 334 335 /* For hangcheck timer */ 336 #define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 337 int hangcheck_count; 338 uint32_t last_acthd; 339 uint32_t last_acthd_bsd; 340 uint32_t last_acthd_blt; 341 uint32_t last_instdone; 342 uint32_t last_instdone1; 343 344 struct intel_opregion opregion; 345 346 347 /* overlay */ 348 struct intel_overlay *overlay; 349 bool sprite_scaling_enabled; 350 351 /* LVDS info */ 352 int backlight_level; /* restore backlight to this value */ 353 bool backlight_enabled; 354 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 355 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 356 357 /* Feature bits from the VBIOS */ 358 unsigned int int_tv_support:1; 359 unsigned int lvds_dither:1; 360 unsigned int lvds_vbt:1; 361 unsigned int int_crt_support:1; 362 unsigned int lvds_use_ssc:1; 363 unsigned int display_clock_mode:1; 364 int lvds_ssc_freq; 365 struct { 366 int rate; 367 int lanes; 368 int preemphasis; 369 int vswing; 370 371 bool initialized; 372 bool support; 373 int bpp; 374 struct edp_power_seq pps; 375 } edp; 376 bool no_aux_handshake; 377 378 int crt_ddc_pin; 379 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 380 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 381 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 382 383 /* PCH chipset type */ 384 enum intel_pch pch_type; 385 386 /* Display functions */ 387 struct drm_i915_display_funcs display; 388 389 unsigned long quirks; 390 391 /* Register state */ 392 bool modeset_on_lid; 393 u8 saveLBB; 394 u32 saveDSPACNTR; 395 u32 saveDSPBCNTR; 396 u32 saveDSPARB; 397 u32 saveHWS; 398 u32 savePIPEACONF; 399 u32 savePIPEBCONF; 400 u32 savePIPEASRC; 401 u32 savePIPEBSRC; 402 u32 saveFPA0; 403 u32 saveFPA1; 404 u32 saveDPLL_A; 405 u32 saveDPLL_A_MD; 406 u32 saveHTOTAL_A; 407 u32 saveHBLANK_A; 408 u32 saveHSYNC_A; 409 u32 saveVTOTAL_A; 410 u32 saveVBLANK_A; 411 u32 saveVSYNC_A; 412 u32 saveBCLRPAT_A; 413 u32 saveTRANSACONF; 414 u32 saveTRANS_HTOTAL_A; 415 u32 saveTRANS_HBLANK_A; 416 u32 saveTRANS_HSYNC_A; 417 u32 saveTRANS_VTOTAL_A; 418 u32 saveTRANS_VBLANK_A; 419 u32 saveTRANS_VSYNC_A; 420 u32 savePIPEASTAT; 421 u32 saveDSPASTRIDE; 422 u32 saveDSPASIZE; 423 u32 saveDSPAPOS; 424 u32 saveDSPAADDR; 425 u32 saveDSPASURF; 426 u32 saveDSPATILEOFF; 427 u32 savePFIT_PGM_RATIOS; 428 u32 saveBLC_HIST_CTL; 429 u32 saveBLC_PWM_CTL; 430 u32 saveBLC_PWM_CTL2; 431 u32 saveBLC_CPU_PWM_CTL; 432 u32 saveBLC_CPU_PWM_CTL2; 433 u32 saveFPB0; 434 u32 saveFPB1; 435 u32 saveDPLL_B; 436 u32 saveDPLL_B_MD; 437 u32 saveHTOTAL_B; 438 u32 saveHBLANK_B; 439 u32 saveHSYNC_B; 440 u32 saveVTOTAL_B; 441 u32 saveVBLANK_B; 442 u32 saveVSYNC_B; 443 u32 saveBCLRPAT_B; 444 u32 saveTRANSBCONF; 445 u32 saveTRANS_HTOTAL_B; 446 u32 saveTRANS_HBLANK_B; 447 u32 saveTRANS_HSYNC_B; 448 u32 saveTRANS_VTOTAL_B; 449 u32 saveTRANS_VBLANK_B; 450 u32 saveTRANS_VSYNC_B; 451 u32 savePIPEBSTAT; 452 u32 saveDSPBSTRIDE; 453 u32 saveDSPBSIZE; 454 u32 saveDSPBPOS; 455 u32 saveDSPBADDR; 456 u32 saveDSPBSURF; 457 u32 saveDSPBTILEOFF; 458 u32 saveVGA0; 459 u32 saveVGA1; 460 u32 saveVGA_PD; 461 u32 saveVGACNTRL; 462 u32 saveADPA; 463 u32 saveLVDS; 464 u32 savePP_ON_DELAYS; 465 u32 savePP_OFF_DELAYS; 466 u32 saveDVOA; 467 u32 saveDVOB; 468 u32 saveDVOC; 469 u32 savePP_ON; 470 u32 savePP_OFF; 471 u32 savePP_CONTROL; 472 u32 savePP_DIVISOR; 473 u32 savePFIT_CONTROL; 474 u32 save_palette_a[256]; 475 u32 save_palette_b[256]; 476 u32 saveDPFC_CB_BASE; 477 u32 saveFBC_CFB_BASE; 478 u32 saveFBC_LL_BASE; 479 u32 saveFBC_CONTROL; 480 u32 saveFBC_CONTROL2; 481 u32 saveIER; 482 u32 saveIIR; 483 u32 saveIMR; 484 u32 saveDEIER; 485 u32 saveDEIMR; 486 u32 saveGTIER; 487 u32 saveGTIMR; 488 u32 saveFDI_RXA_IMR; 489 u32 saveFDI_RXB_IMR; 490 u32 saveCACHE_MODE_0; 491 u32 saveMI_ARB_STATE; 492 u32 saveSWF0[16]; 493 u32 saveSWF1[16]; 494 u32 saveSWF2[3]; 495 u8 saveMSR; 496 u8 saveSR[8]; 497 u8 saveGR[25]; 498 u8 saveAR_INDEX; 499 u8 saveAR[21]; 500 u8 saveDACMASK; 501 u8 saveCR[37]; 502 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 503 u32 saveCURACNTR; 504 u32 saveCURAPOS; 505 u32 saveCURABASE; 506 u32 saveCURBCNTR; 507 u32 saveCURBPOS; 508 u32 saveCURBBASE; 509 u32 saveCURSIZE; 510 u32 saveDP_B; 511 u32 saveDP_C; 512 u32 saveDP_D; 513 u32 savePIPEA_GMCH_DATA_M; 514 u32 savePIPEB_GMCH_DATA_M; 515 u32 savePIPEA_GMCH_DATA_N; 516 u32 savePIPEB_GMCH_DATA_N; 517 u32 savePIPEA_DP_LINK_M; 518 u32 savePIPEB_DP_LINK_M; 519 u32 savePIPEA_DP_LINK_N; 520 u32 savePIPEB_DP_LINK_N; 521 u32 saveFDI_RXA_CTL; 522 u32 saveFDI_TXA_CTL; 523 u32 saveFDI_RXB_CTL; 524 u32 saveFDI_TXB_CTL; 525 u32 savePFA_CTL_1; 526 u32 savePFB_CTL_1; 527 u32 savePFA_WIN_SZ; 528 u32 savePFB_WIN_SZ; 529 u32 savePFA_WIN_POS; 530 u32 savePFB_WIN_POS; 531 u32 savePCH_DREF_CONTROL; 532 u32 saveDISP_ARB_CTL; 533 u32 savePIPEA_DATA_M1; 534 u32 savePIPEA_DATA_N1; 535 u32 savePIPEA_LINK_M1; 536 u32 savePIPEA_LINK_N1; 537 u32 savePIPEB_DATA_M1; 538 u32 savePIPEB_DATA_N1; 539 u32 savePIPEB_LINK_M1; 540 u32 savePIPEB_LINK_N1; 541 u32 saveMCHBAR_RENDER_STANDBY; 542 u32 savePCH_PORT_HOTPLUG; 543 544 struct { 545 /** Bridge to intel-gtt-ko */ 546 const struct intel_gtt *gtt; 547 /** Memory allocator for GTT stolen memory */ 548 struct drm_mm stolen; 549 /** Memory allocator for GTT */ 550 struct drm_mm gtt_space; 551 /** List of all objects in gtt_space. Used to restore gtt 552 * mappings on resume */ 553 struct list_head gtt_list; 554 555 /** Usable portion of the GTT for GEM */ 556 unsigned long gtt_start; 557 unsigned long gtt_mappable_end; 558 unsigned long gtt_end; 559 560 /** PPGTT used for aliasing the PPGTT with the GTT */ 561 struct i915_hw_ppgtt *aliasing_ppgtt; 562 563 /** 564 * List of objects currently involved in rendering from the 565 * ringbuffer. 566 * 567 * Includes buffers having the contents of their GPU caches 568 * flushed, not necessarily primitives. last_rendering_seqno 569 * represents when the rendering involved will be completed. 570 * 571 * A reference is held on the buffer while on this list. 572 */ 573 struct list_head active_list; 574 575 /** 576 * List of objects which are not in the ringbuffer but which 577 * still have a write_domain which needs to be flushed before 578 * unbinding. 579 * 580 * A reference is held on the buffer while on this list. 581 */ 582 struct list_head flushing_list; 583 584 /** 585 * LRU list of objects which are not in the ringbuffer and 586 * are ready to unbind, but are still in the GTT. 587 * 588 * last_rendering_seqno is 0 while an object is in this list. 589 * 590 * A reference is not held on the buffer while on this list, 591 * as merely being GTT-bound shouldn't prevent its being 592 * freed, and we'll pull it off the list in the free path. 593 */ 594 struct list_head inactive_list; 595 596 /** 597 * LRU list of objects which are not in the ringbuffer but 598 * are still pinned in the GTT. 599 */ 600 struct list_head pinned_list; 601 602 /** LRU list of objects with fence regs on them. */ 603 struct list_head fence_list; 604 605 /** 606 * List of objects currently pending being freed. 607 * 608 * These objects are no longer in use, but due to a signal 609 * we were prevented from freeing them at the appointed time. 610 */ 611 struct list_head deferred_free_list; 612 613 /** 614 * We leave the user IRQ off as much as possible, 615 * but this means that requests will finish and never 616 * be retired once the system goes idle. Set a timer to 617 * fire periodically while the ring is running. When it 618 * fires, go retire requests. 619 */ 620 struct timeout_task retire_task; 621 622 /** 623 * Are we in a non-interruptible section of code like 624 * modesetting? 625 */ 626 bool interruptible; 627 628 uint32_t next_gem_seqno; 629 630 /** 631 * Waiting sequence number, if any 632 */ 633 uint32_t waiting_gem_seqno; 634 635 /** 636 * Last seq seen at irq time 637 */ 638 uint32_t irq_gem_seqno; 639 640 /** 641 * Flag if the X Server, and thus DRM, is not currently in 642 * control of the device. 643 * 644 * This is set between LeaveVT and EnterVT. It needs to be 645 * replaced with a semaphore. It also needs to be 646 * transitioned away from for kernel modesetting. 647 */ 648 int suspended; 649 650 /** 651 * Flag if the hardware appears to be wedged. 652 * 653 * This is set when attempts to idle the device timeout. 654 * It prevents command submission from occuring and makes 655 * every pending request fail 656 */ 657 int wedged; 658 659 /** Bit 6 swizzling required for X tiling */ 660 uint32_t bit_6_swizzle_x; 661 /** Bit 6 swizzling required for Y tiling */ 662 uint32_t bit_6_swizzle_y; 663 664 /* storage for physical objects */ 665 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 666 667 /* accounting, useful for userland debugging */ 668 size_t gtt_total; 669 size_t mappable_gtt_total; 670 size_t object_memory; 671 u32 object_count; 672 673 eventhandler_tag i915_lowmem; 674 } mm; 675 676 const struct intel_device_info *info; 677 678 struct sdvo_device_mapping sdvo_mappings[2]; 679 /* indicate whether the LVDS_BORDER should be enabled or not */ 680 unsigned int lvds_border_bits; 681 /* Panel fitter placement and size for Ironlake+ */ 682 u32 pch_pf_pos, pch_pf_size; 683 684 struct drm_crtc *plane_to_crtc_mapping[3]; 685 struct drm_crtc *pipe_to_crtc_mapping[3]; 686 /* wait_queue_head_t pending_flip_queue; XXXKIB */ 687 bool flip_pending_is_done; 688 689 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 690 struct intel_ddi_plls ddi_plls; 691 692 /* Reclocking support */ 693 bool render_reclock_avail; 694 bool lvds_downclock_avail; 695 /* indicates the reduced downclock for LVDS*/ 696 int lvds_downclock; 697 struct task idle_task; 698 struct callout idle_callout; 699 bool busy; 700 u16 orig_clock; 701 int child_dev_num; 702 struct child_device_config *child_dev; 703 struct drm_connector *int_lvds_connector; 704 struct drm_connector *int_edp_connector; 705 706 device_t bridge_dev; 707 bool mchbar_need_disable; 708 int mch_res_rid; 709 struct resource *mch_res; 710 711 struct lock rps_lock; 712 u32 pm_iir; 713 struct task rps_task; 714 715 u8 cur_delay; 716 u8 min_delay; 717 u8 max_delay; 718 u8 fmax; 719 u8 fstart; 720 721 u64 last_count1; 722 unsigned long last_time1; 723 unsigned long chipset_power; 724 u64 last_count2; 725 struct timespec last_time2; 726 unsigned long gfx_power; 727 int c_m; 728 int r_t; 729 u8 corr; 730 struct lock *mchdev_lock; 731 732 enum no_fbc_reason no_fbc_reason; 733 734 unsigned long cfb_size; 735 unsigned int cfb_fb; 736 int cfb_plane; 737 int cfb_y; 738 struct intel_fbc_work *fbc_work; 739 740 unsigned int fsb_freq, mem_freq, is_ddr3; 741 742 struct taskqueue *tq; 743 struct task error_task; 744 struct task hotplug_task; 745 int error_completion; 746 struct lock error_completion_lock; 747 struct drm_i915_error_state *first_error; 748 struct lock error_lock; 749 struct callout hangcheck_timer; 750 751 unsigned long last_gpu_reset; 752 753 struct intel_fbdev *fbdev; 754 755 struct drm_property *broadcast_rgb_property; 756 struct drm_property *force_audio_property; 757 } drm_i915_private_t; 758 759 enum hdmi_force_audio { 760 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 761 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 762 HDMI_AUDIO_AUTO, /* trust EDID */ 763 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 764 }; 765 766 enum i915_cache_level { 767 I915_CACHE_NONE, 768 I915_CACHE_LLC, 769 I915_CACHE_LLC_MLC, /* gen6+ */ 770 }; 771 772 enum intel_chip_family { 773 CHIP_I8XX = 0x01, 774 CHIP_I9XX = 0x02, 775 CHIP_I915 = 0x04, 776 CHIP_I965 = 0x08, 777 }; 778 779 /** driver private structure attached to each drm_gem_object */ 780 struct drm_i915_gem_object { 781 struct drm_gem_object base; 782 783 /** Current space allocated to this object in the GTT, if any. */ 784 struct drm_mm_node *gtt_space; 785 struct list_head gtt_list; 786 /** This object's place on the active/flushing/inactive lists */ 787 struct list_head ring_list; 788 struct list_head mm_list; 789 /** This object's place on GPU write list */ 790 struct list_head gpu_write_list; 791 /** This object's place in the batchbuffer or on the eviction list */ 792 struct list_head exec_list; 793 794 /** 795 * This is set if the object is on the active or flushing lists 796 * (has pending rendering), and is not set if it's on inactive (ready 797 * to be unbound). 798 */ 799 unsigned int active:1; 800 801 /** 802 * This is set if the object has been written to since last bound 803 * to the GTT 804 */ 805 unsigned int dirty:1; 806 807 /** 808 * This is set if the object has been written to since the last 809 * GPU flush. 810 */ 811 unsigned int pending_gpu_write:1; 812 813 /** 814 * Fence register bits (if any) for this object. Will be set 815 * as needed when mapped into the GTT. 816 * Protected by dev->struct_mutex. 817 */ 818 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 819 820 /** 821 * Advice: are the backing pages purgeable? 822 */ 823 unsigned int madv:2; 824 825 /** 826 * Current tiling mode for the object. 827 */ 828 unsigned int tiling_mode:2; 829 unsigned int tiling_changed:1; 830 831 /** How many users have pinned this object in GTT space. The following 832 * users can each hold at most one reference: pwrite/pread, pin_ioctl 833 * (via user_pin_count), execbuffer (objects are not allowed multiple 834 * times for the same batchbuffer), and the framebuffer code. When 835 * switching/pageflipping, the framebuffer code has at most two buffers 836 * pinned per crtc. 837 * 838 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 839 * bits with absolutely no headroom. So use 4 bits. */ 840 unsigned int pin_count:4; 841 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 842 843 /** 844 * Is the object at the current location in the gtt mappable and 845 * fenceable? Used to avoid costly recalculations. 846 */ 847 unsigned int map_and_fenceable:1; 848 849 /** 850 * Whether the current gtt mapping needs to be mappable (and isn't just 851 * mappable by accident). Track pin and fault separate for a more 852 * accurate mappable working set. 853 */ 854 unsigned int fault_mappable:1; 855 unsigned int pin_mappable:1; 856 857 /* 858 * Is the GPU currently using a fence to access this buffer, 859 */ 860 unsigned int pending_fenced_gpu_access:1; 861 unsigned int fenced_gpu_access:1; 862 863 unsigned int cache_level:2; 864 865 unsigned int has_aliasing_ppgtt_mapping:1; 866 867 vm_page_t *pages; 868 869 /** 870 * DMAR support 871 */ 872 struct sglist *sg_list; 873 874 /** 875 * Used for performing relocations during execbuffer insertion. 876 */ 877 struct hlist_node exec_node; 878 unsigned long exec_handle; 879 struct drm_i915_gem_exec_object2 *exec_entry; 880 881 /** 882 * Current offset of the object in GTT space. 883 * 884 * This is the same as gtt_space->start 885 */ 886 uint32_t gtt_offset; 887 888 /** Breadcrumb of last rendering to the buffer. */ 889 uint32_t last_rendering_seqno; 890 struct intel_ring_buffer *ring; 891 892 /** Breadcrumb of last fenced GPU access to the buffer. */ 893 uint32_t last_fenced_seqno; 894 struct intel_ring_buffer *last_fenced_ring; 895 896 /** Current tiling stride for the object, if it's tiled. */ 897 uint32_t stride; 898 899 /** Record of address bit 17 of each page at last unbind. */ 900 unsigned long *bit_17; 901 902 /** 903 * If present, while GEM_DOMAIN_CPU is in the read domain this array 904 * flags which individual pages are valid. 905 */ 906 uint8_t *page_cpu_valid; 907 908 /** User space pin count and filp owning the pin */ 909 uint32_t user_pin_count; 910 struct drm_file *pin_filp; 911 912 /** for phy allocated objects */ 913 struct drm_i915_gem_phys_object *phys_obj; 914 915 /** 916 * Number of crtcs where this object is currently the fb, but 917 * will be page flipped away on the next vblank. When it 918 * reaches 0, dev_priv->pending_flip_queue will be woken up. 919 */ 920 int pending_flip; 921 }; 922 923 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 924 925 /** 926 * Request queue structure. 927 * 928 * The request queue allows us to note sequence numbers that have been emitted 929 * and may be associated with active buffers to be retired. 930 * 931 * By keeping this list, we can avoid having to do questionable 932 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 933 * an emission time with seqnos for tracking how far ahead of the GPU we are. 934 */ 935 struct drm_i915_gem_request { 936 /** On Which ring this request was generated */ 937 struct intel_ring_buffer *ring; 938 939 /** GEM sequence number associated with this request. */ 940 uint32_t seqno; 941 942 /** Postion in the ringbuffer of the end of the request */ 943 u32 tail; 944 945 /** Time at which this request was emitted, in jiffies. */ 946 unsigned long emitted_jiffies; 947 948 /** global list entry for this request */ 949 struct list_head list; 950 951 struct drm_i915_file_private *file_priv; 952 /** file_priv list entry for this request */ 953 struct list_head client_list; 954 }; 955 956 struct drm_i915_file_private { 957 struct { 958 struct spinlock lock; 959 struct list_head request_list; 960 } mm; 961 }; 962 963 struct drm_i915_error_state { 964 u32 eir; 965 u32 pgtbl_er; 966 u32 pipestat[I915_MAX_PIPES]; 967 u32 tail[I915_NUM_RINGS]; 968 u32 head[I915_NUM_RINGS]; 969 u32 ipeir[I915_NUM_RINGS]; 970 u32 ipehr[I915_NUM_RINGS]; 971 u32 instdone[I915_NUM_RINGS]; 972 u32 acthd[I915_NUM_RINGS]; 973 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 974 /* our own tracking of ring head and tail */ 975 u32 cpu_ring_head[I915_NUM_RINGS]; 976 u32 cpu_ring_tail[I915_NUM_RINGS]; 977 u32 error; /* gen6+ */ 978 u32 instpm[I915_NUM_RINGS]; 979 u32 instps[I915_NUM_RINGS]; 980 u32 instdone1; 981 u32 seqno[I915_NUM_RINGS]; 982 u64 bbaddr; 983 u32 fault_reg[I915_NUM_RINGS]; 984 u32 done_reg; 985 u32 faddr[I915_NUM_RINGS]; 986 u64 fence[I915_MAX_NUM_FENCES]; 987 struct timeval time; 988 struct drm_i915_error_ring { 989 struct drm_i915_error_object { 990 int page_count; 991 u32 gtt_offset; 992 u32 *pages[0]; 993 } *ringbuffer, *batchbuffer; 994 struct drm_i915_error_request { 995 long jiffies; 996 u32 seqno; 997 u32 tail; 998 } *requests; 999 int num_requests; 1000 } ring[I915_NUM_RINGS]; 1001 struct drm_i915_error_buffer { 1002 u32 size; 1003 u32 name; 1004 u32 seqno; 1005 u32 gtt_offset; 1006 u32 read_domains; 1007 u32 write_domain; 1008 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 1009 s32 pinned:2; 1010 u32 tiling:2; 1011 u32 dirty:1; 1012 u32 purgeable:1; 1013 s32 ring:4; 1014 u32 cache_level:2; 1015 } *active_bo, *pinned_bo; 1016 u32 active_bo_count, pinned_bo_count; 1017 struct intel_overlay_error_state *overlay; 1018 struct intel_display_error_state *display; 1019 }; 1020 1021 /** 1022 * RC6 is a special power stage which allows the GPU to enter an very 1023 * low-voltage mode when idle, using down to 0V while at this stage. This 1024 * stage is entered automatically when the GPU is idle when RC6 support is 1025 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1026 * 1027 * There are different RC6 modes available in Intel GPU, which differentiate 1028 * among each other with the latency required to enter and leave RC6 and 1029 * voltage consumed by the GPU in different states. 1030 * 1031 * The combination of the following flags define which states GPU is allowed 1032 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1033 * RC6pp is deepest RC6. Their support by hardware varies according to the 1034 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1035 * which brings the most power savings; deeper states save more power, but 1036 * require higher latency to switch to and wake up. 1037 */ 1038 #define INTEL_RC6_ENABLE (1<<0) 1039 #define INTEL_RC6p_ENABLE (1<<1) 1040 #define INTEL_RC6pp_ENABLE (1<<2) 1041 1042 extern int intel_iommu_enabled; 1043 extern struct drm_ioctl_desc i915_ioctls[]; 1044 extern struct drm_driver i915_driver_info; 1045 extern struct cdev_pager_ops i915_gem_pager_ops; 1046 extern int i915_panel_ignore_lid; 1047 extern unsigned int i915_powersave; 1048 extern int i915_semaphores; 1049 extern unsigned int i915_lvds_downclock; 1050 extern int i915_panel_use_ssc; 1051 extern int i915_vbt_sdvo_panel_type; 1052 extern int i915_enable_rc6; 1053 extern int i915_enable_fbc; 1054 extern int i915_enable_ppgtt; 1055 extern int i915_enable_hangcheck; 1056 1057 const struct intel_device_info *i915_get_device_id(int device); 1058 1059 int i915_reset(struct drm_device *dev, u8 flags); 1060 1061 /* i915_debug.c */ 1062 int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1063 struct sysctl_oid *top); 1064 void i915_sysctl_cleanup(struct drm_device *dev); 1065 1066 /* i915_dma.c */ 1067 extern void i915_kernel_lost_context(struct drm_device * dev); 1068 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1069 extern int i915_driver_unload(struct drm_device *); 1070 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1071 extern void i915_driver_lastclose(struct drm_device * dev); 1072 extern void i915_driver_preclose(struct drm_device *dev, 1073 struct drm_file *file_priv); 1074 extern void i915_driver_postclose(struct drm_device *dev, 1075 struct drm_file *file_priv); 1076 extern int i915_driver_device_is_agp(struct drm_device * dev); 1077 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1078 unsigned long arg); 1079 extern int i915_emit_box(struct drm_device *dev, 1080 struct drm_clip_rect __user *boxes, 1081 int i, int DR1, int DR4); 1082 int i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 1083 int DR1, int DR4); 1084 1085 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1086 unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1087 void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1088 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1089 1090 /* i915_irq.c */ 1091 extern int i915_irq_emit(struct drm_device *dev, void *data, 1092 struct drm_file *file_priv); 1093 extern int i915_irq_wait(struct drm_device *dev, void *data, 1094 struct drm_file *file_priv); 1095 1096 extern void intel_irq_init(struct drm_device *dev); 1097 1098 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1099 struct drm_file *file_priv); 1100 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1101 struct drm_file *file_priv); 1102 extern int i915_vblank_swap(struct drm_device *dev, void *data, 1103 struct drm_file *file_priv); 1104 void intel_enable_asle(struct drm_device *dev); 1105 void i915_hangcheck_elapsed(void *context); 1106 void i915_handle_error(struct drm_device *dev, bool wedged); 1107 1108 void i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1109 void i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1110 1111 void i915_destroy_error_state(struct drm_device *dev); 1112 1113 /* i915_gem.c */ 1114 int i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size, 1115 uint32_t *handle_p); 1116 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1117 struct drm_file *file_priv); 1118 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1119 struct drm_file *file_priv); 1120 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1121 struct drm_file *file_priv); 1122 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1123 struct drm_file *file_priv); 1124 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1125 struct drm_file *file_priv); 1126 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1127 struct drm_file *file_priv); 1128 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1129 struct drm_file *file_priv); 1130 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1131 struct drm_file *file_priv); 1132 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1133 struct drm_file *file_priv); 1134 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1135 struct drm_file *file_priv); 1136 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1137 struct drm_file *file_priv); 1138 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1139 struct drm_file *file_priv); 1140 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1141 struct drm_file *file_priv); 1142 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1143 struct drm_file *file_priv); 1144 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1145 struct drm_file *file_priv); 1146 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1147 struct drm_file *file_priv); 1148 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1149 struct drm_file *file_priv); 1150 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1151 struct drm_file *file_priv); 1152 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1153 struct drm_file *file_priv); 1154 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1155 struct drm_file *file_priv); 1156 void i915_gem_load(struct drm_device *dev); 1157 void i915_gem_unload(struct drm_device *dev); 1158 int i915_gem_init_object(struct drm_gem_object *obj); 1159 void i915_gem_free_object(struct drm_gem_object *obj); 1160 int i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1161 bool map_and_fenceable); 1162 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1163 int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1164 void i915_gem_lastclose(struct drm_device *dev); 1165 uint32_t i915_get_gem_seqno(struct drm_device *dev); 1166 1167 static inline void 1168 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1169 { 1170 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1171 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1172 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1173 } 1174 } 1175 1176 static inline void 1177 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1178 { 1179 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1180 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1181 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1182 } 1183 } 1184 1185 void i915_gem_retire_requests(struct drm_device *dev); 1186 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1187 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1188 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1189 size_t size); 1190 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 1191 unsigned long mappable_end, unsigned long end); 1192 uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1193 uint32_t size, int tiling_mode); 1194 int i915_mutex_lock_interruptible(struct drm_device *dev); 1195 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1196 bool write); 1197 int i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1198 u32 alignment, struct intel_ring_buffer *pipelined); 1199 int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1200 int i915_gem_flush_ring(struct intel_ring_buffer *ring, 1201 uint32_t invalidate_domains, uint32_t flush_domains); 1202 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1203 int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1204 int i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1205 int i915_gem_idle(struct drm_device *dev); 1206 int i915_gem_init_hw(struct drm_device *dev); 1207 void i915_gem_init_swizzling(struct drm_device *dev); 1208 void i915_gem_init_ppgtt(struct drm_device *dev); 1209 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1210 int i915_gpu_idle(struct drm_device *dev, bool do_retire); 1211 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1212 struct intel_ring_buffer *ring, uint32_t seqno); 1213 int i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file, 1214 struct drm_i915_gem_request *request); 1215 int i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1216 struct intel_ring_buffer *pipelined); 1217 void i915_gem_reset(struct drm_device *dev); 1218 int i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, 1219 bool do_retire); 1220 int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1221 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1222 uint64_t *phys); 1223 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1224 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1225 enum i915_cache_level cache_level); 1226 1227 void i915_gem_free_all_phys_object(struct drm_device *dev); 1228 void i915_gem_detach_phys_object(struct drm_device *dev, 1229 struct drm_i915_gem_object *obj); 1230 int i915_gem_attach_phys_object(struct drm_device *dev, 1231 struct drm_i915_gem_object *obj, int id, int align); 1232 1233 int i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1234 struct drm_mode_create_dumb *args); 1235 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1236 uint32_t handle, uint64_t *offset); 1237 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1238 uint32_t handle); 1239 1240 /* i915_gem_tiling.c */ 1241 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1242 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1243 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1244 1245 /* i915_gem_evict.c */ 1246 int i915_gem_evict_something(struct drm_device *dev, int min_size, 1247 unsigned alignment, bool mappable); 1248 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1249 int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only); 1250 1251 /* i915_suspend.c */ 1252 extern int i915_save_state(struct drm_device *dev); 1253 extern int i915_restore_state(struct drm_device *dev); 1254 1255 /* intel_iic.c */ 1256 extern int intel_setup_gmbus(struct drm_device *dev); 1257 extern void intel_teardown_gmbus(struct drm_device *dev); 1258 extern void intel_gmbus_set_speed(device_t idev, int speed); 1259 extern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1260 extern void intel_iic_reset(struct drm_device *dev); 1261 1262 /* intel_opregion.c */ 1263 int intel_opregion_setup(struct drm_device *dev); 1264 extern int intel_opregion_init(struct drm_device *dev); 1265 extern void intel_opregion_fini(struct drm_device *dev); 1266 extern void opregion_asle_intr(struct drm_device *dev); 1267 extern void opregion_enable_asle(struct drm_device *dev); 1268 1269 /* i915_gem_gtt.c */ 1270 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1271 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1272 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1273 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1274 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1275 struct drm_i915_gem_object *obj); 1276 1277 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1278 int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1279 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1280 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1281 enum i915_cache_level cache_level); 1282 1283 /* modesetting */ 1284 extern void intel_modeset_init(struct drm_device *dev); 1285 extern void intel_modeset_gem_init(struct drm_device *dev); 1286 extern void intel_modeset_cleanup(struct drm_device *dev); 1287 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1288 extern void intel_disable_fbc(struct drm_device *dev); 1289 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1290 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1291 extern void ironlake_enable_rc6(struct drm_device *dev); 1292 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1293 extern void intel_detect_pch(struct drm_device *dev); 1294 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1295 1296 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1297 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1298 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1299 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1300 1301 extern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1302 struct drm_device *dev); 1303 extern void intel_overlay_print_error_state(struct sbuf *m, 1304 struct intel_overlay_error_state *error); 1305 extern struct intel_display_error_state *intel_display_capture_error_state( 1306 struct drm_device *dev); 1307 extern void intel_display_print_error_state(struct sbuf *m, 1308 struct drm_device *dev, struct intel_display_error_state *error); 1309 1310 static inline void 1311 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1312 { 1313 return; 1314 } 1315 1316 /* On SNB platform, before reading ring registers forcewake bit 1317 * must be set to prevent GT core from power down and stale values being 1318 * returned. 1319 */ 1320 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1321 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1322 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1323 1324 /* We give fast paths for the really cool registers */ 1325 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1326 (((dev_priv)->info->gen >= 6) && \ 1327 ((reg) < 0x40000) && \ 1328 ((reg) != FORCEWAKE)) 1329 1330 #define __i915_read(x, y) \ 1331 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1332 1333 __i915_read(8, 8) 1334 __i915_read(16, 16) 1335 __i915_read(32, 32) 1336 __i915_read(64, 64) 1337 #undef __i915_read 1338 1339 #define __i915_write(x, y) \ 1340 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1341 1342 __i915_write(8, 8) 1343 __i915_write(16, 16) 1344 __i915_write(32, 32) 1345 __i915_write(64, 64) 1346 #undef __i915_write 1347 1348 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1349 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1350 1351 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1352 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1353 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1354 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1355 1356 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1357 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1358 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1359 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1360 1361 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1362 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1363 1364 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1365 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1366 1367 #define I915_VERBOSE 0 1368 1369 #define LP_RING(d) (&((struct drm_i915_private *)(d))->rings[RCS]) 1370 1371 #define BEGIN_LP_RING(n) \ 1372 intel_ring_begin(LP_RING(dev_priv), (n)) 1373 1374 #define OUT_RING(x) \ 1375 intel_ring_emit(LP_RING(dev_priv), x) 1376 1377 #define ADVANCE_LP_RING() \ 1378 intel_ring_advance(LP_RING(dev_priv)) 1379 1380 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1381 if (LP_RING(dev->dev_private)->obj == NULL) \ 1382 LOCK_TEST_WITH_RETURN(dev, file); \ 1383 } while (0) 1384 1385 /** 1386 * Reads a dword out of the status page, which is written to from the command 1387 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1388 * MI_STORE_DATA_IMM. 1389 * 1390 * The following dwords have a reserved meaning: 1391 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1392 * 0x04: ring 0 head pointer 1393 * 0x05: ring 1 head pointer (915-class) 1394 * 0x06: ring 2 head pointer (915-class) 1395 * 0x10-0x1b: Context status DWords (GM45) 1396 * 0x1f: Last written status offset. (GM45) 1397 * 1398 * The area from dword 0x20 to 0x3ff is available for driver usage. 1399 */ 1400 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 1401 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1402 #define I915_GEM_HWS_INDEX 0x20 1403 #define I915_BREADCRUMB_INDEX 0x21 1404 1405 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1406 1407 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1408 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1409 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1410 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1411 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1412 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1413 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1414 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1415 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1416 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1417 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1418 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1419 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1420 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1421 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1422 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1423 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1424 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1425 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1426 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1427 (dev)->pci_device == 0x0152 || \ 1428 (dev)->pci_device == 0x015a) 1429 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1430 (dev)->pci_device == 0x0106 || \ 1431 (dev)->pci_device == 0x010A) 1432 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1433 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1434 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1435 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1436 ((dev)->pci_device & 0xFF00) == 0x0A00) 1437 1438 /* XXXKIB LEGACY */ 1439 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1440 (dev)->pci_device == 0x2982 || \ 1441 (dev)->pci_device == 0x2992 || \ 1442 (dev)->pci_device == 0x29A2 || \ 1443 (dev)->pci_device == 0x2A02 || \ 1444 (dev)->pci_device == 0x2A12 || \ 1445 (dev)->pci_device == 0x2A42 || \ 1446 (dev)->pci_device == 0x2E02 || \ 1447 (dev)->pci_device == 0x2E12 || \ 1448 (dev)->pci_device == 0x2E22 || \ 1449 (dev)->pci_device == 0x2E32) 1450 1451 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1452 1453 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1454 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1455 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1456 1457 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1458 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1459 /* XXXKIB LEGACY END */ 1460 1461 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1462 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1463 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1464 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1465 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1466 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1467 1468 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1469 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1470 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1471 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1472 1473 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1474 1475 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1476 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1477 1478 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1479 * rows, which changed the alignment requirements and fence programming. 1480 */ 1481 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1482 IS_I915GM(dev))) 1483 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1484 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1485 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1486 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1487 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1488 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1489 /* dsparb controlled by hw only */ 1490 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1491 1492 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1493 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1494 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1495 1496 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1497 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1498 1499 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1500 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1501 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1502 1503 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 1504 1505 static inline bool 1506 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1507 { 1508 1509 return ((int32_t)(seq1 - seq2) >= 0); 1510 } 1511 1512 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1513 1514 #endif 1515