1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30 #ifndef _I915_DRV_H_ 31 #define _I915_DRV_H_ 32 33 #include <uapi_drm/i915_drm.h> 34 35 #include "i915_reg.h" 36 #include "intel_bios.h" 37 #include "intel_ringbuffer.h" 38 #include "i915_gem_gtt.h" 39 #include <linux/io-mapping.h> 40 #include <linux/i2c.h> 41 #include <drm/intel-gtt.h> 42 #include <linux/backlight.h> 43 #include <linux/hashtable.h> 44 #include <linux/kref.h> 45 #include <linux/kconfig.h> 46 #include <linux/pm_qos.h> 47 #include <linux/seq_file.h> 48 #include <linux/delay.h> 49 50 #define CONFIG_ACPI 1 51 52 /* General customization: 53 */ 54 55 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 56 57 #define DRIVER_NAME "i915" 58 #define DRIVER_DESC "Intel Graphics" 59 #define DRIVER_DATE "20080730" 60 61 enum i915_pipe { 62 INVALID_PIPE = -1, 63 PIPE_A = 0, 64 PIPE_B, 65 PIPE_C, 66 _PIPE_EDP, 67 I915_MAX_PIPES = _PIPE_EDP 68 }; 69 #define pipe_name(p) ((p) + 'A') 70 71 enum transcoder { 72 TRANSCODER_A = 0, 73 TRANSCODER_B, 74 TRANSCODER_C, 75 TRANSCODER_EDP, 76 I915_MAX_TRANSCODERS 77 }; 78 #define transcoder_name(t) ((t) + 'A') 79 80 enum plane { 81 PLANE_A = 0, 82 PLANE_B, 83 PLANE_C, 84 }; 85 #define plane_name(p) ((p) + 'A') 86 87 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') 88 89 enum port { 90 PORT_A = 0, 91 PORT_B, 92 PORT_C, 93 PORT_D, 94 PORT_E, 95 I915_MAX_PORTS 96 }; 97 #define port_name(p) ((p) + 'A') 98 99 #define I915_NUM_PHYS_VLV 2 100 101 enum dpio_channel { 102 DPIO_CH0, 103 DPIO_CH1 104 }; 105 106 enum dpio_phy { 107 DPIO_PHY0, 108 DPIO_PHY1 109 }; 110 111 enum intel_display_power_domain { 112 POWER_DOMAIN_PIPE_A, 113 POWER_DOMAIN_PIPE_B, 114 POWER_DOMAIN_PIPE_C, 115 POWER_DOMAIN_PIPE_A_PANEL_FITTER, 116 POWER_DOMAIN_PIPE_B_PANEL_FITTER, 117 POWER_DOMAIN_PIPE_C_PANEL_FITTER, 118 POWER_DOMAIN_TRANSCODER_A, 119 POWER_DOMAIN_TRANSCODER_B, 120 POWER_DOMAIN_TRANSCODER_C, 121 POWER_DOMAIN_TRANSCODER_EDP, 122 POWER_DOMAIN_PORT_DDI_A_2_LANES, 123 POWER_DOMAIN_PORT_DDI_A_4_LANES, 124 POWER_DOMAIN_PORT_DDI_B_2_LANES, 125 POWER_DOMAIN_PORT_DDI_B_4_LANES, 126 POWER_DOMAIN_PORT_DDI_C_2_LANES, 127 POWER_DOMAIN_PORT_DDI_C_4_LANES, 128 POWER_DOMAIN_PORT_DDI_D_2_LANES, 129 POWER_DOMAIN_PORT_DDI_D_4_LANES, 130 POWER_DOMAIN_PORT_DSI, 131 POWER_DOMAIN_PORT_CRT, 132 POWER_DOMAIN_PORT_OTHER, 133 POWER_DOMAIN_VGA, 134 POWER_DOMAIN_AUDIO, 135 POWER_DOMAIN_INIT, 136 137 POWER_DOMAIN_NUM, 138 }; 139 140 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) 141 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ 142 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) 143 #define POWER_DOMAIN_TRANSCODER(tran) \ 144 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ 145 (tran) + POWER_DOMAIN_TRANSCODER_A) 146 147 enum hpd_pin { 148 HPD_NONE = 0, 149 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ 150 HPD_TV = HPD_NONE, /* TV is known to be unreliable */ 151 HPD_CRT, 152 HPD_SDVO_B, 153 HPD_SDVO_C, 154 HPD_PORT_B, 155 HPD_PORT_C, 156 HPD_PORT_D, 157 HPD_NUM_PINS 158 }; 159 160 #define I915_GEM_GPU_DOMAINS \ 161 (I915_GEM_DOMAIN_RENDER | \ 162 I915_GEM_DOMAIN_SAMPLER | \ 163 I915_GEM_DOMAIN_COMMAND | \ 164 I915_GEM_DOMAIN_INSTRUCTION | \ 165 I915_GEM_DOMAIN_VERTEX) 166 167 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) 168 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) 169 170 #define for_each_crtc(dev, crtc) \ 171 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 172 173 #define for_each_intel_crtc(dev, intel_crtc) \ 174 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) 175 176 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 177 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 178 if ((intel_encoder)->base.crtc == (__crtc)) 179 180 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ 181 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ 182 if ((intel_connector)->base.encoder == (__encoder)) 183 184 struct drm_i915_private; 185 struct i915_mmu_object; 186 187 enum intel_dpll_id { 188 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ 189 /* real shared dpll ids must be >= 0 */ 190 DPLL_ID_PCH_PLL_A, 191 DPLL_ID_PCH_PLL_B, 192 }; 193 #define I915_NUM_PLLS 2 194 195 struct intel_dpll_hw_state { 196 uint32_t dpll; 197 uint32_t dpll_md; 198 uint32_t fp0; 199 uint32_t fp1; 200 }; 201 202 struct intel_shared_dpll { 203 int refcount; /* count of number of CRTCs sharing this PLL */ 204 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 205 bool on; /* is the PLL actually active? Disabled during modeset */ 206 const char *name; 207 /* should match the index in the dev_priv->shared_dplls array */ 208 enum intel_dpll_id id; 209 struct intel_dpll_hw_state hw_state; 210 void (*mode_set)(struct drm_i915_private *dev_priv, 211 struct intel_shared_dpll *pll); 212 void (*enable)(struct drm_i915_private *dev_priv, 213 struct intel_shared_dpll *pll); 214 void (*disable)(struct drm_i915_private *dev_priv, 215 struct intel_shared_dpll *pll); 216 bool (*get_hw_state)(struct drm_i915_private *dev_priv, 217 struct intel_shared_dpll *pll, 218 struct intel_dpll_hw_state *hw_state); 219 }; 220 221 /* Used by dp and fdi links */ 222 struct intel_link_m_n { 223 uint32_t tu; 224 uint32_t gmch_m; 225 uint32_t gmch_n; 226 uint32_t link_m; 227 uint32_t link_n; 228 }; 229 230 void intel_link_compute_m_n(int bpp, int nlanes, 231 int pixel_clock, int link_clock, 232 struct intel_link_m_n *m_n); 233 234 struct intel_ddi_plls { 235 int spll_refcount; 236 int wrpll1_refcount; 237 int wrpll2_refcount; 238 }; 239 240 /* Interface history: 241 * 242 * 1.1: Original. 243 * 1.2: Add Power Management 244 * 1.3: Add vblank support 245 * 1.4: Fix cmdbuffer path, add heap destroy 246 * 1.5: Add vblank pipe configuration 247 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 248 * - Support vertical blank on secondary display pipe 249 */ 250 #define DRIVER_MAJOR 1 251 #define DRIVER_MINOR 6 252 #define DRIVER_PATCHLEVEL 0 253 254 #define WATCH_LISTS 0 255 #define WATCH_GTT 0 256 257 struct opregion_header; 258 struct opregion_acpi; 259 struct opregion_swsci; 260 struct opregion_asle; 261 262 struct intel_opregion { 263 struct opregion_header __iomem *header; 264 struct opregion_acpi __iomem *acpi; 265 struct opregion_swsci __iomem *swsci; 266 u32 swsci_gbda_sub_functions; 267 u32 swsci_sbcb_sub_functions; 268 struct opregion_asle __iomem *asle; 269 void __iomem *vbt; 270 u32 __iomem *lid_state; 271 struct work_struct asle_work; 272 }; 273 #define OPREGION_SIZE (8*1024) 274 275 struct intel_overlay; 276 struct intel_overlay_error_state; 277 278 struct drm_i915_master_private { 279 drm_local_map_t *sarea; 280 struct _drm_i915_sarea *sarea_priv; 281 }; 282 #define I915_FENCE_REG_NONE -1 283 #define I915_MAX_NUM_FENCES 32 284 /* 32 fences + sign bit for FENCE_REG_NONE */ 285 #define I915_MAX_NUM_FENCE_BITS 6 286 287 struct drm_i915_fence_reg { 288 struct list_head lru_list; 289 struct drm_i915_gem_object *obj; 290 int pin_count; 291 }; 292 293 struct sdvo_device_mapping { 294 u8 initialized; 295 u8 dvo_port; 296 u8 slave_addr; 297 u8 dvo_wiring; 298 u8 i2c_pin; 299 u8 ddc_pin; 300 }; 301 302 struct intel_display_error_state; 303 304 struct drm_i915_error_state { 305 struct kref ref; 306 struct timeval time; 307 308 char error_msg[128]; 309 u32 reset_count; 310 u32 suspend_count; 311 312 /* Generic register state */ 313 u32 eir; 314 u32 pgtbl_er; 315 u32 ier; 316 u32 ccid; 317 u32 derrmr; 318 u32 forcewake; 319 u32 error; /* gen6+ */ 320 u32 err_int; /* gen7 */ 321 u32 done_reg; 322 u32 gac_eco; 323 u32 gam_ecochk; 324 u32 gab_ctl; 325 u32 gfx_mode; 326 u32 extra_instdone[I915_NUM_INSTDONE_REG]; 327 u64 fence[I915_MAX_NUM_FENCES]; 328 struct intel_overlay_error_state *overlay; 329 struct intel_display_error_state *display; 330 331 struct drm_i915_error_ring { 332 bool valid; 333 /* Software tracked state */ 334 bool waiting; 335 int hangcheck_score; 336 enum intel_ring_hangcheck_action hangcheck_action; 337 int num_requests; 338 339 /* our own tracking of ring head and tail */ 340 u32 cpu_ring_head; 341 u32 cpu_ring_tail; 342 343 u32 semaphore_seqno[I915_NUM_RINGS - 1]; 344 345 /* Register state */ 346 u32 tail; 347 u32 head; 348 u32 ctl; 349 u32 hws; 350 u32 ipeir; 351 u32 ipehr; 352 u32 instdone; 353 u32 bbstate; 354 u32 instpm; 355 u32 instps; 356 u32 seqno; 357 u64 bbaddr; 358 u64 acthd; 359 u32 fault_reg; 360 u64 faddr; 361 u32 rc_psmi; /* sleep state */ 362 u32 semaphore_mboxes[I915_NUM_RINGS - 1]; 363 364 struct drm_i915_error_object { 365 int page_count; 366 u32 gtt_offset; 367 u32 *pages[0]; 368 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; 369 370 struct drm_i915_error_request { 371 long jiffies; 372 u32 seqno; 373 u32 tail; 374 } *requests; 375 376 struct { 377 u32 gfx_mode; 378 union { 379 u64 pdp[4]; 380 u32 pp_dir_base; 381 }; 382 } vm_info; 383 384 pid_t pid; 385 char comm[TASK_COMM_LEN]; 386 } ring[I915_NUM_RINGS]; 387 struct drm_i915_error_buffer { 388 u32 size; 389 u32 name; 390 u32 rseqno, wseqno; 391 u32 gtt_offset; 392 u32 read_domains; 393 u32 write_domain; 394 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 395 s32 pinned:2; 396 u32 tiling:2; 397 u32 dirty:1; 398 u32 purgeable:1; 399 u32 userptr:1; 400 s32 ring:4; 401 u32 cache_level:3; 402 } **active_bo, **pinned_bo; 403 404 u32 *active_bo_count, *pinned_bo_count; 405 }; 406 407 struct intel_connector; 408 struct intel_crtc_config; 409 struct intel_plane_config; 410 struct intel_crtc; 411 struct intel_limit; 412 struct dpll; 413 414 struct drm_i915_display_funcs { 415 bool (*fbc_enabled)(struct drm_device *dev); 416 void (*enable_fbc)(struct drm_crtc *crtc); 417 void (*disable_fbc)(struct drm_device *dev); 418 int (*get_display_clock_speed)(struct drm_device *dev); 419 int (*get_fifo_size)(struct drm_device *dev, int plane); 420 /** 421 * find_dpll() - Find the best values for the PLL 422 * @limit: limits for the PLL 423 * @crtc: current CRTC 424 * @target: target frequency in kHz 425 * @refclk: reference clock frequency in kHz 426 * @match_clock: if provided, @best_clock P divider must 427 * match the P divider from @match_clock 428 * used for LVDS downclocking 429 * @best_clock: best PLL values found 430 * 431 * Returns true on success, false on failure. 432 */ 433 bool (*find_dpll)(const struct intel_limit *limit, 434 struct drm_crtc *crtc, 435 int target, int refclk, 436 struct dpll *match_clock, 437 struct dpll *best_clock); 438 void (*update_wm)(struct drm_crtc *crtc); 439 void (*update_sprite_wm)(struct drm_plane *plane, 440 struct drm_crtc *crtc, 441 uint32_t sprite_width, int pixel_size, 442 bool enable, bool scaled); 443 void (*modeset_global_resources)(struct drm_device *dev); 444 /* Returns the active state of the crtc, and if the crtc is active, 445 * fills out the pipe-config with the hw state. */ 446 bool (*get_pipe_config)(struct intel_crtc *, 447 struct intel_crtc_config *); 448 void (*get_plane_config)(struct intel_crtc *, 449 struct intel_plane_config *); 450 int (*crtc_mode_set)(struct drm_crtc *crtc, 451 int x, int y, 452 struct drm_framebuffer *old_fb); 453 void (*crtc_enable)(struct drm_crtc *crtc); 454 void (*crtc_disable)(struct drm_crtc *crtc); 455 void (*off)(struct drm_crtc *crtc); 456 void (*write_eld)(struct drm_connector *connector, 457 struct drm_crtc *crtc, 458 struct drm_display_mode *mode); 459 void (*fdi_link_train)(struct drm_crtc *crtc); 460 void (*init_clock_gating)(struct drm_device *dev); 461 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 462 struct drm_framebuffer *fb, 463 struct drm_i915_gem_object *obj, 464 struct intel_engine_cs *ring, 465 uint32_t flags); 466 void (*update_primary_plane)(struct drm_crtc *crtc, 467 struct drm_framebuffer *fb, 468 int x, int y); 469 void (*hpd_irq_setup)(struct drm_device *dev); 470 /* clock updates for mode set */ 471 /* cursor updates */ 472 /* render clock increase/decrease */ 473 /* display clock increase/decrease */ 474 /* pll clock increase/decrease */ 475 476 int (*setup_backlight)(struct intel_connector *connector); 477 uint32_t (*get_backlight)(struct intel_connector *connector); 478 void (*set_backlight)(struct intel_connector *connector, 479 uint32_t level); 480 void (*disable_backlight)(struct intel_connector *connector); 481 void (*enable_backlight)(struct intel_connector *connector); 482 }; 483 484 struct intel_uncore_funcs { 485 void (*force_wake_get)(struct drm_i915_private *dev_priv, 486 int fw_engine); 487 void (*force_wake_put)(struct drm_i915_private *dev_priv, 488 int fw_engine); 489 490 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 491 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 492 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 493 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 494 495 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, 496 uint8_t val, bool trace); 497 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, 498 uint16_t val, bool trace); 499 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, 500 uint32_t val, bool trace); 501 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, 502 uint64_t val, bool trace); 503 }; 504 505 struct intel_uncore { 506 struct lock lock; /** lock is also taken in irq contexts. */ 507 508 struct intel_uncore_funcs funcs; 509 510 unsigned fifo_count; 511 unsigned forcewake_count; 512 513 unsigned fw_rendercount; 514 unsigned fw_mediacount; 515 516 struct timer_list force_wake_timer; 517 }; 518 519 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ 520 func(is_mobile) sep \ 521 func(is_i85x) sep \ 522 func(is_i915g) sep \ 523 func(is_i945gm) sep \ 524 func(is_g33) sep \ 525 func(need_gfx_hws) sep \ 526 func(is_g4x) sep \ 527 func(is_pineview) sep \ 528 func(is_broadwater) sep \ 529 func(is_crestline) sep \ 530 func(is_ivybridge) sep \ 531 func(is_valleyview) sep \ 532 func(is_haswell) sep \ 533 func(is_preliminary) sep \ 534 func(has_fbc) sep \ 535 func(has_pipe_cxsr) sep \ 536 func(has_hotplug) sep \ 537 func(cursor_needs_physical) sep \ 538 func(has_overlay) sep \ 539 func(overlay_needs_physical) sep \ 540 func(supports_tv) sep \ 541 func(has_llc) sep \ 542 func(has_ddi) sep \ 543 func(has_fpga_dbg) 544 545 #define DEFINE_FLAG(name) u8 name:1 546 #define SEP_SEMICOLON ; 547 548 struct intel_device_info { 549 u32 display_mmio_offset; 550 u8 num_pipes:3; 551 u8 num_sprites[I915_MAX_PIPES]; 552 u8 gen; 553 u8 ring_mask; /* Rings supported by the HW */ 554 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); 555 /* Register offsets for the various display pipes and transcoders */ 556 int pipe_offsets[I915_MAX_TRANSCODERS]; 557 int trans_offsets[I915_MAX_TRANSCODERS]; 558 int dpll_offsets[I915_MAX_PIPES]; 559 int dpll_md_offsets[I915_MAX_PIPES]; 560 int palette_offsets[I915_MAX_PIPES]; 561 int cursor_offsets[I915_MAX_PIPES]; 562 }; 563 564 #undef DEFINE_FLAG 565 #undef SEP_SEMICOLON 566 567 enum i915_cache_level { 568 I915_CACHE_NONE = 0, 569 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ 570 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc 571 caches, eg sampler/render caches, and the 572 large Last-Level-Cache. LLC is coherent with 573 the CPU, but L3 is only visible to the GPU. */ 574 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ 575 }; 576 577 struct i915_ctx_hang_stats { 578 /* This context had batch pending when hang was declared */ 579 unsigned batch_pending; 580 581 /* This context had batch active when hang was declared */ 582 unsigned batch_active; 583 584 /* Time when this context was last blamed for a GPU reset */ 585 unsigned long guilty_ts; 586 587 /* This context is banned to submit more work */ 588 bool banned; 589 }; 590 591 /* This must match up with the value previously used for execbuf2.rsvd1. */ 592 #define DEFAULT_CONTEXT_ID 0 593 struct intel_context { 594 struct kref ref; 595 int id; 596 bool is_initialized; 597 uint8_t remap_slice; 598 struct drm_i915_file_private *file_priv; 599 struct intel_engine_cs *last_ring; 600 struct drm_i915_gem_object *obj; 601 struct i915_ctx_hang_stats hang_stats; 602 struct i915_address_space *vm; 603 604 struct list_head link; 605 }; 606 607 struct i915_fbc { 608 unsigned long size; 609 unsigned int fb_id; 610 enum plane plane; 611 int y; 612 613 struct drm_mm_node *compressed_fb; 614 struct drm_mm_node *compressed_llb; 615 616 struct intel_fbc_work { 617 struct delayed_work work; 618 struct drm_crtc *crtc; 619 struct drm_framebuffer *fb; 620 } *fbc_work; 621 622 enum no_fbc_reason { 623 FBC_OK, /* FBC is enabled */ 624 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ 625 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 626 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ 627 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 628 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 629 FBC_BAD_PLANE, /* fbc not supported on plane */ 630 FBC_NOT_TILED, /* buffer not tiled */ 631 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 632 FBC_MODULE_PARAM, 633 FBC_CHIP_DEFAULT, /* disabled by default on this chip */ 634 } no_fbc_reason; 635 }; 636 637 struct i915_drrs { 638 struct intel_connector *connector; 639 }; 640 641 struct i915_psr { 642 bool sink_support; 643 bool source_ok; 644 }; 645 646 enum intel_pch { 647 PCH_NONE = 0, /* No PCH present */ 648 PCH_IBX, /* Ibexpeak PCH */ 649 PCH_CPT, /* Cougarpoint PCH */ 650 PCH_LPT, /* Lynxpoint PCH */ 651 PCH_NOP, 652 }; 653 654 enum intel_sbi_destination { 655 SBI_ICLK, 656 SBI_MPHY, 657 }; 658 659 #define QUIRK_PIPEA_FORCE (1<<0) 660 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 661 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 662 #define QUIRK_BACKLIGHT_PRESENT (1<<3) 663 664 struct intel_fbdev; 665 struct intel_fbc_work; 666 667 struct intel_gmbus { 668 u32 force_bit; 669 u32 reg0; 670 u32 gpio_reg; 671 struct drm_i915_private *dev_priv; 672 }; 673 674 struct intel_iic_softc { 675 struct drm_device *drm_dev; 676 device_t iic_dev; 677 bool force_bit_dev; 678 char name[32]; 679 uint32_t reg; 680 uint32_t reg0; 681 }; 682 683 struct i915_suspend_saved_registers { 684 u8 saveLBB; 685 u32 saveDSPACNTR; 686 u32 saveDSPBCNTR; 687 u32 saveDSPARB; 688 u32 savePIPEACONF; 689 u32 savePIPEBCONF; 690 u32 savePIPEASRC; 691 u32 savePIPEBSRC; 692 u32 saveFPA0; 693 u32 saveFPA1; 694 u32 saveDPLL_A; 695 u32 saveDPLL_A_MD; 696 u32 saveHTOTAL_A; 697 u32 saveHBLANK_A; 698 u32 saveHSYNC_A; 699 u32 saveVTOTAL_A; 700 u32 saveVBLANK_A; 701 u32 saveVSYNC_A; 702 u32 saveBCLRPAT_A; 703 u32 saveTRANSACONF; 704 u32 saveTRANS_HTOTAL_A; 705 u32 saveTRANS_HBLANK_A; 706 u32 saveTRANS_HSYNC_A; 707 u32 saveTRANS_VTOTAL_A; 708 u32 saveTRANS_VBLANK_A; 709 u32 saveTRANS_VSYNC_A; 710 u32 savePIPEASTAT; 711 u32 saveDSPASTRIDE; 712 u32 saveDSPASIZE; 713 u32 saveDSPAPOS; 714 u32 saveDSPAADDR; 715 u32 saveDSPASURF; 716 u32 saveDSPATILEOFF; 717 u32 savePFIT_PGM_RATIOS; 718 u32 saveBLC_HIST_CTL; 719 u32 saveBLC_PWM_CTL; 720 u32 saveBLC_PWM_CTL2; 721 u32 saveBLC_HIST_CTL_B; 722 u32 saveBLC_CPU_PWM_CTL; 723 u32 saveBLC_CPU_PWM_CTL2; 724 u32 saveFPB0; 725 u32 saveFPB1; 726 u32 saveDPLL_B; 727 u32 saveDPLL_B_MD; 728 u32 saveHTOTAL_B; 729 u32 saveHBLANK_B; 730 u32 saveHSYNC_B; 731 u32 saveVTOTAL_B; 732 u32 saveVBLANK_B; 733 u32 saveVSYNC_B; 734 u32 saveBCLRPAT_B; 735 u32 saveTRANSBCONF; 736 u32 saveTRANS_HTOTAL_B; 737 u32 saveTRANS_HBLANK_B; 738 u32 saveTRANS_HSYNC_B; 739 u32 saveTRANS_VTOTAL_B; 740 u32 saveTRANS_VBLANK_B; 741 u32 saveTRANS_VSYNC_B; 742 u32 savePIPEBSTAT; 743 u32 saveDSPBSTRIDE; 744 u32 saveDSPBSIZE; 745 u32 saveDSPBPOS; 746 u32 saveDSPBADDR; 747 u32 saveDSPBSURF; 748 u32 saveDSPBTILEOFF; 749 u32 saveVGA0; 750 u32 saveVGA1; 751 u32 saveVGA_PD; 752 u32 saveVGACNTRL; 753 u32 saveADPA; 754 u32 saveLVDS; 755 u32 savePP_ON_DELAYS; 756 u32 savePP_OFF_DELAYS; 757 u32 saveDVOA; 758 u32 saveDVOB; 759 u32 saveDVOC; 760 u32 savePP_ON; 761 u32 savePP_OFF; 762 u32 savePP_CONTROL; 763 u32 savePP_DIVISOR; 764 u32 savePFIT_CONTROL; 765 u32 save_palette_a[256]; 766 u32 save_palette_b[256]; 767 u32 saveFBC_CONTROL; 768 u32 saveIER; 769 u32 saveIIR; 770 u32 saveIMR; 771 u32 saveDEIER; 772 u32 saveDEIMR; 773 u32 saveGTIER; 774 u32 saveGTIMR; 775 u32 saveFDI_RXA_IMR; 776 u32 saveFDI_RXB_IMR; 777 u32 saveCACHE_MODE_0; 778 u32 saveMI_ARB_STATE; 779 u32 saveSWF0[16]; 780 u32 saveSWF1[16]; 781 u32 saveSWF2[3]; 782 u8 saveMSR; 783 u8 saveSR[8]; 784 u8 saveGR[25]; 785 u8 saveAR_INDEX; 786 u8 saveAR[21]; 787 u8 saveDACMASK; 788 u8 saveCR[37]; 789 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 790 u32 saveCURACNTR; 791 u32 saveCURAPOS; 792 u32 saveCURABASE; 793 u32 saveCURBCNTR; 794 u32 saveCURBPOS; 795 u32 saveCURBBASE; 796 u32 saveCURSIZE; 797 u32 saveDP_B; 798 u32 saveDP_C; 799 u32 saveDP_D; 800 u32 savePIPEA_GMCH_DATA_M; 801 u32 savePIPEB_GMCH_DATA_M; 802 u32 savePIPEA_GMCH_DATA_N; 803 u32 savePIPEB_GMCH_DATA_N; 804 u32 savePIPEA_DP_LINK_M; 805 u32 savePIPEB_DP_LINK_M; 806 u32 savePIPEA_DP_LINK_N; 807 u32 savePIPEB_DP_LINK_N; 808 u32 saveFDI_RXA_CTL; 809 u32 saveFDI_TXA_CTL; 810 u32 saveFDI_RXB_CTL; 811 u32 saveFDI_TXB_CTL; 812 u32 savePFA_CTL_1; 813 u32 savePFB_CTL_1; 814 u32 savePFA_WIN_SZ; 815 u32 savePFB_WIN_SZ; 816 u32 savePFA_WIN_POS; 817 u32 savePFB_WIN_POS; 818 u32 savePCH_DREF_CONTROL; 819 u32 saveDISP_ARB_CTL; 820 u32 savePIPEA_DATA_M1; 821 u32 savePIPEA_DATA_N1; 822 u32 savePIPEA_LINK_M1; 823 u32 savePIPEA_LINK_N1; 824 u32 savePIPEB_DATA_M1; 825 u32 savePIPEB_DATA_N1; 826 u32 savePIPEB_LINK_M1; 827 u32 savePIPEB_LINK_N1; 828 u32 saveMCHBAR_RENDER_STANDBY; 829 u32 savePCH_PORT_HOTPLUG; 830 }; 831 832 struct vlv_s0ix_state { 833 /* GAM */ 834 u32 wr_watermark; 835 u32 gfx_prio_ctrl; 836 u32 arb_mode; 837 u32 gfx_pend_tlb0; 838 u32 gfx_pend_tlb1; 839 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; 840 u32 media_max_req_count; 841 u32 gfx_max_req_count; 842 u32 render_hwsp; 843 u32 ecochk; 844 u32 bsd_hwsp; 845 u32 blt_hwsp; 846 u32 tlb_rd_addr; 847 848 /* MBC */ 849 u32 g3dctl; 850 u32 gsckgctl; 851 u32 mbctl; 852 853 /* GCP */ 854 u32 ucgctl1; 855 u32 ucgctl3; 856 u32 rcgctl1; 857 u32 rcgctl2; 858 u32 rstctl; 859 u32 misccpctl; 860 861 /* GPM */ 862 u32 gfxpause; 863 u32 rpdeuhwtc; 864 u32 rpdeuc; 865 u32 ecobus; 866 u32 pwrdwnupctl; 867 u32 rp_down_timeout; 868 u32 rp_deucsw; 869 u32 rcubmabdtmr; 870 u32 rcedata; 871 u32 spare2gh; 872 873 /* Display 1 CZ domain */ 874 u32 gt_imr; 875 u32 gt_ier; 876 u32 pm_imr; 877 u32 pm_ier; 878 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; 879 880 /* GT SA CZ domain */ 881 u32 tilectl; 882 u32 gt_fifoctl; 883 u32 gtlc_wake_ctrl; 884 u32 gtlc_survive; 885 u32 pmwgicz; 886 887 /* Display 2 CZ domain */ 888 u32 gu_ctl0; 889 u32 gu_ctl1; 890 u32 clock_gate_dis2; 891 }; 892 893 struct intel_gen6_power_mgmt { 894 /* work and pm_iir are protected by dev_priv->irq_lock */ 895 struct work_struct work; 896 u32 pm_iir; 897 898 /* Frequencies are stored in potentially platform dependent multiples. 899 * In other words, *_freq needs to be multiplied by X to be interesting. 900 * Soft limits are those which are used for the dynamic reclocking done 901 * by the driver (raise frequencies under heavy loads, and lower for 902 * lighter loads). Hard limits are those imposed by the hardware. 903 * 904 * A distinction is made for overclocking, which is never enabled by 905 * default, and is considered to be above the hard limit if it's 906 * possible at all. 907 */ 908 u8 cur_freq; /* Current frequency (cached, may not == HW) */ 909 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ 910 u8 max_freq_softlimit; /* Max frequency permitted by the driver */ 911 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ 912 u8 min_freq; /* AKA RPn. Minimum frequency */ 913 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ 914 u8 rp1_freq; /* "less than" RP0 power/freqency */ 915 u8 rp0_freq; /* Non-overclocked max frequency. */ 916 917 int last_adj; 918 enum { LOW_POWER, BETWEEN, HIGH_POWER } power; 919 920 bool enabled; 921 struct delayed_work delayed_resume_work; 922 923 /* 924 * Protects RPS/RC6 register access and PCU communication. 925 * Must be taken after struct_mutex if nested. 926 */ 927 struct lock hw_lock; 928 }; 929 930 /* defined intel_pm.c */ 931 extern struct lock mchdev_lock; 932 933 struct intel_ilk_power_mgmt { 934 u8 cur_delay; 935 u8 min_delay; 936 u8 max_delay; 937 u8 fmax; 938 u8 fstart; 939 940 u64 last_count1; 941 unsigned long last_time1; 942 unsigned long chipset_power; 943 u64 last_count2; 944 struct timespec last_time2; 945 unsigned long gfx_power; 946 u8 corr; 947 948 int c_m; 949 int r_t; 950 951 struct drm_i915_gem_object *pwrctx; 952 struct drm_i915_gem_object *renderctx; 953 }; 954 955 struct drm_i915_private; 956 struct i915_power_well; 957 958 struct i915_power_well_ops { 959 /* 960 * Synchronize the well's hw state to match the current sw state, for 961 * example enable/disable it based on the current refcount. Called 962 * during driver init and resume time, possibly after first calling 963 * the enable/disable handlers. 964 */ 965 void (*sync_hw)(struct drm_i915_private *dev_priv, 966 struct i915_power_well *power_well); 967 /* 968 * Enable the well and resources that depend on it (for example 969 * interrupts located on the well). Called after the 0->1 refcount 970 * transition. 971 */ 972 void (*enable)(struct drm_i915_private *dev_priv, 973 struct i915_power_well *power_well); 974 /* 975 * Disable the well and resources that depend on it. Called after 976 * the 1->0 refcount transition. 977 */ 978 void (*disable)(struct drm_i915_private *dev_priv, 979 struct i915_power_well *power_well); 980 /* Returns the hw enabled state. */ 981 bool (*is_enabled)(struct drm_i915_private *dev_priv, 982 struct i915_power_well *power_well); 983 }; 984 985 /* Power well structure for haswell */ 986 struct i915_power_well { 987 const char *name; 988 bool always_on; 989 /* power well enable/disable usage count */ 990 int count; 991 /* cached hw enabled state */ 992 bool hw_enabled; 993 unsigned long domains; 994 unsigned long data; 995 const struct i915_power_well_ops *ops; 996 }; 997 998 struct i915_power_domains { 999 /* 1000 * Power wells needed for initialization at driver init and suspend 1001 * time are on. They are kept on until after the first modeset. 1002 */ 1003 bool init_power_on; 1004 bool initializing; 1005 int power_well_count; 1006 1007 struct lock lock; 1008 int domain_use_count[POWER_DOMAIN_NUM]; 1009 struct i915_power_well *power_wells; 1010 }; 1011 1012 struct i915_dri1_state { 1013 unsigned allow_batchbuffer : 1; 1014 u32 __iomem *gfx_hws_cpu_addr; 1015 1016 unsigned int cpp; 1017 int back_offset; 1018 int front_offset; 1019 int current_page; 1020 int page_flipping; 1021 1022 uint32_t counter; 1023 }; 1024 1025 struct i915_ums_state { 1026 /** 1027 * Flag if the X Server, and thus DRM, is not currently in 1028 * control of the device. 1029 * 1030 * This is set between LeaveVT and EnterVT. It needs to be 1031 * replaced with a semaphore. It also needs to be 1032 * transitioned away from for kernel modesetting. 1033 */ 1034 int mm_suspended; 1035 }; 1036 1037 #define MAX_L3_SLICES 2 1038 struct intel_l3_parity { 1039 u32 *remap_info[MAX_L3_SLICES]; 1040 struct work_struct error_work; 1041 int which_slice; 1042 }; 1043 1044 struct i915_gem_mm { 1045 /** Memory allocator for GTT stolen memory */ 1046 struct drm_mm stolen; 1047 /** List of all objects in gtt_space. Used to restore gtt 1048 * mappings on resume */ 1049 struct list_head bound_list; 1050 /** 1051 * List of objects which are not bound to the GTT (thus 1052 * are idle and not used by the GPU) but still have 1053 * (presumably uncached) pages still attached. 1054 */ 1055 struct list_head unbound_list; 1056 1057 /** Usable portion of the GTT for GEM */ 1058 unsigned long stolen_base; /* limited to low memory (32-bit) */ 1059 1060 /** PPGTT used for aliasing the PPGTT with the GTT */ 1061 struct i915_hw_ppgtt *aliasing_ppgtt; 1062 1063 eventhandler_tag inactive_shrinker; 1064 bool shrinker_no_lock_stealing; 1065 1066 /** LRU list of objects with fence regs on them. */ 1067 struct list_head fence_list; 1068 1069 /** 1070 * We leave the user IRQ off as much as possible, 1071 * but this means that requests will finish and never 1072 * be retired once the system goes idle. Set a timer to 1073 * fire periodically while the ring is running. When it 1074 * fires, go retire requests. 1075 */ 1076 struct delayed_work retire_work; 1077 1078 /** 1079 * When we detect an idle GPU, we want to turn on 1080 * powersaving features. So once we see that there 1081 * are no more requests outstanding and no more 1082 * arrive within a small period of time, we fire 1083 * off the idle_work. 1084 */ 1085 struct delayed_work idle_work; 1086 1087 /** 1088 * Are we in a non-interruptible section of code like 1089 * modesetting? 1090 */ 1091 bool interruptible; 1092 1093 /** 1094 * Is the GPU currently considered idle, or busy executing userspace 1095 * requests? Whilst idle, we attempt to power down the hardware and 1096 * display clocks. In order to reduce the effect on performance, there 1097 * is a slight delay before we do so. 1098 */ 1099 bool busy; 1100 1101 /* the indicator for dispatch video commands on two BSD rings */ 1102 int bsd_ring_dispatch_index; 1103 1104 /** Bit 6 swizzling required for X tiling */ 1105 uint32_t bit_6_swizzle_x; 1106 /** Bit 6 swizzling required for Y tiling */ 1107 uint32_t bit_6_swizzle_y; 1108 1109 /* accounting, useful for userland debugging */ 1110 struct spinlock object_stat_lock; 1111 size_t object_memory; 1112 u32 object_count; 1113 }; 1114 1115 struct drm_i915_error_state_buf { 1116 unsigned bytes; 1117 unsigned size; 1118 int err; 1119 u8 *buf; 1120 loff_t start; 1121 loff_t pos; 1122 }; 1123 1124 struct i915_error_state_file_priv { 1125 struct drm_device *dev; 1126 struct drm_i915_error_state *error; 1127 }; 1128 1129 struct i915_gpu_error { 1130 /* For hangcheck timer */ 1131 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ 1132 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 1133 /* Hang gpu twice in this window and your context gets banned */ 1134 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) 1135 1136 struct timer_list hangcheck_timer; 1137 1138 /* For reset and error_state handling. */ 1139 struct lock lock; 1140 /* Protected by the above dev->gpu_error.lock. */ 1141 struct drm_i915_error_state *first_error; 1142 struct work_struct work; 1143 1144 1145 unsigned long missed_irq_rings; 1146 1147 /** 1148 * State variable controlling the reset flow and count 1149 * 1150 * This is a counter which gets incremented when reset is triggered, 1151 * and again when reset has been handled. So odd values (lowest bit set) 1152 * means that reset is in progress and even values that 1153 * (reset_counter >> 1):th reset was successfully completed. 1154 * 1155 * If reset is not completed succesfully, the I915_WEDGE bit is 1156 * set meaning that hardware is terminally sour and there is no 1157 * recovery. All waiters on the reset_queue will be woken when 1158 * that happens. 1159 * 1160 * This counter is used by the wait_seqno code to notice that reset 1161 * event happened and it needs to restart the entire ioctl (since most 1162 * likely the seqno it waited for won't ever signal anytime soon). 1163 * 1164 * This is important for lock-free wait paths, where no contended lock 1165 * naturally enforces the correct ordering between the bail-out of the 1166 * waiter and the gpu reset work code. 1167 */ 1168 atomic_t reset_counter; 1169 1170 #define I915_RESET_IN_PROGRESS_FLAG 1 1171 #define I915_WEDGED (1 << 31) 1172 1173 /** 1174 * Waitqueue to signal when the reset has completed. Used by clients 1175 * that wait for dev_priv->mm.wedged to settle. 1176 */ 1177 wait_queue_head_t reset_queue; 1178 1179 /* Userspace knobs for gpu hang simulation; 1180 * combines both a ring mask, and extra flags 1181 */ 1182 u32 stop_rings; 1183 #define I915_STOP_RING_ALLOW_BAN (1 << 31) 1184 #define I915_STOP_RING_ALLOW_WARN (1 << 30) 1185 1186 /* For missed irq/seqno simulation. */ 1187 unsigned int test_irq_rings; 1188 }; 1189 1190 enum modeset_restore { 1191 MODESET_ON_LID_OPEN, 1192 MODESET_DONE, 1193 MODESET_SUSPENDED, 1194 }; 1195 1196 struct ddi_vbt_port_info { 1197 uint8_t hdmi_level_shift; 1198 1199 uint8_t supports_dvi:1; 1200 uint8_t supports_hdmi:1; 1201 uint8_t supports_dp:1; 1202 }; 1203 1204 enum drrs_support_type { 1205 DRRS_NOT_SUPPORTED = 0, 1206 STATIC_DRRS_SUPPORT = 1, 1207 SEAMLESS_DRRS_SUPPORT = 2 1208 }; 1209 1210 struct intel_vbt_data { 1211 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 1212 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 1213 1214 /* Feature bits */ 1215 unsigned int int_tv_support:1; 1216 unsigned int lvds_dither:1; 1217 unsigned int lvds_vbt:1; 1218 unsigned int int_crt_support:1; 1219 unsigned int lvds_use_ssc:1; 1220 unsigned int display_clock_mode:1; 1221 unsigned int fdi_rx_polarity_inverted:1; 1222 unsigned int has_mipi:1; 1223 int lvds_ssc_freq; 1224 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ 1225 1226 enum drrs_support_type drrs_type; 1227 1228 /* eDP */ 1229 int edp_rate; 1230 int edp_lanes; 1231 int edp_preemphasis; 1232 int edp_vswing; 1233 bool edp_initialized; 1234 bool edp_support; 1235 int edp_bpp; 1236 struct edp_power_seq edp_pps; 1237 1238 struct { 1239 u16 pwm_freq_hz; 1240 bool present; 1241 bool active_low_pwm; 1242 } backlight; 1243 1244 /* MIPI DSI */ 1245 struct { 1246 u16 port; 1247 u16 panel_id; 1248 struct mipi_config *config; 1249 struct mipi_pps_data *pps; 1250 u8 seq_version; 1251 u32 size; 1252 u8 *data; 1253 u8 *sequence[MIPI_SEQ_MAX]; 1254 } dsi; 1255 1256 int crt_ddc_pin; 1257 1258 int child_dev_num; 1259 union child_device_config *child_dev; 1260 1261 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; 1262 }; 1263 1264 enum intel_ddb_partitioning { 1265 INTEL_DDB_PART_1_2, 1266 INTEL_DDB_PART_5_6, /* IVB+ */ 1267 }; 1268 1269 struct intel_wm_level { 1270 bool enable; 1271 uint32_t pri_val; 1272 uint32_t spr_val; 1273 uint32_t cur_val; 1274 uint32_t fbc_val; 1275 }; 1276 1277 struct ilk_wm_values { 1278 uint32_t wm_pipe[3]; 1279 uint32_t wm_lp[3]; 1280 uint32_t wm_lp_spr[3]; 1281 uint32_t wm_linetime[3]; 1282 bool enable_fbc_wm; 1283 enum intel_ddb_partitioning partitioning; 1284 }; 1285 1286 /* 1287 * This struct helps tracking the state needed for runtime PM, which puts the 1288 * device in PCI D3 state. Notice that when this happens, nothing on the 1289 * graphics device works, even register access, so we don't get interrupts nor 1290 * anything else. 1291 * 1292 * Every piece of our code that needs to actually touch the hardware needs to 1293 * either call intel_runtime_pm_get or call intel_display_power_get with the 1294 * appropriate power domain. 1295 * 1296 * Our driver uses the autosuspend delay feature, which means we'll only really 1297 * suspend if we stay with zero refcount for a certain amount of time. The 1298 * default value is currently very conservative (see intel_init_runtime_pm), but 1299 * it can be changed with the standard runtime PM files from sysfs. 1300 * 1301 * The irqs_disabled variable becomes true exactly after we disable the IRQs and 1302 * goes back to false exactly before we reenable the IRQs. We use this variable 1303 * to check if someone is trying to enable/disable IRQs while they're supposed 1304 * to be disabled. This shouldn't happen and we'll print some error messages in 1305 * case it happens. 1306 * 1307 * For more, read the Documentation/power/runtime_pm.txt. 1308 */ 1309 struct i915_runtime_pm { 1310 bool suspended; 1311 bool irqs_disabled; 1312 }; 1313 1314 enum intel_pipe_crc_source { 1315 INTEL_PIPE_CRC_SOURCE_NONE, 1316 INTEL_PIPE_CRC_SOURCE_PLANE1, 1317 INTEL_PIPE_CRC_SOURCE_PLANE2, 1318 INTEL_PIPE_CRC_SOURCE_PF, 1319 INTEL_PIPE_CRC_SOURCE_PIPE, 1320 /* TV/DP on pre-gen5/vlv can't use the pipe source. */ 1321 INTEL_PIPE_CRC_SOURCE_TV, 1322 INTEL_PIPE_CRC_SOURCE_DP_B, 1323 INTEL_PIPE_CRC_SOURCE_DP_C, 1324 INTEL_PIPE_CRC_SOURCE_DP_D, 1325 INTEL_PIPE_CRC_SOURCE_AUTO, 1326 INTEL_PIPE_CRC_SOURCE_MAX, 1327 }; 1328 1329 struct intel_pipe_crc_entry { 1330 uint32_t frame; 1331 uint32_t crc[5]; 1332 }; 1333 1334 #define INTEL_PIPE_CRC_ENTRIES_NR 128 1335 struct intel_pipe_crc { 1336 struct spinlock lock; 1337 bool opened; /* exclusive access to the result file */ 1338 struct intel_pipe_crc_entry *entries; 1339 enum intel_pipe_crc_source source; 1340 int head, tail; 1341 wait_queue_head_t wq; 1342 }; 1343 1344 struct drm_i915_private { 1345 struct drm_device *dev; 1346 struct kmem_cache *slab; 1347 1348 struct intel_device_info info; 1349 1350 int relative_constants_mode; 1351 1352 device_t *gmbus_bridge; 1353 device_t *bbbus_bridge; 1354 device_t *bbbus; 1355 1356 drm_local_map_t *sarea; 1357 drm_local_map_t *mmio_map; 1358 char __iomem *regs; 1359 1360 struct intel_uncore uncore; 1361 1362 device_t *gmbus; 1363 1364 1365 /** gmbus_mutex protects against concurrent usage of the single hw gmbus 1366 * controller on different i2c buses. */ 1367 struct lock gmbus_mutex; 1368 1369 struct _drm_i915_sarea *sarea_priv; 1370 /** 1371 * Base address of the gmbus and gpio block. 1372 */ 1373 uint32_t gpio_mmio_base; 1374 1375 /* MMIO base address for MIPI regs */ 1376 uint32_t mipi_mmio_base; 1377 1378 wait_queue_head_t gmbus_wait_queue; 1379 1380 struct pci_dev *bridge_dev; 1381 struct intel_engine_cs ring[I915_NUM_RINGS]; 1382 uint32_t last_seqno, next_seqno; 1383 1384 drm_dma_handle_t *status_page_dmah; 1385 struct resource *mch_res; 1386 int mch_res_rid; 1387 1388 /* protects the irq masks */ 1389 struct lock irq_lock; 1390 1391 bool display_irqs_enabled; 1392 1393 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ 1394 struct pm_qos_request pm_qos; 1395 1396 /* DPIO indirect register protection */ 1397 struct lock dpio_lock; 1398 1399 /** Cached value of IMR to avoid reads in updating the bitfield */ 1400 union { 1401 u32 irq_mask; 1402 u32 de_irq_mask[I915_MAX_PIPES]; 1403 }; 1404 u32 gt_irq_mask; 1405 u32 pm_irq_mask; 1406 u32 pm_rps_events; 1407 u32 pipestat_irq_mask[I915_MAX_PIPES]; 1408 1409 struct work_struct hotplug_work; 1410 bool enable_hotplug_processing; 1411 struct { 1412 unsigned long hpd_last_jiffies; 1413 int hpd_cnt; 1414 enum { 1415 HPD_ENABLED = 0, 1416 HPD_DISABLED = 1, 1417 HPD_MARK_DISABLED = 2 1418 } hpd_mark; 1419 } hpd_stats[HPD_NUM_PINS]; 1420 u32 hpd_event_bits; 1421 struct timer_list hotplug_reenable_timer; 1422 1423 struct i915_fbc fbc; 1424 struct i915_drrs drrs; 1425 struct intel_opregion opregion; 1426 struct intel_vbt_data vbt; 1427 1428 /* overlay */ 1429 struct intel_overlay *overlay; 1430 1431 /* backlight registers and fields in struct intel_panel */ 1432 struct spinlock backlight_lock; 1433 1434 /* LVDS info */ 1435 bool no_aux_handshake; 1436 1437 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 1438 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 1439 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 1440 1441 unsigned int fsb_freq, mem_freq, is_ddr3; 1442 unsigned int vlv_cdclk_freq; 1443 1444 /** 1445 * wq - Driver workqueue for GEM. 1446 * 1447 * NOTE: Work items scheduled here are not allowed to grab any modeset 1448 * locks, for otherwise the flushing done in the pageflip code will 1449 * result in deadlocks. 1450 */ 1451 struct workqueue_struct *wq; 1452 1453 /* Display functions */ 1454 struct drm_i915_display_funcs display; 1455 1456 /* PCH chipset type */ 1457 enum intel_pch pch_type; 1458 unsigned short pch_id; 1459 1460 unsigned long quirks; 1461 1462 enum modeset_restore modeset_restore; 1463 struct lock modeset_restore_lock; 1464 1465 struct list_head vm_list; /* Global list of all address spaces */ 1466 struct i915_gtt gtt; /* VM representing the global address space */ 1467 1468 struct i915_gem_mm mm; 1469 #if defined(CONFIG_MMU_NOTIFIER) 1470 DECLARE_HASHTABLE(mmu_notifiers, 7); 1471 #endif 1472 1473 /* Kernel Modesetting */ 1474 1475 struct sdvo_device_mapping sdvo_mappings[2]; 1476 1477 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; 1478 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; 1479 wait_queue_head_t pending_flip_queue; 1480 1481 #ifdef CONFIG_DEBUG_FS 1482 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; 1483 #endif 1484 1485 int num_shared_dpll; 1486 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1487 struct intel_ddi_plls ddi_plls; 1488 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; 1489 1490 /* Reclocking support */ 1491 bool render_reclock_avail; 1492 bool lvds_downclock_avail; 1493 /* indicates the reduced downclock for LVDS*/ 1494 int lvds_downclock; 1495 u16 orig_clock; 1496 1497 bool mchbar_need_disable; 1498 1499 struct intel_l3_parity l3_parity; 1500 1501 /* Cannot be determined by PCIID. You must always read a register. */ 1502 size_t ellc_size; 1503 1504 /* gen6+ rps state */ 1505 struct intel_gen6_power_mgmt rps; 1506 1507 /* ilk-only ips/rps state. Everything in here is protected by the global 1508 * mchdev_lock in intel_pm.c */ 1509 struct intel_ilk_power_mgmt ips; 1510 1511 struct i915_power_domains power_domains; 1512 1513 struct i915_psr psr; 1514 1515 struct i915_gpu_error gpu_error; 1516 1517 struct drm_i915_gem_object *vlv_pctx; 1518 1519 #ifdef CONFIG_DRM_I915_FBDEV 1520 /* list of fbdev register on this device */ 1521 struct intel_fbdev *fbdev; 1522 #endif 1523 1524 /* 1525 * The console may be contended at resume, but we don't 1526 * want it to block on it. 1527 */ 1528 struct work_struct console_resume_work; 1529 1530 struct drm_property *broadcast_rgb_property; 1531 struct drm_property *force_audio_property; 1532 1533 uint32_t hw_context_size; 1534 struct list_head context_list; 1535 1536 u32 fdi_rx_config; 1537 1538 u32 suspend_count; 1539 struct i915_suspend_saved_registers regfile; 1540 struct vlv_s0ix_state vlv_s0ix_state; 1541 1542 struct { 1543 /* 1544 * Raw watermark latency values: 1545 * in 0.1us units for WM0, 1546 * in 0.5us units for WM1+. 1547 */ 1548 /* primary */ 1549 uint16_t pri_latency[5]; 1550 /* sprite */ 1551 uint16_t spr_latency[5]; 1552 /* cursor */ 1553 uint16_t cur_latency[5]; 1554 1555 /* current hardware state */ 1556 struct ilk_wm_values hw; 1557 } wm; 1558 1559 struct i915_runtime_pm pm; 1560 1561 /* Old dri1 support infrastructure, beware the dragons ya fools entering 1562 * here! */ 1563 struct i915_dri1_state dri1; 1564 /* Old ums support infrastructure, same warning applies. */ 1565 struct i915_ums_state ums; 1566 1567 /* 1568 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 1569 * will be rejected. Instead look for a better place. 1570 */ 1571 }; 1572 1573 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 1574 { 1575 return dev->dev_private; 1576 } 1577 1578 /* Iterate over initialised rings */ 1579 #define for_each_ring(ring__, dev_priv__, i__) \ 1580 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 1581 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 1582 1583 enum hdmi_force_audio { 1584 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 1585 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 1586 HDMI_AUDIO_AUTO, /* trust EDID */ 1587 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 1588 }; 1589 1590 #define I915_GTT_OFFSET_NONE ((u32)-1) 1591 1592 struct drm_i915_gem_object_ops { 1593 /* Interface between the GEM object and its backing storage. 1594 * get_pages() is called once prior to the use of the associated set 1595 * of pages before to binding them into the GTT, and put_pages() is 1596 * called after we no longer need them. As we expect there to be 1597 * associated cost with migrating pages between the backing storage 1598 * and making them available for the GPU (e.g. clflush), we may hold 1599 * onto the pages after they are no longer referenced by the GPU 1600 * in case they may be used again shortly (for example migrating the 1601 * pages to a different memory domain within the GTT). put_pages() 1602 * will therefore most likely be called when the object itself is 1603 * being released or under memory pressure (where we attempt to 1604 * reap pages for the shrinker). 1605 */ 1606 int (*get_pages)(struct drm_i915_gem_object *); 1607 void (*put_pages)(struct drm_i915_gem_object *); 1608 int (*dmabuf_export)(struct drm_i915_gem_object *); 1609 void (*release)(struct drm_i915_gem_object *); 1610 }; 1611 1612 struct drm_i915_gem_object { 1613 struct drm_gem_object base; 1614 1615 const struct drm_i915_gem_object_ops *ops; 1616 1617 /** List of VMAs backed by this object */ 1618 struct list_head vma_list; 1619 1620 /** Stolen memory for this object, instead of being backed by shmem. */ 1621 struct drm_mm_node *stolen; 1622 struct list_head global_list; 1623 1624 struct list_head ring_list; 1625 /** Used in execbuf to temporarily hold a ref */ 1626 struct list_head obj_exec_link; 1627 1628 /** 1629 * This is set if the object is on the active lists (has pending 1630 * rendering and so a non-zero seqno), and is not set if it i s on 1631 * inactive (ready to be unbound) list. 1632 */ 1633 unsigned int active:1; 1634 1635 /** 1636 * This is set if the object has been written to since last bound 1637 * to the GTT 1638 */ 1639 unsigned int dirty:1; 1640 1641 /** 1642 * Fence register bits (if any) for this object. Will be set 1643 * as needed when mapped into the GTT. 1644 * Protected by dev->struct_mutex. 1645 */ 1646 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1647 1648 /** 1649 * Advice: are the backing pages purgeable? 1650 */ 1651 unsigned int madv:2; 1652 1653 /** 1654 * Current tiling mode for the object. 1655 */ 1656 unsigned int tiling_mode:2; 1657 /** 1658 * Whether the tiling parameters for the currently associated fence 1659 * register have changed. Note that for the purposes of tracking 1660 * tiling changes we also treat the unfenced register, the register 1661 * slot that the object occupies whilst it executes a fenced 1662 * command (such as BLT on gen2/3), as a "fence". 1663 */ 1664 unsigned int fence_dirty:1; 1665 1666 /** 1667 * Is the object at the current location in the gtt mappable and 1668 * fenceable? Used to avoid costly recalculations. 1669 */ 1670 unsigned int map_and_fenceable:1; 1671 1672 /** 1673 * Whether the current gtt mapping needs to be mappable (and isn't just 1674 * mappable by accident). Track pin and fault separate for a more 1675 * accurate mappable working set. 1676 */ 1677 unsigned int fault_mappable:1; 1678 unsigned int pin_mappable:1; 1679 unsigned int pin_display:1; 1680 1681 /* 1682 * Is the GPU currently using a fence to access this buffer, 1683 */ 1684 unsigned int pending_fenced_gpu_access:1; 1685 unsigned int fenced_gpu_access:1; 1686 1687 unsigned int cache_level:3; 1688 1689 unsigned int has_aliasing_ppgtt_mapping:1; 1690 unsigned int has_global_gtt_mapping:1; 1691 unsigned int has_dma_mapping:1; 1692 1693 vm_page_t *pages; 1694 int pages_pin_count; 1695 1696 /* prime dma-buf support */ 1697 void *dma_buf_vmapping; 1698 int vmapping_count; 1699 1700 struct intel_engine_cs *ring; 1701 1702 /** Breadcrumb of last rendering to the buffer. */ 1703 uint32_t last_read_seqno; 1704 uint32_t last_write_seqno; 1705 /** Breadcrumb of last fenced GPU access to the buffer. */ 1706 uint32_t last_fenced_seqno; 1707 1708 /** Current tiling stride for the object, if it's tiled. */ 1709 uint32_t stride; 1710 1711 /** References from framebuffers, locks out tiling changes. */ 1712 unsigned long framebuffer_references; 1713 1714 /** Record of address bit 17 of each page at last unbind. */ 1715 unsigned long *bit_17; 1716 1717 /** User space pin count and filp owning the pin */ 1718 unsigned long user_pin_count; 1719 struct drm_file *pin_filp; 1720 1721 /** for phy allocated objects */ 1722 drm_dma_handle_t *phys_handle; 1723 1724 union { 1725 struct i915_gem_userptr { 1726 uintptr_t ptr; 1727 unsigned read_only :1; 1728 unsigned workers :4; 1729 #define I915_GEM_USERPTR_MAX_WORKERS 15 1730 1731 struct mm_struct *mm; 1732 struct i915_mmu_object *mn; 1733 struct work_struct *work; 1734 } userptr; 1735 }; 1736 }; 1737 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1738 1739 /** 1740 * Request queue structure. 1741 * 1742 * The request queue allows us to note sequence numbers that have been emitted 1743 * and may be associated with active buffers to be retired. 1744 * 1745 * By keeping this list, we can avoid having to do questionable 1746 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1747 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1748 */ 1749 struct drm_i915_gem_request { 1750 /** On Which ring this request was generated */ 1751 struct intel_engine_cs *ring; 1752 1753 /** GEM sequence number associated with this request. */ 1754 uint32_t seqno; 1755 1756 /** Position in the ringbuffer of the start of the request */ 1757 u32 head; 1758 1759 /** Position in the ringbuffer of the end of the request */ 1760 u32 tail; 1761 1762 /** Context related to this request */ 1763 struct intel_context *ctx; 1764 1765 /** Batch buffer related to this request if any */ 1766 struct drm_i915_gem_object *batch_obj; 1767 1768 /** Time at which this request was emitted, in jiffies. */ 1769 unsigned long emitted_jiffies; 1770 1771 /** global list entry for this request */ 1772 struct list_head list; 1773 1774 struct drm_i915_file_private *file_priv; 1775 /** file_priv list entry for this request */ 1776 struct list_head client_list; 1777 }; 1778 1779 struct drm_i915_file_private { 1780 struct drm_i915_private *dev_priv; 1781 struct drm_file *file; 1782 1783 struct { 1784 struct spinlock lock; 1785 struct list_head request_list; 1786 struct delayed_work idle_work; 1787 } mm; 1788 struct idr context_idr; 1789 1790 atomic_t rps_wait_boost; 1791 struct intel_engine_cs *bsd_ring; 1792 }; 1793 1794 /* 1795 * A command that requires special handling by the command parser. 1796 */ 1797 struct drm_i915_cmd_descriptor { 1798 /* 1799 * Flags describing how the command parser processes the command. 1800 * 1801 * CMD_DESC_FIXED: The command has a fixed length if this is set, 1802 * a length mask if not set 1803 * CMD_DESC_SKIP: The command is allowed but does not follow the 1804 * standard length encoding for the opcode range in 1805 * which it falls 1806 * CMD_DESC_REJECT: The command is never allowed 1807 * CMD_DESC_REGISTER: The command should be checked against the 1808 * register whitelist for the appropriate ring 1809 * CMD_DESC_MASTER: The command is allowed if the submitting process 1810 * is the DRM master 1811 */ 1812 u32 flags; 1813 #define CMD_DESC_FIXED (1<<0) 1814 #define CMD_DESC_SKIP (1<<1) 1815 #define CMD_DESC_REJECT (1<<2) 1816 #define CMD_DESC_REGISTER (1<<3) 1817 #define CMD_DESC_BITMASK (1<<4) 1818 #define CMD_DESC_MASTER (1<<5) 1819 1820 /* 1821 * The command's unique identification bits and the bitmask to get them. 1822 * This isn't strictly the opcode field as defined in the spec and may 1823 * also include type, subtype, and/or subop fields. 1824 */ 1825 struct { 1826 u32 value; 1827 u32 mask; 1828 } cmd; 1829 1830 /* 1831 * The command's length. The command is either fixed length (i.e. does 1832 * not include a length field) or has a length field mask. The flag 1833 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has 1834 * a length mask. All command entries in a command table must include 1835 * length information. 1836 */ 1837 union { 1838 u32 fixed; 1839 u32 mask; 1840 } length; 1841 1842 /* 1843 * Describes where to find a register address in the command to check 1844 * against the ring's register whitelist. Only valid if flags has the 1845 * CMD_DESC_REGISTER bit set. 1846 */ 1847 struct { 1848 u32 offset; 1849 u32 mask; 1850 } reg; 1851 1852 #define MAX_CMD_DESC_BITMASKS 3 1853 /* 1854 * Describes command checks where a particular dword is masked and 1855 * compared against an expected value. If the command does not match 1856 * the expected value, the parser rejects it. Only valid if flags has 1857 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero 1858 * are valid. 1859 * 1860 * If the check specifies a non-zero condition_mask then the parser 1861 * only performs the check when the bits specified by condition_mask 1862 * are non-zero. 1863 */ 1864 struct { 1865 u32 offset; 1866 u32 mask; 1867 u32 expected; 1868 u32 condition_offset; 1869 u32 condition_mask; 1870 } bits[MAX_CMD_DESC_BITMASKS]; 1871 }; 1872 1873 /* 1874 * A table of commands requiring special handling by the command parser. 1875 * 1876 * Each ring has an array of tables. Each table consists of an array of command 1877 * descriptors, which must be sorted with command opcodes in ascending order. 1878 */ 1879 struct drm_i915_cmd_table { 1880 const struct drm_i915_cmd_descriptor *table; 1881 int count; 1882 }; 1883 1884 #define INTEL_INFO(dev) (&to_i915(dev)->info) 1885 1886 #define IS_I830(dev) ((dev)->pdev->device == 0x3577) 1887 #define IS_845G(dev) ((dev)->pdev->device == 0x2562) 1888 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1889 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) 1890 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1891 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) 1892 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) 1893 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1894 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1895 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1896 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) 1897 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1898 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) 1899 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) 1900 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1901 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1902 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) 1903 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1904 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ 1905 (dev)->pdev->device == 0x0152 || \ 1906 (dev)->pdev->device == 0x015a) 1907 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ 1908 (dev)->pdev->device == 0x0106 || \ 1909 (dev)->pdev->device == 0x010A) 1910 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1911 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 1912 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1913 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) 1914 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1915 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 1916 ((dev)->pdev->device & 0xFF00) == 0x0C00) 1917 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 1918 (((dev)->pdev->device & 0xf) == 0x2 || \ 1919 ((dev)->pdev->device & 0xf) == 0x6 || \ 1920 ((dev)->pdev->device & 0xf) == 0xe)) 1921 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ 1922 ((dev)->pdev->device & 0xFF00) == 0x0A00) 1923 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) 1924 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 1925 ((dev)->pdev->device & 0x00F0) == 0x0020) 1926 /* ULX machines are also considered ULT. */ 1927 #define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \ 1928 (dev)->pdev->device == 0x0A1E) 1929 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 1930 1931 /* 1932 * The genX designation typically refers to the render engine, so render 1933 * capability related checks should use IS_GEN, while display and other checks 1934 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1935 * chips, etc.). 1936 */ 1937 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1938 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1939 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1940 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1941 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1942 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1943 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) 1944 1945 #define RENDER_RING (1<<RCS) 1946 #define BSD_RING (1<<VCS) 1947 #define BLT_RING (1<<BCS) 1948 #define VEBOX_RING (1<<VECS) 1949 #define BSD2_RING (1<<VCS2) 1950 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) 1951 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) 1952 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) 1953 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) 1954 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1955 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 1956 to_i915(dev)->ellc_size) 1957 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1958 1959 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1960 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && \ 1961 (!IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) 1962 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 \ 1963 && !IS_GEN8(dev)) 1964 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false) 1965 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true) 1966 1967 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1968 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1969 1970 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1971 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1972 /* 1973 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts 1974 * even when in MSI mode. This results in spurious interrupt warnings if the 1975 * legacy irq no. is shared with another device. The kernel then disables that 1976 * interrupt source and so prevents the other device from working properly. 1977 */ 1978 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 1979 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) 1980 1981 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1982 * rows, which changed the alignment requirements and fence programming. 1983 */ 1984 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1985 IS_I915GM(dev))) 1986 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1987 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1988 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1989 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1990 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1991 1992 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1993 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1994 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1995 1996 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) 1997 1998 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 1999 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 2000 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2001 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ 2002 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) 2003 2004 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 2005 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 2006 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 2007 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 2008 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 2009 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 2010 2011 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) 2012 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 2013 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 2014 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 2015 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) 2016 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) 2017 2018 /* DPF == dynamic parity feature */ 2019 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 2020 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) 2021 2022 #define GT_FREQUENCY_MULTIPLIER 50 2023 2024 #include "i915_trace.h" 2025 2026 extern struct drm_ioctl_desc i915_ioctls[]; 2027 extern int i915_max_ioctl; 2028 2029 extern int i915_suspend(device_t kdev); 2030 extern int i915_resume(struct drm_device *dev); 2031 extern int i915_master_create(struct drm_device *dev, struct drm_master *master); 2032 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); 2033 2034 /* i915_params.c */ 2035 struct i915_params { 2036 int modeset; 2037 int panel_ignore_lid; 2038 unsigned int powersave; 2039 int semaphores; 2040 unsigned int lvds_downclock; 2041 int lvds_channel_mode; 2042 int panel_use_ssc; 2043 int vbt_sdvo_panel_type; 2044 int enable_rc6; 2045 int enable_fbc; 2046 int enable_ppgtt; 2047 int enable_psr; 2048 unsigned int preliminary_hw_support; 2049 int disable_power_well; 2050 int enable_ips; 2051 int invert_brightness; 2052 int enable_cmd_parser; 2053 /* leave bools at the end to not create holes */ 2054 bool enable_hangcheck; 2055 bool fastboot; 2056 bool prefault_disable; 2057 int reset; 2058 bool disable_display; 2059 bool disable_vtd_wa; 2060 }; 2061 extern struct i915_params i915 __read_mostly; 2062 2063 /* i915_dma.c */ 2064 void i915_update_dri1_breadcrumb(struct drm_device *dev); 2065 extern void i915_kernel_lost_context(struct drm_device * dev); 2066 extern int i915_driver_load(struct drm_device *, unsigned long flags); 2067 extern int i915_driver_unload(struct drm_device *); 2068 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 2069 extern void i915_driver_lastclose(struct drm_device * dev); 2070 extern void i915_driver_preclose(struct drm_device *dev, 2071 struct drm_file *file_priv); 2072 extern void i915_driver_postclose(struct drm_device *dev, 2073 struct drm_file *file_priv); 2074 extern int i915_driver_device_is_agp(struct drm_device * dev); 2075 #ifdef CONFIG_COMPAT 2076 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 2077 unsigned long arg); 2078 #endif 2079 extern int i915_emit_box(struct drm_device *dev, 2080 struct drm_clip_rect *box, 2081 int DR1, int DR4); 2082 extern int intel_gpu_reset(struct drm_device *dev); 2083 extern int i915_reset(struct drm_device *dev); 2084 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 2085 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 2086 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 2087 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); 2088 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); 2089 2090 extern void intel_console_resume(struct work_struct *work); 2091 2092 /* i915_irq.c */ 2093 void i915_queue_hangcheck(struct drm_device *dev); 2094 __printf(3, 4) 2095 void i915_handle_error(struct drm_device *dev, bool wedged, 2096 const char *fmt, ...); 2097 2098 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir, 2099 int new_delay); 2100 extern void intel_irq_init(struct drm_device *dev); 2101 extern void intel_hpd_init(struct drm_device *dev); 2102 2103 extern void intel_uncore_sanitize(struct drm_device *dev); 2104 extern void intel_uncore_early_sanitize(struct drm_device *dev); 2105 extern void intel_uncore_init(struct drm_device *dev); 2106 extern void intel_uncore_check_errors(struct drm_device *dev); 2107 extern void intel_uncore_fini(struct drm_device *dev); 2108 2109 void 2110 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 2111 u32 status_mask); 2112 2113 void 2114 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 2115 u32 status_mask); 2116 2117 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); 2118 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); 2119 2120 /* i915_gem.c */ 2121 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 2122 struct drm_file *file_priv); 2123 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 2124 struct drm_file *file_priv); 2125 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 2126 struct drm_file *file_priv); 2127 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 2128 struct drm_file *file_priv); 2129 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 2130 struct drm_file *file_priv); 2131 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2132 struct drm_file *file_priv); 2133 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 2134 struct drm_file *file_priv); 2135 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 2136 struct drm_file *file_priv); 2137 int i915_gem_execbuffer(struct drm_device *dev, void *data, 2138 struct drm_file *file_priv); 2139 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 2140 struct drm_file *file_priv); 2141 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 2142 struct drm_file *file_priv); 2143 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 2144 struct drm_file *file_priv); 2145 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 2146 struct drm_file *file_priv); 2147 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 2148 struct drm_file *file); 2149 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 2150 struct drm_file *file); 2151 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 2152 struct drm_file *file_priv); 2153 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 2154 struct drm_file *file_priv); 2155 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 2156 struct drm_file *file_priv); 2157 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 2158 struct drm_file *file_priv); 2159 int i915_gem_set_tiling(struct drm_device *dev, void *data, 2160 struct drm_file *file_priv); 2161 int i915_gem_get_tiling(struct drm_device *dev, void *data, 2162 struct drm_file *file_priv); 2163 int i915_gem_init_userptr(struct drm_device *dev); 2164 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, 2165 struct drm_file *file); 2166 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 2167 struct drm_file *file_priv); 2168 int i915_gem_wait_ioctl(struct drm_device *dev, void *data, 2169 struct drm_file *file_priv); 2170 void i915_gem_load(struct drm_device *dev); 2171 void *i915_gem_object_alloc(struct drm_device *dev); 2172 void i915_gem_object_free(struct drm_i915_gem_object *obj); 2173 void i915_gem_object_init(struct drm_i915_gem_object *obj, 2174 const struct drm_i915_gem_object_ops *ops); 2175 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 2176 size_t size); 2177 void i915_init_vm(struct drm_i915_private *dev_priv, 2178 struct i915_address_space *vm); 2179 void i915_gem_free_object(struct drm_gem_object *obj); 2180 void i915_gem_vma_destroy(struct i915_vma *vma); 2181 2182 #define PIN_MAPPABLE 0x1 2183 #define PIN_NONBLOCK 0x2 2184 #define PIN_GLOBAL 0x4 2185 #define PIN_OFFSET_BIAS 0x8 2186 #define PIN_OFFSET_MASK (~4095) 2187 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, 2188 struct i915_address_space *vm, 2189 uint32_t alignment, 2190 uint64_t flags); 2191 int __must_check i915_vma_unbind(struct i915_vma *vma); 2192 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); 2193 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); 2194 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 2195 void i915_gem_lastclose(struct drm_device *dev); 2196 2197 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 2198 int *needs_clflush); 2199 2200 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); 2201 static inline struct vm_page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) 2202 { 2203 return obj->pages[n]; 2204 } 2205 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) 2206 { 2207 BUG_ON(obj->pages == NULL); 2208 obj->pages_pin_count++; 2209 } 2210 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) 2211 { 2212 BUG_ON(obj->pages_pin_count == 0); 2213 obj->pages_pin_count--; 2214 } 2215 2216 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); 2217 int i915_gem_object_sync(struct drm_i915_gem_object *obj, 2218 struct intel_engine_cs *to); 2219 void i915_vma_move_to_active(struct i915_vma *vma, 2220 struct intel_engine_cs *ring); 2221 int i915_gem_dumb_create(struct drm_file *file_priv, 2222 struct drm_device *dev, 2223 struct drm_mode_create_dumb *args); 2224 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 2225 uint32_t handle, uint64_t *offset); 2226 /** 2227 * Returns true if seq1 is later than seq2. 2228 */ 2229 static inline bool 2230 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 2231 { 2232 return (int32_t)(seq1 - seq2) >= 0; 2233 } 2234 2235 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); 2236 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); 2237 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); 2238 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 2239 2240 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); 2241 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); 2242 2243 struct drm_i915_gem_request * 2244 i915_gem_find_active_request(struct intel_engine_cs *ring); 2245 2246 bool i915_gem_retire_requests(struct drm_device *dev); 2247 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); 2248 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, 2249 bool interruptible); 2250 static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2251 { 2252 return unlikely(atomic_read(&error->reset_counter) 2253 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); 2254 } 2255 2256 static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2257 { 2258 return atomic_read(&error->reset_counter) & I915_WEDGED; 2259 } 2260 2261 static inline u32 i915_reset_count(struct i915_gpu_error *error) 2262 { 2263 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; 2264 } 2265 2266 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) 2267 { 2268 return dev_priv->gpu_error.stop_rings == 0 || 2269 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; 2270 } 2271 2272 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) 2273 { 2274 return dev_priv->gpu_error.stop_rings == 0 || 2275 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; 2276 } 2277 2278 void i915_gem_reset(struct drm_device *dev); 2279 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); 2280 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 2281 int __must_check i915_gem_init(struct drm_device *dev); 2282 int __must_check i915_gem_init_hw(struct drm_device *dev); 2283 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); 2284 void i915_gem_init_swizzling(struct drm_device *dev); 2285 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 2286 int __must_check i915_gpu_idle(struct drm_device *dev); 2287 int __must_check i915_gem_suspend(struct drm_device *dev); 2288 int __i915_add_request(struct intel_engine_cs *ring, 2289 struct drm_file *file, 2290 struct drm_i915_gem_object *batch_obj, 2291 u32 *seqno); 2292 #define i915_add_request(ring, seqno) \ 2293 __i915_add_request(ring, NULL, NULL, seqno) 2294 int __must_check i915_wait_seqno(struct intel_engine_cs *ring, 2295 uint32_t seqno); 2296 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres); 2297 int __must_check 2298 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 2299 bool write); 2300 int __must_check 2301 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 2302 int __must_check 2303 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 2304 u32 alignment, 2305 struct intel_engine_cs *pipelined); 2306 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); 2307 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 2308 int align); 2309 int i915_gem_open(struct drm_device *dev, struct drm_file *file); 2310 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 2311 2312 uint32_t 2313 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); 2314 uint32_t 2315 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2316 int tiling_mode, bool fenced); 2317 2318 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 2319 enum i915_cache_level cache_level); 2320 2321 #if 0 2322 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, 2323 struct dma_buf *dma_buf); 2324 2325 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, 2326 struct drm_gem_object *gem_obj, int flags); 2327 #endif 2328 2329 void i915_gem_restore_fences(struct drm_device *dev); 2330 2331 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, 2332 struct i915_address_space *vm); 2333 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); 2334 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 2335 struct i915_address_space *vm); 2336 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 2337 struct i915_address_space *vm); 2338 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 2339 struct i915_address_space *vm); 2340 struct i915_vma * 2341 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2342 struct i915_address_space *vm); 2343 2344 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); 2345 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { 2346 struct i915_vma *vma; 2347 list_for_each_entry(vma, &obj->vma_list, vma_link) 2348 if (vma->pin_count > 0) 2349 return true; 2350 return false; 2351 } 2352 2353 /* Some GGTT VM helpers */ 2354 #define obj_to_ggtt(obj) \ 2355 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) 2356 static inline bool i915_is_ggtt(struct i915_address_space *vm) 2357 { 2358 struct i915_address_space *ggtt = 2359 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; 2360 return vm == ggtt; 2361 } 2362 2363 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) 2364 { 2365 return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); 2366 } 2367 2368 static inline unsigned long 2369 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) 2370 { 2371 return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); 2372 } 2373 2374 static inline unsigned long 2375 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) 2376 { 2377 return i915_gem_obj_size(obj, obj_to_ggtt(obj)); 2378 } 2379 2380 static inline int __must_check 2381 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, 2382 uint32_t alignment, 2383 unsigned flags) 2384 { 2385 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL); 2386 } 2387 2388 static inline int 2389 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) 2390 { 2391 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); 2392 } 2393 2394 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); 2395 2396 /* i915_gem_context.c */ 2397 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base) 2398 int __must_check i915_gem_context_init(struct drm_device *dev); 2399 void i915_gem_context_fini(struct drm_device *dev); 2400 void i915_gem_context_reset(struct drm_device *dev); 2401 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); 2402 int i915_gem_context_enable(struct drm_i915_private *dev_priv); 2403 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2404 int i915_switch_context(struct intel_engine_cs *ring, 2405 struct intel_context *to); 2406 struct intel_context * 2407 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); 2408 void i915_gem_context_free(struct kref *ctx_ref); 2409 static inline void i915_gem_context_reference(struct intel_context *ctx) 2410 { 2411 kref_get(&ctx->ref); 2412 } 2413 2414 static inline void i915_gem_context_unreference(struct intel_context *ctx) 2415 { 2416 kref_put(&ctx->ref, i915_gem_context_free); 2417 } 2418 2419 static inline bool i915_gem_context_is_default(const struct intel_context *c) 2420 { 2421 return c->id == DEFAULT_CONTEXT_ID; 2422 } 2423 2424 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 2425 struct drm_file *file); 2426 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, 2427 struct drm_file *file); 2428 2429 /* i915_gem_render_state.c */ 2430 int i915_gem_render_state_init(struct intel_engine_cs *ring); 2431 /* i915_gem_evict.c */ 2432 int __must_check i915_gem_evict_something(struct drm_device *dev, 2433 struct i915_address_space *vm, 2434 int min_size, 2435 unsigned alignment, 2436 unsigned cache_level, 2437 unsigned long start, 2438 unsigned long end, 2439 unsigned flags); 2440 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); 2441 int i915_gem_evict_everything(struct drm_device *dev); 2442 2443 /* belongs in i915_gem_gtt.h */ 2444 static inline void i915_gem_chipset_flush(struct drm_device *dev) 2445 { 2446 if (INTEL_INFO(dev)->gen < 6) 2447 intel_gtt_chipset_flush(); 2448 } 2449 2450 /* i915_gem_stolen.c */ 2451 int i915_gem_init_stolen(struct drm_device *dev); 2452 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); 2453 void i915_gem_stolen_cleanup_compression(struct drm_device *dev); 2454 void i915_gem_cleanup_stolen(struct drm_device *dev); 2455 struct drm_i915_gem_object * 2456 i915_gem_object_create_stolen(struct drm_device *dev, u32 size); 2457 struct drm_i915_gem_object * 2458 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, 2459 u32 stolen_offset, 2460 u32 gtt_offset, 2461 u32 size); 2462 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); 2463 2464 /* i915_gem_tiling.c */ 2465 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) 2466 { 2467 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2468 2469 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && 2470 obj->tiling_mode != I915_TILING_NONE; 2471 } 2472 2473 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 2474 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 2475 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 2476 2477 /* i915_gem_debug.c */ 2478 #if WATCH_LISTS 2479 int i915_verify_lists(struct drm_device *dev); 2480 #else 2481 #define i915_verify_lists(dev) 0 2482 #endif 2483 2484 /* i915_debugfs.c */ 2485 int i915_debugfs_init(struct drm_minor *minor); 2486 void i915_debugfs_cleanup(struct drm_minor *minor); 2487 #ifdef CONFIG_DEBUG_FS 2488 void intel_display_crc_init(struct drm_device *dev); 2489 #else 2490 static inline void intel_display_crc_init(struct drm_device *dev) {} 2491 #endif 2492 2493 /* i915_gpu_error.c */ 2494 __printf(2, 3) 2495 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); 2496 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, 2497 const struct i915_error_state_file_priv *error); 2498 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, 2499 size_t count, loff_t pos); 2500 static inline void i915_error_state_buf_release( 2501 struct drm_i915_error_state_buf *eb) 2502 { 2503 kfree(eb->buf); 2504 } 2505 void i915_capture_error_state(struct drm_device *dev, bool wedge, 2506 const char *error_msg); 2507 void i915_error_state_get(struct drm_device *dev, 2508 struct i915_error_state_file_priv *error_priv); 2509 void i915_error_state_put(struct i915_error_state_file_priv *error_priv); 2510 void i915_destroy_error_state(struct drm_device *dev); 2511 2512 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); 2513 const char *i915_cache_level_str(int type); 2514 2515 /* i915_cmd_parser.c */ 2516 int i915_cmd_parser_get_version(void); 2517 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); 2518 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); 2519 bool i915_needs_cmd_parser(struct intel_engine_cs *ring); 2520 int i915_parse_cmds(struct intel_engine_cs *ring, 2521 struct drm_i915_gem_object *batch_obj, 2522 u32 batch_start_offset, 2523 bool is_master); 2524 2525 /* i915_suspend.c */ 2526 extern int i915_save_state(struct drm_device *dev); 2527 extern int i915_restore_state(struct drm_device *dev); 2528 2529 /* i915_ums.c */ 2530 void i915_save_display_reg(struct drm_device *dev); 2531 void i915_restore_display_reg(struct drm_device *dev); 2532 2533 /* i915_sysfs.c */ 2534 void i915_setup_sysfs(struct drm_device *dev_priv); 2535 void i915_teardown_sysfs(struct drm_device *dev_priv); 2536 2537 /* intel_i2c.c */ 2538 extern int intel_setup_gmbus(struct drm_device *dev); 2539 extern void intel_teardown_gmbus(struct drm_device *dev); 2540 static inline bool intel_gmbus_is_port_valid(unsigned port) 2541 { 2542 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); 2543 } 2544 2545 extern struct device *intel_gmbus_get_adapter( 2546 struct drm_i915_private *dev_priv, unsigned port); 2547 extern void intel_gmbus_set_speed(struct device *adapter, int speed); 2548 extern void intel_gmbus_force_bit(struct device *adapter, bool force_bit); 2549 static inline bool intel_gmbus_is_forced_bit(struct device *adapter) 2550 { 2551 struct intel_iic_softc *sc; 2552 sc = device_get_softc(device_get_parent(adapter)); 2553 2554 return sc->force_bit_dev; 2555 } 2556 extern void intel_i2c_reset(struct drm_device *dev); 2557 2558 /* intel_opregion.c */ 2559 struct intel_encoder; 2560 #ifdef CONFIG_ACPI 2561 extern int intel_opregion_setup(struct drm_device *dev); 2562 extern void intel_opregion_init(struct drm_device *dev); 2563 extern void intel_opregion_fini(struct drm_device *dev); 2564 extern void intel_opregion_asle_intr(struct drm_device *dev); 2565 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, 2566 bool enable); 2567 extern int intel_opregion_notify_adapter(struct drm_device *dev, 2568 pci_power_t state); 2569 #else 2570 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } 2571 static inline void intel_opregion_init(struct drm_device *dev) { return; } 2572 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 2573 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 2574 static inline int 2575 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) 2576 { 2577 return 0; 2578 } 2579 static inline int 2580 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) 2581 { 2582 return 0; 2583 } 2584 #endif 2585 2586 /* intel_acpi.c */ 2587 #ifdef CONFIG_ACPI 2588 extern void intel_register_dsm_handler(void); 2589 extern void intel_unregister_dsm_handler(void); 2590 #else 2591 static inline void intel_register_dsm_handler(void) { return; } 2592 static inline void intel_unregister_dsm_handler(void) { return; } 2593 #endif /* CONFIG_ACPI */ 2594 2595 /* modesetting */ 2596 extern void intel_modeset_init_hw(struct drm_device *dev); 2597 extern void intel_modeset_suspend_hw(struct drm_device *dev); 2598 extern void intel_modeset_init(struct drm_device *dev); 2599 extern void intel_modeset_gem_init(struct drm_device *dev); 2600 extern void intel_modeset_cleanup(struct drm_device *dev); 2601 extern void intel_connector_unregister(struct intel_connector *); 2602 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 2603 extern void intel_modeset_setup_hw_state(struct drm_device *dev, 2604 bool force_restore); 2605 extern void i915_redisable_vga(struct drm_device *dev); 2606 extern void i915_redisable_vga_power_on(struct drm_device *dev); 2607 extern void intel_disable_fbc(struct drm_device *dev); 2608 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 2609 extern void intel_init_pch_refclk(struct drm_device *dev); 2610 extern void gen6_set_rps(struct drm_device *dev, u8 val); 2611 extern void valleyview_set_rps(struct drm_device *dev, u8 val); 2612 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); 2613 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); 2614 extern void intel_detect_pch(struct drm_device *dev); 2615 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 2616 extern int intel_enable_rc6(const struct drm_device *dev); 2617 2618 extern bool i915_semaphore_is_enabled(struct drm_device *dev); 2619 int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2620 struct drm_file *file); 2621 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, 2622 struct drm_file *file); 2623 2624 struct intel_device_info *i915_get_device_id(int device); 2625 2626 /* overlay */ 2627 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2628 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, 2629 struct intel_overlay_error_state *error); 2630 2631 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); 2632 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, 2633 struct drm_device *dev, 2634 struct intel_display_error_state *error); 2635 2636 /* On SNB platform, before reading ring registers forcewake bit 2637 * must be set to prevent GT core from power down and stale values being 2638 * returned. 2639 */ 2640 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); 2641 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); 2642 void assert_force_wake_inactive(struct drm_i915_private *dev_priv); 2643 2644 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 2645 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 2646 2647 /* intel_sideband.c */ 2648 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); 2649 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); 2650 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); 2651 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); 2652 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2653 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); 2654 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2655 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 2656 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2657 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); 2658 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2659 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 2660 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2661 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg); 2662 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int reg, u32 val); 2663 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 2664 enum intel_sbi_destination destination); 2665 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2666 enum intel_sbi_destination destination); 2667 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); 2668 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2669 2670 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); 2671 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); 2672 2673 #define FORCEWAKE_RENDER (1 << 0) 2674 #define FORCEWAKE_MEDIA (1 << 1) 2675 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) 2676 2677 2678 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 2679 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 2680 2681 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) 2682 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) 2683 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) 2684 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) 2685 2686 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) 2687 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) 2688 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) 2689 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) 2690 2691 /* Be very careful with read/write 64-bit values. On 32-bit machines, they 2692 * will be implemented using 2 32-bit writes in an arbitrary order with 2693 * an arbitrary delay between them. This can cause the hardware to 2694 * act upon the intermediate value, possibly leading to corruption and 2695 * machine death. You have been warned. 2696 */ 2697 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) 2698 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) 2699 2700 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ 2701 u32 upper = I915_READ(upper_reg); \ 2702 u32 lower = I915_READ(lower_reg); \ 2703 u32 tmp = I915_READ(upper_reg); \ 2704 if (upper != tmp) { \ 2705 upper = tmp; \ 2706 lower = I915_READ(lower_reg); \ 2707 WARN_ON(I915_READ(upper_reg) != upper); \ 2708 } \ 2709 (u64)upper << 32 | lower; }) 2710 2711 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 2712 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 2713 2714 /* "Broadcast RGB" property */ 2715 #define INTEL_BROADCAST_RGB_AUTO 0 2716 #define INTEL_BROADCAST_RGB_FULL 1 2717 #define INTEL_BROADCAST_RGB_LIMITED 2 2718 2719 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) 2720 { 2721 if (HAS_PCH_SPLIT(dev)) 2722 return CPU_VGACNTRL; 2723 else if (IS_VALLEYVIEW(dev)) 2724 return VLV_VGACNTRL; 2725 else 2726 return VGACNTRL; 2727 } 2728 2729 static inline void __user *to_user_ptr(u64 address) 2730 { 2731 return (void __user *)(uintptr_t)address; 2732 } 2733 2734 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) 2735 { 2736 unsigned long j = msecs_to_jiffies(m); 2737 2738 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2739 } 2740 2741 static inline unsigned long 2742 timespec_to_jiffies_timeout(const struct timespec *value) 2743 { 2744 unsigned long j = timespec_to_jiffies(value); 2745 2746 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); 2747 } 2748 2749 /* 2750 * If you need to wait X milliseconds between events A and B, but event B 2751 * doesn't happen exactly after event A, you record the timestamp (jiffies) of 2752 * when event A happened, then just before event B you call this function and 2753 * pass the timestamp as the first argument, and X as the second argument. 2754 */ 2755 static inline void 2756 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) 2757 { 2758 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; 2759 2760 /* 2761 * Don't re-read the value of "jiffies" every time since it may change 2762 * behind our back and break the math. 2763 */ 2764 tmp_jiffies = jiffies; 2765 target_jiffies = timestamp_jiffies + 2766 msecs_to_jiffies_timeout(to_wait_ms); 2767 2768 if (time_after(target_jiffies, tmp_jiffies)) { 2769 remaining_jiffies = target_jiffies - tmp_jiffies; 2770 2771 #if 0 2772 while (remaining_jiffies) 2773 remaining_jiffies = 2774 schedule_timeout_uninterruptible(remaining_jiffies); 2775 #else 2776 msleep(jiffies_to_msecs(remaining_jiffies)); 2777 #endif 2778 } 2779 } 2780 2781 #endif 2782