1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 29 */ 30 31 #ifndef _I915_DRV_H_ 32 #define _I915_DRV_H_ 33 34 #include <sys/eventhandler.h> 35 36 #include <dev/agp/agp_i810.h> 37 #include "i915_reg.h" 38 #include "intel_bios.h" 39 #include "intel_ringbuffer.h" 40 #include <linux/workqueue.h> 41 42 /* General customization: 43 */ 44 45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46 47 #define DRIVER_NAME "i915" 48 #define DRIVER_DESC "Intel Graphics" 49 #define DRIVER_DATE "20080730" 50 51 MALLOC_DECLARE(DRM_I915_GEM); 52 53 enum i915_pipe { 54 PIPE_A = 0, 55 PIPE_B, 56 PIPE_C, 57 I915_MAX_PIPES 58 }; 59 #define pipe_name(p) ((p) + 'A') 60 #define I915_NUM_PIPE 2 61 62 enum transcoder { 63 TRANSCODER_A = 0, 64 TRANSCODER_B, 65 TRANSCODER_C, 66 TRANSCODER_EDP = 0xF, 67 }; 68 #define transcoder_name(t) ((t) + 'A') 69 70 enum plane { 71 PLANE_A = 0, 72 PLANE_B, 73 PLANE_C, 74 }; 75 #define plane_name(p) ((p) + 'A') 76 77 enum port { 78 PORT_A = 0, 79 PORT_B, 80 PORT_C, 81 PORT_D, 82 PORT_E, 83 I915_MAX_PORTS 84 }; 85 #define port_name(p) ((p) + 'A') 86 87 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 88 89 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 90 91 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 92 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 93 if ((intel_encoder)->base.crtc == (__crtc)) 94 95 struct intel_pch_pll { 96 int refcount; /* count of number of CRTCs sharing this PLL */ 97 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 98 bool on; /* is the PLL actually active? Disabled during modeset */ 99 int pll_reg; 100 int fp0_reg; 101 int fp1_reg; 102 }; 103 #define I915_NUM_PLLS 2 104 105 struct intel_ddi_plls { 106 int spll_refcount; 107 int wrpll1_refcount; 108 int wrpll2_refcount; 109 }; 110 111 /* Interface history: 112 * 113 * 1.1: Original. 114 * 1.2: Add Power Management 115 * 1.3: Add vblank support 116 * 1.4: Fix cmdbuffer path, add heap destroy 117 * 1.5: Add vblank pipe configuration 118 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 119 * - Support vertical blank on secondary display pipe 120 */ 121 #define DRIVER_MAJOR 1 122 #define DRIVER_MINOR 6 123 #define DRIVER_PATCHLEVEL 0 124 125 #define WATCH_COHERENCY 0 126 #define WATCH_LISTS 0 127 #define WATCH_GTT 0 128 129 #define I915_GEM_PHYS_CURSOR_0 1 130 #define I915_GEM_PHYS_CURSOR_1 2 131 #define I915_GEM_PHYS_OVERLAY_REGS 3 132 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 133 134 struct drm_i915_gem_phys_object { 135 int id; 136 drm_dma_handle_t *handle; 137 struct drm_i915_gem_object *cur_obj; 138 }; 139 140 struct opregion_header; 141 struct opregion_acpi; 142 struct opregion_swsci; 143 struct opregion_asle; 144 struct drm_i915_private; 145 146 struct intel_opregion { 147 struct opregion_header __iomem *header; 148 struct opregion_acpi __iomem *acpi; 149 struct opregion_swsci __iomem *swsci; 150 struct opregion_asle __iomem *asle; 151 void __iomem *vbt; 152 u32 __iomem *lid_state; 153 }; 154 #define OPREGION_SIZE (8*1024) 155 156 struct intel_overlay; 157 struct intel_overlay_error_state; 158 159 struct drm_i915_master_private { 160 drm_local_map_t *sarea; 161 struct _drm_i915_sarea *sarea_priv; 162 }; 163 #define I915_FENCE_REG_NONE -1 164 #define I915_MAX_NUM_FENCES 16 165 /* 16 fences + sign bit for FENCE_REG_NONE */ 166 #define I915_MAX_NUM_FENCE_BITS 5 167 168 struct drm_i915_fence_reg { 169 struct list_head lru_list; 170 struct drm_i915_gem_object *obj; 171 uint32_t setup_seqno; 172 int pin_count; 173 }; 174 175 struct sdvo_device_mapping { 176 u8 initialized; 177 u8 dvo_port; 178 u8 slave_addr; 179 u8 dvo_wiring; 180 u8 i2c_pin; 181 u8 ddc_pin; 182 }; 183 184 struct drm_i915_error_state { 185 u32 eir; 186 u32 pgtbl_er; 187 u32 pipestat[I915_MAX_PIPES]; 188 u32 tail[I915_NUM_RINGS]; 189 u32 head[I915_NUM_RINGS]; 190 u32 ipeir[I915_NUM_RINGS]; 191 u32 ipehr[I915_NUM_RINGS]; 192 u32 instdone[I915_NUM_RINGS]; 193 u32 acthd[I915_NUM_RINGS]; 194 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 195 /* our own tracking of ring head and tail */ 196 u32 cpu_ring_head[I915_NUM_RINGS]; 197 u32 cpu_ring_tail[I915_NUM_RINGS]; 198 u32 error; /* gen6+ */ 199 u32 instpm[I915_NUM_RINGS]; 200 u32 instps[I915_NUM_RINGS]; 201 u32 instdone1; 202 u32 seqno[I915_NUM_RINGS]; 203 u64 bbaddr; 204 u32 fault_reg[I915_NUM_RINGS]; 205 u32 done_reg; 206 u32 faddr[I915_NUM_RINGS]; 207 u64 fence[I915_MAX_NUM_FENCES]; 208 struct timeval time; 209 struct drm_i915_error_ring { 210 struct drm_i915_error_object { 211 int page_count; 212 u32 gtt_offset; 213 u32 *pages[0]; 214 } *ringbuffer, *batchbuffer; 215 struct drm_i915_error_request { 216 long jiffies; 217 u32 seqno; 218 u32 tail; 219 } *requests; 220 int num_requests; 221 } ring[I915_NUM_RINGS]; 222 struct drm_i915_error_buffer { 223 u32 size; 224 u32 name; 225 u32 seqno; 226 u32 gtt_offset; 227 u32 read_domains; 228 u32 write_domain; 229 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 230 s32 pinned:2; 231 u32 tiling:2; 232 u32 dirty:1; 233 u32 purgeable:1; 234 s32 ring:4; 235 u32 cache_level:2; 236 } *active_bo, *pinned_bo; 237 u32 active_bo_count, pinned_bo_count; 238 struct intel_overlay_error_state *overlay; 239 struct intel_display_error_state *display; 240 }; 241 242 struct drm_i915_display_funcs { 243 void (*dpms)(struct drm_crtc *crtc, int mode); 244 bool (*fbc_enabled)(struct drm_device *dev); 245 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 246 void (*disable_fbc)(struct drm_device *dev); 247 int (*get_display_clock_speed)(struct drm_device *dev); 248 int (*get_fifo_size)(struct drm_device *dev, int plane); 249 void (*update_wm)(struct drm_device *dev); 250 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 251 uint32_t sprite_width, int pixel_size); 252 int (*crtc_mode_set)(struct drm_crtc *crtc, 253 struct drm_display_mode *mode, 254 struct drm_display_mode *adjusted_mode, 255 int x, int y, 256 struct drm_framebuffer *old_fb); 257 void (*write_eld)(struct drm_connector *connector, 258 struct drm_crtc *crtc); 259 void (*fdi_link_train)(struct drm_crtc *crtc); 260 void (*init_clock_gating)(struct drm_device *dev); 261 void (*init_pch_clock_gating)(struct drm_device *dev); 262 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 263 struct drm_framebuffer *fb, 264 struct drm_i915_gem_object *obj); 265 void (*force_wake_get)(struct drm_i915_private *dev_priv); 266 void (*force_wake_put)(struct drm_i915_private *dev_priv); 267 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 268 int x, int y); 269 /* clock updates for mode set */ 270 /* cursor updates */ 271 /* render clock increase/decrease */ 272 /* display clock increase/decrease */ 273 /* pll clock increase/decrease */ 274 }; 275 276 struct drm_i915_gt_funcs { 277 void (*force_wake_get)(struct drm_i915_private *dev_priv); 278 void (*force_wake_put)(struct drm_i915_private *dev_priv); 279 }; 280 281 #define DEV_INFO_FLAGS \ 282 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ 283 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ 284 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ 285 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ 286 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ 287 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ 288 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ 289 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ 290 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ 291 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ 292 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ 293 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ 294 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ 295 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ 296 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ 297 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ 298 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ 299 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ 300 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ 301 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ 302 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ 303 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ 304 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ 305 DEV_INFO_FLAG(has_llc) 306 307 struct intel_device_info { 308 u8 gen; 309 u8 is_mobile:1; 310 u8 is_i85x:1; 311 u8 is_i915g:1; 312 u8 is_i945gm:1; 313 u8 is_g33:1; 314 u8 need_gfx_hws:1; 315 u8 is_g4x:1; 316 u8 is_pineview:1; 317 u8 is_broadwater:1; 318 u8 is_crestline:1; 319 u8 is_ivybridge:1; 320 u8 is_valleyview:1; 321 u8 has_force_wake:1; 322 u8 is_haswell:1; 323 u8 has_fbc:1; 324 u8 has_pipe_cxsr:1; 325 u8 has_hotplug:1; 326 u8 cursor_needs_physical:1; 327 u8 has_overlay:1; 328 u8 overlay_needs_physical:1; 329 u8 supports_tv:1; 330 u8 has_bsd_ring:1; 331 u8 has_blt_ring:1; 332 u8 has_llc:1; 333 }; 334 335 #define I915_PPGTT_PD_ENTRIES 512 336 #define I915_PPGTT_PT_ENTRIES 1024 337 struct i915_hw_ppgtt { 338 unsigned num_pd_entries; 339 vm_page_t *pt_pages; 340 uint32_t pd_offset; 341 vm_paddr_t *pt_dma_addr; 342 vm_paddr_t scratch_page_dma_addr; 343 }; 344 345 enum no_fbc_reason { 346 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 347 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 348 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 349 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 350 FBC_BAD_PLANE, /* fbc not supported on plane */ 351 FBC_NOT_TILED, /* buffer not tiled */ 352 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 353 FBC_MODULE_PARAM, 354 }; 355 356 /* defined intel_pm.c */ 357 extern struct lock mchdev_lock; 358 359 struct mem_block { 360 struct mem_block *next; 361 struct mem_block *prev; 362 int start; 363 int size; 364 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 365 }; 366 367 struct opregion_header; 368 struct opregion_acpi; 369 struct opregion_swsci; 370 struct opregion_asle; 371 372 #define I915_FENCE_REG_NONE -1 373 #define I915_MAX_NUM_FENCES 16 374 /* 16 fences + sign bit for FENCE_REG_NONE */ 375 #define I915_MAX_NUM_FENCE_BITS 5 376 377 enum intel_pch { 378 PCH_IBX, /* Ibexpeak PCH */ 379 PCH_CPT, /* Cougarpoint PCH */ 380 }; 381 382 #define QUIRK_PIPEA_FORCE (1<<0) 383 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 384 385 struct intel_fbdev; 386 struct intel_fbc_work; 387 388 struct intel_gen6_power_mgmt { 389 struct work_struct work; 390 u32 pm_iir; 391 /* lock - irqsave spinlock that protectects the work_struct and 392 * pm_iir. */ 393 struct spinlock lock; 394 395 /* The below variables an all the rps hw state are protected by 396 * dev->struct mutext. */ 397 u8 cur_delay; 398 u8 min_delay; 399 u8 max_delay; 400 401 struct delayed_work delayed_resume_work; 402 403 /* 404 * Protects RPS/RC6 register access and PCU communication. 405 * Must be taken after struct_mutex if nested. 406 */ 407 struct lock hw_lock; 408 }; 409 410 typedef struct drm_i915_private { 411 struct drm_device *dev; 412 413 device_t *gmbus_bridge; 414 device_t *bbbus_bridge; 415 device_t *gmbus; 416 device_t *bbbus; 417 /** gmbus_sx protects against concurrent usage of the single hw gmbus 418 * controller on different i2c buses. */ 419 struct lock gmbus_lock; 420 421 int has_gem; 422 int relative_constants_mode; 423 424 drm_local_map_t *sarea; 425 drm_local_map_t *mmio_map; 426 427 /** gt_fifo_count and the subsequent register write are synchronized 428 * with dev->struct_mutex. */ 429 unsigned gt_fifo_count; 430 /** forcewake_count is protected by gt_lock */ 431 unsigned forcewake_count; 432 /** gt_lock is also taken in irq contexts. */ 433 struct lock gt_lock; 434 435 drm_i915_sarea_t *sarea_priv; 436 struct intel_ring_buffer ring[I915_NUM_RINGS]; 437 uint32_t next_seqno; 438 439 drm_dma_handle_t *status_page_dmah; 440 struct resource *mch_res; 441 442 void *hw_status_page; 443 dma_addr_t dma_status_page; 444 uint32_t counter; 445 unsigned int status_gfx_addr; 446 drm_local_map_t hws_map; 447 struct drm_gem_object *hws_obj; 448 449 struct drm_i915_gem_object *pwrctx; 450 struct drm_i915_gem_object *renderctx; 451 452 unsigned int cpp; 453 int back_offset; 454 int front_offset; 455 int current_page; 456 int page_flipping; 457 458 atomic_t irq_received; 459 u32 trace_irq_seqno; 460 461 /** Cached value of IER to avoid reads in updating the bitfield */ 462 u32 pipestat[2]; 463 u32 irq_mask; 464 u32 gt_irq_mask; 465 u32 pch_irq_mask; 466 struct lock irq_lock; 467 468 u32 hotplug_supported_mask; 469 470 int tex_lru_log_granularity; 471 int allow_batchbuffer; 472 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 473 int vblank_pipe; 474 475 int num_pipe; 476 int num_pch_pll; 477 478 /* For hangcheck timer */ 479 #define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 480 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 481 struct timer_list hangcheck_timer; 482 int hangcheck_count; 483 uint32_t last_acthd; 484 uint32_t last_acthd_bsd; 485 uint32_t last_acthd_blt; 486 uint32_t last_instdone; 487 uint32_t last_instdone1; 488 489 struct intel_opregion opregion; 490 491 492 /* overlay */ 493 struct intel_overlay *overlay; 494 bool sprite_scaling_enabled; 495 496 /* LVDS info */ 497 int backlight_level; /* restore backlight to this value */ 498 bool backlight_enabled; 499 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 500 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 501 502 /* Feature bits from the VBIOS */ 503 unsigned int int_tv_support:1; 504 unsigned int lvds_dither:1; 505 unsigned int lvds_vbt:1; 506 unsigned int int_crt_support:1; 507 unsigned int lvds_use_ssc:1; 508 unsigned int display_clock_mode:1; 509 int lvds_ssc_freq; 510 struct { 511 int rate; 512 int lanes; 513 int preemphasis; 514 int vswing; 515 516 bool initialized; 517 bool support; 518 int bpp; 519 struct edp_power_seq pps; 520 } edp; 521 bool no_aux_handshake; 522 523 int crt_ddc_pin; 524 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 525 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 526 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 527 528 /* PCH chipset type */ 529 enum intel_pch pch_type; 530 531 /* Display functions */ 532 struct drm_i915_display_funcs display; 533 534 unsigned long quirks; 535 536 /* Register state */ 537 bool modeset_on_lid; 538 u8 saveLBB; 539 u32 saveDSPACNTR; 540 u32 saveDSPBCNTR; 541 u32 saveDSPARB; 542 u32 saveHWS; 543 u32 savePIPEACONF; 544 u32 savePIPEBCONF; 545 u32 savePIPEASRC; 546 u32 savePIPEBSRC; 547 u32 saveFPA0; 548 u32 saveFPA1; 549 u32 saveDPLL_A; 550 u32 saveDPLL_A_MD; 551 u32 saveHTOTAL_A; 552 u32 saveHBLANK_A; 553 u32 saveHSYNC_A; 554 u32 saveVTOTAL_A; 555 u32 saveVBLANK_A; 556 u32 saveVSYNC_A; 557 u32 saveBCLRPAT_A; 558 u32 saveTRANSACONF; 559 u32 saveTRANS_HTOTAL_A; 560 u32 saveTRANS_HBLANK_A; 561 u32 saveTRANS_HSYNC_A; 562 u32 saveTRANS_VTOTAL_A; 563 u32 saveTRANS_VBLANK_A; 564 u32 saveTRANS_VSYNC_A; 565 u32 savePIPEASTAT; 566 u32 saveDSPASTRIDE; 567 u32 saveDSPASIZE; 568 u32 saveDSPAPOS; 569 u32 saveDSPAADDR; 570 u32 saveDSPASURF; 571 u32 saveDSPATILEOFF; 572 u32 savePFIT_PGM_RATIOS; 573 u32 saveBLC_HIST_CTL; 574 u32 saveBLC_PWM_CTL; 575 u32 saveBLC_PWM_CTL2; 576 u32 saveBLC_CPU_PWM_CTL; 577 u32 saveBLC_CPU_PWM_CTL2; 578 u32 saveFPB0; 579 u32 saveFPB1; 580 u32 saveDPLL_B; 581 u32 saveDPLL_B_MD; 582 u32 saveHTOTAL_B; 583 u32 saveHBLANK_B; 584 u32 saveHSYNC_B; 585 u32 saveVTOTAL_B; 586 u32 saveVBLANK_B; 587 u32 saveVSYNC_B; 588 u32 saveBCLRPAT_B; 589 u32 saveTRANSBCONF; 590 u32 saveTRANS_HTOTAL_B; 591 u32 saveTRANS_HBLANK_B; 592 u32 saveTRANS_HSYNC_B; 593 u32 saveTRANS_VTOTAL_B; 594 u32 saveTRANS_VBLANK_B; 595 u32 saveTRANS_VSYNC_B; 596 u32 savePIPEBSTAT; 597 u32 saveDSPBSTRIDE; 598 u32 saveDSPBSIZE; 599 u32 saveDSPBPOS; 600 u32 saveDSPBADDR; 601 u32 saveDSPBSURF; 602 u32 saveDSPBTILEOFF; 603 u32 saveVGA0; 604 u32 saveVGA1; 605 u32 saveVGA_PD; 606 u32 saveVGACNTRL; 607 u32 saveADPA; 608 u32 saveLVDS; 609 u32 savePP_ON_DELAYS; 610 u32 savePP_OFF_DELAYS; 611 u32 saveDVOA; 612 u32 saveDVOB; 613 u32 saveDVOC; 614 u32 savePP_ON; 615 u32 savePP_OFF; 616 u32 savePP_CONTROL; 617 u32 savePP_DIVISOR; 618 u32 savePFIT_CONTROL; 619 u32 save_palette_a[256]; 620 u32 save_palette_b[256]; 621 u32 saveDPFC_CB_BASE; 622 u32 saveFBC_CFB_BASE; 623 u32 saveFBC_LL_BASE; 624 u32 saveFBC_CONTROL; 625 u32 saveFBC_CONTROL2; 626 u32 saveIER; 627 u32 saveIIR; 628 u32 saveIMR; 629 u32 saveDEIER; 630 u32 saveDEIMR; 631 u32 saveGTIER; 632 u32 saveGTIMR; 633 u32 saveFDI_RXA_IMR; 634 u32 saveFDI_RXB_IMR; 635 u32 saveCACHE_MODE_0; 636 u32 saveMI_ARB_STATE; 637 u32 saveSWF0[16]; 638 u32 saveSWF1[16]; 639 u32 saveSWF2[3]; 640 u8 saveMSR; 641 u8 saveSR[8]; 642 u8 saveGR[25]; 643 u8 saveAR_INDEX; 644 u8 saveAR[21]; 645 u8 saveDACMASK; 646 u8 saveCR[37]; 647 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 648 u32 saveCURACNTR; 649 u32 saveCURAPOS; 650 u32 saveCURABASE; 651 u32 saveCURBCNTR; 652 u32 saveCURBPOS; 653 u32 saveCURBBASE; 654 u32 saveCURSIZE; 655 u32 saveDP_B; 656 u32 saveDP_C; 657 u32 saveDP_D; 658 u32 savePIPEA_GMCH_DATA_M; 659 u32 savePIPEB_GMCH_DATA_M; 660 u32 savePIPEA_GMCH_DATA_N; 661 u32 savePIPEB_GMCH_DATA_N; 662 u32 savePIPEA_DP_LINK_M; 663 u32 savePIPEB_DP_LINK_M; 664 u32 savePIPEA_DP_LINK_N; 665 u32 savePIPEB_DP_LINK_N; 666 u32 saveFDI_RXA_CTL; 667 u32 saveFDI_TXA_CTL; 668 u32 saveFDI_RXB_CTL; 669 u32 saveFDI_TXB_CTL; 670 u32 savePFA_CTL_1; 671 u32 savePFB_CTL_1; 672 u32 savePFA_WIN_SZ; 673 u32 savePFB_WIN_SZ; 674 u32 savePFA_WIN_POS; 675 u32 savePFB_WIN_POS; 676 u32 savePCH_DREF_CONTROL; 677 u32 saveDISP_ARB_CTL; 678 u32 savePIPEA_DATA_M1; 679 u32 savePIPEA_DATA_N1; 680 u32 savePIPEA_LINK_M1; 681 u32 savePIPEA_LINK_N1; 682 u32 savePIPEB_DATA_M1; 683 u32 savePIPEB_DATA_N1; 684 u32 savePIPEB_LINK_M1; 685 u32 savePIPEB_LINK_N1; 686 u32 saveMCHBAR_RENDER_STANDBY; 687 u32 savePCH_PORT_HOTPLUG; 688 689 struct { 690 /** Bridge to intel-gtt-ko */ 691 const struct intel_gtt *gtt; 692 /** Memory allocator for GTT stolen memory */ 693 struct drm_mm stolen; 694 /** Memory allocator for GTT */ 695 struct drm_mm gtt_space; 696 /** List of all objects in gtt_space. Used to restore gtt 697 * mappings on resume */ 698 struct list_head gtt_list; 699 700 /** Usable portion of the GTT for GEM */ 701 unsigned long gtt_start; 702 unsigned long gtt_mappable_end; 703 unsigned long gtt_end; 704 705 /** PPGTT used for aliasing the PPGTT with the GTT */ 706 struct i915_hw_ppgtt *aliasing_ppgtt; 707 708 /** 709 * List of objects currently involved in rendering from the 710 * ringbuffer. 711 * 712 * Includes buffers having the contents of their GPU caches 713 * flushed, not necessarily primitives. last_rendering_seqno 714 * represents when the rendering involved will be completed. 715 * 716 * A reference is held on the buffer while on this list. 717 */ 718 struct list_head active_list; 719 720 /** 721 * List of objects which are not in the ringbuffer but which 722 * still have a write_domain which needs to be flushed before 723 * unbinding. 724 * 725 * A reference is held on the buffer while on this list. 726 */ 727 struct list_head flushing_list; 728 729 /** 730 * LRU list of objects which are not in the ringbuffer and 731 * are ready to unbind, but are still in the GTT. 732 * 733 * last_rendering_seqno is 0 while an object is in this list. 734 * 735 * A reference is not held on the buffer while on this list, 736 * as merely being GTT-bound shouldn't prevent its being 737 * freed, and we'll pull it off the list in the free path. 738 */ 739 struct list_head inactive_list; 740 741 /** 742 * LRU list of objects which are not in the ringbuffer but 743 * are still pinned in the GTT. 744 */ 745 struct list_head pinned_list; 746 747 /** LRU list of objects with fence regs on them. */ 748 struct list_head fence_list; 749 750 /** 751 * List of objects currently pending being freed. 752 * 753 * These objects are no longer in use, but due to a signal 754 * we were prevented from freeing them at the appointed time. 755 */ 756 struct list_head deferred_free_list; 757 758 /** 759 * We leave the user IRQ off as much as possible, 760 * but this means that requests will finish and never 761 * be retired once the system goes idle. Set a timer to 762 * fire periodically while the ring is running. When it 763 * fires, go retire requests. 764 */ 765 struct delayed_work retire_work; 766 767 /** 768 * Are we in a non-interruptible section of code like 769 * modesetting? 770 */ 771 bool interruptible; 772 773 uint32_t next_gem_seqno; 774 775 /** 776 * Waiting sequence number, if any 777 */ 778 uint32_t waiting_gem_seqno; 779 780 /** 781 * Last seq seen at irq time 782 */ 783 uint32_t irq_gem_seqno; 784 785 /** 786 * Flag if the X Server, and thus DRM, is not currently in 787 * control of the device. 788 * 789 * This is set between LeaveVT and EnterVT. It needs to be 790 * replaced with a semaphore. It also needs to be 791 * transitioned away from for kernel modesetting. 792 */ 793 int suspended; 794 795 /** 796 * Flag if the hardware appears to be wedged. 797 * 798 * This is set when attempts to idle the device timeout. 799 * It prevents command submission from occuring and makes 800 * every pending request fail 801 */ 802 atomic_t wedged; 803 804 /** Bit 6 swizzling required for X tiling */ 805 uint32_t bit_6_swizzle_x; 806 /** Bit 6 swizzling required for Y tiling */ 807 uint32_t bit_6_swizzle_y; 808 809 /* storage for physical objects */ 810 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 811 812 /* accounting, useful for userland debugging */ 813 size_t gtt_total; 814 size_t mappable_gtt_total; 815 size_t object_memory; 816 u32 object_count; 817 818 eventhandler_tag i915_lowmem; 819 } mm; 820 821 const struct intel_device_info *info; 822 823 struct sdvo_device_mapping sdvo_mappings[2]; 824 /* indicate whether the LVDS_BORDER should be enabled or not */ 825 unsigned int lvds_border_bits; 826 /* Panel fitter placement and size for Ironlake+ */ 827 u32 pch_pf_pos, pch_pf_size; 828 829 struct drm_crtc *plane_to_crtc_mapping[3]; 830 struct drm_crtc *pipe_to_crtc_mapping[3]; 831 /* wait_queue_head_t pending_flip_queue; XXXKIB */ 832 bool flip_pending_is_done; 833 834 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 835 struct intel_ddi_plls ddi_plls; 836 837 /* Reclocking support */ 838 bool render_reclock_avail; 839 bool lvds_downclock_avail; 840 /* indicates the reduced downclock for LVDS*/ 841 int lvds_downclock; 842 struct task idle_task; 843 struct callout idle_callout; 844 bool busy; 845 u16 orig_clock; 846 int child_dev_num; 847 struct child_device_config *child_dev; 848 struct drm_connector *int_lvds_connector; 849 struct drm_connector *int_edp_connector; 850 851 device_t bridge_dev; 852 bool mchbar_need_disable; 853 854 int mch_res_rid; 855 856 /* gen6+ rps state */ 857 struct intel_gen6_power_mgmt rps; 858 859 u8 fmax; 860 u8 fstart; 861 862 u64 last_count1; 863 unsigned long last_time1; 864 unsigned long chipset_power; 865 u64 last_count2; 866 struct timespec last_time2; 867 unsigned long gfx_power; 868 int c_m; 869 int r_t; 870 u8 corr; 871 struct lock *mchdev_lock; 872 873 enum no_fbc_reason no_fbc_reason; 874 875 unsigned long cfb_size; 876 unsigned int cfb_fb; 877 int cfb_plane; 878 int cfb_y; 879 struct intel_fbc_work *fbc_work; 880 881 unsigned int fsb_freq, mem_freq, is_ddr3; 882 883 struct lock error_lock; 884 /* Protected by dev->error_lock. */ 885 struct drm_i915_error_state *first_error; 886 struct work_struct error_work; 887 int error_completion; 888 struct lock error_completion_lock; 889 struct workqueue_struct *wq; 890 struct work_struct hotplug_work; 891 892 unsigned long last_gpu_reset; 893 894 struct intel_fbdev *fbdev; 895 896 struct drm_property *broadcast_rgb_property; 897 struct drm_property *force_audio_property; 898 } drm_i915_private_t; 899 900 /* Iterate over initialised rings */ 901 #define for_each_ring(ring__, dev_priv__, i__) \ 902 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 903 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 904 905 enum hdmi_force_audio { 906 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 907 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 908 HDMI_AUDIO_AUTO, /* trust EDID */ 909 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 910 }; 911 912 enum i915_cache_level { 913 I915_CACHE_NONE, 914 I915_CACHE_LLC, 915 I915_CACHE_LLC_MLC, /* gen6+ */ 916 }; 917 918 enum intel_chip_family { 919 CHIP_I8XX = 0x01, 920 CHIP_I9XX = 0x02, 921 CHIP_I915 = 0x04, 922 CHIP_I965 = 0x08, 923 }; 924 925 /** driver private structure attached to each drm_gem_object */ 926 struct drm_i915_gem_object { 927 struct drm_gem_object base; 928 929 /** Current space allocated to this object in the GTT, if any. */ 930 struct drm_mm_node *gtt_space; 931 struct list_head gtt_list; 932 /** This object's place on the active/flushing/inactive lists */ 933 struct list_head ring_list; 934 struct list_head mm_list; 935 /** This object's place on GPU write list */ 936 struct list_head gpu_write_list; 937 /** This object's place in the batchbuffer or on the eviction list */ 938 struct list_head exec_list; 939 940 /** 941 * This is set if the object is on the active or flushing lists 942 * (has pending rendering), and is not set if it's on inactive (ready 943 * to be unbound). 944 */ 945 unsigned int active:1; 946 947 /** 948 * This is set if the object has been written to since last bound 949 * to the GTT 950 */ 951 unsigned int dirty:1; 952 953 /** 954 * This is set if the object has been written to since the last 955 * GPU flush. 956 */ 957 unsigned int pending_gpu_write:1; 958 959 /** 960 * Fence register bits (if any) for this object. Will be set 961 * as needed when mapped into the GTT. 962 * Protected by dev->struct_mutex. 963 */ 964 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 965 966 /** 967 * Advice: are the backing pages purgeable? 968 */ 969 unsigned int madv:2; 970 971 /** 972 * Current tiling mode for the object. 973 */ 974 unsigned int tiling_mode:2; 975 unsigned int tiling_changed:1; 976 977 /** How many users have pinned this object in GTT space. The following 978 * users can each hold at most one reference: pwrite/pread, pin_ioctl 979 * (via user_pin_count), execbuffer (objects are not allowed multiple 980 * times for the same batchbuffer), and the framebuffer code. When 981 * switching/pageflipping, the framebuffer code has at most two buffers 982 * pinned per crtc. 983 * 984 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 985 * bits with absolutely no headroom. So use 4 bits. */ 986 unsigned int pin_count:4; 987 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 988 989 /** 990 * Is the object at the current location in the gtt mappable and 991 * fenceable? Used to avoid costly recalculations. 992 */ 993 unsigned int map_and_fenceable:1; 994 995 /** 996 * Whether the current gtt mapping needs to be mappable (and isn't just 997 * mappable by accident). Track pin and fault separate for a more 998 * accurate mappable working set. 999 */ 1000 unsigned int fault_mappable:1; 1001 unsigned int pin_mappable:1; 1002 1003 /* 1004 * Is the GPU currently using a fence to access this buffer, 1005 */ 1006 unsigned int pending_fenced_gpu_access:1; 1007 unsigned int fenced_gpu_access:1; 1008 1009 unsigned int cache_level:2; 1010 1011 unsigned int has_aliasing_ppgtt_mapping:1; 1012 1013 vm_page_t *pages; 1014 1015 /** 1016 * DMAR support 1017 */ 1018 struct sglist *sg_list; 1019 1020 /** 1021 * Used for performing relocations during execbuffer insertion. 1022 */ 1023 struct hlist_node exec_node; 1024 unsigned long exec_handle; 1025 struct drm_i915_gem_exec_object2 *exec_entry; 1026 1027 /** 1028 * Current offset of the object in GTT space. 1029 * 1030 * This is the same as gtt_space->start 1031 */ 1032 uint32_t gtt_offset; 1033 1034 /** Breadcrumb of last rendering to the buffer. */ 1035 uint32_t last_rendering_seqno; 1036 struct intel_ring_buffer *ring; 1037 1038 /** Breadcrumb of last fenced GPU access to the buffer. */ 1039 uint32_t last_fenced_seqno; 1040 struct intel_ring_buffer *last_fenced_ring; 1041 1042 /** Current tiling stride for the object, if it's tiled. */ 1043 uint32_t stride; 1044 1045 /** Record of address bit 17 of each page at last unbind. */ 1046 unsigned long *bit_17; 1047 1048 /** 1049 * If present, while GEM_DOMAIN_CPU is in the read domain this array 1050 * flags which individual pages are valid. 1051 */ 1052 uint8_t *page_cpu_valid; 1053 1054 /** User space pin count and filp owning the pin */ 1055 uint32_t user_pin_count; 1056 struct drm_file *pin_filp; 1057 1058 /** for phy allocated objects */ 1059 struct drm_i915_gem_phys_object *phys_obj; 1060 1061 /** 1062 * Number of crtcs where this object is currently the fb, but 1063 * will be page flipped away on the next vblank. When it 1064 * reaches 0, dev_priv->pending_flip_queue will be woken up. 1065 */ 1066 atomic_t pending_flip; 1067 }; 1068 1069 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1070 1071 /** 1072 * Request queue structure. 1073 * 1074 * The request queue allows us to note sequence numbers that have been emitted 1075 * and may be associated with active buffers to be retired. 1076 * 1077 * By keeping this list, we can avoid having to do questionable 1078 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1079 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1080 */ 1081 struct drm_i915_gem_request { 1082 /** On Which ring this request was generated */ 1083 struct intel_ring_buffer *ring; 1084 1085 /** GEM sequence number associated with this request. */ 1086 uint32_t seqno; 1087 1088 /** Postion in the ringbuffer of the end of the request */ 1089 u32 tail; 1090 1091 /** Time at which this request was emitted, in jiffies. */ 1092 unsigned long emitted_jiffies; 1093 1094 /** global list entry for this request */ 1095 struct list_head list; 1096 1097 struct drm_i915_file_private *file_priv; 1098 /** file_priv list entry for this request */ 1099 struct list_head client_list; 1100 }; 1101 1102 struct drm_i915_file_private { 1103 struct { 1104 struct spinlock lock; 1105 struct list_head request_list; 1106 } mm; 1107 }; 1108 1109 /** 1110 * RC6 is a special power stage which allows the GPU to enter an very 1111 * low-voltage mode when idle, using down to 0V while at this stage. This 1112 * stage is entered automatically when the GPU is idle when RC6 support is 1113 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1114 * 1115 * There are different RC6 modes available in Intel GPU, which differentiate 1116 * among each other with the latency required to enter and leave RC6 and 1117 * voltage consumed by the GPU in different states. 1118 * 1119 * The combination of the following flags define which states GPU is allowed 1120 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1121 * RC6pp is deepest RC6. Their support by hardware varies according to the 1122 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1123 * which brings the most power savings; deeper states save more power, but 1124 * require higher latency to switch to and wake up. 1125 */ 1126 #define INTEL_RC6_ENABLE (1<<0) 1127 #define INTEL_RC6p_ENABLE (1<<1) 1128 #define INTEL_RC6pp_ENABLE (1<<2) 1129 1130 extern int intel_iommu_enabled; 1131 extern struct drm_ioctl_desc i915_ioctls[]; 1132 extern struct drm_driver i915_driver_info; 1133 extern struct cdev_pager_ops i915_gem_pager_ops; 1134 extern int i915_panel_ignore_lid; 1135 extern unsigned int i915_powersave; 1136 extern int i915_semaphores; 1137 extern unsigned int i915_lvds_downclock; 1138 extern int i915_panel_use_ssc; 1139 extern int i915_vbt_sdvo_panel_type; 1140 extern int i915_enable_rc6; 1141 extern int i915_enable_fbc; 1142 extern int i915_enable_ppgtt; 1143 extern int i915_enable_hangcheck; 1144 1145 const struct intel_device_info *i915_get_device_id(int device); 1146 1147 int i915_reset(struct drm_device *dev, u8 flags); 1148 1149 /* i915_debug.c */ 1150 int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1151 struct sysctl_oid *top); 1152 void i915_sysctl_cleanup(struct drm_device *dev); 1153 1154 /* i915_dma.c */ 1155 extern void i915_kernel_lost_context(struct drm_device * dev); 1156 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1157 extern int i915_driver_unload(struct drm_device *); 1158 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1159 extern void i915_driver_lastclose(struct drm_device * dev); 1160 extern void i915_driver_preclose(struct drm_device *dev, 1161 struct drm_file *file_priv); 1162 extern void i915_driver_postclose(struct drm_device *dev, 1163 struct drm_file *file_priv); 1164 extern int i915_driver_device_is_agp(struct drm_device * dev); 1165 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1166 unsigned long arg); 1167 extern int i915_emit_box(struct drm_device *dev, 1168 struct drm_clip_rect __user *boxes, 1169 int i, int DR1, int DR4); 1170 int i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 1171 int DR1, int DR4); 1172 1173 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1174 unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1175 void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1176 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1177 1178 /* i915_irq.c */ 1179 extern int i915_irq_emit(struct drm_device *dev, void *data, 1180 struct drm_file *file_priv); 1181 extern int i915_irq_wait(struct drm_device *dev, void *data, 1182 struct drm_file *file_priv); 1183 1184 extern void intel_irq_init(struct drm_device *dev); 1185 1186 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1187 struct drm_file *file_priv); 1188 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1189 struct drm_file *file_priv); 1190 extern int i915_vblank_swap(struct drm_device *dev, void *data, 1191 struct drm_file *file_priv); 1192 void intel_enable_asle(struct drm_device *dev); 1193 void i915_hangcheck_elapsed(unsigned long data); 1194 void i915_handle_error(struct drm_device *dev, bool wedged); 1195 1196 void i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1197 void i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1198 1199 void i915_destroy_error_state(struct drm_device *dev); 1200 1201 /* i915_gem.c */ 1202 int i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size, 1203 uint32_t *handle_p); 1204 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1205 struct drm_file *file_priv); 1206 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1207 struct drm_file *file_priv); 1208 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1209 struct drm_file *file_priv); 1210 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1211 struct drm_file *file_priv); 1212 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1213 struct drm_file *file_priv); 1214 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1215 struct drm_file *file_priv); 1216 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1217 struct drm_file *file_priv); 1218 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1219 struct drm_file *file_priv); 1220 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1221 struct drm_file *file_priv); 1222 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1223 struct drm_file *file_priv); 1224 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1225 struct drm_file *file_priv); 1226 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1227 struct drm_file *file_priv); 1228 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1229 struct drm_file *file_priv); 1230 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1231 struct drm_file *file_priv); 1232 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1233 struct drm_file *file_priv); 1234 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1235 struct drm_file *file_priv); 1236 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1237 struct drm_file *file_priv); 1238 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1239 struct drm_file *file_priv); 1240 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1241 struct drm_file *file_priv); 1242 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1243 struct drm_file *file_priv); 1244 void i915_gem_load(struct drm_device *dev); 1245 void i915_gem_unload(struct drm_device *dev); 1246 int i915_gem_init_object(struct drm_gem_object *obj); 1247 void i915_gem_free_object(struct drm_gem_object *obj); 1248 int i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1249 bool map_and_fenceable); 1250 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1251 int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1252 void i915_gem_lastclose(struct drm_device *dev); 1253 uint32_t i915_get_gem_seqno(struct drm_device *dev); 1254 1255 static inline void 1256 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1257 { 1258 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1259 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1260 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1261 } 1262 } 1263 1264 static inline void 1265 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1266 { 1267 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1268 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1269 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1270 } 1271 } 1272 1273 void i915_gem_retire_requests(struct drm_device *dev); 1274 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1275 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1276 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1277 size_t size); 1278 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 1279 unsigned long mappable_end, unsigned long end); 1280 uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1281 uint32_t size, int tiling_mode); 1282 int i915_mutex_lock_interruptible(struct drm_device *dev); 1283 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1284 bool write); 1285 int i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1286 u32 alignment, struct intel_ring_buffer *pipelined); 1287 int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1288 int i915_gem_flush_ring(struct intel_ring_buffer *ring, 1289 uint32_t invalidate_domains, uint32_t flush_domains); 1290 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1291 int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1292 int i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1293 int i915_gem_idle(struct drm_device *dev); 1294 int i915_gem_init_hw(struct drm_device *dev); 1295 void i915_gem_init_swizzling(struct drm_device *dev); 1296 void i915_gem_init_ppgtt(struct drm_device *dev); 1297 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1298 int i915_gpu_idle(struct drm_device *dev, bool do_retire); 1299 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1300 struct intel_ring_buffer *ring, uint32_t seqno); 1301 int i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file, 1302 struct drm_i915_gem_request *request); 1303 int i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1304 struct intel_ring_buffer *pipelined); 1305 void i915_gem_reset(struct drm_device *dev); 1306 int i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, 1307 bool do_retire); 1308 int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1309 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1310 uint64_t *phys); 1311 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1312 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1313 enum i915_cache_level cache_level); 1314 1315 void i915_gem_free_all_phys_object(struct drm_device *dev); 1316 void i915_gem_detach_phys_object(struct drm_device *dev, 1317 struct drm_i915_gem_object *obj); 1318 int i915_gem_attach_phys_object(struct drm_device *dev, 1319 struct drm_i915_gem_object *obj, int id, int align); 1320 1321 int i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1322 struct drm_mode_create_dumb *args); 1323 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1324 uint32_t handle, uint64_t *offset); 1325 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1326 uint32_t handle); 1327 1328 /* i915_gem_tiling.c */ 1329 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1330 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1331 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1332 1333 /* i915_gem_evict.c */ 1334 int i915_gem_evict_something(struct drm_device *dev, int min_size, 1335 unsigned alignment, bool mappable); 1336 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1337 int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only); 1338 1339 /* i915_suspend.c */ 1340 extern int i915_save_state(struct drm_device *dev); 1341 extern int i915_restore_state(struct drm_device *dev); 1342 1343 /* intel_iic.c */ 1344 extern int intel_setup_gmbus(struct drm_device *dev); 1345 extern void intel_teardown_gmbus(struct drm_device *dev); 1346 extern void intel_gmbus_set_speed(device_t idev, int speed); 1347 extern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1348 extern void intel_iic_reset(struct drm_device *dev); 1349 1350 /* intel_opregion.c */ 1351 int intel_opregion_setup(struct drm_device *dev); 1352 extern int intel_opregion_init(struct drm_device *dev); 1353 extern void intel_opregion_fini(struct drm_device *dev); 1354 extern void opregion_asle_intr(struct drm_device *dev); 1355 extern void intel_opregion_gse_intr(struct drm_device *dev); 1356 extern void opregion_enable_asle(struct drm_device *dev); 1357 1358 /* i915_gem_gtt.c */ 1359 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1360 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1361 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1362 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1363 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1364 struct drm_i915_gem_object *obj); 1365 1366 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1367 int i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); 1368 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1369 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, 1370 enum i915_cache_level cache_level); 1371 1372 /* modesetting */ 1373 extern void intel_modeset_init(struct drm_device *dev); 1374 extern void intel_modeset_gem_init(struct drm_device *dev); 1375 extern void intel_modeset_cleanup(struct drm_device *dev); 1376 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1377 extern void intel_disable_fbc(struct drm_device *dev); 1378 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1379 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1380 extern void ironlake_enable_rc6(struct drm_device *dev); 1381 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1382 extern void intel_detect_pch(struct drm_device *dev); 1383 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1384 1385 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1386 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv); 1387 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1388 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv); 1389 1390 extern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1391 struct drm_device *dev); 1392 extern void intel_overlay_print_error_state(struct sbuf *m, 1393 struct intel_overlay_error_state *error); 1394 extern struct intel_display_error_state *intel_display_capture_error_state( 1395 struct drm_device *dev); 1396 extern void intel_display_print_error_state(struct sbuf *m, 1397 struct drm_device *dev, struct intel_display_error_state *error); 1398 1399 static inline void 1400 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1401 { 1402 return; 1403 } 1404 1405 /* On SNB platform, before reading ring registers forcewake bit 1406 * must be set to prevent GT core from power down and stale values being 1407 * returned. 1408 */ 1409 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1410 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1411 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1412 1413 /* We give fast paths for the really cool registers */ 1414 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ 1415 (((dev_priv)->info->gen >= 6) && \ 1416 ((reg) < 0x40000) && \ 1417 ((reg) != FORCEWAKE)) 1418 1419 #define __i915_read(x, y) \ 1420 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1421 1422 __i915_read(8, 8) 1423 __i915_read(16, 16) 1424 __i915_read(32, 32) 1425 __i915_read(64, 64) 1426 #undef __i915_read 1427 1428 #define __i915_write(x, y) \ 1429 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1430 1431 __i915_write(8, 8) 1432 __i915_write(16, 16) 1433 __i915_write(32, 32) 1434 __i915_write(64, 64) 1435 #undef __i915_write 1436 1437 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1438 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1439 1440 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1441 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1442 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1443 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1444 1445 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1446 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1447 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1448 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1449 1450 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1451 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1452 1453 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1454 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1455 1456 #define I915_VERBOSE 0 1457 1458 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) 1459 1460 #define BEGIN_LP_RING(n) \ 1461 intel_ring_begin(LP_RING(dev_priv), (n)) 1462 1463 #define OUT_RING(x) \ 1464 intel_ring_emit(LP_RING(dev_priv), x) 1465 1466 #define ADVANCE_LP_RING() \ 1467 intel_ring_advance(LP_RING(dev_priv)) 1468 1469 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1470 if (LP_RING(dev->dev_private)->obj == NULL) \ 1471 LOCK_TEST_WITH_RETURN(dev, file); \ 1472 } while (0) 1473 1474 /** 1475 * Reads a dword out of the status page, which is written to from the command 1476 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 1477 * MI_STORE_DATA_IMM. 1478 * 1479 * The following dwords have a reserved meaning: 1480 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 1481 * 0x04: ring 0 head pointer 1482 * 0x05: ring 1 head pointer (915-class) 1483 * 0x06: ring 2 head pointer (915-class) 1484 * 0x10-0x1b: Context status DWords (GM45) 1485 * 0x1f: Last written status offset. (GM45) 1486 * 1487 * The area from dword 0x20 to 0x3ff is available for driver usage. 1488 */ 1489 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 1490 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1491 #define I915_GEM_HWS_INDEX 0x20 1492 #define I915_BREADCRUMB_INDEX 0x21 1493 1494 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1495 1496 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1497 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1498 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1499 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1500 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1501 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1502 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1503 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1504 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1505 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1506 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1507 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1508 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1509 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1510 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1511 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1512 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1513 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1514 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1515 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1516 (dev)->pci_device == 0x0152 || \ 1517 (dev)->pci_device == 0x015a) 1518 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1519 (dev)->pci_device == 0x0106 || \ 1520 (dev)->pci_device == 0x010A) 1521 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1522 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1523 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1524 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1525 ((dev)->pci_device & 0xFF00) == 0x0A00) 1526 1527 /* XXXKIB LEGACY */ 1528 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ 1529 (dev)->pci_device == 0x2982 || \ 1530 (dev)->pci_device == 0x2992 || \ 1531 (dev)->pci_device == 0x29A2 || \ 1532 (dev)->pci_device == 0x2A02 || \ 1533 (dev)->pci_device == 0x2A12 || \ 1534 (dev)->pci_device == 0x2A42 || \ 1535 (dev)->pci_device == 0x2E02 || \ 1536 (dev)->pci_device == 0x2E12 || \ 1537 (dev)->pci_device == 0x2E22 || \ 1538 (dev)->pci_device == 0x2E32) 1539 1540 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) 1541 1542 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001) 1543 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011) 1544 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev)) 1545 1546 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1547 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1548 /* XXXKIB LEGACY END */ 1549 1550 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1551 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1552 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1553 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1554 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1555 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1556 1557 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1558 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1559 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1560 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1561 1562 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1563 1564 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1565 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1566 1567 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1568 * rows, which changed the alignment requirements and fence programming. 1569 */ 1570 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1571 IS_I915GM(dev))) 1572 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1573 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1574 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1575 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1576 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1577 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1578 /* dsparb controlled by hw only */ 1579 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1580 1581 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1582 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1583 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1584 1585 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1586 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1587 1588 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1589 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1590 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1591 1592 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1593 1594 #define PRIMARY_RINGBUFFER_SIZE (128*1024) 1595 1596 static inline bool 1597 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1598 { 1599 1600 return ((int32_t)(seq1 - seq2) >= 0); 1601 } 1602 1603 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1604 1605 #endif 1606