1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 */ 27 28 #include <drm/drmP.h> 29 #include <drm/drm_vma_manager.h> 30 #include <drm/i915_drm.h> 31 #include "i915_drv.h" 32 #include "i915_vgpu.h" 33 #include "i915_trace.h" 34 #include "intel_drv.h" 35 #include <linux/shmem_fs.h> 36 #include <linux/slab.h> 37 #include <linux/swap.h> 38 #include <linux/pci.h> 39 40 #define RQ_BUG_ON(expr) 41 42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); 43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); 44 static void 45 i915_gem_object_retire__write(struct drm_i915_gem_object *obj); 46 static void 47 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); 48 49 static bool cpu_cache_is_coherent(struct drm_device *dev, 50 enum i915_cache_level level) 51 { 52 return HAS_LLC(dev) || level != I915_CACHE_NONE; 53 } 54 55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) 56 { 57 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) 58 return true; 59 60 return obj->pin_display; 61 } 62 63 /* some bookkeeping */ 64 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, 65 size_t size) 66 { 67 spin_lock(&dev_priv->mm.object_stat_lock); 68 dev_priv->mm.object_count++; 69 dev_priv->mm.object_memory += size; 70 spin_unlock(&dev_priv->mm.object_stat_lock); 71 } 72 73 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, 74 size_t size) 75 { 76 spin_lock(&dev_priv->mm.object_stat_lock); 77 dev_priv->mm.object_count--; 78 dev_priv->mm.object_memory -= size; 79 spin_unlock(&dev_priv->mm.object_stat_lock); 80 } 81 82 static int 83 i915_gem_wait_for_error(struct i915_gpu_error *error) 84 { 85 int ret; 86 87 #define EXIT_COND (!i915_reset_in_progress(error) || \ 88 i915_terminally_wedged(error)) 89 if (EXIT_COND) 90 return 0; 91 92 /* 93 * Only wait 10 seconds for the gpu reset to complete to avoid hanging 94 * userspace. If it takes that long something really bad is going on and 95 * we should simply try to bail out and fail as gracefully as possible. 96 */ 97 ret = wait_event_interruptible_timeout(error->reset_queue, 98 EXIT_COND, 99 10*HZ); 100 if (ret == 0) { 101 DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); 102 return -EIO; 103 } else if (ret < 0) { 104 return ret; 105 } 106 #undef EXIT_COND 107 108 return 0; 109 } 110 111 int i915_mutex_lock_interruptible(struct drm_device *dev) 112 { 113 struct drm_i915_private *dev_priv = dev->dev_private; 114 int ret; 115 116 ret = i915_gem_wait_for_error(&dev_priv->gpu_error); 117 if (ret) 118 return ret; 119 120 ret = mutex_lock_interruptible(&dev->struct_mutex); 121 if (ret) 122 return ret; 123 124 WARN_ON(i915_verify_lists(dev)); 125 return 0; 126 } 127 128 int 129 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 130 struct drm_file *file) 131 { 132 struct drm_i915_private *dev_priv = dev->dev_private; 133 struct drm_i915_gem_get_aperture *args = data; 134 struct i915_gtt *ggtt = &dev_priv->gtt; 135 struct i915_vma *vma; 136 size_t pinned; 137 138 pinned = 0; 139 mutex_lock(&dev->struct_mutex); 140 list_for_each_entry(vma, &ggtt->base.active_list, mm_list) 141 if (vma->pin_count) 142 pinned += vma->node.size; 143 list_for_each_entry(vma, &ggtt->base.inactive_list, mm_list) 144 if (vma->pin_count) 145 pinned += vma->node.size; 146 mutex_unlock(&dev->struct_mutex); 147 148 args->aper_size = dev_priv->gtt.base.total; 149 args->aper_available_size = args->aper_size - pinned; 150 151 return 0; 152 } 153 154 #if 0 155 static int 156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) 157 { 158 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; 159 char *vaddr = obj->phys_handle->vaddr; 160 struct sg_table *st; 161 struct scatterlist *sg; 162 int i; 163 164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) 165 return -EINVAL; 166 167 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { 168 struct page *page; 169 char *src; 170 171 page = shmem_read_mapping_page(mapping, i); 172 if (IS_ERR(page)) 173 return PTR_ERR(page); 174 175 src = kmap_atomic(page); 176 memcpy(vaddr, src, PAGE_SIZE); 177 drm_clflush_virt_range(vaddr, PAGE_SIZE); 178 kunmap_atomic(src); 179 180 page_cache_release(page); 181 vaddr += PAGE_SIZE; 182 } 183 184 i915_gem_chipset_flush(obj->base.dev); 185 186 st = kmalloc(sizeof(*st), GFP_KERNEL); 187 if (st == NULL) 188 return -ENOMEM; 189 190 if (sg_alloc_table(st, 1, GFP_KERNEL)) { 191 kfree(st); 192 return -ENOMEM; 193 } 194 195 sg = st->sgl; 196 sg->offset = 0; 197 sg->length = obj->base.size; 198 199 sg_dma_address(sg) = obj->phys_handle->busaddr; 200 sg_dma_len(sg) = obj->base.size; 201 202 obj->pages = st; 203 return 0; 204 } 205 206 static void 207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) 208 { 209 int ret; 210 211 BUG_ON(obj->madv == __I915_MADV_PURGED); 212 213 ret = i915_gem_object_set_to_cpu_domain(obj, true); 214 if (ret) { 215 /* In the event of a disaster, abandon all caches and 216 * hope for the best. 217 */ 218 WARN_ON(ret != -EIO); 219 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; 220 } 221 222 if (obj->madv == I915_MADV_DONTNEED) 223 obj->dirty = 0; 224 225 if (obj->dirty) { 226 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; 227 char *vaddr = obj->phys_handle->vaddr; 228 int i; 229 230 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { 231 struct page *page; 232 char *dst; 233 234 page = shmem_read_mapping_page(mapping, i); 235 if (IS_ERR(page)) 236 continue; 237 238 dst = kmap_atomic(page); 239 drm_clflush_virt_range(vaddr, PAGE_SIZE); 240 memcpy(dst, vaddr, PAGE_SIZE); 241 kunmap_atomic(dst); 242 243 set_page_dirty(page); 244 if (obj->madv == I915_MADV_WILLNEED) 245 mark_page_accessed(page); 246 page_cache_release(page); 247 vaddr += PAGE_SIZE; 248 } 249 obj->dirty = 0; 250 } 251 252 sg_free_table(obj->pages); 253 kfree(obj->pages); 254 } 255 256 static void 257 i915_gem_object_release_phys(struct drm_i915_gem_object *obj) 258 { 259 drm_pci_free(obj->base.dev, obj->phys_handle); 260 } 261 262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { 263 .get_pages = i915_gem_object_get_pages_phys, 264 .put_pages = i915_gem_object_put_pages_phys, 265 .release = i915_gem_object_release_phys, 266 }; 267 #endif 268 269 static int 270 drop_pages(struct drm_i915_gem_object *obj) 271 { 272 struct i915_vma *vma, *next; 273 int ret; 274 275 drm_gem_object_reference(&obj->base); 276 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) 277 if (i915_vma_unbind(vma)) 278 break; 279 280 ret = i915_gem_object_put_pages(obj); 281 drm_gem_object_unreference(&obj->base); 282 283 return ret; 284 } 285 286 int 287 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, 288 int align) 289 { 290 drm_dma_handle_t *phys; 291 int ret; 292 293 if (obj->phys_handle) { 294 if ((unsigned long)obj->phys_handle->vaddr & (align -1)) 295 return -EBUSY; 296 297 return 0; 298 } 299 300 if (obj->madv != I915_MADV_WILLNEED) 301 return -EFAULT; 302 303 #if 0 304 if (obj->base.filp == NULL) 305 return -EINVAL; 306 #endif 307 308 ret = drop_pages(obj); 309 if (ret) 310 return ret; 311 312 /* create a new object */ 313 phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); 314 if (!phys) 315 return -ENOMEM; 316 317 obj->phys_handle = phys; 318 #if 0 319 obj->ops = &i915_gem_phys_ops; 320 #endif 321 322 return i915_gem_object_get_pages(obj); 323 } 324 325 static int 326 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, 327 struct drm_i915_gem_pwrite *args, 328 struct drm_file *file_priv) 329 { 330 struct drm_device *dev = obj->base.dev; 331 void *vaddr = (char *)obj->phys_handle->vaddr + args->offset; 332 char __user *user_data = to_user_ptr(args->data_ptr); 333 int ret = 0; 334 335 /* We manually control the domain here and pretend that it 336 * remains coherent i.e. in the GTT domain, like shmem_pwrite. 337 */ 338 ret = i915_gem_object_wait_rendering(obj, false); 339 if (ret) 340 return ret; 341 342 intel_fb_obj_invalidate(obj, ORIGIN_CPU); 343 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { 344 unsigned long unwritten; 345 346 /* The physical object once assigned is fixed for the lifetime 347 * of the obj, so we can safely drop the lock and continue 348 * to access vaddr. 349 */ 350 mutex_unlock(&dev->struct_mutex); 351 unwritten = copy_from_user(vaddr, user_data, args->size); 352 mutex_lock(&dev->struct_mutex); 353 if (unwritten) { 354 ret = -EFAULT; 355 goto out; 356 } 357 } 358 359 drm_clflush_virt_range(vaddr, args->size); 360 i915_gem_chipset_flush(dev); 361 362 out: 363 intel_fb_obj_flush(obj, false, ORIGIN_CPU); 364 return ret; 365 } 366 367 void *i915_gem_object_alloc(struct drm_device *dev) 368 { 369 return kmalloc(sizeof(struct drm_i915_gem_object), 370 M_DRM, M_WAITOK | M_ZERO); 371 } 372 373 void i915_gem_object_free(struct drm_i915_gem_object *obj) 374 { 375 kfree(obj); 376 } 377 378 static int 379 i915_gem_create(struct drm_file *file, 380 struct drm_device *dev, 381 uint64_t size, 382 uint32_t *handle_p) 383 { 384 struct drm_i915_gem_object *obj; 385 int ret; 386 u32 handle; 387 388 size = roundup(size, PAGE_SIZE); 389 if (size == 0) 390 return -EINVAL; 391 392 /* Allocate the new object */ 393 obj = i915_gem_alloc_object(dev, size); 394 if (obj == NULL) 395 return -ENOMEM; 396 397 ret = drm_gem_handle_create(file, &obj->base, &handle); 398 /* drop reference from allocate - handle holds it now */ 399 drm_gem_object_unreference_unlocked(&obj->base); 400 if (ret) 401 return ret; 402 403 *handle_p = handle; 404 return 0; 405 } 406 407 int 408 i915_gem_dumb_create(struct drm_file *file, 409 struct drm_device *dev, 410 struct drm_mode_create_dumb *args) 411 { 412 /* have to work out size/pitch and return them */ 413 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); 414 args->size = args->pitch * args->height; 415 return i915_gem_create(file, dev, 416 args->size, &args->handle); 417 } 418 419 /** 420 * Creates a new mm object and returns a handle to it. 421 */ 422 int 423 i915_gem_create_ioctl(struct drm_device *dev, void *data, 424 struct drm_file *file) 425 { 426 struct drm_i915_gem_create *args = data; 427 428 return i915_gem_create(file, dev, 429 args->size, &args->handle); 430 } 431 432 static inline int 433 __copy_to_user_swizzled(char __user *cpu_vaddr, 434 const char *gpu_vaddr, int gpu_offset, 435 int length) 436 { 437 int ret, cpu_offset = 0; 438 439 while (length > 0) { 440 int cacheline_end = ALIGN(gpu_offset + 1, 64); 441 int this_length = min(cacheline_end - gpu_offset, length); 442 int swizzled_gpu_offset = gpu_offset ^ 64; 443 444 ret = __copy_to_user(cpu_vaddr + cpu_offset, 445 gpu_vaddr + swizzled_gpu_offset, 446 this_length); 447 if (ret) 448 return ret + length; 449 450 cpu_offset += this_length; 451 gpu_offset += this_length; 452 length -= this_length; 453 } 454 455 return 0; 456 } 457 458 static inline int 459 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, 460 const char __user *cpu_vaddr, 461 int length) 462 { 463 int ret, cpu_offset = 0; 464 465 while (length > 0) { 466 int cacheline_end = ALIGN(gpu_offset + 1, 64); 467 int this_length = min(cacheline_end - gpu_offset, length); 468 int swizzled_gpu_offset = gpu_offset ^ 64; 469 470 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, 471 cpu_vaddr + cpu_offset, 472 this_length); 473 if (ret) 474 return ret + length; 475 476 cpu_offset += this_length; 477 gpu_offset += this_length; 478 length -= this_length; 479 } 480 481 return 0; 482 } 483 484 /* 485 * Pins the specified object's pages and synchronizes the object with 486 * GPU accesses. Sets needs_clflush to non-zero if the caller should 487 * flush the object from the CPU cache. 488 */ 489 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, 490 int *needs_clflush) 491 { 492 int ret; 493 494 *needs_clflush = 0; 495 496 #if 0 497 if (!obj->base.filp) 498 return -EINVAL; 499 #endif 500 501 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { 502 /* If we're not in the cpu read domain, set ourself into the gtt 503 * read domain and manually flush cachelines (if required). This 504 * optimizes for the case when the gpu will dirty the data 505 * anyway again before the next pread happens. */ 506 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, 507 obj->cache_level); 508 ret = i915_gem_object_wait_rendering(obj, true); 509 if (ret) 510 return ret; 511 } 512 513 ret = i915_gem_object_get_pages(obj); 514 if (ret) 515 return ret; 516 517 i915_gem_object_pin_pages(obj); 518 519 return ret; 520 } 521 522 /* Per-page copy function for the shmem pread fastpath. 523 * Flushes invalid cachelines before reading the target if 524 * needs_clflush is set. */ 525 static int 526 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length, 527 char __user *user_data, 528 bool page_do_bit17_swizzling, bool needs_clflush) 529 { 530 char *vaddr; 531 int ret; 532 533 if (unlikely(page_do_bit17_swizzling)) 534 return -EINVAL; 535 536 vaddr = kmap_atomic(page); 537 if (needs_clflush) 538 drm_clflush_virt_range(vaddr + shmem_page_offset, 539 page_length); 540 ret = __copy_to_user_inatomic(user_data, 541 vaddr + shmem_page_offset, 542 page_length); 543 kunmap_atomic(vaddr); 544 545 return ret ? -EFAULT : 0; 546 } 547 548 static void 549 shmem_clflush_swizzled_range(char *addr, unsigned long length, 550 bool swizzled) 551 { 552 if (unlikely(swizzled)) { 553 unsigned long start = (unsigned long) addr; 554 unsigned long end = (unsigned long) addr + length; 555 556 /* For swizzling simply ensure that we always flush both 557 * channels. Lame, but simple and it works. Swizzled 558 * pwrite/pread is far from a hotpath - current userspace 559 * doesn't use it at all. */ 560 start = round_down(start, 128); 561 end = round_up(end, 128); 562 563 drm_clflush_virt_range((void *)start, end - start); 564 } else { 565 drm_clflush_virt_range(addr, length); 566 } 567 568 } 569 570 /* Only difference to the fast-path function is that this can handle bit17 571 * and uses non-atomic copy and kmap functions. */ 572 static int 573 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length, 574 char __user *user_data, 575 bool page_do_bit17_swizzling, bool needs_clflush) 576 { 577 char *vaddr; 578 int ret; 579 580 vaddr = kmap(page); 581 if (needs_clflush) 582 shmem_clflush_swizzled_range(vaddr + shmem_page_offset, 583 page_length, 584 page_do_bit17_swizzling); 585 586 if (page_do_bit17_swizzling) 587 ret = __copy_to_user_swizzled(user_data, 588 vaddr, shmem_page_offset, 589 page_length); 590 else 591 ret = __copy_to_user(user_data, 592 vaddr + shmem_page_offset, 593 page_length); 594 kunmap(page); 595 596 return ret ? - EFAULT : 0; 597 } 598 599 static int 600 i915_gem_shmem_pread(struct drm_device *dev, 601 struct drm_i915_gem_object *obj, 602 struct drm_i915_gem_pread *args, 603 struct drm_file *file) 604 { 605 char __user *user_data; 606 ssize_t remain; 607 loff_t offset; 608 int shmem_page_offset, page_length, ret = 0; 609 int obj_do_bit17_swizzling, page_do_bit17_swizzling; 610 int prefaulted = 0; 611 int needs_clflush = 0; 612 struct sg_page_iter sg_iter; 613 614 user_data = to_user_ptr(args->data_ptr); 615 remain = args->size; 616 617 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); 618 619 ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); 620 if (ret) 621 return ret; 622 623 offset = args->offset; 624 625 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 626 offset >> PAGE_SHIFT) { 627 struct vm_page *page = sg_page_iter_page(&sg_iter); 628 629 if (remain <= 0) 630 break; 631 632 /* Operation in this page 633 * 634 * shmem_page_offset = offset within page in shmem file 635 * page_length = bytes to copy for this page 636 */ 637 shmem_page_offset = offset_in_page(offset); 638 page_length = remain; 639 if ((shmem_page_offset + page_length) > PAGE_SIZE) 640 page_length = PAGE_SIZE - shmem_page_offset; 641 642 page_do_bit17_swizzling = obj_do_bit17_swizzling && 643 (page_to_phys(page) & (1 << 17)) != 0; 644 645 ret = shmem_pread_fast(page, shmem_page_offset, page_length, 646 user_data, page_do_bit17_swizzling, 647 needs_clflush); 648 if (ret == 0) 649 goto next_page; 650 651 mutex_unlock(&dev->struct_mutex); 652 653 if (likely(!i915.prefault_disable) && !prefaulted) { 654 ret = fault_in_multipages_writeable(user_data, remain); 655 /* Userspace is tricking us, but we've already clobbered 656 * its pages with the prefault and promised to write the 657 * data up to the first fault. Hence ignore any errors 658 * and just continue. */ 659 (void)ret; 660 prefaulted = 1; 661 } 662 663 ret = shmem_pread_slow(page, shmem_page_offset, page_length, 664 user_data, page_do_bit17_swizzling, 665 needs_clflush); 666 667 mutex_lock(&dev->struct_mutex); 668 669 if (ret) 670 goto out; 671 672 next_page: 673 remain -= page_length; 674 user_data += page_length; 675 offset += page_length; 676 } 677 678 out: 679 i915_gem_object_unpin_pages(obj); 680 681 return ret; 682 } 683 684 /** 685 * Reads data from the object referenced by handle. 686 * 687 * On error, the contents of *data are undefined. 688 */ 689 int 690 i915_gem_pread_ioctl(struct drm_device *dev, void *data, 691 struct drm_file *file) 692 { 693 struct drm_i915_gem_pread *args = data; 694 struct drm_i915_gem_object *obj; 695 int ret = 0; 696 697 if (args->size == 0) 698 return 0; 699 700 ret = i915_mutex_lock_interruptible(dev); 701 if (ret) 702 return ret; 703 704 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 705 if (&obj->base == NULL) { 706 ret = -ENOENT; 707 goto unlock; 708 } 709 710 /* Bounds check source. */ 711 if (args->offset > obj->base.size || 712 args->size > obj->base.size - args->offset) { 713 ret = -EINVAL; 714 goto out; 715 } 716 717 /* prime objects have no backing filp to GEM pread/pwrite 718 * pages from. 719 */ 720 721 trace_i915_gem_object_pread(obj, args->offset, args->size); 722 723 ret = i915_gem_shmem_pread(dev, obj, args, file); 724 725 out: 726 drm_gem_object_unreference(&obj->base); 727 unlock: 728 mutex_unlock(&dev->struct_mutex); 729 return ret; 730 } 731 732 /* This is the fast write path which cannot handle 733 * page faults in the source data 734 */ 735 736 static inline int 737 fast_user_write(struct io_mapping *mapping, 738 loff_t page_base, int page_offset, 739 char __user *user_data, 740 int length) 741 { 742 void __iomem *vaddr_atomic; 743 void *vaddr; 744 unsigned long unwritten; 745 746 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); 747 /* We can use the cpu mem copy function because this is X86. */ 748 vaddr = (char __force*)vaddr_atomic + page_offset; 749 unwritten = __copy_from_user_inatomic_nocache(vaddr, 750 user_data, length); 751 io_mapping_unmap_atomic(vaddr_atomic); 752 return unwritten; 753 } 754 755 /** 756 * This is the fast pwrite path, where we copy the data directly from the 757 * user into the GTT, uncached. 758 */ 759 static int 760 i915_gem_gtt_pwrite_fast(struct drm_device *dev, 761 struct drm_i915_gem_object *obj, 762 struct drm_i915_gem_pwrite *args, 763 struct drm_file *file) 764 { 765 struct drm_i915_private *dev_priv = dev->dev_private; 766 ssize_t remain; 767 loff_t offset, page_base; 768 char __user *user_data; 769 int page_offset, page_length, ret; 770 771 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); 772 if (ret) 773 goto out; 774 775 ret = i915_gem_object_set_to_gtt_domain(obj, true); 776 if (ret) 777 goto out_unpin; 778 779 ret = i915_gem_object_put_fence(obj); 780 if (ret) 781 goto out_unpin; 782 783 user_data = to_user_ptr(args->data_ptr); 784 remain = args->size; 785 786 offset = i915_gem_obj_ggtt_offset(obj) + args->offset; 787 788 intel_fb_obj_invalidate(obj, ORIGIN_GTT); 789 790 while (remain > 0) { 791 /* Operation in this page 792 * 793 * page_base = page offset within aperture 794 * page_offset = offset within page 795 * page_length = bytes to copy for this page 796 */ 797 page_base = offset & ~PAGE_MASK; 798 page_offset = offset_in_page(offset); 799 page_length = remain; 800 if ((page_offset + remain) > PAGE_SIZE) 801 page_length = PAGE_SIZE - page_offset; 802 803 /* If we get a fault while copying data, then (presumably) our 804 * source page isn't available. Return the error and we'll 805 * retry in the slow path. 806 */ 807 if (fast_user_write(dev_priv->gtt.mappable, page_base, 808 page_offset, user_data, page_length)) { 809 ret = -EFAULT; 810 goto out_flush; 811 } 812 813 remain -= page_length; 814 user_data += page_length; 815 offset += page_length; 816 } 817 818 out_flush: 819 intel_fb_obj_flush(obj, false, ORIGIN_GTT); 820 out_unpin: 821 i915_gem_object_ggtt_unpin(obj); 822 out: 823 return ret; 824 } 825 826 /* Per-page copy function for the shmem pwrite fastpath. 827 * Flushes invalid cachelines before writing to the target if 828 * needs_clflush_before is set and flushes out any written cachelines after 829 * writing if needs_clflush is set. */ 830 static int 831 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length, 832 char __user *user_data, 833 bool page_do_bit17_swizzling, 834 bool needs_clflush_before, 835 bool needs_clflush_after) 836 { 837 char *vaddr; 838 int ret; 839 840 if (unlikely(page_do_bit17_swizzling)) 841 return -EINVAL; 842 843 vaddr = kmap_atomic(page); 844 if (needs_clflush_before) 845 drm_clflush_virt_range(vaddr + shmem_page_offset, 846 page_length); 847 ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, 848 user_data, page_length); 849 if (needs_clflush_after) 850 drm_clflush_virt_range(vaddr + shmem_page_offset, 851 page_length); 852 kunmap_atomic(vaddr); 853 854 return ret ? -EFAULT : 0; 855 } 856 857 /* Only difference to the fast-path function is that this can handle bit17 858 * and uses non-atomic copy and kmap functions. */ 859 static int 860 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length, 861 char __user *user_data, 862 bool page_do_bit17_swizzling, 863 bool needs_clflush_before, 864 bool needs_clflush_after) 865 { 866 char *vaddr; 867 int ret; 868 869 vaddr = kmap(page); 870 if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) 871 shmem_clflush_swizzled_range(vaddr + shmem_page_offset, 872 page_length, 873 page_do_bit17_swizzling); 874 if (page_do_bit17_swizzling) 875 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, 876 user_data, 877 page_length); 878 else 879 ret = __copy_from_user(vaddr + shmem_page_offset, 880 user_data, 881 page_length); 882 if (needs_clflush_after) 883 shmem_clflush_swizzled_range(vaddr + shmem_page_offset, 884 page_length, 885 page_do_bit17_swizzling); 886 kunmap(page); 887 888 return ret ? -EFAULT : 0; 889 } 890 891 static int 892 i915_gem_shmem_pwrite(struct drm_device *dev, 893 struct drm_i915_gem_object *obj, 894 struct drm_i915_gem_pwrite *args, 895 struct drm_file *file) 896 { 897 ssize_t remain; 898 loff_t offset; 899 char __user *user_data; 900 int shmem_page_offset, page_length, ret = 0; 901 int obj_do_bit17_swizzling, page_do_bit17_swizzling; 902 int hit_slowpath = 0; 903 int needs_clflush_after = 0; 904 int needs_clflush_before = 0; 905 struct sg_page_iter sg_iter; 906 907 user_data = to_user_ptr(args->data_ptr); 908 remain = args->size; 909 910 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); 911 912 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { 913 /* If we're not in the cpu write domain, set ourself into the gtt 914 * write domain and manually flush cachelines (if required). This 915 * optimizes for the case when the gpu will use the data 916 * right away and we therefore have to clflush anyway. */ 917 needs_clflush_after = cpu_write_needs_clflush(obj); 918 ret = i915_gem_object_wait_rendering(obj, false); 919 if (ret) 920 return ret; 921 } 922 /* Same trick applies to invalidate partially written cachelines read 923 * before writing. */ 924 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) 925 needs_clflush_before = 926 !cpu_cache_is_coherent(dev, obj->cache_level); 927 928 ret = i915_gem_object_get_pages(obj); 929 if (ret) 930 return ret; 931 932 intel_fb_obj_invalidate(obj, ORIGIN_CPU); 933 934 i915_gem_object_pin_pages(obj); 935 936 offset = args->offset; 937 obj->dirty = 1; 938 939 VM_OBJECT_LOCK(obj->base.vm_obj); 940 vm_object_pip_add(obj->base.vm_obj, 1); 941 942 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 943 offset >> PAGE_SHIFT) { 944 struct vm_page *page = sg_page_iter_page(&sg_iter); 945 int partial_cacheline_write; 946 947 if (remain <= 0) 948 break; 949 950 /* Operation in this page 951 * 952 * shmem_page_offset = offset within page in shmem file 953 * page_length = bytes to copy for this page 954 */ 955 shmem_page_offset = offset_in_page(offset); 956 957 page_length = remain; 958 if ((shmem_page_offset + page_length) > PAGE_SIZE) 959 page_length = PAGE_SIZE - shmem_page_offset; 960 961 /* If we don't overwrite a cacheline completely we need to be 962 * careful to have up-to-date data by first clflushing. Don't 963 * overcomplicate things and flush the entire patch. */ 964 partial_cacheline_write = needs_clflush_before && 965 ((shmem_page_offset | page_length) 966 & (cpu_clflush_line_size - 1)); 967 968 page_do_bit17_swizzling = obj_do_bit17_swizzling && 969 (page_to_phys(page) & (1 << 17)) != 0; 970 971 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, 972 user_data, page_do_bit17_swizzling, 973 partial_cacheline_write, 974 needs_clflush_after); 975 if (ret == 0) 976 goto next_page; 977 978 hit_slowpath = 1; 979 mutex_unlock(&dev->struct_mutex); 980 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, 981 user_data, page_do_bit17_swizzling, 982 partial_cacheline_write, 983 needs_clflush_after); 984 985 mutex_lock(&dev->struct_mutex); 986 987 if (ret) 988 goto out; 989 990 next_page: 991 remain -= page_length; 992 user_data += page_length; 993 offset += page_length; 994 } 995 vm_object_pip_wakeup(obj->base.vm_obj); 996 VM_OBJECT_UNLOCK(obj->base.vm_obj); 997 998 out: 999 i915_gem_object_unpin_pages(obj); 1000 1001 if (hit_slowpath) { 1002 /* 1003 * Fixup: Flush cpu caches in case we didn't flush the dirty 1004 * cachelines in-line while writing and the object moved 1005 * out of the cpu write domain while we've dropped the lock. 1006 */ 1007 if (!needs_clflush_after && 1008 obj->base.write_domain != I915_GEM_DOMAIN_CPU) { 1009 if (i915_gem_clflush_object(obj, obj->pin_display)) 1010 i915_gem_chipset_flush(dev); 1011 } 1012 } 1013 1014 if (needs_clflush_after) 1015 i915_gem_chipset_flush(dev); 1016 1017 intel_fb_obj_flush(obj, false, ORIGIN_CPU); 1018 return ret; 1019 } 1020 1021 /** 1022 * Writes data to the object referenced by handle. 1023 * 1024 * On error, the contents of the buffer that were to be modified are undefined. 1025 */ 1026 int 1027 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1028 struct drm_file *file) 1029 { 1030 struct drm_i915_private *dev_priv = dev->dev_private; 1031 struct drm_i915_gem_pwrite *args = data; 1032 struct drm_i915_gem_object *obj; 1033 int ret; 1034 1035 if (args->size == 0) 1036 return 0; 1037 1038 if (likely(!i915.prefault_disable)) { 1039 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), 1040 args->size); 1041 if (ret) 1042 return -EFAULT; 1043 } 1044 1045 intel_runtime_pm_get(dev_priv); 1046 1047 ret = i915_mutex_lock_interruptible(dev); 1048 if (ret) 1049 goto put_rpm; 1050 1051 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 1052 if (&obj->base == NULL) { 1053 ret = -ENOENT; 1054 goto unlock; 1055 } 1056 1057 /* Bounds check destination. */ 1058 if (args->offset > obj->base.size || 1059 args->size > obj->base.size - args->offset) { 1060 ret = -EINVAL; 1061 goto out; 1062 } 1063 1064 /* prime objects have no backing filp to GEM pread/pwrite 1065 * pages from. 1066 */ 1067 1068 trace_i915_gem_object_pwrite(obj, args->offset, args->size); 1069 1070 ret = -EFAULT; 1071 /* We can only do the GTT pwrite on untiled buffers, as otherwise 1072 * it would end up going through the fenced access, and we'll get 1073 * different detiling behavior between reading and writing. 1074 * pread/pwrite currently are reading and writing from the CPU 1075 * perspective, requiring manual detiling by the client. 1076 */ 1077 if (obj->tiling_mode == I915_TILING_NONE && 1078 obj->base.write_domain != I915_GEM_DOMAIN_CPU && 1079 cpu_write_needs_clflush(obj)) { 1080 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); 1081 /* Note that the gtt paths might fail with non-page-backed user 1082 * pointers (e.g. gtt mappings when moving data between 1083 * textures). Fallback to the shmem path in that case. */ 1084 } 1085 1086 if (ret == -EFAULT || ret == -ENOSPC) { 1087 if (obj->phys_handle) 1088 ret = i915_gem_phys_pwrite(obj, args, file); 1089 else 1090 ret = i915_gem_shmem_pwrite(dev, obj, args, file); 1091 } 1092 1093 out: 1094 drm_gem_object_unreference(&obj->base); 1095 unlock: 1096 mutex_unlock(&dev->struct_mutex); 1097 put_rpm: 1098 intel_runtime_pm_put(dev_priv); 1099 1100 return ret; 1101 } 1102 1103 int 1104 i915_gem_check_wedge(struct i915_gpu_error *error, 1105 bool interruptible) 1106 { 1107 if (i915_reset_in_progress(error)) { 1108 /* Non-interruptible callers can't handle -EAGAIN, hence return 1109 * -EIO unconditionally for these. */ 1110 if (!interruptible) 1111 return -EIO; 1112 1113 /* Recovery complete, but the reset failed ... */ 1114 if (i915_terminally_wedged(error)) 1115 return -EIO; 1116 1117 /* 1118 * Check if GPU Reset is in progress - we need intel_ring_begin 1119 * to work properly to reinit the hw state while the gpu is 1120 * still marked as reset-in-progress. Handle this with a flag. 1121 */ 1122 if (!error->reload_in_reset) 1123 return -EAGAIN; 1124 } 1125 1126 return 0; 1127 } 1128 1129 static void fake_irq(unsigned long data) 1130 { 1131 wakeup_one((void *)data); 1132 } 1133 1134 static bool missed_irq(struct drm_i915_private *dev_priv, 1135 struct intel_engine_cs *ring) 1136 { 1137 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); 1138 } 1139 1140 #if 0 1141 static int __i915_spin_request(struct drm_i915_gem_request *req) 1142 { 1143 unsigned long timeout; 1144 1145 if (i915_gem_request_get_ring(req)->irq_refcount) 1146 return -EBUSY; 1147 1148 timeout = jiffies + 1; 1149 while (!need_resched()) { 1150 if (i915_gem_request_completed(req, true)) 1151 return 0; 1152 1153 if (time_after_eq(jiffies, timeout)) 1154 break; 1155 1156 cpu_relax_lowlatency(); 1157 } 1158 if (i915_gem_request_completed(req, false)) 1159 return 0; 1160 1161 return -EAGAIN; 1162 } 1163 #endif 1164 1165 /** 1166 * __i915_wait_request - wait until execution of request has finished 1167 * @req: duh! 1168 * @reset_counter: reset sequence associated with the given request 1169 * @interruptible: do an interruptible wait (normally yes) 1170 * @timeout: in - how long to wait (NULL forever); out - how much time remaining 1171 * 1172 * Note: It is of utmost importance that the passed in seqno and reset_counter 1173 * values have been read by the caller in an smp safe manner. Where read-side 1174 * locks are involved, it is sufficient to read the reset_counter before 1175 * unlocking the lock that protects the seqno. For lockless tricks, the 1176 * reset_counter _must_ be read before, and an appropriate smp_rmb must be 1177 * inserted. 1178 * 1179 * Returns 0 if the request was found within the alloted time. Else returns the 1180 * errno with remaining time filled in timeout argument. 1181 */ 1182 int __i915_wait_request(struct drm_i915_gem_request *req, 1183 unsigned reset_counter, 1184 bool interruptible, 1185 s64 *timeout, 1186 struct intel_rps_client *rps) 1187 { 1188 struct intel_engine_cs *ring = i915_gem_request_get_ring(req); 1189 struct drm_device *dev = ring->dev; 1190 struct drm_i915_private *dev_priv = dev->dev_private; 1191 const bool irq_test_in_progress = 1192 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); 1193 unsigned long timeout_expire; 1194 s64 before, now; 1195 int ret, sl_timeout = 1; 1196 1197 WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); 1198 1199 if (list_empty(&req->list)) 1200 return 0; 1201 1202 if (i915_gem_request_completed(req, true)) 1203 return 0; 1204 1205 timeout_expire = timeout ? 1206 jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; 1207 1208 if (INTEL_INFO(dev_priv)->gen >= 6) 1209 gen6_rps_boost(dev_priv, rps, req->emitted_jiffies); 1210 1211 /* Record current time in case interrupted by signal, or wedged */ 1212 trace_i915_gem_request_wait_begin(req); 1213 before = ktime_get_raw_ns(); 1214 1215 /* Optimistic spin for the next jiffie before touching IRQs */ 1216 #if 0 1217 ret = __i915_spin_request(req); 1218 if (ret == 0) 1219 goto out; 1220 #endif 1221 1222 if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) { 1223 ret = -ENODEV; 1224 goto out; 1225 } 1226 1227 lockmgr(&ring->irq_queue.lock, LK_EXCLUSIVE); 1228 for (;;) { 1229 struct timer_list timer; 1230 1231 /* We need to check whether any gpu reset happened in between 1232 * the caller grabbing the seqno and now ... */ 1233 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { 1234 /* ... but upgrade the -EAGAIN to an -EIO if the gpu 1235 * is truely gone. */ 1236 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); 1237 if (ret == 0) 1238 ret = -EAGAIN; 1239 break; 1240 } 1241 1242 if (i915_gem_request_completed(req, false)) { 1243 ret = 0; 1244 break; 1245 } 1246 1247 if (interruptible && signal_pending(curthread->td_lwp)) { 1248 ret = -ERESTARTSYS; 1249 break; 1250 } 1251 1252 if (timeout && time_after_eq(jiffies, timeout_expire)) { 1253 ret = -ETIME; 1254 break; 1255 } 1256 1257 timer.function = NULL; 1258 if (timeout || missed_irq(dev_priv, ring)) { 1259 unsigned long expire; 1260 1261 setup_timer_on_stack(&timer, fake_irq, (unsigned long)&ring->irq_queue); 1262 expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; 1263 sl_timeout = expire - jiffies; 1264 if (sl_timeout < 1) 1265 sl_timeout = 1; 1266 mod_timer(&timer, expire); 1267 } 1268 1269 #if 0 1270 io_schedule(); 1271 #endif 1272 1273 if (timer.function) { 1274 del_singleshot_timer_sync(&timer); 1275 destroy_timer_on_stack(&timer); 1276 } 1277 1278 lksleep(&ring->irq_queue, &ring->irq_queue.lock, 1279 interruptible ? PCATCH : 0, "lwe", sl_timeout); 1280 } 1281 lockmgr(&ring->irq_queue.lock, LK_RELEASE); 1282 if (!irq_test_in_progress) 1283 ring->irq_put(ring); 1284 1285 out: 1286 now = ktime_get_raw_ns(); 1287 trace_i915_gem_request_wait_end(req); 1288 1289 if (timeout) { 1290 s64 tres = *timeout - (now - before); 1291 1292 *timeout = tres < 0 ? 0 : tres; 1293 1294 /* 1295 * Apparently ktime isn't accurate enough and occasionally has a 1296 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch 1297 * things up to make the test happy. We allow up to 1 jiffy. 1298 * 1299 * This is a regrssion from the timespec->ktime conversion. 1300 */ 1301 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) 1302 *timeout = 0; 1303 } 1304 1305 return ret; 1306 } 1307 1308 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, 1309 struct drm_file *file) 1310 { 1311 struct drm_i915_private *dev_private; 1312 struct drm_i915_file_private *file_priv; 1313 1314 WARN_ON(!req || !file || req->file_priv); 1315 1316 if (!req || !file) 1317 return -EINVAL; 1318 1319 if (req->file_priv) 1320 return -EINVAL; 1321 1322 dev_private = req->ring->dev->dev_private; 1323 file_priv = file->driver_priv; 1324 1325 spin_lock(&file_priv->mm.lock); 1326 req->file_priv = file_priv; 1327 list_add_tail(&req->client_list, &file_priv->mm.request_list); 1328 spin_unlock(&file_priv->mm.lock); 1329 1330 req->pid = curproc->p_pid; 1331 1332 return 0; 1333 } 1334 1335 static inline void 1336 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) 1337 { 1338 struct drm_i915_file_private *file_priv = request->file_priv; 1339 1340 if (!file_priv) 1341 return; 1342 1343 spin_lock(&file_priv->mm.lock); 1344 list_del(&request->client_list); 1345 request->file_priv = NULL; 1346 spin_unlock(&file_priv->mm.lock); 1347 1348 #if 0 1349 put_pid(request->pid); 1350 request->pid = NULL; 1351 #endif 1352 } 1353 1354 static void i915_gem_request_retire(struct drm_i915_gem_request *request) 1355 { 1356 trace_i915_gem_request_retire(request); 1357 1358 /* We know the GPU must have read the request to have 1359 * sent us the seqno + interrupt, so use the position 1360 * of tail of the request to update the last known position 1361 * of the GPU head. 1362 * 1363 * Note this requires that we are always called in request 1364 * completion order. 1365 */ 1366 request->ringbuf->last_retired_head = request->postfix; 1367 1368 list_del_init(&request->list); 1369 i915_gem_request_remove_from_client(request); 1370 1371 i915_gem_request_unreference(request); 1372 } 1373 1374 static void 1375 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) 1376 { 1377 struct intel_engine_cs *engine = req->ring; 1378 struct drm_i915_gem_request *tmp; 1379 1380 lockdep_assert_held(&engine->dev->struct_mutex); 1381 1382 if (list_empty(&req->list)) 1383 return; 1384 1385 do { 1386 tmp = list_first_entry(&engine->request_list, 1387 typeof(*tmp), list); 1388 1389 i915_gem_request_retire(tmp); 1390 } while (tmp != req); 1391 1392 WARN_ON(i915_verify_lists(engine->dev)); 1393 } 1394 1395 /** 1396 * Waits for a request to be signaled, and cleans up the 1397 * request and object lists appropriately for that event. 1398 */ 1399 int 1400 i915_wait_request(struct drm_i915_gem_request *req) 1401 { 1402 struct drm_device *dev; 1403 struct drm_i915_private *dev_priv; 1404 bool interruptible; 1405 int ret; 1406 1407 BUG_ON(req == NULL); 1408 1409 dev = req->ring->dev; 1410 dev_priv = dev->dev_private; 1411 interruptible = dev_priv->mm.interruptible; 1412 1413 BUG_ON(!mutex_is_locked(&dev->struct_mutex)); 1414 1415 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); 1416 if (ret) 1417 return ret; 1418 1419 ret = __i915_wait_request(req, 1420 atomic_read(&dev_priv->gpu_error.reset_counter), 1421 interruptible, NULL, NULL); 1422 if (ret) 1423 return ret; 1424 1425 __i915_gem_request_retire__upto(req); 1426 return 0; 1427 } 1428 1429 /** 1430 * Ensures that all rendering to the object has completed and the object is 1431 * safe to unbind from the GTT or access from the CPU. 1432 */ 1433 int 1434 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, 1435 bool readonly) 1436 { 1437 int ret, i; 1438 1439 if (!obj->active) 1440 return 0; 1441 1442 if (readonly) { 1443 if (obj->last_write_req != NULL) { 1444 ret = i915_wait_request(obj->last_write_req); 1445 if (ret) 1446 return ret; 1447 1448 i = obj->last_write_req->ring->id; 1449 if (obj->last_read_req[i] == obj->last_write_req) 1450 i915_gem_object_retire__read(obj, i); 1451 else 1452 i915_gem_object_retire__write(obj); 1453 } 1454 } else { 1455 for (i = 0; i < I915_NUM_RINGS; i++) { 1456 if (obj->last_read_req[i] == NULL) 1457 continue; 1458 1459 ret = i915_wait_request(obj->last_read_req[i]); 1460 if (ret) 1461 return ret; 1462 1463 i915_gem_object_retire__read(obj, i); 1464 } 1465 RQ_BUG_ON(obj->active); 1466 } 1467 1468 return 0; 1469 } 1470 1471 static void 1472 i915_gem_object_retire_request(struct drm_i915_gem_object *obj, 1473 struct drm_i915_gem_request *req) 1474 { 1475 int ring = req->ring->id; 1476 1477 if (obj->last_read_req[ring] == req) 1478 i915_gem_object_retire__read(obj, ring); 1479 else if (obj->last_write_req == req) 1480 i915_gem_object_retire__write(obj); 1481 1482 __i915_gem_request_retire__upto(req); 1483 } 1484 1485 /* A nonblocking variant of the above wait. This is a highly dangerous routine 1486 * as the object state may change during this call. 1487 */ 1488 static __must_check int 1489 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, 1490 struct intel_rps_client *rps, 1491 bool readonly) 1492 { 1493 struct drm_device *dev = obj->base.dev; 1494 struct drm_i915_private *dev_priv = dev->dev_private; 1495 struct drm_i915_gem_request *requests[I915_NUM_RINGS]; 1496 unsigned reset_counter; 1497 int ret, i, n = 0; 1498 1499 BUG_ON(!mutex_is_locked(&dev->struct_mutex)); 1500 BUG_ON(!dev_priv->mm.interruptible); 1501 1502 if (!obj->active) 1503 return 0; 1504 1505 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); 1506 if (ret) 1507 return ret; 1508 1509 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); 1510 1511 if (readonly) { 1512 struct drm_i915_gem_request *req; 1513 1514 req = obj->last_write_req; 1515 if (req == NULL) 1516 return 0; 1517 1518 requests[n++] = i915_gem_request_reference(req); 1519 } else { 1520 for (i = 0; i < I915_NUM_RINGS; i++) { 1521 struct drm_i915_gem_request *req; 1522 1523 req = obj->last_read_req[i]; 1524 if (req == NULL) 1525 continue; 1526 1527 requests[n++] = i915_gem_request_reference(req); 1528 } 1529 } 1530 1531 mutex_unlock(&dev->struct_mutex); 1532 for (i = 0; ret == 0 && i < n; i++) 1533 ret = __i915_wait_request(requests[i], reset_counter, true, 1534 NULL, rps); 1535 mutex_lock(&dev->struct_mutex); 1536 1537 for (i = 0; i < n; i++) { 1538 if (ret == 0) 1539 i915_gem_object_retire_request(obj, requests[i]); 1540 i915_gem_request_unreference(requests[i]); 1541 } 1542 1543 return ret; 1544 } 1545 1546 static struct intel_rps_client *to_rps_client(struct drm_file *file) 1547 { 1548 struct drm_i915_file_private *fpriv = file->driver_priv; 1549 return &fpriv->rps; 1550 } 1551 1552 /** 1553 * Called when user space prepares to use an object with the CPU, either 1554 * through the mmap ioctl's mapping or a GTT mapping. 1555 */ 1556 int 1557 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1558 struct drm_file *file) 1559 { 1560 struct drm_i915_gem_set_domain *args = data; 1561 struct drm_i915_gem_object *obj; 1562 uint32_t read_domains = args->read_domains; 1563 uint32_t write_domain = args->write_domain; 1564 int ret; 1565 1566 /* Only handle setting domains to types used by the CPU. */ 1567 if (write_domain & I915_GEM_GPU_DOMAINS) 1568 return -EINVAL; 1569 1570 if (read_domains & I915_GEM_GPU_DOMAINS) 1571 return -EINVAL; 1572 1573 /* Having something in the write domain implies it's in the read 1574 * domain, and only that read domain. Enforce that in the request. 1575 */ 1576 if (write_domain != 0 && read_domains != write_domain) 1577 return -EINVAL; 1578 1579 ret = i915_mutex_lock_interruptible(dev); 1580 if (ret) 1581 return ret; 1582 1583 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 1584 if (&obj->base == NULL) { 1585 ret = -ENOENT; 1586 goto unlock; 1587 } 1588 1589 /* Try to flush the object off the GPU without holding the lock. 1590 * We will repeat the flush holding the lock in the normal manner 1591 * to catch cases where we are gazumped. 1592 */ 1593 ret = i915_gem_object_wait_rendering__nonblocking(obj, 1594 to_rps_client(file), 1595 !write_domain); 1596 if (ret) 1597 goto unref; 1598 1599 if (read_domains & I915_GEM_DOMAIN_GTT) 1600 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); 1601 else 1602 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); 1603 1604 if (write_domain != 0) 1605 intel_fb_obj_invalidate(obj, 1606 write_domain == I915_GEM_DOMAIN_GTT ? 1607 ORIGIN_GTT : ORIGIN_CPU); 1608 1609 unref: 1610 drm_gem_object_unreference(&obj->base); 1611 unlock: 1612 mutex_unlock(&dev->struct_mutex); 1613 return ret; 1614 } 1615 1616 /** 1617 * Called when user space has done writes to this buffer 1618 */ 1619 int 1620 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1621 struct drm_file *file) 1622 { 1623 struct drm_i915_gem_sw_finish *args = data; 1624 struct drm_i915_gem_object *obj; 1625 int ret = 0; 1626 1627 ret = i915_mutex_lock_interruptible(dev); 1628 if (ret) 1629 return ret; 1630 1631 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 1632 if (&obj->base == NULL) { 1633 ret = -ENOENT; 1634 goto unlock; 1635 } 1636 1637 /* Pinned buffers may be scanout, so flush the cache */ 1638 if (obj->pin_display) 1639 i915_gem_object_flush_cpu_write_domain(obj); 1640 1641 drm_gem_object_unreference(&obj->base); 1642 unlock: 1643 mutex_unlock(&dev->struct_mutex); 1644 return ret; 1645 } 1646 1647 /** 1648 * Maps the contents of an object, returning the address it is mapped 1649 * into. 1650 * 1651 * While the mapping holds a reference on the contents of the object, it doesn't 1652 * imply a ref on the object itself. 1653 * 1654 * IMPORTANT: 1655 * 1656 * DRM driver writers who look a this function as an example for how to do GEM 1657 * mmap support, please don't implement mmap support like here. The modern way 1658 * to implement DRM mmap support is with an mmap offset ioctl (like 1659 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. 1660 * That way debug tooling like valgrind will understand what's going on, hiding 1661 * the mmap call in a driver private ioctl will break that. The i915 driver only 1662 * does cpu mmaps this way because we didn't know better. 1663 */ 1664 int 1665 i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1666 struct drm_file *file) 1667 { 1668 struct drm_i915_gem_mmap *args = data; 1669 struct drm_gem_object *obj; 1670 unsigned long addr; 1671 1672 struct proc *p = curproc; 1673 vm_map_t map = &p->p_vmspace->vm_map; 1674 vm_size_t size; 1675 int error = 0, rv; 1676 1677 if (args->flags & ~(I915_MMAP_WC)) 1678 return -EINVAL; 1679 1680 obj = drm_gem_object_lookup(dev, file, args->handle); 1681 if (obj == NULL) 1682 return -ENOENT; 1683 1684 if (args->size == 0) 1685 goto out; 1686 1687 size = round_page(args->size); 1688 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) { 1689 error = -ENOMEM; 1690 goto out; 1691 } 1692 1693 /* prime objects have no backing filp to GEM mmap 1694 * pages from. 1695 */ 1696 1697 /* 1698 * Call hint to ensure that NULL is not returned as a valid address 1699 * and to reduce vm_map traversals. XXX causes instability, use a 1700 * fixed low address as the start point instead to avoid the NULL 1701 * return issue. 1702 */ 1703 1704 addr = PAGE_SIZE; 1705 1706 /* 1707 * Use 256KB alignment. It is unclear why this matters for a 1708 * virtual address but it appears to fix a number of application/X 1709 * crashes and kms console switching is much faster. 1710 */ 1711 vm_object_hold(obj->vm_obj); 1712 vm_object_reference_locked(obj->vm_obj); 1713 vm_object_drop(obj->vm_obj); 1714 1715 rv = vm_map_find(map, obj->vm_obj, NULL, 1716 args->offset, &addr, args->size, 1717 256 * 1024, /* align */ 1718 TRUE, /* fitit */ 1719 VM_MAPTYPE_NORMAL, /* maptype */ 1720 VM_PROT_READ | VM_PROT_WRITE, /* prot */ 1721 VM_PROT_READ | VM_PROT_WRITE, /* max */ 1722 MAP_SHARED /* cow */); 1723 if (rv != KERN_SUCCESS) { 1724 vm_object_deallocate(obj->vm_obj); 1725 error = -vm_mmap_to_errno(rv); 1726 } else { 1727 args->addr_ptr = (uint64_t)addr; 1728 } 1729 out: 1730 drm_gem_object_unreference(obj); 1731 return (error); 1732 } 1733 1734 /** 1735 * i915_gem_fault - fault a page into the GTT 1736 * 1737 * vm_obj is locked on entry and expected to be locked on return. 1738 * 1739 * The vm_pager has placemarked the object with an anonymous memory page 1740 * which we must replace atomically to avoid races against concurrent faults 1741 * on the same page. XXX we currently are unable to do this atomically. 1742 * 1743 * If we are to return an error we should not touch the anonymous page, 1744 * the caller will deallocate it. 1745 * 1746 * XXX Most GEM calls appear to be interruptable, but we can't hard loop 1747 * in that case. Release all resources and wait 1 tick before retrying. 1748 * This is a huge problem which needs to be fixed by getting rid of most 1749 * of the interruptability. The linux code does not retry but does appear 1750 * to have some sort of mechanism (VM_FAULT_NOPAGE ?) for the higher level 1751 * to be able to retry. 1752 * 1753 * -- 1754 * vma: VMA in question 1755 * vmf: fault info 1756 * 1757 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped 1758 * from userspace. The fault handler takes care of binding the object to 1759 * the GTT (if needed), allocating and programming a fence register (again, 1760 * only if needed based on whether the old reg is still valid or the object 1761 * is tiled) and inserting a new PTE into the faulting process. 1762 * 1763 * Note that the faulting process may involve evicting existing objects 1764 * from the GTT and/or fence registers to make room. So performance may 1765 * suffer if the GTT working set is large or there are few fence registers 1766 * left. 1767 * 1768 * vm_obj is locked on entry and expected to be locked on return. The VM 1769 * pager has placed an anonymous memory page at (obj,offset) which we have 1770 * to replace. 1771 */ 1772 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres) 1773 { 1774 struct drm_i915_gem_object *obj = to_intel_bo(vm_obj->handle); 1775 struct drm_device *dev = obj->base.dev; 1776 struct drm_i915_private *dev_priv = dev->dev_private; 1777 struct i915_ggtt_view view = i915_ggtt_view_normal; 1778 unsigned long page_offset; 1779 vm_page_t m, oldm = NULL; 1780 int ret = 0; 1781 bool write = !!(prot & VM_PROT_WRITE); 1782 1783 intel_runtime_pm_get(dev_priv); 1784 1785 /* We don't use vmf->pgoff since that has the fake offset */ 1786 page_offset = (unsigned long)offset; 1787 1788 retry: 1789 ret = i915_mutex_lock_interruptible(dev); 1790 if (ret) 1791 goto out; 1792 1793 trace_i915_gem_object_fault(obj, page_offset, true, write); 1794 1795 /* Try to flush the object off the GPU first without holding the lock. 1796 * Upon reacquiring the lock, we will perform our sanity checks and then 1797 * repeat the flush holding the lock in the normal manner to catch cases 1798 * where we are gazumped. 1799 */ 1800 ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); 1801 if (ret) 1802 goto unlock; 1803 1804 /* Access to snoopable pages through the GTT is incoherent. */ 1805 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { 1806 ret = -EFAULT; 1807 goto unlock; 1808 } 1809 1810 /* Use a partial view if the object is bigger than the aperture. */ 1811 if (obj->base.size >= dev_priv->gtt.mappable_end && 1812 obj->tiling_mode == I915_TILING_NONE) { 1813 #if 0 1814 static const unsigned int chunk_size = 256; // 1 MiB 1815 1816 memset(&view, 0, sizeof(view)); 1817 view.type = I915_GGTT_VIEW_PARTIAL; 1818 view.params.partial.offset = rounddown(page_offset, chunk_size); 1819 view.params.partial.size = 1820 min_t(unsigned int, 1821 chunk_size, 1822 (vma->vm_end - vma->vm_start)/PAGE_SIZE - 1823 view.params.partial.offset); 1824 #endif 1825 } 1826 1827 /* Now pin it into the GTT if needed */ 1828 ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); 1829 if (ret) 1830 goto unlock; 1831 1832 ret = i915_gem_object_set_to_gtt_domain(obj, write); 1833 if (ret) 1834 goto unpin; 1835 1836 ret = i915_gem_object_get_fence(obj); 1837 if (ret) 1838 goto unpin; 1839 1840 /* 1841 * START FREEBSD MAGIC 1842 * 1843 * Add a pip count to avoid destruction and certain other 1844 * complex operations (such as collapses?) while unlocked. 1845 */ 1846 vm_object_pip_add(vm_obj, 1); 1847 1848 /* 1849 * XXX We must currently remove the placeholder page now to avoid 1850 * a deadlock against a concurrent i915_gem_release_mmap(). 1851 * Otherwise concurrent operation will block on the busy page 1852 * while holding locks which we need to obtain. 1853 */ 1854 if (*mres != NULL) { 1855 oldm = *mres; 1856 if ((oldm->flags & PG_BUSY) == 0) 1857 kprintf("i915_gem_fault: Page was not busy\n"); 1858 else 1859 vm_page_remove(oldm); 1860 *mres = NULL; 1861 } else { 1862 oldm = NULL; 1863 } 1864 1865 ret = 0; 1866 m = NULL; 1867 1868 /* 1869 * Since the object lock was dropped, another thread might have 1870 * faulted on the same GTT address and instantiated the mapping. 1871 * Recheck. 1872 */ 1873 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset)); 1874 if (m != NULL) { 1875 /* 1876 * Try to busy the page, retry on failure (non-zero ret). 1877 */ 1878 if (vm_page_busy_try(m, false)) { 1879 kprintf("i915_gem_fault: PG_BUSY\n"); 1880 ret = -EINTR; 1881 goto unlock; 1882 } 1883 goto have_page; 1884 } 1885 /* 1886 * END FREEBSD MAGIC 1887 */ 1888 1889 obj->fault_mappable = true; 1890 1891 /* Finally, remap it using the new GTT offset */ 1892 m = vm_phys_fictitious_to_vm_page(dev_priv->gtt.mappable_base + 1893 i915_gem_obj_ggtt_offset_view(obj, &view) + offset); 1894 if (m == NULL) { 1895 ret = -EFAULT; 1896 goto unpin; 1897 } 1898 KASSERT((m->flags & PG_FICTITIOUS) != 0, ("not fictitious %p", m)); 1899 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m)); 1900 1901 /* 1902 * Try to busy the page. Fails on non-zero return. 1903 */ 1904 if (vm_page_busy_try(m, false)) { 1905 kprintf("i915_gem_fault: PG_BUSY(2)\n"); 1906 ret = -EINTR; 1907 goto unpin; 1908 } 1909 m->valid = VM_PAGE_BITS_ALL; 1910 1911 #if 0 1912 if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { 1913 /* Overriding existing pages in partial view does not cause 1914 * us any trouble as TLBs are still valid because the fault 1915 * is due to userspace losing part of the mapping or never 1916 * having accessed it before (at this partials' range). 1917 */ 1918 unsigned long base = vma->vm_start + 1919 (view.params.partial.offset << PAGE_SHIFT); 1920 unsigned int i; 1921 1922 for (i = 0; i < view.params.partial.size; i++) { 1923 ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); 1924 if (ret) 1925 break; 1926 } 1927 1928 obj->fault_mappable = true; 1929 } else { 1930 if (!obj->fault_mappable) { 1931 unsigned long size = min_t(unsigned long, 1932 vma->vm_end - vma->vm_start, 1933 obj->base.size); 1934 int i; 1935 1936 for (i = 0; i < size >> PAGE_SHIFT; i++) { 1937 ret = vm_insert_pfn(vma, 1938 (unsigned long)vma->vm_start + i * PAGE_SIZE, 1939 pfn + i); 1940 if (ret) 1941 break; 1942 } 1943 1944 obj->fault_mappable = true; 1945 } else 1946 ret = vm_insert_pfn(vma, 1947 (unsigned long)vmf->virtual_address, 1948 pfn + page_offset); 1949 #endif 1950 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset)); 1951 #if 0 1952 } 1953 #endif 1954 1955 have_page: 1956 *mres = m; 1957 1958 i915_gem_object_ggtt_unpin_view(obj, &view); 1959 mutex_unlock(&dev->struct_mutex); 1960 ret = VM_PAGER_OK; 1961 goto done; 1962 1963 /* 1964 * ALTERNATIVE ERROR RETURN. 1965 * 1966 * OBJECT EXPECTED TO BE LOCKED. 1967 */ 1968 unpin: 1969 i915_gem_object_ggtt_unpin_view(obj, &view); 1970 unlock: 1971 mutex_unlock(&dev->struct_mutex); 1972 out: 1973 switch (ret) { 1974 case -EIO: 1975 /* 1976 * We eat errors when the gpu is terminally wedged to avoid 1977 * userspace unduly crashing (gl has no provisions for mmaps to 1978 * fail). But any other -EIO isn't ours (e.g. swap in failure) 1979 * and so needs to be reported. 1980 */ 1981 if (!i915_terminally_wedged(&dev_priv->gpu_error)) { 1982 // ret = VM_FAULT_SIGBUS; 1983 break; 1984 } 1985 case -EAGAIN: 1986 /* 1987 * EAGAIN means the gpu is hung and we'll wait for the error 1988 * handler to reset everything when re-faulting in 1989 * i915_mutex_lock_interruptible. 1990 */ 1991 case -ERESTARTSYS: 1992 case -EINTR: 1993 VM_OBJECT_UNLOCK(vm_obj); 1994 int dummy; 1995 tsleep(&dummy, 0, "delay", 1); /* XXX */ 1996 VM_OBJECT_LOCK(vm_obj); 1997 goto retry; 1998 default: 1999 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); 2000 ret = VM_PAGER_ERROR; 2001 break; 2002 } 2003 2004 done: 2005 if (oldm != NULL) 2006 vm_page_free(oldm); 2007 vm_object_pip_wakeup(vm_obj); 2008 2009 intel_runtime_pm_put(dev_priv); 2010 return ret; 2011 } 2012 2013 /** 2014 * i915_gem_release_mmap - remove physical page mappings 2015 * @obj: obj in question 2016 * 2017 * Preserve the reservation of the mmapping with the DRM core code, but 2018 * relinquish ownership of the pages back to the system. 2019 * 2020 * It is vital that we remove the page mapping if we have mapped a tiled 2021 * object through the GTT and then lose the fence register due to 2022 * resource pressure. Similarly if the object has been moved out of the 2023 * aperture, than pages mapped into userspace must be revoked. Removing the 2024 * mapping will then trigger a page fault on the next user access, allowing 2025 * fixup by i915_gem_fault(). 2026 */ 2027 void 2028 i915_gem_release_mmap(struct drm_i915_gem_object *obj) 2029 { 2030 vm_object_t devobj; 2031 vm_page_t m; 2032 int i, page_count; 2033 2034 if (!obj->fault_mappable) 2035 return; 2036 2037 devobj = cdev_pager_lookup(obj); 2038 if (devobj != NULL) { 2039 page_count = OFF_TO_IDX(obj->base.size); 2040 2041 VM_OBJECT_LOCK(devobj); 2042 for (i = 0; i < page_count; i++) { 2043 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm"); 2044 if (m == NULL) 2045 continue; 2046 cdev_pager_free_page(devobj, m); 2047 } 2048 VM_OBJECT_UNLOCK(devobj); 2049 vm_object_deallocate(devobj); 2050 } 2051 2052 obj->fault_mappable = false; 2053 } 2054 2055 void 2056 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) 2057 { 2058 struct drm_i915_gem_object *obj; 2059 2060 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) 2061 i915_gem_release_mmap(obj); 2062 } 2063 2064 uint32_t 2065 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) 2066 { 2067 uint32_t gtt_size; 2068 2069 if (INTEL_INFO(dev)->gen >= 4 || 2070 tiling_mode == I915_TILING_NONE) 2071 return size; 2072 2073 /* Previous chips need a power-of-two fence region when tiling */ 2074 if (INTEL_INFO(dev)->gen == 3) 2075 gtt_size = 1024*1024; 2076 else 2077 gtt_size = 512*1024; 2078 2079 while (gtt_size < size) 2080 gtt_size <<= 1; 2081 2082 return gtt_size; 2083 } 2084 2085 /** 2086 * i915_gem_get_gtt_alignment - return required GTT alignment for an object 2087 * @obj: object to check 2088 * 2089 * Return the required GTT alignment for an object, taking into account 2090 * potential fence register mapping. 2091 */ 2092 uint32_t 2093 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, 2094 int tiling_mode, bool fenced) 2095 { 2096 /* 2097 * Minimum alignment is 4k (GTT page size), but might be greater 2098 * if a fence register is needed for the object. 2099 */ 2100 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || 2101 tiling_mode == I915_TILING_NONE) 2102 return 4096; 2103 2104 /* 2105 * Previous chips need to be aligned to the size of the smallest 2106 * fence register that can contain the object. 2107 */ 2108 return i915_gem_get_gtt_size(dev, size, tiling_mode); 2109 } 2110 2111 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) 2112 { 2113 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2114 int ret; 2115 2116 #if 0 2117 if (drm_vma_node_has_offset(&obj->base.vma_node)) 2118 return 0; 2119 #endif 2120 2121 dev_priv->mm.shrinker_no_lock_stealing = true; 2122 2123 ret = drm_gem_create_mmap_offset(&obj->base); 2124 if (ret != -ENOSPC) 2125 goto out; 2126 2127 /* Badly fragmented mmap space? The only way we can recover 2128 * space is by destroying unwanted objects. We can't randomly release 2129 * mmap_offsets as userspace expects them to be persistent for the 2130 * lifetime of the objects. The closest we can is to release the 2131 * offsets on purgeable objects by truncating it and marking it purged, 2132 * which prevents userspace from ever using that object again. 2133 */ 2134 i915_gem_shrink(dev_priv, 2135 obj->base.size >> PAGE_SHIFT, 2136 I915_SHRINK_BOUND | 2137 I915_SHRINK_UNBOUND | 2138 I915_SHRINK_PURGEABLE); 2139 ret = drm_gem_create_mmap_offset(&obj->base); 2140 if (ret != -ENOSPC) 2141 goto out; 2142 2143 i915_gem_shrink_all(dev_priv); 2144 ret = drm_gem_create_mmap_offset(&obj->base); 2145 out: 2146 dev_priv->mm.shrinker_no_lock_stealing = false; 2147 2148 return ret; 2149 } 2150 2151 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) 2152 { 2153 drm_gem_free_mmap_offset(&obj->base); 2154 } 2155 2156 int 2157 i915_gem_mmap_gtt(struct drm_file *file, 2158 struct drm_device *dev, 2159 uint32_t handle, 2160 uint64_t *offset) 2161 { 2162 struct drm_i915_gem_object *obj; 2163 int ret; 2164 2165 ret = i915_mutex_lock_interruptible(dev); 2166 if (ret) 2167 return ret; 2168 2169 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); 2170 if (&obj->base == NULL) { 2171 ret = -ENOENT; 2172 goto unlock; 2173 } 2174 2175 if (obj->madv != I915_MADV_WILLNEED) { 2176 DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); 2177 ret = -EFAULT; 2178 goto out; 2179 } 2180 2181 ret = i915_gem_object_create_mmap_offset(obj); 2182 if (ret) 2183 goto out; 2184 2185 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) | 2186 DRM_GEM_MAPPING_KEY; 2187 2188 out: 2189 drm_gem_object_unreference(&obj->base); 2190 unlock: 2191 mutex_unlock(&dev->struct_mutex); 2192 return ret; 2193 } 2194 2195 /** 2196 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing 2197 * @dev: DRM device 2198 * @data: GTT mapping ioctl data 2199 * @file: GEM object info 2200 * 2201 * Simply returns the fake offset to userspace so it can mmap it. 2202 * The mmap call will end up in drm_gem_mmap(), which will set things 2203 * up so we can get faults in the handler above. 2204 * 2205 * The fault handler will take care of binding the object into the GTT 2206 * (since it may have been evicted to make room for something), allocating 2207 * a fence register, and mapping the appropriate aperture address into 2208 * userspace. 2209 */ 2210 int 2211 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 2212 struct drm_file *file) 2213 { 2214 struct drm_i915_gem_mmap_gtt *args = data; 2215 2216 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); 2217 } 2218 2219 /* Immediately discard the backing storage */ 2220 static void 2221 i915_gem_object_truncate(struct drm_i915_gem_object *obj) 2222 { 2223 vm_object_t vm_obj; 2224 2225 vm_obj = obj->base.vm_obj; 2226 VM_OBJECT_LOCK(vm_obj); 2227 vm_object_page_remove(vm_obj, 0, 0, false); 2228 VM_OBJECT_UNLOCK(vm_obj); 2229 2230 obj->madv = __I915_MADV_PURGED; 2231 } 2232 2233 /* Try to discard unwanted pages */ 2234 static void 2235 i915_gem_object_invalidate(struct drm_i915_gem_object *obj) 2236 { 2237 #if 0 2238 struct address_space *mapping; 2239 #endif 2240 2241 switch (obj->madv) { 2242 case I915_MADV_DONTNEED: 2243 i915_gem_object_truncate(obj); 2244 case __I915_MADV_PURGED: 2245 return; 2246 } 2247 2248 #if 0 2249 if (obj->base.filp == NULL) 2250 return; 2251 2252 mapping = file_inode(obj->base.filp)->i_mapping, 2253 invalidate_mapping_pages(mapping, 0, (loff_t)-1); 2254 #endif 2255 } 2256 2257 static void 2258 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) 2259 { 2260 struct sg_page_iter sg_iter; 2261 int ret; 2262 2263 BUG_ON(obj->madv == __I915_MADV_PURGED); 2264 2265 ret = i915_gem_object_set_to_cpu_domain(obj, true); 2266 if (ret) { 2267 /* In the event of a disaster, abandon all caches and 2268 * hope for the best. 2269 */ 2270 WARN_ON(ret != -EIO); 2271 i915_gem_clflush_object(obj, true); 2272 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; 2273 } 2274 2275 i915_gem_gtt_finish_object(obj); 2276 2277 if (i915_gem_object_needs_bit17_swizzle(obj)) 2278 i915_gem_object_save_bit_17_swizzle(obj); 2279 2280 if (obj->madv == I915_MADV_DONTNEED) 2281 obj->dirty = 0; 2282 2283 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { 2284 struct vm_page *page = sg_page_iter_page(&sg_iter); 2285 2286 if (obj->dirty) 2287 set_page_dirty(page); 2288 2289 if (obj->madv == I915_MADV_WILLNEED) 2290 mark_page_accessed(page); 2291 2292 vm_page_busy_wait(page, FALSE, "i915gem"); 2293 vm_page_unwire(page, 1); 2294 vm_page_wakeup(page); 2295 } 2296 obj->dirty = 0; 2297 2298 sg_free_table(obj->pages); 2299 kfree(obj->pages); 2300 } 2301 2302 int 2303 i915_gem_object_put_pages(struct drm_i915_gem_object *obj) 2304 { 2305 const struct drm_i915_gem_object_ops *ops = obj->ops; 2306 2307 if (obj->pages == NULL) 2308 return 0; 2309 2310 if (obj->pages_pin_count) 2311 return -EBUSY; 2312 2313 BUG_ON(i915_gem_obj_bound_any(obj)); 2314 2315 /* ->put_pages might need to allocate memory for the bit17 swizzle 2316 * array, hence protect them from being reaped by removing them from gtt 2317 * lists early. */ 2318 list_del(&obj->global_list); 2319 2320 ops->put_pages(obj); 2321 obj->pages = NULL; 2322 2323 i915_gem_object_invalidate(obj); 2324 2325 return 0; 2326 } 2327 2328 static int 2329 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) 2330 { 2331 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2332 int page_count, i; 2333 vm_object_t vm_obj; 2334 struct sg_table *st; 2335 struct scatterlist *sg; 2336 struct sg_page_iter sg_iter; 2337 struct vm_page *page; 2338 unsigned long last_pfn = 0; /* suppress gcc warning */ 2339 int ret; 2340 2341 /* Assert that the object is not currently in any GPU domain. As it 2342 * wasn't in the GTT, there shouldn't be any way it could have been in 2343 * a GPU cache 2344 */ 2345 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); 2346 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); 2347 2348 st = kmalloc(sizeof(*st), M_DRM, M_WAITOK); 2349 if (st == NULL) 2350 return -ENOMEM; 2351 2352 page_count = obj->base.size / PAGE_SIZE; 2353 if (sg_alloc_table(st, page_count, GFP_KERNEL)) { 2354 kfree(st); 2355 return -ENOMEM; 2356 } 2357 2358 /* Get the list of pages out of our struct file. They'll be pinned 2359 * at this point until we release them. 2360 * 2361 * Fail silently without starting the shrinker 2362 */ 2363 vm_obj = obj->base.vm_obj; 2364 VM_OBJECT_LOCK(vm_obj); 2365 sg = st->sgl; 2366 st->nents = 0; 2367 for (i = 0; i < page_count; i++) { 2368 page = shmem_read_mapping_page(vm_obj, i); 2369 if (IS_ERR(page)) { 2370 i915_gem_shrink(dev_priv, 2371 page_count, 2372 I915_SHRINK_BOUND | 2373 I915_SHRINK_UNBOUND | 2374 I915_SHRINK_PURGEABLE); 2375 page = shmem_read_mapping_page(vm_obj, i); 2376 } 2377 if (IS_ERR(page)) { 2378 /* We've tried hard to allocate the memory by reaping 2379 * our own buffer, now let the real VM do its job and 2380 * go down in flames if truly OOM. 2381 */ 2382 i915_gem_shrink_all(dev_priv); 2383 page = shmem_read_mapping_page(vm_obj, i); 2384 if (IS_ERR(page)) { 2385 ret = PTR_ERR(page); 2386 goto err_pages; 2387 } 2388 } 2389 #ifdef CONFIG_SWIOTLB 2390 if (swiotlb_nr_tbl()) { 2391 st->nents++; 2392 sg_set_page(sg, page, PAGE_SIZE, 0); 2393 sg = sg_next(sg); 2394 continue; 2395 } 2396 #endif 2397 if (!i || page_to_pfn(page) != last_pfn + 1) { 2398 if (i) 2399 sg = sg_next(sg); 2400 st->nents++; 2401 sg_set_page(sg, page, PAGE_SIZE, 0); 2402 } else { 2403 sg->length += PAGE_SIZE; 2404 } 2405 last_pfn = page_to_pfn(page); 2406 2407 /* Check that the i965g/gm workaround works. */ 2408 } 2409 #ifdef CONFIG_SWIOTLB 2410 if (!swiotlb_nr_tbl()) 2411 #endif 2412 sg_mark_end(sg); 2413 obj->pages = st; 2414 VM_OBJECT_UNLOCK(vm_obj); 2415 2416 ret = i915_gem_gtt_prepare_object(obj); 2417 if (ret) 2418 goto err_pages; 2419 2420 if (i915_gem_object_needs_bit17_swizzle(obj)) 2421 i915_gem_object_do_bit_17_swizzle(obj); 2422 2423 if (obj->tiling_mode != I915_TILING_NONE && 2424 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) 2425 i915_gem_object_pin_pages(obj); 2426 2427 return 0; 2428 2429 err_pages: 2430 sg_mark_end(sg); 2431 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 2432 page = sg_page_iter_page(&sg_iter); 2433 vm_page_busy_wait(page, FALSE, "i915gem"); 2434 vm_page_unwire(page, 0); 2435 vm_page_wakeup(page); 2436 } 2437 VM_OBJECT_UNLOCK(vm_obj); 2438 sg_free_table(st); 2439 kfree(st); 2440 2441 /* shmemfs first checks if there is enough memory to allocate the page 2442 * and reports ENOSPC should there be insufficient, along with the usual 2443 * ENOMEM for a genuine allocation failure. 2444 * 2445 * We use ENOSPC in our driver to mean that we have run out of aperture 2446 * space and so want to translate the error from shmemfs back to our 2447 * usual understanding of ENOMEM. 2448 */ 2449 if (ret == -ENOSPC) 2450 ret = -ENOMEM; 2451 2452 return ret; 2453 } 2454 2455 /* Ensure that the associated pages are gathered from the backing storage 2456 * and pinned into our object. i915_gem_object_get_pages() may be called 2457 * multiple times before they are released by a single call to 2458 * i915_gem_object_put_pages() - once the pages are no longer referenced 2459 * either as a result of memory pressure (reaping pages under the shrinker) 2460 * or as the object is itself released. 2461 */ 2462 int 2463 i915_gem_object_get_pages(struct drm_i915_gem_object *obj) 2464 { 2465 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2466 const struct drm_i915_gem_object_ops *ops = obj->ops; 2467 int ret; 2468 2469 if (obj->pages) 2470 return 0; 2471 2472 if (obj->madv != I915_MADV_WILLNEED) { 2473 DRM_DEBUG("Attempting to obtain a purgeable object\n"); 2474 return -EFAULT; 2475 } 2476 2477 BUG_ON(obj->pages_pin_count); 2478 2479 ret = ops->get_pages(obj); 2480 if (ret) 2481 return ret; 2482 2483 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); 2484 2485 obj->get_page.sg = obj->pages->sgl; 2486 obj->get_page.last = 0; 2487 2488 return 0; 2489 } 2490 2491 void i915_vma_move_to_active(struct i915_vma *vma, 2492 struct drm_i915_gem_request *req) 2493 { 2494 struct drm_i915_gem_object *obj = vma->obj; 2495 struct intel_engine_cs *ring; 2496 2497 ring = i915_gem_request_get_ring(req); 2498 2499 /* Add a reference if we're newly entering the active list. */ 2500 if (obj->active == 0) 2501 drm_gem_object_reference(&obj->base); 2502 obj->active |= intel_ring_flag(ring); 2503 2504 list_move_tail(&obj->ring_list[ring->id], &ring->active_list); 2505 i915_gem_request_assign(&obj->last_read_req[ring->id], req); 2506 2507 list_move_tail(&vma->mm_list, &vma->vm->active_list); 2508 } 2509 2510 static void 2511 i915_gem_object_retire__write(struct drm_i915_gem_object *obj) 2512 { 2513 RQ_BUG_ON(obj->last_write_req == NULL); 2514 RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring))); 2515 2516 i915_gem_request_assign(&obj->last_write_req, NULL); 2517 intel_fb_obj_flush(obj, true, ORIGIN_CS); 2518 } 2519 2520 static void 2521 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) 2522 { 2523 struct i915_vma *vma; 2524 2525 RQ_BUG_ON(obj->last_read_req[ring] == NULL); 2526 RQ_BUG_ON(!(obj->active & (1 << ring))); 2527 2528 list_del_init(&obj->ring_list[ring]); 2529 i915_gem_request_assign(&obj->last_read_req[ring], NULL); 2530 2531 if (obj->last_write_req && obj->last_write_req->ring->id == ring) 2532 i915_gem_object_retire__write(obj); 2533 2534 obj->active &= ~(1 << ring); 2535 if (obj->active) 2536 return; 2537 2538 /* Bump our place on the bound list to keep it roughly in LRU order 2539 * so that we don't steal from recently used but inactive objects 2540 * (unless we are forced to ofc!) 2541 */ 2542 list_move_tail(&obj->global_list, 2543 &to_i915(obj->base.dev)->mm.bound_list); 2544 2545 list_for_each_entry(vma, &obj->vma_list, vma_link) { 2546 if (!list_empty(&vma->mm_list)) 2547 list_move_tail(&vma->mm_list, &vma->vm->inactive_list); 2548 } 2549 2550 i915_gem_request_assign(&obj->last_fenced_req, NULL); 2551 drm_gem_object_unreference(&obj->base); 2552 } 2553 2554 static int 2555 i915_gem_init_seqno(struct drm_device *dev, u32 seqno) 2556 { 2557 struct drm_i915_private *dev_priv = dev->dev_private; 2558 struct intel_engine_cs *ring; 2559 int ret, i, j; 2560 2561 /* Carefully retire all requests without writing to the rings */ 2562 for_each_ring(ring, dev_priv, i) { 2563 ret = intel_ring_idle(ring); 2564 if (ret) 2565 return ret; 2566 } 2567 i915_gem_retire_requests(dev); 2568 2569 /* Finally reset hw state */ 2570 for_each_ring(ring, dev_priv, i) { 2571 intel_ring_init_seqno(ring, seqno); 2572 2573 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) 2574 ring->semaphore.sync_seqno[j] = 0; 2575 } 2576 2577 return 0; 2578 } 2579 2580 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) 2581 { 2582 struct drm_i915_private *dev_priv = dev->dev_private; 2583 int ret; 2584 2585 if (seqno == 0) 2586 return -EINVAL; 2587 2588 /* HWS page needs to be set less than what we 2589 * will inject to ring 2590 */ 2591 ret = i915_gem_init_seqno(dev, seqno - 1); 2592 if (ret) 2593 return ret; 2594 2595 /* Carefully set the last_seqno value so that wrap 2596 * detection still works 2597 */ 2598 dev_priv->next_seqno = seqno; 2599 dev_priv->last_seqno = seqno - 1; 2600 if (dev_priv->last_seqno == 0) 2601 dev_priv->last_seqno--; 2602 2603 return 0; 2604 } 2605 2606 int 2607 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) 2608 { 2609 struct drm_i915_private *dev_priv = dev->dev_private; 2610 2611 /* reserve 0 for non-seqno */ 2612 if (dev_priv->next_seqno == 0) { 2613 int ret = i915_gem_init_seqno(dev, 0); 2614 if (ret) 2615 return ret; 2616 2617 dev_priv->next_seqno = 1; 2618 } 2619 2620 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; 2621 return 0; 2622 } 2623 2624 /* 2625 * NB: This function is not allowed to fail. Doing so would mean the the 2626 * request is not being tracked for completion but the work itself is 2627 * going to happen on the hardware. This would be a Bad Thing(tm). 2628 */ 2629 void __i915_add_request(struct drm_i915_gem_request *request, 2630 struct drm_i915_gem_object *obj, 2631 bool flush_caches) 2632 { 2633 struct intel_engine_cs *ring; 2634 struct drm_i915_private *dev_priv; 2635 struct intel_ringbuffer *ringbuf; 2636 u32 request_start; 2637 int ret; 2638 2639 if (WARN_ON(request == NULL)) 2640 return; 2641 2642 ring = request->ring; 2643 dev_priv = ring->dev->dev_private; 2644 ringbuf = request->ringbuf; 2645 2646 /* 2647 * To ensure that this call will not fail, space for its emissions 2648 * should already have been reserved in the ring buffer. Let the ring 2649 * know that it is time to use that space up. 2650 */ 2651 intel_ring_reserved_space_use(ringbuf); 2652 2653 request_start = intel_ring_get_tail(ringbuf); 2654 /* 2655 * Emit any outstanding flushes - execbuf can fail to emit the flush 2656 * after having emitted the batchbuffer command. Hence we need to fix 2657 * things up similar to emitting the lazy request. The difference here 2658 * is that the flush _must_ happen before the next request, no matter 2659 * what. 2660 */ 2661 if (flush_caches) { 2662 if (i915.enable_execlists) 2663 ret = logical_ring_flush_all_caches(request); 2664 else 2665 ret = intel_ring_flush_all_caches(request); 2666 /* Not allowed to fail! */ 2667 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); 2668 } 2669 2670 /* Record the position of the start of the request so that 2671 * should we detect the updated seqno part-way through the 2672 * GPU processing the request, we never over-estimate the 2673 * position of the head. 2674 */ 2675 request->postfix = intel_ring_get_tail(ringbuf); 2676 2677 if (i915.enable_execlists) 2678 ret = ring->emit_request(request); 2679 else { 2680 ret = ring->add_request(request); 2681 2682 request->tail = intel_ring_get_tail(ringbuf); 2683 } 2684 2685 /* Not allowed to fail! */ 2686 WARN(ret, "emit|add_request failed: %d!\n", ret); 2687 2688 request->head = request_start; 2689 2690 /* Whilst this request exists, batch_obj will be on the 2691 * active_list, and so will hold the active reference. Only when this 2692 * request is retired will the the batch_obj be moved onto the 2693 * inactive_list and lose its active reference. Hence we do not need 2694 * to explicitly hold another reference here. 2695 */ 2696 request->batch_obj = obj; 2697 2698 request->emitted_jiffies = jiffies; 2699 ring->last_submitted_seqno = request->seqno; 2700 list_add_tail(&request->list, &ring->request_list); 2701 2702 trace_i915_gem_request_add(request); 2703 2704 i915_queue_hangcheck(ring->dev); 2705 2706 queue_delayed_work(dev_priv->wq, 2707 &dev_priv->mm.retire_work, 2708 round_jiffies_up_relative(HZ)); 2709 intel_mark_busy(dev_priv->dev); 2710 2711 /* Sanity check that the reserved size was large enough. */ 2712 intel_ring_reserved_space_end(ringbuf); 2713 } 2714 2715 static bool i915_context_is_banned(struct drm_i915_private *dev_priv, 2716 const struct intel_context *ctx) 2717 { 2718 unsigned long elapsed; 2719 2720 elapsed = get_seconds() - ctx->hang_stats.guilty_ts; 2721 2722 if (ctx->hang_stats.banned) 2723 return true; 2724 2725 if (ctx->hang_stats.ban_period_seconds && 2726 elapsed <= ctx->hang_stats.ban_period_seconds) { 2727 if (!i915_gem_context_is_default(ctx)) { 2728 DRM_DEBUG("context hanging too fast, banning!\n"); 2729 return true; 2730 } else if (i915_stop_ring_allow_ban(dev_priv)) { 2731 if (i915_stop_ring_allow_warn(dev_priv)) 2732 DRM_ERROR("gpu hanging too fast, banning!\n"); 2733 return true; 2734 } 2735 } 2736 2737 return false; 2738 } 2739 2740 static void i915_set_reset_status(struct drm_i915_private *dev_priv, 2741 struct intel_context *ctx, 2742 const bool guilty) 2743 { 2744 struct i915_ctx_hang_stats *hs; 2745 2746 if (WARN_ON(!ctx)) 2747 return; 2748 2749 hs = &ctx->hang_stats; 2750 2751 if (guilty) { 2752 hs->banned = i915_context_is_banned(dev_priv, ctx); 2753 hs->batch_active++; 2754 hs->guilty_ts = get_seconds(); 2755 } else { 2756 hs->batch_pending++; 2757 } 2758 } 2759 2760 void i915_gem_request_free(struct kref *req_ref) 2761 { 2762 struct drm_i915_gem_request *req = container_of(req_ref, 2763 typeof(*req), ref); 2764 struct intel_context *ctx = req->ctx; 2765 2766 if (req->file_priv) 2767 i915_gem_request_remove_from_client(req); 2768 2769 if (ctx) { 2770 if (i915.enable_execlists) { 2771 if (ctx != req->ring->default_context) 2772 intel_lr_context_unpin(req); 2773 } 2774 2775 i915_gem_context_unreference(ctx); 2776 } 2777 2778 kfree(req); 2779 } 2780 2781 int i915_gem_request_alloc(struct intel_engine_cs *ring, 2782 struct intel_context *ctx, 2783 struct drm_i915_gem_request **req_out) 2784 { 2785 struct drm_i915_private *dev_priv = to_i915(ring->dev); 2786 struct drm_i915_gem_request *req; 2787 int ret; 2788 2789 if (!req_out) 2790 return -EINVAL; 2791 2792 *req_out = NULL; 2793 2794 req = kzalloc(sizeof(*req), GFP_KERNEL); 2795 if (req == NULL) 2796 return -ENOMEM; 2797 2798 ret = i915_gem_get_seqno(ring->dev, &req->seqno); 2799 if (ret) 2800 goto err; 2801 2802 kref_init(&req->ref); 2803 req->i915 = dev_priv; 2804 req->ring = ring; 2805 req->ctx = ctx; 2806 i915_gem_context_reference(req->ctx); 2807 2808 if (i915.enable_execlists) 2809 ret = intel_logical_ring_alloc_request_extras(req); 2810 else 2811 ret = intel_ring_alloc_request_extras(req); 2812 if (ret) { 2813 i915_gem_context_unreference(req->ctx); 2814 goto err; 2815 } 2816 2817 /* 2818 * Reserve space in the ring buffer for all the commands required to 2819 * eventually emit this request. This is to guarantee that the 2820 * i915_add_request() call can't fail. Note that the reserve may need 2821 * to be redone if the request is not actually submitted straight 2822 * away, e.g. because a GPU scheduler has deferred it. 2823 */ 2824 if (i915.enable_execlists) 2825 ret = intel_logical_ring_reserve_space(req); 2826 else 2827 ret = intel_ring_reserve_space(req); 2828 if (ret) { 2829 /* 2830 * At this point, the request is fully allocated even if not 2831 * fully prepared. Thus it can be cleaned up using the proper 2832 * free code. 2833 */ 2834 i915_gem_request_cancel(req); 2835 return ret; 2836 } 2837 2838 *req_out = req; 2839 return 0; 2840 2841 err: 2842 kfree(req); 2843 return ret; 2844 } 2845 2846 void i915_gem_request_cancel(struct drm_i915_gem_request *req) 2847 { 2848 intel_ring_reserved_space_cancel(req->ringbuf); 2849 2850 i915_gem_request_unreference(req); 2851 } 2852 2853 struct drm_i915_gem_request * 2854 i915_gem_find_active_request(struct intel_engine_cs *ring) 2855 { 2856 struct drm_i915_gem_request *request; 2857 2858 list_for_each_entry(request, &ring->request_list, list) { 2859 if (i915_gem_request_completed(request, false)) 2860 continue; 2861 2862 return request; 2863 } 2864 2865 return NULL; 2866 } 2867 2868 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, 2869 struct intel_engine_cs *ring) 2870 { 2871 struct drm_i915_gem_request *request; 2872 bool ring_hung; 2873 2874 request = i915_gem_find_active_request(ring); 2875 2876 if (request == NULL) 2877 return; 2878 2879 ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; 2880 2881 i915_set_reset_status(dev_priv, request->ctx, ring_hung); 2882 2883 list_for_each_entry_continue(request, &ring->request_list, list) 2884 i915_set_reset_status(dev_priv, request->ctx, false); 2885 } 2886 2887 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, 2888 struct intel_engine_cs *ring) 2889 { 2890 while (!list_empty(&ring->active_list)) { 2891 struct drm_i915_gem_object *obj; 2892 2893 obj = list_first_entry(&ring->active_list, 2894 struct drm_i915_gem_object, 2895 ring_list[ring->id]); 2896 2897 i915_gem_object_retire__read(obj, ring->id); 2898 } 2899 2900 /* 2901 * Clear the execlists queue up before freeing the requests, as those 2902 * are the ones that keep the context and ringbuffer backing objects 2903 * pinned in place. 2904 */ 2905 while (!list_empty(&ring->execlist_queue)) { 2906 struct drm_i915_gem_request *submit_req; 2907 2908 submit_req = list_first_entry(&ring->execlist_queue, 2909 struct drm_i915_gem_request, 2910 execlist_link); 2911 list_del(&submit_req->execlist_link); 2912 2913 if (submit_req->ctx != ring->default_context) 2914 intel_lr_context_unpin(submit_req); 2915 2916 i915_gem_request_unreference(submit_req); 2917 } 2918 2919 /* 2920 * We must free the requests after all the corresponding objects have 2921 * been moved off active lists. Which is the same order as the normal 2922 * retire_requests function does. This is important if object hold 2923 * implicit references on things like e.g. ppgtt address spaces through 2924 * the request. 2925 */ 2926 while (!list_empty(&ring->request_list)) { 2927 struct drm_i915_gem_request *request; 2928 2929 request = list_first_entry(&ring->request_list, 2930 struct drm_i915_gem_request, 2931 list); 2932 2933 i915_gem_request_retire(request); 2934 } 2935 } 2936 2937 void i915_gem_reset(struct drm_device *dev) 2938 { 2939 struct drm_i915_private *dev_priv = dev->dev_private; 2940 struct intel_engine_cs *ring; 2941 int i; 2942 2943 /* 2944 * Before we free the objects from the requests, we need to inspect 2945 * them for finding the guilty party. As the requests only borrow 2946 * their reference to the objects, the inspection must be done first. 2947 */ 2948 for_each_ring(ring, dev_priv, i) 2949 i915_gem_reset_ring_status(dev_priv, ring); 2950 2951 for_each_ring(ring, dev_priv, i) 2952 i915_gem_reset_ring_cleanup(dev_priv, ring); 2953 2954 i915_gem_context_reset(dev); 2955 2956 i915_gem_restore_fences(dev); 2957 2958 WARN_ON(i915_verify_lists(dev)); 2959 } 2960 2961 /** 2962 * This function clears the request list as sequence numbers are passed. 2963 */ 2964 void 2965 i915_gem_retire_requests_ring(struct intel_engine_cs *ring) 2966 { 2967 WARN_ON(i915_verify_lists(ring->dev)); 2968 2969 /* Retire requests first as we use it above for the early return. 2970 * If we retire requests last, we may use a later seqno and so clear 2971 * the requests lists without clearing the active list, leading to 2972 * confusion. 2973 */ 2974 while (!list_empty(&ring->request_list)) { 2975 struct drm_i915_gem_request *request; 2976 2977 request = list_first_entry(&ring->request_list, 2978 struct drm_i915_gem_request, 2979 list); 2980 2981 if (!i915_gem_request_completed(request, true)) 2982 break; 2983 2984 i915_gem_request_retire(request); 2985 } 2986 2987 /* Move any buffers on the active list that are no longer referenced 2988 * by the ringbuffer to the flushing/inactive lists as appropriate, 2989 * before we free the context associated with the requests. 2990 */ 2991 while (!list_empty(&ring->active_list)) { 2992 struct drm_i915_gem_object *obj; 2993 2994 obj = list_first_entry(&ring->active_list, 2995 struct drm_i915_gem_object, 2996 ring_list[ring->id]); 2997 2998 if (!list_empty(&obj->last_read_req[ring->id]->list)) 2999 break; 3000 3001 i915_gem_object_retire__read(obj, ring->id); 3002 } 3003 3004 if (unlikely(ring->trace_irq_req && 3005 i915_gem_request_completed(ring->trace_irq_req, true))) { 3006 ring->irq_put(ring); 3007 i915_gem_request_assign(&ring->trace_irq_req, NULL); 3008 } 3009 3010 WARN_ON(i915_verify_lists(ring->dev)); 3011 } 3012 3013 bool 3014 i915_gem_retire_requests(struct drm_device *dev) 3015 { 3016 struct drm_i915_private *dev_priv = dev->dev_private; 3017 struct intel_engine_cs *ring; 3018 bool idle = true; 3019 int i; 3020 3021 for_each_ring(ring, dev_priv, i) { 3022 i915_gem_retire_requests_ring(ring); 3023 idle &= list_empty(&ring->request_list); 3024 if (i915.enable_execlists) { 3025 unsigned long flags; 3026 3027 spin_lock_irqsave(&ring->execlist_lock, flags); 3028 idle &= list_empty(&ring->execlist_queue); 3029 spin_unlock_irqrestore(&ring->execlist_lock, flags); 3030 3031 intel_execlists_retire_requests(ring); 3032 } 3033 } 3034 3035 if (idle) 3036 mod_delayed_work(dev_priv->wq, 3037 &dev_priv->mm.idle_work, 3038 msecs_to_jiffies(100)); 3039 3040 return idle; 3041 } 3042 3043 static void 3044 i915_gem_retire_work_handler(struct work_struct *work) 3045 { 3046 struct drm_i915_private *dev_priv = 3047 container_of(work, typeof(*dev_priv), mm.retire_work.work); 3048 struct drm_device *dev = dev_priv->dev; 3049 bool idle; 3050 3051 /* Come back later if the device is busy... */ 3052 idle = false; 3053 if (mutex_trylock(&dev->struct_mutex)) { 3054 idle = i915_gem_retire_requests(dev); 3055 mutex_unlock(&dev->struct_mutex); 3056 } 3057 if (!idle) 3058 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 3059 round_jiffies_up_relative(HZ)); 3060 } 3061 3062 static void 3063 i915_gem_idle_work_handler(struct work_struct *work) 3064 { 3065 struct drm_i915_private *dev_priv = 3066 container_of(work, typeof(*dev_priv), mm.idle_work.work); 3067 struct drm_device *dev = dev_priv->dev; 3068 struct intel_engine_cs *ring; 3069 int i; 3070 3071 for_each_ring(ring, dev_priv, i) 3072 if (!list_empty(&ring->request_list)) 3073 return; 3074 3075 intel_mark_idle(dev); 3076 3077 if (mutex_trylock(&dev->struct_mutex)) { 3078 struct intel_engine_cs *ring; 3079 int i; 3080 3081 for_each_ring(ring, dev_priv, i) 3082 i915_gem_batch_pool_fini(&ring->batch_pool); 3083 3084 mutex_unlock(&dev->struct_mutex); 3085 } 3086 } 3087 3088 /** 3089 * Ensures that an object will eventually get non-busy by flushing any required 3090 * write domains, emitting any outstanding lazy request and retiring and 3091 * completed requests. 3092 */ 3093 static int 3094 i915_gem_object_flush_active(struct drm_i915_gem_object *obj) 3095 { 3096 int i; 3097 3098 if (!obj->active) 3099 return 0; 3100 3101 for (i = 0; i < I915_NUM_RINGS; i++) { 3102 struct drm_i915_gem_request *req; 3103 3104 req = obj->last_read_req[i]; 3105 if (req == NULL) 3106 continue; 3107 3108 if (list_empty(&req->list)) 3109 goto retire; 3110 3111 if (i915_gem_request_completed(req, true)) { 3112 __i915_gem_request_retire__upto(req); 3113 retire: 3114 i915_gem_object_retire__read(obj, i); 3115 } 3116 } 3117 3118 return 0; 3119 } 3120 3121 /** 3122 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT 3123 * @DRM_IOCTL_ARGS: standard ioctl arguments 3124 * 3125 * Returns 0 if successful, else an error is returned with the remaining time in 3126 * the timeout parameter. 3127 * -ETIME: object is still busy after timeout 3128 * -ERESTARTSYS: signal interrupted the wait 3129 * -ENONENT: object doesn't exist 3130 * Also possible, but rare: 3131 * -EAGAIN: GPU wedged 3132 * -ENOMEM: damn 3133 * -ENODEV: Internal IRQ fail 3134 * -E?: The add request failed 3135 * 3136 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any 3137 * non-zero timeout parameter the wait ioctl will wait for the given number of 3138 * nanoseconds on an object becoming unbusy. Since the wait itself does so 3139 * without holding struct_mutex the object may become re-busied before this 3140 * function completes. A similar but shorter * race condition exists in the busy 3141 * ioctl 3142 */ 3143 int 3144 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) 3145 { 3146 struct drm_i915_private *dev_priv = dev->dev_private; 3147 struct drm_i915_gem_wait *args = data; 3148 struct drm_i915_gem_object *obj; 3149 struct drm_i915_gem_request *req[I915_NUM_RINGS]; 3150 unsigned reset_counter; 3151 int i, n = 0; 3152 int ret; 3153 3154 if (args->flags != 0) 3155 return -EINVAL; 3156 3157 ret = i915_mutex_lock_interruptible(dev); 3158 if (ret) 3159 return ret; 3160 3161 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); 3162 if (&obj->base == NULL) { 3163 mutex_unlock(&dev->struct_mutex); 3164 return -ENOENT; 3165 } 3166 3167 /* Need to make sure the object gets inactive eventually. */ 3168 ret = i915_gem_object_flush_active(obj); 3169 if (ret) 3170 goto out; 3171 3172 if (!obj->active) 3173 goto out; 3174 3175 /* Do this after OLR check to make sure we make forward progress polling 3176 * on this IOCTL with a timeout == 0 (like busy ioctl) 3177 */ 3178 if (args->timeout_ns == 0) { 3179 ret = -ETIME; 3180 goto out; 3181 } 3182 3183 drm_gem_object_unreference(&obj->base); 3184 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); 3185 3186 for (i = 0; i < I915_NUM_RINGS; i++) { 3187 if (obj->last_read_req[i] == NULL) 3188 continue; 3189 3190 req[n++] = i915_gem_request_reference(obj->last_read_req[i]); 3191 } 3192 3193 mutex_unlock(&dev->struct_mutex); 3194 3195 for (i = 0; i < n; i++) { 3196 if (ret == 0) 3197 ret = __i915_wait_request(req[i], reset_counter, true, 3198 args->timeout_ns > 0 ? &args->timeout_ns : NULL, 3199 file->driver_priv); 3200 i915_gem_request_unreference__unlocked(req[i]); 3201 } 3202 return ret; 3203 3204 out: 3205 drm_gem_object_unreference(&obj->base); 3206 mutex_unlock(&dev->struct_mutex); 3207 return ret; 3208 } 3209 3210 static int 3211 __i915_gem_object_sync(struct drm_i915_gem_object *obj, 3212 struct intel_engine_cs *to, 3213 struct drm_i915_gem_request *from_req, 3214 struct drm_i915_gem_request **to_req) 3215 { 3216 struct intel_engine_cs *from; 3217 int ret; 3218 3219 from = i915_gem_request_get_ring(from_req); 3220 if (to == from) 3221 return 0; 3222 3223 if (i915_gem_request_completed(from_req, true)) 3224 return 0; 3225 3226 if (!i915_semaphore_is_enabled(obj->base.dev)) { 3227 struct drm_i915_private *i915 = to_i915(obj->base.dev); 3228 ret = __i915_wait_request(from_req, 3229 atomic_read(&i915->gpu_error.reset_counter), 3230 i915->mm.interruptible, 3231 NULL, 3232 &i915->rps.semaphores); 3233 if (ret) 3234 return ret; 3235 3236 i915_gem_object_retire_request(obj, from_req); 3237 } else { 3238 int idx = intel_ring_sync_index(from, to); 3239 u32 seqno = i915_gem_request_get_seqno(from_req); 3240 3241 WARN_ON(!to_req); 3242 3243 if (seqno <= from->semaphore.sync_seqno[idx]) 3244 return 0; 3245 3246 if (*to_req == NULL) { 3247 ret = i915_gem_request_alloc(to, to->default_context, to_req); 3248 if (ret) 3249 return ret; 3250 } 3251 3252 trace_i915_gem_ring_sync_to(*to_req, from, from_req); 3253 ret = to->semaphore.sync_to(*to_req, from, seqno); 3254 if (ret) 3255 return ret; 3256 3257 /* We use last_read_req because sync_to() 3258 * might have just caused seqno wrap under 3259 * the radar. 3260 */ 3261 from->semaphore.sync_seqno[idx] = 3262 i915_gem_request_get_seqno(obj->last_read_req[from->id]); 3263 } 3264 3265 return 0; 3266 } 3267 3268 /** 3269 * i915_gem_object_sync - sync an object to a ring. 3270 * 3271 * @obj: object which may be in use on another ring. 3272 * @to: ring we wish to use the object on. May be NULL. 3273 * @to_req: request we wish to use the object for. See below. 3274 * This will be allocated and returned if a request is 3275 * required but not passed in. 3276 * 3277 * This code is meant to abstract object synchronization with the GPU. 3278 * Calling with NULL implies synchronizing the object with the CPU 3279 * rather than a particular GPU ring. Conceptually we serialise writes 3280 * between engines inside the GPU. We only allow one engine to write 3281 * into a buffer at any time, but multiple readers. To ensure each has 3282 * a coherent view of memory, we must: 3283 * 3284 * - If there is an outstanding write request to the object, the new 3285 * request must wait for it to complete (either CPU or in hw, requests 3286 * on the same ring will be naturally ordered). 3287 * 3288 * - If we are a write request (pending_write_domain is set), the new 3289 * request must wait for outstanding read requests to complete. 3290 * 3291 * For CPU synchronisation (NULL to) no request is required. For syncing with 3292 * rings to_req must be non-NULL. However, a request does not have to be 3293 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a 3294 * request will be allocated automatically and returned through *to_req. Note 3295 * that it is not guaranteed that commands will be emitted (because the system 3296 * might already be idle). Hence there is no need to create a request that 3297 * might never have any work submitted. Note further that if a request is 3298 * returned in *to_req, it is the responsibility of the caller to submit 3299 * that request (after potentially adding more work to it). 3300 * 3301 * Returns 0 if successful, else propagates up the lower layer error. 3302 */ 3303 int 3304 i915_gem_object_sync(struct drm_i915_gem_object *obj, 3305 struct intel_engine_cs *to, 3306 struct drm_i915_gem_request **to_req) 3307 { 3308 const bool readonly = obj->base.pending_write_domain == 0; 3309 struct drm_i915_gem_request *req[I915_NUM_RINGS]; 3310 int ret, i, n; 3311 3312 if (!obj->active) 3313 return 0; 3314 3315 if (to == NULL) 3316 return i915_gem_object_wait_rendering(obj, readonly); 3317 3318 n = 0; 3319 if (readonly) { 3320 if (obj->last_write_req) 3321 req[n++] = obj->last_write_req; 3322 } else { 3323 for (i = 0; i < I915_NUM_RINGS; i++) 3324 if (obj->last_read_req[i]) 3325 req[n++] = obj->last_read_req[i]; 3326 } 3327 for (i = 0; i < n; i++) { 3328 ret = __i915_gem_object_sync(obj, to, req[i], to_req); 3329 if (ret) 3330 return ret; 3331 } 3332 3333 return 0; 3334 } 3335 3336 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) 3337 { 3338 u32 old_write_domain, old_read_domains; 3339 3340 /* Force a pagefault for domain tracking on next user access */ 3341 i915_gem_release_mmap(obj); 3342 3343 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) 3344 return; 3345 3346 /* Wait for any direct GTT access to complete */ 3347 mb(); 3348 3349 old_read_domains = obj->base.read_domains; 3350 old_write_domain = obj->base.write_domain; 3351 3352 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; 3353 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; 3354 3355 trace_i915_gem_object_change_domain(obj, 3356 old_read_domains, 3357 old_write_domain); 3358 } 3359 3360 int i915_vma_unbind(struct i915_vma *vma) 3361 { 3362 struct drm_i915_gem_object *obj = vma->obj; 3363 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 3364 int ret; 3365 3366 if (list_empty(&vma->vma_link)) 3367 return 0; 3368 3369 if (!drm_mm_node_allocated(&vma->node)) { 3370 i915_gem_vma_destroy(vma); 3371 return 0; 3372 } 3373 3374 if (vma->pin_count) 3375 return -EBUSY; 3376 3377 BUG_ON(obj->pages == NULL); 3378 3379 ret = i915_gem_object_wait_rendering(obj, false); 3380 if (ret) 3381 return ret; 3382 /* Continue on if we fail due to EIO, the GPU is hung so we 3383 * should be safe and we need to cleanup or else we might 3384 * cause memory corruption through use-after-free. 3385 */ 3386 3387 if (i915_is_ggtt(vma->vm) && 3388 vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { 3389 i915_gem_object_finish_gtt(obj); 3390 3391 /* release the fence reg _after_ flushing */ 3392 ret = i915_gem_object_put_fence(obj); 3393 if (ret) 3394 return ret; 3395 } 3396 3397 trace_i915_vma_unbind(vma); 3398 3399 vma->vm->unbind_vma(vma); 3400 vma->bound = 0; 3401 3402 list_del_init(&vma->mm_list); 3403 if (i915_is_ggtt(vma->vm)) { 3404 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { 3405 obj->map_and_fenceable = false; 3406 } else if (vma->ggtt_view.pages) { 3407 sg_free_table(vma->ggtt_view.pages); 3408 kfree(vma->ggtt_view.pages); 3409 } 3410 vma->ggtt_view.pages = NULL; 3411 } 3412 3413 drm_mm_remove_node(&vma->node); 3414 i915_gem_vma_destroy(vma); 3415 3416 /* Since the unbound list is global, only move to that list if 3417 * no more VMAs exist. */ 3418 if (list_empty(&obj->vma_list)) 3419 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); 3420 3421 /* And finally now the object is completely decoupled from this vma, 3422 * we can drop its hold on the backing storage and allow it to be 3423 * reaped by the shrinker. 3424 */ 3425 i915_gem_object_unpin_pages(obj); 3426 3427 return 0; 3428 } 3429 3430 int i915_gpu_idle(struct drm_device *dev) 3431 { 3432 struct drm_i915_private *dev_priv = dev->dev_private; 3433 struct intel_engine_cs *ring; 3434 int ret, i; 3435 3436 /* Flush everything onto the inactive list. */ 3437 for_each_ring(ring, dev_priv, i) { 3438 if (!i915.enable_execlists) { 3439 struct drm_i915_gem_request *req; 3440 3441 ret = i915_gem_request_alloc(ring, ring->default_context, &req); 3442 if (ret) 3443 return ret; 3444 3445 ret = i915_switch_context(req); 3446 if (ret) { 3447 i915_gem_request_cancel(req); 3448 return ret; 3449 } 3450 3451 i915_add_request_no_flush(req); 3452 } 3453 3454 ret = intel_ring_idle(ring); 3455 if (ret) 3456 return ret; 3457 } 3458 3459 WARN_ON(i915_verify_lists(dev)); 3460 return 0; 3461 } 3462 3463 static bool i915_gem_valid_gtt_space(struct i915_vma *vma, 3464 unsigned long cache_level) 3465 { 3466 struct drm_mm_node *gtt_space = &vma->node; 3467 struct drm_mm_node *other; 3468 3469 /* 3470 * On some machines we have to be careful when putting differing types 3471 * of snoopable memory together to avoid the prefetcher crossing memory 3472 * domains and dying. During vm initialisation, we decide whether or not 3473 * these constraints apply and set the drm_mm.color_adjust 3474 * appropriately. 3475 */ 3476 if (vma->vm->mm.color_adjust == NULL) 3477 return true; 3478 3479 if (!drm_mm_node_allocated(gtt_space)) 3480 return true; 3481 3482 if (list_empty(>t_space->node_list)) 3483 return true; 3484 3485 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); 3486 if (other->allocated && !other->hole_follows && other->color != cache_level) 3487 return false; 3488 3489 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); 3490 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) 3491 return false; 3492 3493 return true; 3494 } 3495 3496 /** 3497 * Finds free space in the GTT aperture and binds the object or a view of it 3498 * there. 3499 */ 3500 static struct i915_vma * 3501 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, 3502 struct i915_address_space *vm, 3503 const struct i915_ggtt_view *ggtt_view, 3504 unsigned alignment, 3505 uint64_t flags) 3506 { 3507 struct drm_device *dev = obj->base.dev; 3508 struct drm_i915_private *dev_priv = dev->dev_private; 3509 u32 size, fence_size, fence_alignment, unfenced_alignment; 3510 u64 start = 3511 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; 3512 u64 end = 3513 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; 3514 struct i915_vma *vma; 3515 int ret; 3516 3517 if (i915_is_ggtt(vm)) { 3518 u32 view_size; 3519 3520 if (WARN_ON(!ggtt_view)) 3521 return ERR_PTR(-EINVAL); 3522 3523 view_size = i915_ggtt_view_size(obj, ggtt_view); 3524 3525 fence_size = i915_gem_get_gtt_size(dev, 3526 view_size, 3527 obj->tiling_mode); 3528 fence_alignment = i915_gem_get_gtt_alignment(dev, 3529 view_size, 3530 obj->tiling_mode, 3531 true); 3532 unfenced_alignment = i915_gem_get_gtt_alignment(dev, 3533 view_size, 3534 obj->tiling_mode, 3535 false); 3536 size = flags & PIN_MAPPABLE ? fence_size : view_size; 3537 } else { 3538 fence_size = i915_gem_get_gtt_size(dev, 3539 obj->base.size, 3540 obj->tiling_mode); 3541 fence_alignment = i915_gem_get_gtt_alignment(dev, 3542 obj->base.size, 3543 obj->tiling_mode, 3544 true); 3545 unfenced_alignment = 3546 i915_gem_get_gtt_alignment(dev, 3547 obj->base.size, 3548 obj->tiling_mode, 3549 false); 3550 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; 3551 } 3552 3553 if (alignment == 0) 3554 alignment = flags & PIN_MAPPABLE ? fence_alignment : 3555 unfenced_alignment; 3556 if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { 3557 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", 3558 ggtt_view ? ggtt_view->type : 0, 3559 alignment); 3560 return ERR_PTR(-EINVAL); 3561 } 3562 3563 /* If binding the object/GGTT view requires more space than the entire 3564 * aperture has, reject it early before evicting everything in a vain 3565 * attempt to find space. 3566 */ 3567 if (size > end) { 3568 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n", 3569 ggtt_view ? ggtt_view->type : 0, 3570 size, 3571 flags & PIN_MAPPABLE ? "mappable" : "total", 3572 end); 3573 return ERR_PTR(-E2BIG); 3574 } 3575 3576 ret = i915_gem_object_get_pages(obj); 3577 if (ret) 3578 return ERR_PTR(ret); 3579 3580 i915_gem_object_pin_pages(obj); 3581 3582 vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : 3583 i915_gem_obj_lookup_or_create_vma(obj, vm); 3584 3585 if (IS_ERR(vma)) 3586 goto err_unpin; 3587 3588 search_free: 3589 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, 3590 size, alignment, 3591 obj->cache_level, 3592 start, end, 3593 DRM_MM_SEARCH_DEFAULT, 3594 DRM_MM_CREATE_DEFAULT); 3595 if (ret) { 3596 ret = i915_gem_evict_something(dev, vm, size, alignment, 3597 obj->cache_level, 3598 start, end, 3599 flags); 3600 if (ret == 0) 3601 goto search_free; 3602 3603 goto err_free_vma; 3604 } 3605 if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { 3606 ret = -EINVAL; 3607 goto err_remove_node; 3608 } 3609 3610 trace_i915_vma_bind(vma, flags); 3611 ret = i915_vma_bind(vma, obj->cache_level, flags); 3612 if (ret) 3613 goto err_remove_node; 3614 3615 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); 3616 list_add_tail(&vma->mm_list, &vm->inactive_list); 3617 3618 return vma; 3619 3620 err_remove_node: 3621 drm_mm_remove_node(&vma->node); 3622 err_free_vma: 3623 i915_gem_vma_destroy(vma); 3624 vma = ERR_PTR(ret); 3625 err_unpin: 3626 i915_gem_object_unpin_pages(obj); 3627 return vma; 3628 } 3629 3630 bool 3631 i915_gem_clflush_object(struct drm_i915_gem_object *obj, 3632 bool force) 3633 { 3634 /* If we don't have a page list set up, then we're not pinned 3635 * to GPU, and we can ignore the cache flush because it'll happen 3636 * again at bind time. 3637 */ 3638 if (obj->pages == NULL) 3639 return false; 3640 3641 /* 3642 * Stolen memory is always coherent with the GPU as it is explicitly 3643 * marked as wc by the system, or the system is cache-coherent. 3644 */ 3645 if (obj->stolen || obj->phys_handle) 3646 return false; 3647 3648 /* If the GPU is snooping the contents of the CPU cache, 3649 * we do not need to manually clear the CPU cache lines. However, 3650 * the caches are only snooped when the render cache is 3651 * flushed/invalidated. As we always have to emit invalidations 3652 * and flushes when moving into and out of the RENDER domain, correct 3653 * snooping behaviour occurs naturally as the result of our domain 3654 * tracking. 3655 */ 3656 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { 3657 obj->cache_dirty = true; 3658 return false; 3659 } 3660 3661 trace_i915_gem_object_clflush(obj); 3662 drm_clflush_sg(obj->pages); 3663 obj->cache_dirty = false; 3664 3665 return true; 3666 } 3667 3668 /** Flushes the GTT write domain for the object if it's dirty. */ 3669 static void 3670 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) 3671 { 3672 uint32_t old_write_domain; 3673 3674 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) 3675 return; 3676 3677 /* No actual flushing is required for the GTT write domain. Writes 3678 * to it immediately go to main memory as far as we know, so there's 3679 * no chipset flush. It also doesn't land in render cache. 3680 * 3681 * However, we do have to enforce the order so that all writes through 3682 * the GTT land before any writes to the device, such as updates to 3683 * the GATT itself. 3684 */ 3685 wmb(); 3686 3687 old_write_domain = obj->base.write_domain; 3688 obj->base.write_domain = 0; 3689 3690 intel_fb_obj_flush(obj, false, ORIGIN_GTT); 3691 3692 trace_i915_gem_object_change_domain(obj, 3693 obj->base.read_domains, 3694 old_write_domain); 3695 } 3696 3697 /** Flushes the CPU write domain for the object if it's dirty. */ 3698 static void 3699 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) 3700 { 3701 uint32_t old_write_domain; 3702 3703 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) 3704 return; 3705 3706 if (i915_gem_clflush_object(obj, obj->pin_display)) 3707 i915_gem_chipset_flush(obj->base.dev); 3708 3709 old_write_domain = obj->base.write_domain; 3710 obj->base.write_domain = 0; 3711 3712 intel_fb_obj_flush(obj, false, ORIGIN_CPU); 3713 3714 trace_i915_gem_object_change_domain(obj, 3715 obj->base.read_domains, 3716 old_write_domain); 3717 } 3718 3719 /** 3720 * Moves a single object to the GTT read, and possibly write domain. 3721 * 3722 * This function returns when the move is complete, including waiting on 3723 * flushes to occur. 3724 */ 3725 int 3726 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) 3727 { 3728 uint32_t old_write_domain, old_read_domains; 3729 struct i915_vma *vma; 3730 int ret; 3731 3732 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) 3733 return 0; 3734 3735 ret = i915_gem_object_wait_rendering(obj, !write); 3736 if (ret) 3737 return ret; 3738 3739 /* Flush and acquire obj->pages so that we are coherent through 3740 * direct access in memory with previous cached writes through 3741 * shmemfs and that our cache domain tracking remains valid. 3742 * For example, if the obj->filp was moved to swap without us 3743 * being notified and releasing the pages, we would mistakenly 3744 * continue to assume that the obj remained out of the CPU cached 3745 * domain. 3746 */ 3747 ret = i915_gem_object_get_pages(obj); 3748 if (ret) 3749 return ret; 3750 3751 i915_gem_object_flush_cpu_write_domain(obj); 3752 3753 /* Serialise direct access to this object with the barriers for 3754 * coherent writes from the GPU, by effectively invalidating the 3755 * GTT domain upon first access. 3756 */ 3757 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) 3758 mb(); 3759 3760 old_write_domain = obj->base.write_domain; 3761 old_read_domains = obj->base.read_domains; 3762 3763 /* It should now be out of any other write domains, and we can update 3764 * the domain values for our changes. 3765 */ 3766 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); 3767 obj->base.read_domains |= I915_GEM_DOMAIN_GTT; 3768 if (write) { 3769 obj->base.read_domains = I915_GEM_DOMAIN_GTT; 3770 obj->base.write_domain = I915_GEM_DOMAIN_GTT; 3771 obj->dirty = 1; 3772 } 3773 3774 trace_i915_gem_object_change_domain(obj, 3775 old_read_domains, 3776 old_write_domain); 3777 3778 /* And bump the LRU for this access */ 3779 vma = i915_gem_obj_to_ggtt(obj); 3780 if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) 3781 list_move_tail(&vma->mm_list, 3782 &to_i915(obj->base.dev)->gtt.base.inactive_list); 3783 3784 return 0; 3785 } 3786 3787 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 3788 enum i915_cache_level cache_level) 3789 { 3790 struct drm_device *dev = obj->base.dev; 3791 struct i915_vma *vma, *next; 3792 int ret; 3793 3794 if (obj->cache_level == cache_level) 3795 return 0; 3796 3797 if (i915_gem_obj_is_pinned(obj)) { 3798 DRM_DEBUG("can not change the cache level of pinned objects\n"); 3799 return -EBUSY; 3800 } 3801 3802 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { 3803 if (!i915_gem_valid_gtt_space(vma, cache_level)) { 3804 ret = i915_vma_unbind(vma); 3805 if (ret) 3806 return ret; 3807 } 3808 } 3809 3810 if (i915_gem_obj_bound_any(obj)) { 3811 ret = i915_gem_object_wait_rendering(obj, false); 3812 if (ret) 3813 return ret; 3814 3815 i915_gem_object_finish_gtt(obj); 3816 3817 /* Before SandyBridge, you could not use tiling or fence 3818 * registers with snooped memory, so relinquish any fences 3819 * currently pointing to our region in the aperture. 3820 */ 3821 if (INTEL_INFO(dev)->gen < 6) { 3822 ret = i915_gem_object_put_fence(obj); 3823 if (ret) 3824 return ret; 3825 } 3826 3827 list_for_each_entry(vma, &obj->vma_list, vma_link) 3828 if (drm_mm_node_allocated(&vma->node)) { 3829 ret = i915_vma_bind(vma, cache_level, 3830 PIN_UPDATE); 3831 if (ret) 3832 return ret; 3833 } 3834 } 3835 3836 list_for_each_entry(vma, &obj->vma_list, vma_link) 3837 vma->node.color = cache_level; 3838 obj->cache_level = cache_level; 3839 3840 if (obj->cache_dirty && 3841 obj->base.write_domain != I915_GEM_DOMAIN_CPU && 3842 cpu_write_needs_clflush(obj)) { 3843 if (i915_gem_clflush_object(obj, true)) 3844 i915_gem_chipset_flush(obj->base.dev); 3845 } 3846 3847 return 0; 3848 } 3849 3850 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, 3851 struct drm_file *file) 3852 { 3853 struct drm_i915_gem_caching *args = data; 3854 struct drm_i915_gem_object *obj; 3855 3856 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 3857 if (&obj->base == NULL) 3858 return -ENOENT; 3859 3860 switch (obj->cache_level) { 3861 case I915_CACHE_LLC: 3862 case I915_CACHE_L3_LLC: 3863 args->caching = I915_CACHING_CACHED; 3864 break; 3865 3866 case I915_CACHE_WT: 3867 args->caching = I915_CACHING_DISPLAY; 3868 break; 3869 3870 default: 3871 args->caching = I915_CACHING_NONE; 3872 break; 3873 } 3874 3875 drm_gem_object_unreference_unlocked(&obj->base); 3876 return 0; 3877 } 3878 3879 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, 3880 struct drm_file *file) 3881 { 3882 struct drm_i915_gem_caching *args = data; 3883 struct drm_i915_gem_object *obj; 3884 enum i915_cache_level level; 3885 int ret; 3886 3887 switch (args->caching) { 3888 case I915_CACHING_NONE: 3889 level = I915_CACHE_NONE; 3890 break; 3891 case I915_CACHING_CACHED: 3892 level = I915_CACHE_LLC; 3893 break; 3894 case I915_CACHING_DISPLAY: 3895 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; 3896 break; 3897 default: 3898 return -EINVAL; 3899 } 3900 3901 ret = i915_mutex_lock_interruptible(dev); 3902 if (ret) 3903 return ret; 3904 3905 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 3906 if (&obj->base == NULL) { 3907 ret = -ENOENT; 3908 goto unlock; 3909 } 3910 3911 ret = i915_gem_object_set_cache_level(obj, level); 3912 3913 drm_gem_object_unreference(&obj->base); 3914 unlock: 3915 mutex_unlock(&dev->struct_mutex); 3916 return ret; 3917 } 3918 3919 /* 3920 * Prepare buffer for display plane (scanout, cursors, etc). 3921 * Can be called from an uninterruptible phase (modesetting) and allows 3922 * any flushes to be pipelined (for pageflips). 3923 */ 3924 int 3925 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 3926 u32 alignment, 3927 struct intel_engine_cs *pipelined, 3928 struct drm_i915_gem_request **pipelined_request, 3929 const struct i915_ggtt_view *view) 3930 { 3931 u32 old_read_domains, old_write_domain; 3932 int ret; 3933 3934 ret = i915_gem_object_sync(obj, pipelined, pipelined_request); 3935 if (ret) 3936 return ret; 3937 3938 /* Mark the pin_display early so that we account for the 3939 * display coherency whilst setting up the cache domains. 3940 */ 3941 obj->pin_display++; 3942 3943 /* The display engine is not coherent with the LLC cache on gen6. As 3944 * a result, we make sure that the pinning that is about to occur is 3945 * done with uncached PTEs. This is lowest common denominator for all 3946 * chipsets. 3947 * 3948 * However for gen6+, we could do better by using the GFDT bit instead 3949 * of uncaching, which would allow us to flush all the LLC-cached data 3950 * with that bit in the PTE to main memory with just one PIPE_CONTROL. 3951 */ 3952 ret = i915_gem_object_set_cache_level(obj, 3953 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); 3954 if (ret) 3955 goto err_unpin_display; 3956 3957 /* As the user may map the buffer once pinned in the display plane 3958 * (e.g. libkms for the bootup splash), we have to ensure that we 3959 * always use map_and_fenceable for all scanout buffers. 3960 */ 3961 ret = i915_gem_object_ggtt_pin(obj, view, alignment, 3962 view->type == I915_GGTT_VIEW_NORMAL ? 3963 PIN_MAPPABLE : 0); 3964 if (ret) 3965 goto err_unpin_display; 3966 3967 i915_gem_object_flush_cpu_write_domain(obj); 3968 3969 old_write_domain = obj->base.write_domain; 3970 old_read_domains = obj->base.read_domains; 3971 3972 /* It should now be out of any other write domains, and we can update 3973 * the domain values for our changes. 3974 */ 3975 obj->base.write_domain = 0; 3976 obj->base.read_domains |= I915_GEM_DOMAIN_GTT; 3977 3978 trace_i915_gem_object_change_domain(obj, 3979 old_read_domains, 3980 old_write_domain); 3981 3982 return 0; 3983 3984 err_unpin_display: 3985 obj->pin_display--; 3986 return ret; 3987 } 3988 3989 void 3990 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, 3991 const struct i915_ggtt_view *view) 3992 { 3993 if (WARN_ON(obj->pin_display == 0)) 3994 return; 3995 3996 i915_gem_object_ggtt_unpin_view(obj, view); 3997 3998 obj->pin_display--; 3999 } 4000 4001 /** 4002 * Moves a single object to the CPU read, and possibly write domain. 4003 * 4004 * This function returns when the move is complete, including waiting on 4005 * flushes to occur. 4006 */ 4007 int 4008 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) 4009 { 4010 uint32_t old_write_domain, old_read_domains; 4011 int ret; 4012 4013 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) 4014 return 0; 4015 4016 ret = i915_gem_object_wait_rendering(obj, !write); 4017 if (ret) 4018 return ret; 4019 4020 i915_gem_object_flush_gtt_write_domain(obj); 4021 4022 old_write_domain = obj->base.write_domain; 4023 old_read_domains = obj->base.read_domains; 4024 4025 /* Flush the CPU cache if it's still invalid. */ 4026 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { 4027 i915_gem_clflush_object(obj, false); 4028 4029 obj->base.read_domains |= I915_GEM_DOMAIN_CPU; 4030 } 4031 4032 /* It should now be out of any other write domains, and we can update 4033 * the domain values for our changes. 4034 */ 4035 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); 4036 4037 /* If we're writing through the CPU, then the GPU read domains will 4038 * need to be invalidated at next use. 4039 */ 4040 if (write) { 4041 obj->base.read_domains = I915_GEM_DOMAIN_CPU; 4042 obj->base.write_domain = I915_GEM_DOMAIN_CPU; 4043 } 4044 4045 trace_i915_gem_object_change_domain(obj, 4046 old_read_domains, 4047 old_write_domain); 4048 4049 return 0; 4050 } 4051 4052 /* Throttle our rendering by waiting until the ring has completed our requests 4053 * emitted over 20 msec ago. 4054 * 4055 * Note that if we were to use the current jiffies each time around the loop, 4056 * we wouldn't escape the function with any frames outstanding if the time to 4057 * render a frame was over 20ms. 4058 * 4059 * This should get us reasonable parallelism between CPU and GPU but also 4060 * relatively low latency when blocking on a particular request to finish. 4061 */ 4062 static int 4063 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) 4064 { 4065 struct drm_i915_private *dev_priv = dev->dev_private; 4066 struct drm_i915_file_private *file_priv = file->driver_priv; 4067 unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; 4068 struct drm_i915_gem_request *request, *target = NULL; 4069 unsigned reset_counter; 4070 int ret; 4071 4072 ret = i915_gem_wait_for_error(&dev_priv->gpu_error); 4073 if (ret) 4074 return ret; 4075 4076 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); 4077 if (ret) 4078 return ret; 4079 4080 spin_lock(&file_priv->mm.lock); 4081 list_for_each_entry(request, &file_priv->mm.request_list, client_list) { 4082 if (time_after_eq(request->emitted_jiffies, recent_enough)) 4083 break; 4084 4085 /* 4086 * Note that the request might not have been submitted yet. 4087 * In which case emitted_jiffies will be zero. 4088 */ 4089 if (!request->emitted_jiffies) 4090 continue; 4091 4092 target = request; 4093 } 4094 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); 4095 if (target) 4096 i915_gem_request_reference(target); 4097 spin_unlock(&file_priv->mm.lock); 4098 4099 if (target == NULL) 4100 return 0; 4101 4102 ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); 4103 if (ret == 0) 4104 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); 4105 4106 i915_gem_request_unreference__unlocked(target); 4107 4108 return ret; 4109 } 4110 4111 static bool 4112 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) 4113 { 4114 struct drm_i915_gem_object *obj = vma->obj; 4115 4116 if (alignment && 4117 vma->node.start & (alignment - 1)) 4118 return true; 4119 4120 if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) 4121 return true; 4122 4123 if (flags & PIN_OFFSET_BIAS && 4124 vma->node.start < (flags & PIN_OFFSET_MASK)) 4125 return true; 4126 4127 return false; 4128 } 4129 4130 static int 4131 i915_gem_object_do_pin(struct drm_i915_gem_object *obj, 4132 struct i915_address_space *vm, 4133 const struct i915_ggtt_view *ggtt_view, 4134 uint32_t alignment, 4135 uint64_t flags) 4136 { 4137 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 4138 struct i915_vma *vma; 4139 unsigned bound; 4140 int ret; 4141 4142 if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) 4143 return -ENODEV; 4144 4145 if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) 4146 return -EINVAL; 4147 4148 if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) 4149 return -EINVAL; 4150 4151 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) 4152 return -EINVAL; 4153 4154 vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : 4155 i915_gem_obj_to_vma(obj, vm); 4156 4157 if (IS_ERR(vma)) 4158 return PTR_ERR(vma); 4159 4160 if (vma) { 4161 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) 4162 return -EBUSY; 4163 4164 if (i915_vma_misplaced(vma, alignment, flags)) { 4165 unsigned long offset; 4166 offset = ggtt_view ? i915_gem_obj_ggtt_offset_view(obj, ggtt_view) : 4167 i915_gem_obj_offset(obj, vm); 4168 WARN(vma->pin_count, 4169 "bo is already pinned in %s with incorrect alignment:" 4170 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," 4171 " obj->map_and_fenceable=%d\n", 4172 ggtt_view ? "ggtt" : "ppgtt", 4173 offset, 4174 alignment, 4175 !!(flags & PIN_MAPPABLE), 4176 obj->map_and_fenceable); 4177 ret = i915_vma_unbind(vma); 4178 if (ret) 4179 return ret; 4180 4181 vma = NULL; 4182 } 4183 } 4184 4185 bound = vma ? vma->bound : 0; 4186 if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { 4187 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, 4188 flags); 4189 if (IS_ERR(vma)) 4190 return PTR_ERR(vma); 4191 } else { 4192 ret = i915_vma_bind(vma, obj->cache_level, flags); 4193 if (ret) 4194 return ret; 4195 } 4196 4197 if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && 4198 (bound ^ vma->bound) & GLOBAL_BIND) { 4199 bool mappable, fenceable; 4200 u32 fence_size, fence_alignment; 4201 4202 fence_size = i915_gem_get_gtt_size(obj->base.dev, 4203 obj->base.size, 4204 obj->tiling_mode); 4205 fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, 4206 obj->base.size, 4207 obj->tiling_mode, 4208 true); 4209 4210 fenceable = (vma->node.size == fence_size && 4211 (vma->node.start & (fence_alignment - 1)) == 0); 4212 4213 mappable = (vma->node.start + fence_size <= 4214 dev_priv->gtt.mappable_end); 4215 4216 obj->map_and_fenceable = mappable && fenceable; 4217 4218 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); 4219 } 4220 4221 vma->pin_count++; 4222 return 0; 4223 } 4224 4225 int 4226 i915_gem_object_pin(struct drm_i915_gem_object *obj, 4227 struct i915_address_space *vm, 4228 uint32_t alignment, 4229 uint64_t flags) 4230 { 4231 return i915_gem_object_do_pin(obj, vm, 4232 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, 4233 alignment, flags); 4234 } 4235 4236 int 4237 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, 4238 const struct i915_ggtt_view *view, 4239 uint32_t alignment, 4240 uint64_t flags) 4241 { 4242 if (WARN_ONCE(!view, "no view specified")) 4243 return -EINVAL; 4244 4245 return i915_gem_object_do_pin(obj, i915_obj_to_ggtt(obj), view, 4246 alignment, flags | PIN_GLOBAL); 4247 } 4248 4249 void 4250 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, 4251 const struct i915_ggtt_view *view) 4252 { 4253 struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); 4254 4255 BUG_ON(!vma); 4256 WARN_ON(vma->pin_count == 0); 4257 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); 4258 4259 --vma->pin_count; 4260 } 4261 4262 int 4263 i915_gem_busy_ioctl(struct drm_device *dev, void *data, 4264 struct drm_file *file) 4265 { 4266 struct drm_i915_gem_busy *args = data; 4267 struct drm_i915_gem_object *obj; 4268 int ret; 4269 4270 ret = i915_mutex_lock_interruptible(dev); 4271 if (ret) 4272 return ret; 4273 4274 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); 4275 if (&obj->base == NULL) { 4276 ret = -ENOENT; 4277 goto unlock; 4278 } 4279 4280 /* Count all active objects as busy, even if they are currently not used 4281 * by the gpu. Users of this interface expect objects to eventually 4282 * become non-busy without any further actions, therefore emit any 4283 * necessary flushes here. 4284 */ 4285 ret = i915_gem_object_flush_active(obj); 4286 if (ret) 4287 goto unref; 4288 4289 BUILD_BUG_ON(I915_NUM_RINGS > 16); 4290 args->busy = obj->active << 16; 4291 if (obj->last_write_req) 4292 args->busy |= obj->last_write_req->ring->id; 4293 4294 unref: 4295 drm_gem_object_unreference(&obj->base); 4296 unlock: 4297 mutex_unlock(&dev->struct_mutex); 4298 return ret; 4299 } 4300 4301 int 4302 i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 4303 struct drm_file *file_priv) 4304 { 4305 return i915_gem_ring_throttle(dev, file_priv); 4306 } 4307 4308 int 4309 i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 4310 struct drm_file *file_priv) 4311 { 4312 struct drm_i915_private *dev_priv = dev->dev_private; 4313 struct drm_i915_gem_madvise *args = data; 4314 struct drm_i915_gem_object *obj; 4315 int ret; 4316 4317 switch (args->madv) { 4318 case I915_MADV_DONTNEED: 4319 case I915_MADV_WILLNEED: 4320 break; 4321 default: 4322 return -EINVAL; 4323 } 4324 4325 ret = i915_mutex_lock_interruptible(dev); 4326 if (ret) 4327 return ret; 4328 4329 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); 4330 if (&obj->base == NULL) { 4331 ret = -ENOENT; 4332 goto unlock; 4333 } 4334 4335 if (i915_gem_obj_is_pinned(obj)) { 4336 ret = -EINVAL; 4337 goto out; 4338 } 4339 4340 if (obj->pages && 4341 obj->tiling_mode != I915_TILING_NONE && 4342 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { 4343 if (obj->madv == I915_MADV_WILLNEED) 4344 i915_gem_object_unpin_pages(obj); 4345 if (args->madv == I915_MADV_WILLNEED) 4346 i915_gem_object_pin_pages(obj); 4347 } 4348 4349 if (obj->madv != __I915_MADV_PURGED) 4350 obj->madv = args->madv; 4351 4352 /* if the object is no longer attached, discard its backing storage */ 4353 if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) 4354 i915_gem_object_truncate(obj); 4355 4356 args->retained = obj->madv != __I915_MADV_PURGED; 4357 4358 out: 4359 drm_gem_object_unreference(&obj->base); 4360 unlock: 4361 mutex_unlock(&dev->struct_mutex); 4362 return ret; 4363 } 4364 4365 void i915_gem_object_init(struct drm_i915_gem_object *obj, 4366 const struct drm_i915_gem_object_ops *ops) 4367 { 4368 int i; 4369 4370 INIT_LIST_HEAD(&obj->global_list); 4371 for (i = 0; i < I915_NUM_RINGS; i++) 4372 INIT_LIST_HEAD(&obj->ring_list[i]); 4373 INIT_LIST_HEAD(&obj->obj_exec_link); 4374 INIT_LIST_HEAD(&obj->vma_list); 4375 INIT_LIST_HEAD(&obj->batch_pool_link); 4376 4377 obj->ops = ops; 4378 4379 obj->fence_reg = I915_FENCE_REG_NONE; 4380 obj->madv = I915_MADV_WILLNEED; 4381 4382 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); 4383 } 4384 4385 static const struct drm_i915_gem_object_ops i915_gem_object_ops = { 4386 .get_pages = i915_gem_object_get_pages_gtt, 4387 .put_pages = i915_gem_object_put_pages_gtt, 4388 }; 4389 4390 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 4391 size_t size) 4392 { 4393 struct drm_i915_gem_object *obj; 4394 #if 0 4395 struct address_space *mapping; 4396 gfp_t mask; 4397 #endif 4398 4399 obj = i915_gem_object_alloc(dev); 4400 if (obj == NULL) 4401 return NULL; 4402 4403 if (drm_gem_object_init(dev, &obj->base, size) != 0) { 4404 i915_gem_object_free(obj); 4405 return NULL; 4406 } 4407 4408 #if 0 4409 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; 4410 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { 4411 /* 965gm cannot relocate objects above 4GiB. */ 4412 mask &= ~__GFP_HIGHMEM; 4413 mask |= __GFP_DMA32; 4414 } 4415 4416 mapping = file_inode(obj->base.filp)->i_mapping; 4417 mapping_set_gfp_mask(mapping, mask); 4418 #endif 4419 4420 i915_gem_object_init(obj, &i915_gem_object_ops); 4421 4422 obj->base.write_domain = I915_GEM_DOMAIN_CPU; 4423 obj->base.read_domains = I915_GEM_DOMAIN_CPU; 4424 4425 if (HAS_LLC(dev)) { 4426 /* On some devices, we can have the GPU use the LLC (the CPU 4427 * cache) for about a 10% performance improvement 4428 * compared to uncached. Graphics requests other than 4429 * display scanout are coherent with the CPU in 4430 * accessing this cache. This means in this mode we 4431 * don't need to clflush on the CPU side, and on the 4432 * GPU side we only need to flush internal caches to 4433 * get data visible to the CPU. 4434 * 4435 * However, we maintain the display planes as UC, and so 4436 * need to rebind when first used as such. 4437 */ 4438 obj->cache_level = I915_CACHE_LLC; 4439 } else 4440 obj->cache_level = I915_CACHE_NONE; 4441 4442 trace_i915_gem_object_create(obj); 4443 4444 return obj; 4445 } 4446 4447 static bool discard_backing_storage(struct drm_i915_gem_object *obj) 4448 { 4449 /* If we are the last user of the backing storage (be it shmemfs 4450 * pages or stolen etc), we know that the pages are going to be 4451 * immediately released. In this case, we can then skip copying 4452 * back the contents from the GPU. 4453 */ 4454 4455 if (obj->madv != I915_MADV_WILLNEED) 4456 return false; 4457 4458 if (obj->base.vm_obj == NULL) 4459 return true; 4460 4461 /* At first glance, this looks racy, but then again so would be 4462 * userspace racing mmap against close. However, the first external 4463 * reference to the filp can only be obtained through the 4464 * i915_gem_mmap_ioctl() which safeguards us against the user 4465 * acquiring such a reference whilst we are in the middle of 4466 * freeing the object. 4467 */ 4468 #if 0 4469 return atomic_long_read(&obj->base.filp->f_count) == 1; 4470 #else 4471 return false; 4472 #endif 4473 } 4474 4475 void i915_gem_free_object(struct drm_gem_object *gem_obj) 4476 { 4477 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); 4478 struct drm_device *dev = obj->base.dev; 4479 struct drm_i915_private *dev_priv = dev->dev_private; 4480 struct i915_vma *vma, *next; 4481 4482 intel_runtime_pm_get(dev_priv); 4483 4484 trace_i915_gem_object_destroy(obj); 4485 4486 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { 4487 int ret; 4488 4489 vma->pin_count = 0; 4490 ret = i915_vma_unbind(vma); 4491 if (WARN_ON(ret == -ERESTARTSYS)) { 4492 bool was_interruptible; 4493 4494 was_interruptible = dev_priv->mm.interruptible; 4495 dev_priv->mm.interruptible = false; 4496 4497 WARN_ON(i915_vma_unbind(vma)); 4498 4499 dev_priv->mm.interruptible = was_interruptible; 4500 } 4501 } 4502 4503 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up 4504 * before progressing. */ 4505 if (obj->stolen) 4506 i915_gem_object_unpin_pages(obj); 4507 4508 WARN_ON(obj->frontbuffer_bits); 4509 4510 if (obj->pages && obj->madv == I915_MADV_WILLNEED && 4511 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && 4512 obj->tiling_mode != I915_TILING_NONE) 4513 i915_gem_object_unpin_pages(obj); 4514 4515 if (WARN_ON(obj->pages_pin_count)) 4516 obj->pages_pin_count = 0; 4517 if (discard_backing_storage(obj)) 4518 obj->madv = I915_MADV_DONTNEED; 4519 i915_gem_object_put_pages(obj); 4520 i915_gem_object_free_mmap_offset(obj); 4521 4522 BUG_ON(obj->pages); 4523 4524 #if 0 4525 if (obj->base.import_attach) 4526 drm_prime_gem_destroy(&obj->base, NULL); 4527 #endif 4528 4529 if (obj->ops->release) 4530 obj->ops->release(obj); 4531 4532 drm_gem_object_release(&obj->base); 4533 i915_gem_info_remove_obj(dev_priv, obj->base.size); 4534 4535 kfree(obj->bit_17); 4536 i915_gem_object_free(obj); 4537 4538 intel_runtime_pm_put(dev_priv); 4539 } 4540 4541 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, 4542 struct i915_address_space *vm) 4543 { 4544 struct i915_vma *vma; 4545 list_for_each_entry(vma, &obj->vma_list, vma_link) { 4546 if (i915_is_ggtt(vma->vm) && 4547 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) 4548 continue; 4549 if (vma->vm == vm) 4550 return vma; 4551 } 4552 return NULL; 4553 } 4554 4555 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, 4556 const struct i915_ggtt_view *view) 4557 { 4558 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); 4559 struct i915_vma *vma; 4560 4561 if (WARN_ONCE(!view, "no view specified")) 4562 return ERR_PTR(-EINVAL); 4563 4564 list_for_each_entry(vma, &obj->vma_list, vma_link) 4565 if (vma->vm == ggtt && 4566 i915_ggtt_view_equal(&vma->ggtt_view, view)) 4567 return vma; 4568 return NULL; 4569 } 4570 4571 void i915_gem_vma_destroy(struct i915_vma *vma) 4572 { 4573 struct i915_address_space *vm = NULL; 4574 WARN_ON(vma->node.allocated); 4575 4576 /* Keep the vma as a placeholder in the execbuffer reservation lists */ 4577 if (!list_empty(&vma->exec_list)) 4578 return; 4579 4580 vm = vma->vm; 4581 4582 if (!i915_is_ggtt(vm)) 4583 i915_ppgtt_put(i915_vm_to_ppgtt(vm)); 4584 4585 list_del(&vma->vma_link); 4586 4587 kfree(vma); 4588 } 4589 4590 static void 4591 i915_gem_stop_ringbuffers(struct drm_device *dev) 4592 { 4593 struct drm_i915_private *dev_priv = dev->dev_private; 4594 struct intel_engine_cs *ring; 4595 int i; 4596 4597 for_each_ring(ring, dev_priv, i) 4598 dev_priv->gt.stop_ring(ring); 4599 } 4600 4601 int 4602 i915_gem_suspend(struct drm_device *dev) 4603 { 4604 struct drm_i915_private *dev_priv = dev->dev_private; 4605 int ret = 0; 4606 4607 mutex_lock(&dev->struct_mutex); 4608 ret = i915_gpu_idle(dev); 4609 if (ret) 4610 goto err; 4611 4612 i915_gem_retire_requests(dev); 4613 4614 i915_gem_stop_ringbuffers(dev); 4615 mutex_unlock(&dev->struct_mutex); 4616 4617 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); 4618 cancel_delayed_work_sync(&dev_priv->mm.retire_work); 4619 #if 0 4620 flush_delayed_work(&dev_priv->mm.idle_work); 4621 #endif 4622 4623 /* Assert that we sucessfully flushed all the work and 4624 * reset the GPU back to its idle, low power state. 4625 */ 4626 WARN_ON(dev_priv->mm.busy); 4627 4628 return 0; 4629 4630 err: 4631 mutex_unlock(&dev->struct_mutex); 4632 return ret; 4633 } 4634 4635 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice) 4636 { 4637 struct intel_engine_cs *ring = req->ring; 4638 struct drm_device *dev = ring->dev; 4639 struct drm_i915_private *dev_priv = dev->dev_private; 4640 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); 4641 u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; 4642 int i, ret; 4643 4644 if (!HAS_L3_DPF(dev) || !remap_info) 4645 return 0; 4646 4647 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3); 4648 if (ret) 4649 return ret; 4650 4651 /* 4652 * Note: We do not worry about the concurrent register cacheline hang 4653 * here because no other code should access these registers other than 4654 * at initialization time. 4655 */ 4656 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { 4657 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 4658 intel_ring_emit(ring, reg_base + i); 4659 intel_ring_emit(ring, remap_info[i/4]); 4660 } 4661 4662 intel_ring_advance(ring); 4663 4664 return ret; 4665 } 4666 4667 void i915_gem_init_swizzling(struct drm_device *dev) 4668 { 4669 struct drm_i915_private *dev_priv = dev->dev_private; 4670 4671 if (INTEL_INFO(dev)->gen < 5 || 4672 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) 4673 return; 4674 4675 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | 4676 DISP_TILE_SURFACE_SWIZZLING); 4677 4678 if (IS_GEN5(dev)) 4679 return; 4680 4681 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); 4682 if (IS_GEN6(dev)) 4683 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); 4684 else if (IS_GEN7(dev)) 4685 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); 4686 else if (IS_GEN8(dev)) 4687 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); 4688 else 4689 BUG(); 4690 } 4691 4692 static bool 4693 intel_enable_blt(struct drm_device *dev) 4694 { 4695 if (!HAS_BLT(dev)) 4696 return false; 4697 4698 /* The blitter was dysfunctional on early prototypes */ 4699 if (IS_GEN6(dev) && dev->pdev->revision < 8) { 4700 DRM_INFO("BLT not supported on this pre-production hardware;" 4701 " graphics performance will be degraded.\n"); 4702 return false; 4703 } 4704 4705 return true; 4706 } 4707 4708 static void init_unused_ring(struct drm_device *dev, u32 base) 4709 { 4710 struct drm_i915_private *dev_priv = dev->dev_private; 4711 4712 I915_WRITE(RING_CTL(base), 0); 4713 I915_WRITE(RING_HEAD(base), 0); 4714 I915_WRITE(RING_TAIL(base), 0); 4715 I915_WRITE(RING_START(base), 0); 4716 } 4717 4718 static void init_unused_rings(struct drm_device *dev) 4719 { 4720 if (IS_I830(dev)) { 4721 init_unused_ring(dev, PRB1_BASE); 4722 init_unused_ring(dev, SRB0_BASE); 4723 init_unused_ring(dev, SRB1_BASE); 4724 init_unused_ring(dev, SRB2_BASE); 4725 init_unused_ring(dev, SRB3_BASE); 4726 } else if (IS_GEN2(dev)) { 4727 init_unused_ring(dev, SRB0_BASE); 4728 init_unused_ring(dev, SRB1_BASE); 4729 } else if (IS_GEN3(dev)) { 4730 init_unused_ring(dev, PRB1_BASE); 4731 init_unused_ring(dev, PRB2_BASE); 4732 } 4733 } 4734 4735 int i915_gem_init_rings(struct drm_device *dev) 4736 { 4737 struct drm_i915_private *dev_priv = dev->dev_private; 4738 int ret; 4739 4740 ret = intel_init_render_ring_buffer(dev); 4741 if (ret) 4742 return ret; 4743 4744 if (HAS_BSD(dev)) { 4745 ret = intel_init_bsd_ring_buffer(dev); 4746 if (ret) 4747 goto cleanup_render_ring; 4748 } 4749 4750 if (intel_enable_blt(dev)) { 4751 ret = intel_init_blt_ring_buffer(dev); 4752 if (ret) 4753 goto cleanup_bsd_ring; 4754 } 4755 4756 if (HAS_VEBOX(dev)) { 4757 ret = intel_init_vebox_ring_buffer(dev); 4758 if (ret) 4759 goto cleanup_blt_ring; 4760 } 4761 4762 if (HAS_BSD2(dev)) { 4763 ret = intel_init_bsd2_ring_buffer(dev); 4764 if (ret) 4765 goto cleanup_vebox_ring; 4766 } 4767 4768 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); 4769 if (ret) 4770 goto cleanup_bsd2_ring; 4771 4772 return 0; 4773 4774 cleanup_bsd2_ring: 4775 intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); 4776 cleanup_vebox_ring: 4777 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); 4778 cleanup_blt_ring: 4779 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); 4780 cleanup_bsd_ring: 4781 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); 4782 cleanup_render_ring: 4783 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); 4784 4785 return ret; 4786 } 4787 4788 int 4789 i915_gem_init_hw(struct drm_device *dev) 4790 { 4791 struct drm_i915_private *dev_priv = dev->dev_private; 4792 struct intel_engine_cs *ring; 4793 int ret, i, j; 4794 4795 #if 0 4796 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) 4797 return -EIO; 4798 #endif 4799 4800 /* Double layer security blanket, see i915_gem_init() */ 4801 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4802 4803 if (dev_priv->ellc_size) 4804 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); 4805 4806 if (IS_HASWELL(dev)) 4807 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? 4808 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); 4809 4810 if (HAS_PCH_NOP(dev)) { 4811 if (IS_IVYBRIDGE(dev)) { 4812 u32 temp = I915_READ(GEN7_MSG_CTL); 4813 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); 4814 I915_WRITE(GEN7_MSG_CTL, temp); 4815 } else if (INTEL_INFO(dev)->gen >= 7) { 4816 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); 4817 temp &= ~RESET_PCH_HANDSHAKE_ENABLE; 4818 I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); 4819 } 4820 } 4821 4822 i915_gem_init_swizzling(dev); 4823 4824 /* 4825 * At least 830 can leave some of the unused rings 4826 * "active" (ie. head != tail) after resume which 4827 * will prevent c3 entry. Makes sure all unused rings 4828 * are totally idle. 4829 */ 4830 init_unused_rings(dev); 4831 4832 BUG_ON(!dev_priv->ring[RCS].default_context); 4833 4834 ret = i915_ppgtt_init_hw(dev); 4835 if (ret) { 4836 DRM_ERROR("PPGTT enable HW failed %d\n", ret); 4837 goto out; 4838 } 4839 4840 /* Need to do basic initialisation of all rings first: */ 4841 for_each_ring(ring, dev_priv, i) { 4842 ret = ring->init_hw(ring); 4843 if (ret) 4844 goto out; 4845 } 4846 4847 /* Now it is safe to go back round and do everything else: */ 4848 for_each_ring(ring, dev_priv, i) { 4849 struct drm_i915_gem_request *req; 4850 4851 WARN_ON(!ring->default_context); 4852 4853 ret = i915_gem_request_alloc(ring, ring->default_context, &req); 4854 if (ret) { 4855 i915_gem_cleanup_ringbuffer(dev); 4856 goto out; 4857 } 4858 4859 if (ring->id == RCS) { 4860 for (j = 0; j < NUM_L3_SLICES(dev); j++) 4861 i915_gem_l3_remap(req, j); 4862 } 4863 4864 ret = i915_ppgtt_init_ring(req); 4865 if (ret && ret != -EIO) { 4866 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret); 4867 i915_gem_request_cancel(req); 4868 i915_gem_cleanup_ringbuffer(dev); 4869 goto out; 4870 } 4871 4872 ret = i915_gem_context_enable(req); 4873 if (ret && ret != -EIO) { 4874 DRM_ERROR("Context enable ring #%d failed %d\n", i, ret); 4875 i915_gem_request_cancel(req); 4876 i915_gem_cleanup_ringbuffer(dev); 4877 goto out; 4878 } 4879 4880 i915_add_request_no_flush(req); 4881 } 4882 4883 out: 4884 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4885 return ret; 4886 } 4887 4888 int i915_gem_init(struct drm_device *dev) 4889 { 4890 struct drm_i915_private *dev_priv = dev->dev_private; 4891 int ret; 4892 4893 i915.enable_execlists = intel_sanitize_enable_execlists(dev, 4894 i915.enable_execlists); 4895 4896 mutex_lock(&dev->struct_mutex); 4897 4898 if (IS_VALLEYVIEW(dev)) { 4899 /* VLVA0 (potential hack), BIOS isn't actually waking us */ 4900 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); 4901 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 4902 VLV_GTLC_ALLOWWAKEACK), 10)) 4903 DRM_DEBUG_DRIVER("allow wake ack timed out\n"); 4904 } 4905 4906 if (!i915.enable_execlists) { 4907 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; 4908 dev_priv->gt.init_rings = i915_gem_init_rings; 4909 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; 4910 dev_priv->gt.stop_ring = intel_stop_ring_buffer; 4911 } else { 4912 dev_priv->gt.execbuf_submit = intel_execlists_submission; 4913 dev_priv->gt.init_rings = intel_logical_rings_init; 4914 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; 4915 dev_priv->gt.stop_ring = intel_logical_ring_stop; 4916 } 4917 4918 /* This is just a security blanket to placate dragons. 4919 * On some systems, we very sporadically observe that the first TLBs 4920 * used by the CS may be stale, despite us poking the TLB reset. If 4921 * we hold the forcewake during initialisation these problems 4922 * just magically go away. 4923 */ 4924 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4925 4926 ret = i915_gem_init_userptr(dev); 4927 if (ret) 4928 goto out_unlock; 4929 4930 i915_gem_init_global_gtt(dev); 4931 4932 ret = i915_gem_context_init(dev); 4933 if (ret) 4934 goto out_unlock; 4935 4936 ret = dev_priv->gt.init_rings(dev); 4937 if (ret) 4938 goto out_unlock; 4939 4940 ret = i915_gem_init_hw(dev); 4941 if (ret == -EIO) { 4942 /* Allow ring initialisation to fail by marking the GPU as 4943 * wedged. But we only want to do this where the GPU is angry, 4944 * for all other failure, such as an allocation failure, bail. 4945 */ 4946 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); 4947 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); 4948 ret = 0; 4949 } 4950 4951 out_unlock: 4952 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4953 mutex_unlock(&dev->struct_mutex); 4954 4955 return ret; 4956 } 4957 4958 void 4959 i915_gem_cleanup_ringbuffer(struct drm_device *dev) 4960 { 4961 struct drm_i915_private *dev_priv = dev->dev_private; 4962 struct intel_engine_cs *ring; 4963 int i; 4964 4965 for_each_ring(ring, dev_priv, i) 4966 dev_priv->gt.cleanup_ring(ring); 4967 4968 if (i915.enable_execlists) 4969 /* 4970 * Neither the BIOS, ourselves or any other kernel 4971 * expects the system to be in execlists mode on startup, 4972 * so we need to reset the GPU back to legacy mode. 4973 */ 4974 intel_gpu_reset(dev); 4975 } 4976 4977 static void 4978 init_ring_lists(struct intel_engine_cs *ring) 4979 { 4980 INIT_LIST_HEAD(&ring->active_list); 4981 INIT_LIST_HEAD(&ring->request_list); 4982 } 4983 4984 void i915_init_vm(struct drm_i915_private *dev_priv, 4985 struct i915_address_space *vm) 4986 { 4987 if (!i915_is_ggtt(vm)) 4988 drm_mm_init(&vm->mm, vm->start, vm->total); 4989 vm->dev = dev_priv->dev; 4990 INIT_LIST_HEAD(&vm->active_list); 4991 INIT_LIST_HEAD(&vm->inactive_list); 4992 INIT_LIST_HEAD(&vm->global_link); 4993 list_add_tail(&vm->global_link, &dev_priv->vm_list); 4994 } 4995 4996 void 4997 i915_gem_load(struct drm_device *dev) 4998 { 4999 struct drm_i915_private *dev_priv = dev->dev_private; 5000 int i; 5001 5002 INIT_LIST_HEAD(&dev_priv->vm_list); 5003 i915_init_vm(dev_priv, &dev_priv->gtt.base); 5004 5005 INIT_LIST_HEAD(&dev_priv->context_list); 5006 INIT_LIST_HEAD(&dev_priv->mm.unbound_list); 5007 INIT_LIST_HEAD(&dev_priv->mm.bound_list); 5008 INIT_LIST_HEAD(&dev_priv->mm.fence_list); 5009 for (i = 0; i < I915_NUM_RINGS; i++) 5010 init_ring_lists(&dev_priv->ring[i]); 5011 for (i = 0; i < I915_MAX_NUM_FENCES; i++) 5012 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); 5013 INIT_DELAYED_WORK(&dev_priv->mm.retire_work, 5014 i915_gem_retire_work_handler); 5015 INIT_DELAYED_WORK(&dev_priv->mm.idle_work, 5016 i915_gem_idle_work_handler); 5017 init_waitqueue_head(&dev_priv->gpu_error.reset_queue); 5018 5019 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; 5020 5021 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) 5022 dev_priv->num_fence_regs = 32; 5023 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 5024 dev_priv->num_fence_regs = 16; 5025 else 5026 dev_priv->num_fence_regs = 8; 5027 5028 if (intel_vgpu_active(dev)) 5029 dev_priv->num_fence_regs = 5030 I915_READ(vgtif_reg(avail_rs.fence_num)); 5031 5032 /* Initialize fence registers to zero */ 5033 INIT_LIST_HEAD(&dev_priv->mm.fence_list); 5034 i915_gem_restore_fences(dev); 5035 5036 i915_gem_detect_bit_6_swizzle(dev); 5037 init_waitqueue_head(&dev_priv->pending_flip_queue); 5038 5039 dev_priv->mm.interruptible = true; 5040 5041 i915_gem_shrinker_init(dev_priv); 5042 5043 lockinit(&dev_priv->fb_tracking.lock, "drmftl", 0, LK_CANRECURSE); 5044 } 5045 5046 void i915_gem_release(struct drm_device *dev, struct drm_file *file) 5047 { 5048 struct drm_i915_file_private *file_priv = file->driver_priv; 5049 5050 /* Clean up our request list when the client is going away, so that 5051 * later retire_requests won't dereference our soon-to-be-gone 5052 * file_priv. 5053 */ 5054 spin_lock(&file_priv->mm.lock); 5055 while (!list_empty(&file_priv->mm.request_list)) { 5056 struct drm_i915_gem_request *request; 5057 5058 request = list_first_entry(&file_priv->mm.request_list, 5059 struct drm_i915_gem_request, 5060 client_list); 5061 list_del(&request->client_list); 5062 request->file_priv = NULL; 5063 } 5064 spin_unlock(&file_priv->mm.lock); 5065 5066 if (!list_empty(&file_priv->rps.link)) { 5067 lockmgr(&to_i915(dev)->rps.client_lock, LK_EXCLUSIVE); 5068 list_del(&file_priv->rps.link); 5069 lockmgr(&to_i915(dev)->rps.client_lock, LK_RELEASE); 5070 } 5071 } 5072 5073 int 5074 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot, 5075 vm_ooffset_t foff, struct ucred *cred, u_short *color) 5076 { 5077 *color = 0; /* XXXKIB */ 5078 return (0); 5079 } 5080 5081 void 5082 i915_gem_pager_dtor(void *handle) 5083 { 5084 struct drm_gem_object *obj; 5085 struct drm_device *dev; 5086 5087 obj = handle; 5088 dev = obj->dev; 5089 5090 mutex_lock(&dev->struct_mutex); 5091 drm_gem_free_mmap_offset(obj); 5092 i915_gem_release_mmap(to_intel_bo(obj)); 5093 drm_gem_object_unreference(obj); 5094 mutex_unlock(&dev->struct_mutex); 5095 } 5096 5097 int i915_gem_open(struct drm_device *dev, struct drm_file *file) 5098 { 5099 struct drm_i915_file_private *file_priv; 5100 int ret; 5101 5102 DRM_DEBUG_DRIVER("\n"); 5103 5104 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); 5105 if (!file_priv) 5106 return -ENOMEM; 5107 5108 file->driver_priv = file_priv; 5109 file_priv->dev_priv = dev->dev_private; 5110 file_priv->file = file; 5111 INIT_LIST_HEAD(&file_priv->rps.link); 5112 5113 spin_init(&file_priv->mm.lock, "i915_priv"); 5114 INIT_LIST_HEAD(&file_priv->mm.request_list); 5115 5116 ret = i915_gem_context_open(dev, file); 5117 if (ret) 5118 kfree(file_priv); 5119 5120 return ret; 5121 } 5122 5123 /** 5124 * i915_gem_track_fb - update frontbuffer tracking 5125 * old: current GEM buffer for the frontbuffer slots 5126 * new: new GEM buffer for the frontbuffer slots 5127 * frontbuffer_bits: bitmask of frontbuffer slots 5128 * 5129 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them 5130 * from @old and setting them in @new. Both @old and @new can be NULL. 5131 */ 5132 void i915_gem_track_fb(struct drm_i915_gem_object *old, 5133 struct drm_i915_gem_object *new, 5134 unsigned frontbuffer_bits) 5135 { 5136 if (old) { 5137 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); 5138 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); 5139 old->frontbuffer_bits &= ~frontbuffer_bits; 5140 } 5141 5142 if (new) { 5143 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); 5144 WARN_ON(new->frontbuffer_bits & frontbuffer_bits); 5145 new->frontbuffer_bits |= frontbuffer_bits; 5146 } 5147 } 5148 5149 /* All the new VM stuff */ 5150 unsigned long 5151 i915_gem_obj_offset(struct drm_i915_gem_object *o, 5152 struct i915_address_space *vm) 5153 { 5154 struct drm_i915_private *dev_priv = o->base.dev->dev_private; 5155 struct i915_vma *vma; 5156 5157 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); 5158 5159 list_for_each_entry(vma, &o->vma_list, vma_link) { 5160 if (i915_is_ggtt(vma->vm) && 5161 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) 5162 continue; 5163 if (vma->vm == vm) 5164 return vma->node.start; 5165 } 5166 5167 WARN(1, "%s vma for this object not found.\n", 5168 i915_is_ggtt(vm) ? "global" : "ppgtt"); 5169 return -1; 5170 } 5171 5172 unsigned long 5173 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, 5174 const struct i915_ggtt_view *view) 5175 { 5176 struct i915_address_space *ggtt = i915_obj_to_ggtt(o); 5177 struct i915_vma *vma; 5178 5179 list_for_each_entry(vma, &o->vma_list, vma_link) 5180 if (vma->vm == ggtt && 5181 i915_ggtt_view_equal(&vma->ggtt_view, view)) 5182 return vma->node.start; 5183 5184 WARN(1, "global vma for this object not found. (view=%u)\n", view->type); 5185 return -1; 5186 } 5187 5188 bool i915_gem_obj_bound(struct drm_i915_gem_object *o, 5189 struct i915_address_space *vm) 5190 { 5191 struct i915_vma *vma; 5192 5193 list_for_each_entry(vma, &o->vma_list, vma_link) { 5194 if (i915_is_ggtt(vma->vm) && 5195 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) 5196 continue; 5197 if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) 5198 return true; 5199 } 5200 5201 return false; 5202 } 5203 5204 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, 5205 const struct i915_ggtt_view *view) 5206 { 5207 struct i915_address_space *ggtt = i915_obj_to_ggtt(o); 5208 struct i915_vma *vma; 5209 5210 list_for_each_entry(vma, &o->vma_list, vma_link) 5211 if (vma->vm == ggtt && 5212 i915_ggtt_view_equal(&vma->ggtt_view, view) && 5213 drm_mm_node_allocated(&vma->node)) 5214 return true; 5215 5216 return false; 5217 } 5218 5219 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) 5220 { 5221 struct i915_vma *vma; 5222 5223 list_for_each_entry(vma, &o->vma_list, vma_link) 5224 if (drm_mm_node_allocated(&vma->node)) 5225 return true; 5226 5227 return false; 5228 } 5229 5230 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, 5231 struct i915_address_space *vm) 5232 { 5233 struct drm_i915_private *dev_priv = o->base.dev->dev_private; 5234 struct i915_vma *vma; 5235 5236 WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); 5237 5238 BUG_ON(list_empty(&o->vma_list)); 5239 5240 list_for_each_entry(vma, &o->vma_list, vma_link) { 5241 if (i915_is_ggtt(vma->vm) && 5242 vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) 5243 continue; 5244 if (vma->vm == vm) 5245 return vma->node.size; 5246 } 5247 return 0; 5248 } 5249 5250 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) 5251 { 5252 struct i915_vma *vma; 5253 list_for_each_entry(vma, &obj->vma_list, vma_link) 5254 if (vma->pin_count > 0) 5255 return true; 5256 5257 return false; 5258 } 5259 5260 #if 0 5261 /* Allocate a new GEM object and fill it with the supplied data */ 5262 struct drm_i915_gem_object * 5263 i915_gem_object_create_from_data(struct drm_device *dev, 5264 const void *data, size_t size) 5265 { 5266 struct drm_i915_gem_object *obj; 5267 struct sg_table *sg; 5268 size_t bytes; 5269 int ret; 5270 5271 obj = i915_gem_alloc_object(dev, round_up(size, PAGE_SIZE)); 5272 if (IS_ERR_OR_NULL(obj)) 5273 return obj; 5274 5275 ret = i915_gem_object_set_to_cpu_domain(obj, true); 5276 if (ret) 5277 goto fail; 5278 5279 ret = i915_gem_object_get_pages(obj); 5280 if (ret) 5281 goto fail; 5282 5283 i915_gem_object_pin_pages(obj); 5284 sg = obj->pages; 5285 bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); 5286 i915_gem_object_unpin_pages(obj); 5287 5288 if (WARN_ON(bytes != size)) { 5289 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); 5290 ret = -EFAULT; 5291 goto fail; 5292 } 5293 5294 return obj; 5295 5296 fail: 5297 drm_gem_object_unreference(&obj->base); 5298 return ERR_PTR(ret); 5299 } 5300 #endif 5301