1 /* 2 * Copyright © 2008,2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Chris Wilson <chris@chris-wilson.co.uk> 26 * 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/i915_drm.h> 31 #include "i915_drv.h" 32 #include "i915_trace.h" 33 #include "intel_drv.h" 34 #include <linux/pagemap.h> 35 #include <asm/cpufeature.h> 36 37 #define __EXEC_OBJECT_HAS_PIN (1<<31) 38 #define __EXEC_OBJECT_HAS_FENCE (1<<30) 39 #define __EXEC_OBJECT_NEEDS_MAP (1<<29) 40 #define __EXEC_OBJECT_NEEDS_BIAS (1<<28) 41 42 #define BATCH_OFFSET_BIAS (256*1024) 43 44 struct eb_vmas { 45 struct list_head vmas; 46 int and; 47 union { 48 struct i915_vma *lut[0]; 49 struct hlist_head buckets[0]; 50 }; 51 }; 52 53 static struct eb_vmas * 54 eb_create(struct drm_i915_gem_execbuffer2 *args) 55 { 56 struct eb_vmas *eb = NULL; 57 58 if (args->flags & I915_EXEC_HANDLE_LUT) { 59 unsigned size = args->buffer_count; 60 size *= sizeof(struct i915_vma *); 61 size += sizeof(struct eb_vmas); 62 eb = kmalloc(size, M_DRM, M_NOWAIT); 63 } 64 65 if (eb == NULL) { 66 unsigned size = args->buffer_count; 67 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2; 68 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head)); 69 while (count > 2*size) 70 count >>= 1; 71 eb = kzalloc(count*sizeof(struct hlist_head) + 72 sizeof(struct eb_vmas), 73 GFP_TEMPORARY); 74 if (eb == NULL) 75 return eb; 76 77 eb->and = count - 1; 78 } else 79 eb->and = -args->buffer_count; 80 81 INIT_LIST_HEAD(&eb->vmas); 82 return eb; 83 } 84 85 static void 86 eb_reset(struct eb_vmas *eb) 87 { 88 if (eb->and >= 0) 89 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head)); 90 } 91 92 static int 93 eb_lookup_vmas(struct eb_vmas *eb, 94 struct drm_i915_gem_exec_object2 *exec, 95 const struct drm_i915_gem_execbuffer2 *args, 96 struct i915_address_space *vm, 97 struct drm_file *file) 98 { 99 struct drm_i915_gem_object *obj; 100 struct list_head objects; 101 int i, ret; 102 103 INIT_LIST_HEAD(&objects); 104 lockmgr(&file->table_lock, LK_EXCLUSIVE); 105 /* Grab a reference to the object and release the lock so we can lookup 106 * or create the VMA without using GFP_ATOMIC */ 107 for (i = 0; i < args->buffer_count; i++) { 108 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle)); 109 if (obj == NULL) { 110 lockmgr(&file->table_lock, LK_RELEASE); 111 DRM_DEBUG("Invalid object handle %d at index %d\n", 112 exec[i].handle, i); 113 ret = -ENOENT; 114 goto err; 115 } 116 117 if (!list_empty(&obj->obj_exec_link)) { 118 lockmgr(&file->table_lock, LK_RELEASE); 119 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n", 120 obj, exec[i].handle, i); 121 ret = -EINVAL; 122 goto err; 123 } 124 125 drm_gem_object_reference(&obj->base); 126 list_add_tail(&obj->obj_exec_link, &objects); 127 } 128 lockmgr(&file->table_lock, LK_RELEASE); 129 130 i = 0; 131 while (!list_empty(&objects)) { 132 struct i915_vma *vma; 133 134 obj = list_first_entry(&objects, 135 struct drm_i915_gem_object, 136 obj_exec_link); 137 138 /* 139 * NOTE: We can leak any vmas created here when something fails 140 * later on. But that's no issue since vma_unbind can deal with 141 * vmas which are not actually bound. And since only 142 * lookup_or_create exists as an interface to get at the vma 143 * from the (obj, vm) we don't run the risk of creating 144 * duplicated vmas for the same vm. 145 */ 146 vma = i915_gem_obj_lookup_or_create_vma(obj, vm); 147 if (IS_ERR(vma)) { 148 DRM_DEBUG("Failed to lookup VMA\n"); 149 ret = PTR_ERR(vma); 150 goto err; 151 } 152 153 /* Transfer ownership from the objects list to the vmas list. */ 154 list_add_tail(&vma->exec_list, &eb->vmas); 155 list_del_init(&obj->obj_exec_link); 156 157 vma->exec_entry = &exec[i]; 158 if (eb->and < 0) { 159 eb->lut[i] = vma; 160 } else { 161 uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle; 162 vma->exec_handle = handle; 163 hlist_add_head(&vma->exec_node, 164 &eb->buckets[handle & eb->and]); 165 } 166 ++i; 167 } 168 169 return 0; 170 171 172 err: 173 while (!list_empty(&objects)) { 174 obj = list_first_entry(&objects, 175 struct drm_i915_gem_object, 176 obj_exec_link); 177 list_del_init(&obj->obj_exec_link); 178 drm_gem_object_unreference(&obj->base); 179 } 180 /* 181 * Objects already transfered to the vmas list will be unreferenced by 182 * eb_destroy. 183 */ 184 185 return ret; 186 } 187 188 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle) 189 { 190 if (eb->and < 0) { 191 if (handle >= -eb->and) 192 return NULL; 193 return eb->lut[handle]; 194 } else { 195 struct hlist_head *head; 196 struct hlist_node *node; 197 198 head = &eb->buckets[handle & eb->and]; 199 hlist_for_each(node, head) { 200 struct i915_vma *vma; 201 202 vma = hlist_entry(node, struct i915_vma, exec_node); 203 if (vma->exec_handle == handle) 204 return vma; 205 } 206 return NULL; 207 } 208 } 209 210 static void 211 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma) 212 { 213 struct drm_i915_gem_exec_object2 *entry; 214 struct drm_i915_gem_object *obj = vma->obj; 215 216 if (!drm_mm_node_allocated(&vma->node)) 217 return; 218 219 entry = vma->exec_entry; 220 221 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) 222 i915_gem_object_unpin_fence(obj); 223 224 if (entry->flags & __EXEC_OBJECT_HAS_PIN) 225 vma->pin_count--; 226 227 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN); 228 } 229 230 static void eb_destroy(struct eb_vmas *eb) 231 { 232 while (!list_empty(&eb->vmas)) { 233 struct i915_vma *vma; 234 235 vma = list_first_entry(&eb->vmas, 236 struct i915_vma, 237 exec_list); 238 list_del_init(&vma->exec_list); 239 i915_gem_execbuffer_unreserve_vma(vma); 240 drm_gem_object_unreference(&vma->obj->base); 241 } 242 kfree(eb); 243 } 244 245 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) 246 { 247 return (HAS_LLC(obj->base.dev) || 248 obj->base.write_domain == I915_GEM_DOMAIN_CPU || 249 obj->cache_level != I915_CACHE_NONE); 250 } 251 252 static int 253 relocate_entry_cpu(struct drm_i915_gem_object *obj, 254 struct drm_i915_gem_relocation_entry *reloc, 255 uint64_t target_offset) 256 { 257 struct drm_device *dev = obj->base.dev; 258 uint32_t page_offset = offset_in_page(reloc->offset); 259 uint64_t delta = reloc->delta + target_offset; 260 char *vaddr; 261 int ret; 262 263 ret = i915_gem_object_set_to_cpu_domain(obj, true); 264 if (ret) 265 return ret; 266 267 vaddr = kmap_atomic(i915_gem_object_get_page(obj, 268 reloc->offset >> PAGE_SHIFT)); 269 *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta); 270 271 if (INTEL_INFO(dev)->gen >= 8) { 272 page_offset = offset_in_page(page_offset + sizeof(uint32_t)); 273 274 if (page_offset == 0) { 275 kunmap_atomic(vaddr); 276 vaddr = kmap_atomic(i915_gem_object_get_page(obj, 277 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); 278 } 279 280 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta); 281 } 282 283 kunmap_atomic(vaddr); 284 285 return 0; 286 } 287 288 static int 289 relocate_entry_gtt(struct drm_i915_gem_object *obj, 290 struct drm_i915_gem_relocation_entry *reloc, 291 uint64_t target_offset) 292 { 293 struct drm_device *dev = obj->base.dev; 294 struct drm_i915_private *dev_priv = dev->dev_private; 295 uint64_t delta = reloc->delta + target_offset; 296 uint64_t offset; 297 void __iomem *reloc_page; 298 int ret; 299 300 ret = i915_gem_object_set_to_gtt_domain(obj, true); 301 if (ret) 302 return ret; 303 304 ret = i915_gem_object_put_fence(obj); 305 if (ret) 306 return ret; 307 308 /* Map the page containing the relocation we're going to perform. */ 309 offset = i915_gem_obj_ggtt_offset(obj); 310 offset += reloc->offset; 311 reloc_page = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 312 offset & ~PAGE_MASK); 313 iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset)); 314 315 if (INTEL_INFO(dev)->gen >= 8) { 316 offset += sizeof(uint32_t); 317 318 if (offset_in_page(offset) == 0) { 319 io_mapping_unmap_atomic(reloc_page); 320 reloc_page = 321 io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 322 offset); 323 } 324 325 iowrite32(upper_32_bits(delta), 326 reloc_page + offset_in_page(offset)); 327 } 328 329 io_mapping_unmap_atomic(reloc_page); 330 331 return 0; 332 } 333 334 static void 335 clflush_write32(void *addr, uint32_t value) 336 { 337 /* This is not a fast path, so KISS. */ 338 drm_clflush_virt_range(addr, sizeof(uint32_t)); 339 *(uint32_t *)addr = value; 340 drm_clflush_virt_range(addr, sizeof(uint32_t)); 341 } 342 343 static int 344 relocate_entry_clflush(struct drm_i915_gem_object *obj, 345 struct drm_i915_gem_relocation_entry *reloc, 346 uint64_t target_offset) 347 { 348 struct drm_device *dev = obj->base.dev; 349 uint32_t page_offset = offset_in_page(reloc->offset); 350 uint64_t delta = (int)reloc->delta + target_offset; 351 char *vaddr; 352 int ret; 353 354 ret = i915_gem_object_set_to_gtt_domain(obj, true); 355 if (ret) 356 return ret; 357 358 vaddr = kmap_atomic(i915_gem_object_get_page(obj, 359 reloc->offset >> PAGE_SHIFT)); 360 clflush_write32(vaddr + page_offset, lower_32_bits(delta)); 361 362 if (INTEL_INFO(dev)->gen >= 8) { 363 page_offset = offset_in_page(page_offset + sizeof(uint32_t)); 364 365 if (page_offset == 0) { 366 kunmap_atomic(vaddr); 367 vaddr = kmap_atomic(i915_gem_object_get_page(obj, 368 (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT)); 369 } 370 371 clflush_write32(vaddr + page_offset, upper_32_bits(delta)); 372 } 373 374 kunmap_atomic(vaddr); 375 376 return 0; 377 } 378 379 static int 380 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, 381 struct eb_vmas *eb, 382 struct drm_i915_gem_relocation_entry *reloc) 383 { 384 struct drm_device *dev = obj->base.dev; 385 struct drm_gem_object *target_obj; 386 struct drm_i915_gem_object *target_i915_obj; 387 struct i915_vma *target_vma; 388 uint64_t target_offset; 389 int ret; 390 391 /* we've already hold a reference to all valid objects */ 392 target_vma = eb_get_vma(eb, reloc->target_handle); 393 if (unlikely(target_vma == NULL)) 394 return -ENOENT; 395 target_i915_obj = target_vma->obj; 396 target_obj = &target_vma->obj->base; 397 398 target_offset = target_vma->node.start; 399 400 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and 401 * pipe_control writes because the gpu doesn't properly redirect them 402 * through the ppgtt for non_secure batchbuffers. */ 403 if (unlikely(IS_GEN6(dev) && 404 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) { 405 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level, 406 PIN_GLOBAL); 407 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!")) 408 return ret; 409 } 410 411 /* Validate that the target is in a valid r/w GPU domain */ 412 if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) { 413 DRM_DEBUG("reloc with multiple write domains: " 414 "obj %p target %d offset %d " 415 "read %08x write %08x", 416 obj, reloc->target_handle, 417 (int) reloc->offset, 418 reloc->read_domains, 419 reloc->write_domain); 420 return -EINVAL; 421 } 422 if (unlikely((reloc->write_domain | reloc->read_domains) 423 & ~I915_GEM_GPU_DOMAINS)) { 424 DRM_DEBUG("reloc with read/write non-GPU domains: " 425 "obj %p target %d offset %d " 426 "read %08x write %08x", 427 obj, reloc->target_handle, 428 (int) reloc->offset, 429 reloc->read_domains, 430 reloc->write_domain); 431 return -EINVAL; 432 } 433 434 target_obj->pending_read_domains |= reloc->read_domains; 435 target_obj->pending_write_domain |= reloc->write_domain; 436 437 /* If the relocation already has the right value in it, no 438 * more work needs to be done. 439 */ 440 if (target_offset == reloc->presumed_offset) 441 return 0; 442 443 /* Check that the relocation address is valid... */ 444 if (unlikely(reloc->offset > 445 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) { 446 DRM_DEBUG("Relocation beyond object bounds: " 447 "obj %p target %d offset %d size %d.\n", 448 obj, reloc->target_handle, 449 (int) reloc->offset, 450 (int) obj->base.size); 451 return -EINVAL; 452 } 453 if (unlikely(reloc->offset & 3)) { 454 DRM_DEBUG("Relocation not 4-byte aligned: " 455 "obj %p target %d offset %d.\n", 456 obj, reloc->target_handle, 457 (int) reloc->offset); 458 return -EINVAL; 459 } 460 461 /* We can't wait for rendering with pagefaults disabled */ 462 if (obj->active && (curthread->td_flags & TDF_NOFAULT)) 463 return -EFAULT; 464 465 if (use_cpu_reloc(obj)) 466 ret = relocate_entry_cpu(obj, reloc, target_offset); 467 else if (obj->map_and_fenceable) 468 ret = relocate_entry_gtt(obj, reloc, target_offset); 469 else if (cpu_has_clflush) 470 ret = relocate_entry_clflush(obj, reloc, target_offset); 471 else { 472 WARN_ONCE(1, "Impossible case in relocation handling\n"); 473 ret = -ENODEV; 474 } 475 476 if (ret) 477 return ret; 478 479 /* and update the user's relocation entry */ 480 reloc->presumed_offset = target_offset; 481 482 return 0; 483 } 484 485 static int 486 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma, 487 struct eb_vmas *eb) 488 { 489 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry)) 490 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)]; 491 struct drm_i915_gem_relocation_entry __user *user_relocs; 492 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; 493 int remain, ret; 494 495 user_relocs = to_user_ptr(entry->relocs_ptr); 496 497 remain = entry->relocation_count; 498 while (remain) { 499 struct drm_i915_gem_relocation_entry *r = stack_reloc; 500 int count = remain; 501 if (count > ARRAY_SIZE(stack_reloc)) 502 count = ARRAY_SIZE(stack_reloc); 503 remain -= count; 504 505 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0]))) 506 return -EFAULT; 507 508 do { 509 u64 offset = r->presumed_offset; 510 511 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r); 512 if (ret) 513 return ret; 514 515 if (r->presumed_offset != offset && 516 __copy_to_user_inatomic(&user_relocs->presumed_offset, 517 &r->presumed_offset, 518 sizeof(r->presumed_offset))) { 519 return -EFAULT; 520 } 521 522 user_relocs++; 523 r++; 524 } while (--count); 525 } 526 527 return 0; 528 #undef N_RELOC 529 } 530 531 static int 532 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma, 533 struct eb_vmas *eb, 534 struct drm_i915_gem_relocation_entry *relocs) 535 { 536 const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; 537 int i, ret; 538 539 for (i = 0; i < entry->relocation_count; i++) { 540 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]); 541 if (ret) 542 return ret; 543 } 544 545 return 0; 546 } 547 548 static int 549 i915_gem_execbuffer_relocate(struct eb_vmas *eb) 550 { 551 struct i915_vma *vma; 552 int ret = 0; 553 554 /* This is the fast path and we cannot handle a pagefault whilst 555 * holding the struct mutex lest the user pass in the relocations 556 * contained within a mmaped bo. For in such a case we, the page 557 * fault handler would call i915_gem_fault() and we would try to 558 * acquire the struct mutex again. Obviously this is bad and so 559 * lockdep complains vehemently. 560 */ 561 pagefault_disable(); 562 list_for_each_entry(vma, &eb->vmas, exec_list) { 563 ret = i915_gem_execbuffer_relocate_vma(vma, eb); 564 if (ret) 565 break; 566 } 567 pagefault_enable(); 568 569 return ret; 570 } 571 572 static bool only_mappable_for_reloc(unsigned int flags) 573 { 574 return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) == 575 __EXEC_OBJECT_NEEDS_MAP; 576 } 577 578 static int 579 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma, 580 struct intel_engine_cs *ring, 581 bool *need_reloc) 582 { 583 struct drm_i915_gem_object *obj = vma->obj; 584 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; 585 uint64_t flags; 586 int ret; 587 588 flags = PIN_USER; 589 if (entry->flags & EXEC_OBJECT_NEEDS_GTT) 590 flags |= PIN_GLOBAL; 591 592 if (!drm_mm_node_allocated(&vma->node)) { 593 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP) 594 flags |= PIN_GLOBAL | PIN_MAPPABLE; 595 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS) 596 flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS; 597 } 598 599 ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags); 600 if ((ret == -ENOSPC || ret == -E2BIG) && 601 only_mappable_for_reloc(entry->flags)) 602 ret = i915_gem_object_pin(obj, vma->vm, 603 entry->alignment, 604 flags & ~PIN_MAPPABLE); 605 if (ret) 606 return ret; 607 608 entry->flags |= __EXEC_OBJECT_HAS_PIN; 609 610 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { 611 ret = i915_gem_object_get_fence(obj); 612 if (ret) 613 return ret; 614 615 if (i915_gem_object_pin_fence(obj)) 616 entry->flags |= __EXEC_OBJECT_HAS_FENCE; 617 } 618 619 if (entry->offset != vma->node.start) { 620 entry->offset = vma->node.start; 621 *need_reloc = true; 622 } 623 624 if (entry->flags & EXEC_OBJECT_WRITE) { 625 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER; 626 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER; 627 } 628 629 return 0; 630 } 631 632 static bool 633 need_reloc_mappable(struct i915_vma *vma) 634 { 635 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; 636 637 if (entry->relocation_count == 0) 638 return false; 639 640 if (!i915_is_ggtt(vma->vm)) 641 return false; 642 643 /* See also use_cpu_reloc() */ 644 if (HAS_LLC(vma->obj->base.dev)) 645 return false; 646 647 if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU) 648 return false; 649 650 return true; 651 } 652 653 static bool 654 eb_vma_misplaced(struct i915_vma *vma) 655 { 656 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; 657 struct drm_i915_gem_object *obj = vma->obj; 658 659 WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && 660 !i915_is_ggtt(vma->vm)); 661 662 if (entry->alignment && 663 vma->node.start & (entry->alignment - 1)) 664 return true; 665 666 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS && 667 vma->node.start < BATCH_OFFSET_BIAS) 668 return true; 669 670 /* avoid costly ping-pong once a batch bo ended up non-mappable */ 671 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable) 672 return !only_mappable_for_reloc(entry->flags); 673 674 return false; 675 } 676 677 static int 678 i915_gem_execbuffer_reserve(struct intel_engine_cs *ring, 679 struct list_head *vmas, 680 struct intel_context *ctx, 681 bool *need_relocs) 682 { 683 struct drm_i915_gem_object *obj; 684 struct i915_vma *vma; 685 struct i915_address_space *vm; 686 struct list_head ordered_vmas; 687 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; 688 int retry; 689 690 i915_gem_retire_requests_ring(ring); 691 692 vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm; 693 694 INIT_LIST_HEAD(&ordered_vmas); 695 while (!list_empty(vmas)) { 696 struct drm_i915_gem_exec_object2 *entry; 697 bool need_fence, need_mappable; 698 699 vma = list_first_entry(vmas, struct i915_vma, exec_list); 700 obj = vma->obj; 701 entry = vma->exec_entry; 702 703 if (ctx->flags & CONTEXT_NO_ZEROMAP) 704 entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; 705 706 if (!has_fenced_gpu_access) 707 entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE; 708 need_fence = 709 entry->flags & EXEC_OBJECT_NEEDS_FENCE && 710 obj->tiling_mode != I915_TILING_NONE; 711 need_mappable = need_fence || need_reloc_mappable(vma); 712 713 if (need_mappable) { 714 entry->flags |= __EXEC_OBJECT_NEEDS_MAP; 715 list_move(&vma->exec_list, &ordered_vmas); 716 } else 717 list_move_tail(&vma->exec_list, &ordered_vmas); 718 719 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; 720 obj->base.pending_write_domain = 0; 721 } 722 list_splice(&ordered_vmas, vmas); 723 724 /* Attempt to pin all of the buffers into the GTT. 725 * This is done in 3 phases: 726 * 727 * 1a. Unbind all objects that do not match the GTT constraints for 728 * the execbuffer (fenceable, mappable, alignment etc). 729 * 1b. Increment pin count for already bound objects. 730 * 2. Bind new objects. 731 * 3. Decrement pin count. 732 * 733 * This avoid unnecessary unbinding of later objects in order to make 734 * room for the earlier objects *unless* we need to defragment. 735 */ 736 retry = 0; 737 do { 738 int ret = 0; 739 740 /* Unbind any ill-fitting objects or pin. */ 741 list_for_each_entry(vma, vmas, exec_list) { 742 if (!drm_mm_node_allocated(&vma->node)) 743 continue; 744 745 if (eb_vma_misplaced(vma)) 746 ret = i915_vma_unbind(vma); 747 else 748 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); 749 if (ret) 750 goto err; 751 } 752 753 /* Bind fresh objects */ 754 list_for_each_entry(vma, vmas, exec_list) { 755 if (drm_mm_node_allocated(&vma->node)) 756 continue; 757 758 ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs); 759 if (ret) 760 goto err; 761 } 762 763 err: 764 if (ret != -ENOSPC || retry++) 765 return ret; 766 767 /* Decrement pin count for bound objects */ 768 list_for_each_entry(vma, vmas, exec_list) 769 i915_gem_execbuffer_unreserve_vma(vma); 770 771 ret = i915_gem_evict_vm(vm, true); 772 if (ret) 773 return ret; 774 } while (1); 775 } 776 777 static int 778 i915_gem_execbuffer_relocate_slow(struct drm_device *dev, 779 struct drm_i915_gem_execbuffer2 *args, 780 struct drm_file *file, 781 struct intel_engine_cs *ring, 782 struct eb_vmas *eb, 783 struct drm_i915_gem_exec_object2 *exec, 784 struct intel_context *ctx) 785 { 786 struct drm_i915_gem_relocation_entry *reloc; 787 struct i915_address_space *vm; 788 struct i915_vma *vma; 789 bool need_relocs; 790 int *reloc_offset; 791 int i, total, ret; 792 unsigned count = args->buffer_count; 793 794 vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm; 795 796 /* We may process another execbuffer during the unlock... */ 797 while (!list_empty(&eb->vmas)) { 798 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list); 799 list_del_init(&vma->exec_list); 800 i915_gem_execbuffer_unreserve_vma(vma); 801 drm_gem_object_unreference(&vma->obj->base); 802 } 803 804 mutex_unlock(&dev->struct_mutex); 805 806 total = 0; 807 for (i = 0; i < count; i++) 808 total += exec[i].relocation_count; 809 810 reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset)); 811 reloc = drm_malloc_ab(total, sizeof(*reloc)); 812 if (reloc == NULL || reloc_offset == NULL) { 813 drm_free_large(reloc); 814 drm_free_large(reloc_offset); 815 mutex_lock(&dev->struct_mutex); 816 return -ENOMEM; 817 } 818 819 total = 0; 820 for (i = 0; i < count; i++) { 821 struct drm_i915_gem_relocation_entry __user *user_relocs; 822 u64 invalid_offset = (u64)-1; 823 int j; 824 825 user_relocs = to_user_ptr(exec[i].relocs_ptr); 826 827 if (copy_from_user(reloc+total, user_relocs, 828 exec[i].relocation_count * sizeof(*reloc))) { 829 ret = -EFAULT; 830 mutex_lock(&dev->struct_mutex); 831 goto err; 832 } 833 834 /* As we do not update the known relocation offsets after 835 * relocating (due to the complexities in lock handling), 836 * we need to mark them as invalid now so that we force the 837 * relocation processing next time. Just in case the target 838 * object is evicted and then rebound into its old 839 * presumed_offset before the next execbuffer - if that 840 * happened we would make the mistake of assuming that the 841 * relocations were valid. 842 */ 843 for (j = 0; j < exec[i].relocation_count; j++) { 844 if (__copy_to_user(&user_relocs[j].presumed_offset, 845 &invalid_offset, 846 sizeof(invalid_offset))) { 847 ret = -EFAULT; 848 mutex_lock(&dev->struct_mutex); 849 goto err; 850 } 851 } 852 853 reloc_offset[i] = total; 854 total += exec[i].relocation_count; 855 } 856 857 ret = i915_mutex_lock_interruptible(dev); 858 if (ret) { 859 mutex_lock(&dev->struct_mutex); 860 goto err; 861 } 862 863 /* reacquire the objects */ 864 eb_reset(eb); 865 ret = eb_lookup_vmas(eb, exec, args, vm, file); 866 if (ret) 867 goto err; 868 869 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; 870 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs); 871 if (ret) 872 goto err; 873 874 list_for_each_entry(vma, &eb->vmas, exec_list) { 875 int offset = vma->exec_entry - exec; 876 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb, 877 reloc + reloc_offset[offset]); 878 if (ret) 879 goto err; 880 } 881 882 /* Leave the user relocations as are, this is the painfully slow path, 883 * and we want to avoid the complication of dropping the lock whilst 884 * having buffers reserved in the aperture and so causing spurious 885 * ENOSPC for random operations. 886 */ 887 888 err: 889 drm_free_large(reloc); 890 drm_free_large(reloc_offset); 891 return ret; 892 } 893 894 static int 895 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req, 896 struct list_head *vmas) 897 { 898 const unsigned other_rings = ~intel_ring_flag(req->ring); 899 struct i915_vma *vma; 900 uint32_t flush_domains = 0; 901 bool flush_chipset = false; 902 int ret; 903 904 list_for_each_entry(vma, vmas, exec_list) { 905 struct drm_i915_gem_object *obj = vma->obj; 906 907 if (obj->active & other_rings) { 908 ret = i915_gem_object_sync(obj, req->ring, &req); 909 if (ret) 910 return ret; 911 } 912 913 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) 914 flush_chipset |= i915_gem_clflush_object(obj, false); 915 916 flush_domains |= obj->base.write_domain; 917 } 918 919 if (flush_chipset) 920 i915_gem_chipset_flush(req->ring->dev); 921 922 if (flush_domains & I915_GEM_DOMAIN_GTT) 923 wmb(); 924 925 /* Unconditionally invalidate gpu caches and ensure that we do flush 926 * any residual writes from the previous batch. 927 */ 928 return intel_ring_invalidate_all_caches(req); 929 } 930 931 static bool 932 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec) 933 { 934 if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS) 935 return false; 936 937 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0; 938 } 939 940 static int 941 validate_exec_list(struct drm_device *dev, 942 struct drm_i915_gem_exec_object2 *exec, 943 int count) 944 { 945 unsigned relocs_total = 0; 946 unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry); 947 unsigned invalid_flags; 948 int i; 949 950 invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS; 951 if (USES_FULL_PPGTT(dev)) 952 invalid_flags |= EXEC_OBJECT_NEEDS_GTT; 953 954 for (i = 0; i < count; i++) { 955 char __user *ptr = to_user_ptr(exec[i].relocs_ptr); 956 int length; /* limited by fault_in_pages_readable() */ 957 958 if (exec[i].flags & invalid_flags) 959 return -EINVAL; 960 961 if (exec[i].alignment && !is_power_of_2(exec[i].alignment)) 962 return -EINVAL; 963 964 /* First check for malicious input causing overflow in 965 * the worst case where we need to allocate the entire 966 * relocation tree as a single array. 967 */ 968 if (exec[i].relocation_count > relocs_max - relocs_total) 969 return -EINVAL; 970 relocs_total += exec[i].relocation_count; 971 972 length = exec[i].relocation_count * 973 sizeof(struct drm_i915_gem_relocation_entry); 974 /* 975 * We must check that the entire relocation array is safe 976 * to read, but since we may need to update the presumed 977 * offsets during execution, check for full write access. 978 */ 979 #if 0 980 if (!access_ok(VERIFY_WRITE, ptr, length)) 981 return -EFAULT; 982 #endif 983 984 if (likely(!i915.prefault_disable)) { 985 if (fault_in_multipages_readable(ptr, length)) 986 return -EFAULT; 987 } 988 } 989 990 return 0; 991 } 992 993 static struct intel_context * 994 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file, 995 struct intel_engine_cs *ring, const u32 ctx_id) 996 { 997 struct intel_context *ctx = NULL; 998 struct i915_ctx_hang_stats *hs; 999 1000 if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE) 1001 return ERR_PTR(-EINVAL); 1002 1003 ctx = i915_gem_context_get(file->driver_priv, ctx_id); 1004 if (IS_ERR(ctx)) 1005 return ctx; 1006 1007 hs = &ctx->hang_stats; 1008 if (hs->banned) { 1009 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id); 1010 return ERR_PTR(-EIO); 1011 } 1012 1013 if (i915.enable_execlists && !ctx->engine[ring->id].state) { 1014 int ret = intel_lr_context_deferred_create(ctx, ring); 1015 if (ret) { 1016 DRM_DEBUG("Could not create LRC %u: %d\n", ctx_id, ret); 1017 return ERR_PTR(ret); 1018 } 1019 } 1020 1021 return ctx; 1022 } 1023 1024 void 1025 i915_gem_execbuffer_move_to_active(struct list_head *vmas, 1026 struct drm_i915_gem_request *req) 1027 { 1028 struct intel_engine_cs *ring = i915_gem_request_get_ring(req); 1029 struct i915_vma *vma; 1030 1031 list_for_each_entry(vma, vmas, exec_list) { 1032 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry; 1033 struct drm_i915_gem_object *obj = vma->obj; 1034 u32 old_read = obj->base.read_domains; 1035 u32 old_write = obj->base.write_domain; 1036 1037 obj->dirty = 1; /* be paranoid */ 1038 obj->base.write_domain = obj->base.pending_write_domain; 1039 if (obj->base.write_domain == 0) 1040 obj->base.pending_read_domains |= obj->base.read_domains; 1041 obj->base.read_domains = obj->base.pending_read_domains; 1042 1043 i915_vma_move_to_active(vma, req); 1044 if (obj->base.write_domain) { 1045 i915_gem_request_assign(&obj->last_write_req, req); 1046 1047 intel_fb_obj_invalidate(obj, ORIGIN_CS); 1048 1049 /* update for the implicit flush after a batch */ 1050 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; 1051 } 1052 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) { 1053 i915_gem_request_assign(&obj->last_fenced_req, req); 1054 if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { 1055 struct drm_i915_private *dev_priv = to_i915(ring->dev); 1056 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list, 1057 &dev_priv->mm.fence_list); 1058 } 1059 } 1060 1061 trace_i915_gem_object_change_domain(obj, old_read, old_write); 1062 } 1063 } 1064 1065 void 1066 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params) 1067 { 1068 /* Unconditionally force add_request to emit a full flush. */ 1069 params->ring->gpu_caches_dirty = true; 1070 1071 /* Add a breadcrumb for the completion of the batch buffer */ 1072 __i915_add_request(params->request, params->batch_obj, true); 1073 } 1074 1075 static int 1076 i915_reset_gen7_sol_offsets(struct drm_device *dev, 1077 struct drm_i915_gem_request *req) 1078 { 1079 struct intel_engine_cs *ring = req->ring; 1080 struct drm_i915_private *dev_priv = dev->dev_private; 1081 int ret, i; 1082 1083 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) { 1084 DRM_DEBUG("sol reset is gen7/rcs only\n"); 1085 return -EINVAL; 1086 } 1087 1088 ret = intel_ring_begin(req, 4 * 3); 1089 if (ret) 1090 return ret; 1091 1092 for (i = 0; i < 4; i++) { 1093 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 1094 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); 1095 intel_ring_emit(ring, 0); 1096 } 1097 1098 intel_ring_advance(ring); 1099 1100 return 0; 1101 } 1102 1103 static int 1104 i915_emit_box(struct drm_i915_gem_request *req, 1105 struct drm_clip_rect *box, 1106 int DR1, int DR4) 1107 { 1108 struct intel_engine_cs *ring = req->ring; 1109 int ret; 1110 1111 if (box->y2 <= box->y1 || box->x2 <= box->x1 || 1112 box->y2 <= 0 || box->x2 <= 0) { 1113 DRM_ERROR("Bad box %d,%d..%d,%d\n", 1114 box->x1, box->y1, box->x2, box->y2); 1115 return -EINVAL; 1116 } 1117 1118 if (INTEL_INFO(ring->dev)->gen >= 4) { 1119 ret = intel_ring_begin(req, 4); 1120 if (ret) 1121 return ret; 1122 1123 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965); 1124 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); 1125 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); 1126 intel_ring_emit(ring, DR4); 1127 } else { 1128 ret = intel_ring_begin(req, 6); 1129 if (ret) 1130 return ret; 1131 1132 intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO); 1133 intel_ring_emit(ring, DR1); 1134 intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16); 1135 intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16); 1136 intel_ring_emit(ring, DR4); 1137 intel_ring_emit(ring, 0); 1138 } 1139 intel_ring_advance(ring); 1140 1141 return 0; 1142 } 1143 1144 static struct drm_i915_gem_object* 1145 i915_gem_execbuffer_parse(struct intel_engine_cs *ring, 1146 struct drm_i915_gem_exec_object2 *shadow_exec_entry, 1147 struct eb_vmas *eb, 1148 struct drm_i915_gem_object *batch_obj, 1149 u32 batch_start_offset, 1150 u32 batch_len, 1151 bool is_master) 1152 { 1153 struct drm_i915_gem_object *shadow_batch_obj; 1154 struct i915_vma *vma; 1155 int ret; 1156 1157 shadow_batch_obj = i915_gem_batch_pool_get(&ring->batch_pool, 1158 PAGE_ALIGN(batch_len)); 1159 if (IS_ERR(shadow_batch_obj)) 1160 return shadow_batch_obj; 1161 1162 ret = i915_parse_cmds(ring, 1163 batch_obj, 1164 shadow_batch_obj, 1165 batch_start_offset, 1166 batch_len, 1167 is_master); 1168 if (ret) 1169 goto err; 1170 1171 ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0); 1172 if (ret) 1173 goto err; 1174 1175 i915_gem_object_unpin_pages(shadow_batch_obj); 1176 1177 memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry)); 1178 1179 vma = i915_gem_obj_to_ggtt(shadow_batch_obj); 1180 vma->exec_entry = shadow_exec_entry; 1181 vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN; 1182 drm_gem_object_reference(&shadow_batch_obj->base); 1183 list_add_tail(&vma->exec_list, &eb->vmas); 1184 1185 shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND; 1186 1187 return shadow_batch_obj; 1188 1189 err: 1190 i915_gem_object_unpin_pages(shadow_batch_obj); 1191 if (ret == -EACCES) /* unhandled chained batch */ 1192 return batch_obj; 1193 else 1194 return ERR_PTR(ret); 1195 } 1196 1197 int 1198 i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, 1199 struct drm_i915_gem_execbuffer2 *args, 1200 struct list_head *vmas) 1201 { 1202 struct drm_clip_rect *cliprects = NULL; 1203 struct drm_device *dev = params->dev; 1204 struct intel_engine_cs *ring = params->ring; 1205 struct drm_i915_private *dev_priv = dev->dev_private; 1206 u64 exec_start, exec_len; 1207 int instp_mode; 1208 u32 instp_mask; 1209 int i, ret = 0; 1210 1211 if (args->num_cliprects != 0) { 1212 if (ring != &dev_priv->ring[RCS]) { 1213 DRM_DEBUG("clip rectangles are only valid with the render ring\n"); 1214 return -EINVAL; 1215 } 1216 1217 if (INTEL_INFO(dev)->gen >= 5) { 1218 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); 1219 return -EINVAL; 1220 } 1221 1222 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) { 1223 DRM_DEBUG("execbuf with %u cliprects\n", 1224 args->num_cliprects); 1225 return -EINVAL; 1226 } 1227 1228 cliprects = kcalloc(args->num_cliprects, 1229 sizeof(*cliprects), 1230 GFP_KERNEL); 1231 if (cliprects == NULL) { 1232 ret = -ENOMEM; 1233 goto error; 1234 } 1235 1236 if (copy_from_user(cliprects, 1237 to_user_ptr(args->cliprects_ptr), 1238 sizeof(*cliprects)*args->num_cliprects)) { 1239 ret = -EFAULT; 1240 goto error; 1241 } 1242 } else { 1243 if (args->DR4 == 0xffffffff) { 1244 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); 1245 args->DR4 = 0; 1246 } 1247 1248 if (args->DR1 || args->DR4 || args->cliprects_ptr) { 1249 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); 1250 return -EINVAL; 1251 } 1252 } 1253 1254 ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas); 1255 if (ret) 1256 goto error; 1257 1258 ret = i915_switch_context(params->request); 1259 if (ret) 1260 goto error; 1261 1262 WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id), 1263 "%s didn't clear reload\n", ring->name); 1264 1265 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; 1266 instp_mask = I915_EXEC_CONSTANTS_MASK; 1267 switch (instp_mode) { 1268 case I915_EXEC_CONSTANTS_REL_GENERAL: 1269 case I915_EXEC_CONSTANTS_ABSOLUTE: 1270 case I915_EXEC_CONSTANTS_REL_SURFACE: 1271 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { 1272 DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); 1273 ret = -EINVAL; 1274 goto error; 1275 } 1276 1277 if (instp_mode != dev_priv->relative_constants_mode) { 1278 if (INTEL_INFO(dev)->gen < 4) { 1279 DRM_DEBUG("no rel constants on pre-gen4\n"); 1280 ret = -EINVAL; 1281 goto error; 1282 } 1283 1284 if (INTEL_INFO(dev)->gen > 5 && 1285 instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { 1286 DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); 1287 ret = -EINVAL; 1288 goto error; 1289 } 1290 1291 /* The HW changed the meaning on this bit on gen6 */ 1292 if (INTEL_INFO(dev)->gen >= 6) 1293 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; 1294 } 1295 break; 1296 default: 1297 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); 1298 ret = -EINVAL; 1299 goto error; 1300 } 1301 1302 if (ring == &dev_priv->ring[RCS] && 1303 instp_mode != dev_priv->relative_constants_mode) { 1304 ret = intel_ring_begin(params->request, 4); 1305 if (ret) 1306 goto error; 1307 1308 intel_ring_emit(ring, MI_NOOP); 1309 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 1310 intel_ring_emit(ring, INSTPM); 1311 intel_ring_emit(ring, instp_mask << 16 | instp_mode); 1312 intel_ring_advance(ring); 1313 1314 dev_priv->relative_constants_mode = instp_mode; 1315 } 1316 1317 if (args->flags & I915_EXEC_GEN7_SOL_RESET) { 1318 ret = i915_reset_gen7_sol_offsets(dev, params->request); 1319 if (ret) 1320 goto error; 1321 } 1322 1323 exec_len = args->batch_len; 1324 exec_start = params->batch_obj_vm_offset + 1325 params->args_batch_start_offset; 1326 1327 if (cliprects) { 1328 for (i = 0; i < args->num_cliprects; i++) { 1329 ret = i915_emit_box(params->request, &cliprects[i], 1330 args->DR1, args->DR4); 1331 if (ret) 1332 goto error; 1333 1334 ret = ring->dispatch_execbuffer(params->request, 1335 exec_start, exec_len, 1336 params->dispatch_flags); 1337 if (ret) 1338 goto error; 1339 } 1340 } else { 1341 ret = ring->dispatch_execbuffer(params->request, 1342 exec_start, exec_len, 1343 params->dispatch_flags); 1344 if (ret) 1345 return ret; 1346 } 1347 1348 trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); 1349 1350 i915_gem_execbuffer_move_to_active(vmas, params->request); 1351 i915_gem_execbuffer_retire_commands(params); 1352 1353 error: 1354 kfree(cliprects); 1355 return ret; 1356 } 1357 1358 /** 1359 * Find one BSD ring to dispatch the corresponding BSD command. 1360 * The Ring ID is returned. 1361 */ 1362 static int gen8_dispatch_bsd_ring(struct drm_device *dev, 1363 struct drm_file *file) 1364 { 1365 struct drm_i915_private *dev_priv = dev->dev_private; 1366 struct drm_i915_file_private *file_priv = file->driver_priv; 1367 1368 /* Check whether the file_priv is using one ring */ 1369 if (file_priv->bsd_ring) 1370 return file_priv->bsd_ring->id; 1371 else { 1372 /* If no, use the ping-pong mechanism to select one ring */ 1373 int ring_id; 1374 1375 mutex_lock(&dev->struct_mutex); 1376 if (dev_priv->mm.bsd_ring_dispatch_index == 0) { 1377 ring_id = VCS; 1378 dev_priv->mm.bsd_ring_dispatch_index = 1; 1379 } else { 1380 ring_id = VCS2; 1381 dev_priv->mm.bsd_ring_dispatch_index = 0; 1382 } 1383 file_priv->bsd_ring = &dev_priv->ring[ring_id]; 1384 mutex_unlock(&dev->struct_mutex); 1385 return ring_id; 1386 } 1387 } 1388 1389 static struct drm_i915_gem_object * 1390 eb_get_batch(struct eb_vmas *eb) 1391 { 1392 struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list); 1393 1394 /* 1395 * SNA is doing fancy tricks with compressing batch buffers, which leads 1396 * to negative relocation deltas. Usually that works out ok since the 1397 * relocate address is still positive, except when the batch is placed 1398 * very low in the GTT. Ensure this doesn't happen. 1399 * 1400 * Note that actual hangs have only been observed on gen7, but for 1401 * paranoia do it everywhere. 1402 */ 1403 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS; 1404 1405 return vma->obj; 1406 } 1407 1408 static int 1409 i915_gem_do_execbuffer(struct drm_device *dev, void *data, 1410 struct drm_file *file, 1411 struct drm_i915_gem_execbuffer2 *args, 1412 struct drm_i915_gem_exec_object2 *exec) 1413 { 1414 struct drm_i915_private *dev_priv = dev->dev_private; 1415 struct eb_vmas *eb; 1416 struct drm_i915_gem_object *batch_obj; 1417 struct drm_i915_gem_exec_object2 shadow_exec_entry; 1418 struct intel_engine_cs *ring; 1419 struct intel_context *ctx; 1420 struct i915_address_space *vm; 1421 struct i915_execbuffer_params params_master; /* XXX: will be removed later */ 1422 struct i915_execbuffer_params *params = ¶ms_master; 1423 const u32 ctx_id = i915_execbuffer2_get_context_id(*args); 1424 u32 dispatch_flags; 1425 int ret; 1426 bool need_relocs; 1427 1428 if (!i915_gem_check_execbuffer(args)) 1429 return -EINVAL; 1430 1431 ret = validate_exec_list(dev, exec, args->buffer_count); 1432 if (ret) 1433 return ret; 1434 1435 dispatch_flags = 0; 1436 if (args->flags & I915_EXEC_SECURE) { 1437 dispatch_flags |= I915_DISPATCH_SECURE; 1438 } 1439 if (args->flags & I915_EXEC_IS_PINNED) 1440 dispatch_flags |= I915_DISPATCH_PINNED; 1441 1442 if ((args->flags & I915_EXEC_RING_MASK) > LAST_USER_RING) { 1443 DRM_DEBUG("execbuf with unknown ring: %d\n", 1444 (int)(args->flags & I915_EXEC_RING_MASK)); 1445 return -EINVAL; 1446 } 1447 1448 if (((args->flags & I915_EXEC_RING_MASK) != I915_EXEC_BSD) && 1449 ((args->flags & I915_EXEC_BSD_MASK) != 0)) { 1450 DRM_DEBUG("execbuf with non bsd ring but with invalid " 1451 "bsd dispatch flags: %d\n", (int)(args->flags)); 1452 return -EINVAL; 1453 } 1454 1455 if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_DEFAULT) 1456 ring = &dev_priv->ring[RCS]; 1457 else if ((args->flags & I915_EXEC_RING_MASK) == I915_EXEC_BSD) { 1458 if (HAS_BSD2(dev)) { 1459 int ring_id; 1460 1461 switch (args->flags & I915_EXEC_BSD_MASK) { 1462 case I915_EXEC_BSD_DEFAULT: 1463 ring_id = gen8_dispatch_bsd_ring(dev, file); 1464 ring = &dev_priv->ring[ring_id]; 1465 break; 1466 case I915_EXEC_BSD_RING1: 1467 ring = &dev_priv->ring[VCS]; 1468 break; 1469 case I915_EXEC_BSD_RING2: 1470 ring = &dev_priv->ring[VCS2]; 1471 break; 1472 default: 1473 DRM_DEBUG("execbuf with unknown bsd ring: %d\n", 1474 (int)(args->flags & I915_EXEC_BSD_MASK)); 1475 return -EINVAL; 1476 } 1477 } else 1478 ring = &dev_priv->ring[VCS]; 1479 } else 1480 ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1]; 1481 1482 if (!intel_ring_initialized(ring)) { 1483 DRM_DEBUG("execbuf with invalid ring: %d\n", 1484 (int)(args->flags & I915_EXEC_RING_MASK)); 1485 return -EINVAL; 1486 } 1487 1488 if (args->buffer_count < 1) { 1489 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); 1490 return -EINVAL; 1491 } 1492 1493 if (args->flags & I915_EXEC_RESOURCE_STREAMER) { 1494 if (!HAS_RESOURCE_STREAMER(dev)) { 1495 DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n"); 1496 return -EINVAL; 1497 } 1498 if (ring->id != RCS) { 1499 DRM_DEBUG("RS is not available on %s\n", 1500 ring->name); 1501 return -EINVAL; 1502 } 1503 1504 dispatch_flags |= I915_DISPATCH_RS; 1505 } 1506 1507 intel_runtime_pm_get(dev_priv); 1508 1509 ret = i915_mutex_lock_interruptible(dev); 1510 if (ret) 1511 goto pre_mutex_err; 1512 1513 ctx = i915_gem_validate_context(dev, file, ring, ctx_id); 1514 if (IS_ERR(ctx)) { 1515 mutex_unlock(&dev->struct_mutex); 1516 ret = PTR_ERR(ctx); 1517 goto pre_mutex_err; 1518 } 1519 1520 i915_gem_context_reference(ctx); 1521 1522 if (ctx->ppgtt) 1523 vm = &ctx->ppgtt->base; 1524 else 1525 vm = &dev_priv->gtt.base; 1526 1527 memset(¶ms_master, 0x00, sizeof(params_master)); 1528 1529 eb = eb_create(args); 1530 if (eb == NULL) { 1531 i915_gem_context_unreference(ctx); 1532 mutex_unlock(&dev->struct_mutex); 1533 ret = -ENOMEM; 1534 goto pre_mutex_err; 1535 } 1536 1537 /* Look up object handles */ 1538 ret = eb_lookup_vmas(eb, exec, args, vm, file); 1539 if (ret) 1540 goto err; 1541 1542 /* take note of the batch buffer before we might reorder the lists */ 1543 batch_obj = eb_get_batch(eb); 1544 1545 /* Move the objects en-masse into the GTT, evicting if necessary. */ 1546 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0; 1547 ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, ctx, &need_relocs); 1548 if (ret) 1549 goto err; 1550 1551 /* The objects are in their final locations, apply the relocations. */ 1552 if (need_relocs) 1553 ret = i915_gem_execbuffer_relocate(eb); 1554 if (ret) { 1555 if (ret == -EFAULT) { 1556 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, 1557 eb, exec, ctx); 1558 BUG_ON(!mutex_is_locked(&dev->struct_mutex)); 1559 } 1560 if (ret) 1561 goto err; 1562 } 1563 1564 /* Set the pending read domains for the batch buffer to COMMAND */ 1565 if (batch_obj->base.pending_write_domain) { 1566 DRM_DEBUG("Attempting to use self-modifying batch buffer\n"); 1567 ret = -EINVAL; 1568 goto err; 1569 } 1570 1571 params->args_batch_start_offset = args->batch_start_offset; 1572 if (i915_needs_cmd_parser(ring) && args->batch_len) { 1573 struct drm_i915_gem_object *parsed_batch_obj; 1574 1575 parsed_batch_obj = i915_gem_execbuffer_parse(ring, 1576 &shadow_exec_entry, 1577 eb, 1578 batch_obj, 1579 args->batch_start_offset, 1580 args->batch_len, 1581 file->is_master); 1582 if (IS_ERR(parsed_batch_obj)) { 1583 ret = PTR_ERR(parsed_batch_obj); 1584 goto err; 1585 } 1586 1587 /* 1588 * parsed_batch_obj == batch_obj means batch not fully parsed: 1589 * Accept, but don't promote to secure. 1590 */ 1591 1592 if (parsed_batch_obj != batch_obj) { 1593 /* 1594 * Batch parsed and accepted: 1595 * 1596 * Set the DISPATCH_SECURE bit to remove the NON_SECURE 1597 * bit from MI_BATCH_BUFFER_START commands issued in 1598 * the dispatch_execbuffer implementations. We 1599 * specifically don't want that set on batches the 1600 * command parser has accepted. 1601 */ 1602 dispatch_flags |= I915_DISPATCH_SECURE; 1603 params->args_batch_start_offset = 0; 1604 batch_obj = parsed_batch_obj; 1605 } 1606 } 1607 1608 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; 1609 1610 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure 1611 * batch" bit. Hence we need to pin secure batches into the global gtt. 1612 * hsw should have this fixed, but bdw mucks it up again. */ 1613 if (dispatch_flags & I915_DISPATCH_SECURE) { 1614 /* 1615 * So on first glance it looks freaky that we pin the batch here 1616 * outside of the reservation loop. But: 1617 * - The batch is already pinned into the relevant ppgtt, so we 1618 * already have the backing storage fully allocated. 1619 * - No other BO uses the global gtt (well contexts, but meh), 1620 * so we don't really have issues with multiple objects not 1621 * fitting due to fragmentation. 1622 * So this is actually safe. 1623 */ 1624 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0); 1625 if (ret) 1626 goto err; 1627 1628 params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj); 1629 } else 1630 params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm); 1631 1632 /* Allocate a request for this batch buffer nice and early. */ 1633 ret = i915_gem_request_alloc(ring, ctx, ¶ms->request); 1634 if (ret) 1635 goto err_batch_unpin; 1636 1637 ret = i915_gem_request_add_to_client(params->request, file); 1638 if (ret) 1639 goto err_batch_unpin; 1640 1641 /* 1642 * Save assorted stuff away to pass through to *_submission(). 1643 * NB: This data should be 'persistent' and not local as it will 1644 * kept around beyond the duration of the IOCTL once the GPU 1645 * scheduler arrives. 1646 */ 1647 params->dev = dev; 1648 params->file = file; 1649 params->ring = ring; 1650 params->dispatch_flags = dispatch_flags; 1651 params->batch_obj = batch_obj; 1652 params->ctx = ctx; 1653 1654 ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas); 1655 1656 err_batch_unpin: 1657 /* 1658 * FIXME: We crucially rely upon the active tracking for the (ppgtt) 1659 * batch vma for correctness. For less ugly and less fragility this 1660 * needs to be adjusted to also track the ggtt batch vma properly as 1661 * active. 1662 */ 1663 if (dispatch_flags & I915_DISPATCH_SECURE) 1664 i915_gem_object_ggtt_unpin(batch_obj); 1665 1666 err: 1667 /* the request owns the ref now */ 1668 i915_gem_context_unreference(ctx); 1669 eb_destroy(eb); 1670 1671 /* 1672 * If the request was created but not successfully submitted then it 1673 * must be freed again. If it was submitted then it is being tracked 1674 * on the active request list and no clean up is required here. 1675 */ 1676 if (ret && params->request) 1677 i915_gem_request_cancel(params->request); 1678 1679 mutex_unlock(&dev->struct_mutex); 1680 1681 pre_mutex_err: 1682 /* intel_gpu_busy should also get a ref, so it will free when the device 1683 * is really idle. */ 1684 intel_runtime_pm_put(dev_priv); 1685 return ret; 1686 } 1687 1688 /* 1689 * Legacy execbuffer just creates an exec2 list from the original exec object 1690 * list array and passes it to the real function. 1691 */ 1692 int 1693 i915_gem_execbuffer(struct drm_device *dev, void *data, 1694 struct drm_file *file) 1695 { 1696 struct drm_i915_gem_execbuffer *args = data; 1697 struct drm_i915_gem_execbuffer2 exec2; 1698 struct drm_i915_gem_exec_object *exec_list = NULL; 1699 struct drm_i915_gem_exec_object2 *exec2_list = NULL; 1700 int ret, i; 1701 1702 if (args->buffer_count < 1) { 1703 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count); 1704 return -EINVAL; 1705 } 1706 1707 /* Copy in the exec list from userland */ 1708 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); 1709 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); 1710 if (exec_list == NULL || exec2_list == NULL) { 1711 DRM_DEBUG("Failed to allocate exec list for %d buffers\n", 1712 args->buffer_count); 1713 drm_free_large(exec_list); 1714 drm_free_large(exec2_list); 1715 return -ENOMEM; 1716 } 1717 ret = copy_from_user(exec_list, 1718 to_user_ptr(args->buffers_ptr), 1719 sizeof(*exec_list) * args->buffer_count); 1720 if (ret != 0) { 1721 DRM_DEBUG("copy %d exec entries failed %d\n", 1722 args->buffer_count, ret); 1723 drm_free_large(exec_list); 1724 drm_free_large(exec2_list); 1725 return -EFAULT; 1726 } 1727 1728 for (i = 0; i < args->buffer_count; i++) { 1729 exec2_list[i].handle = exec_list[i].handle; 1730 exec2_list[i].relocation_count = exec_list[i].relocation_count; 1731 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; 1732 exec2_list[i].alignment = exec_list[i].alignment; 1733 exec2_list[i].offset = exec_list[i].offset; 1734 if (INTEL_INFO(dev)->gen < 4) 1735 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; 1736 else 1737 exec2_list[i].flags = 0; 1738 } 1739 1740 exec2.buffers_ptr = args->buffers_ptr; 1741 exec2.buffer_count = args->buffer_count; 1742 exec2.batch_start_offset = args->batch_start_offset; 1743 exec2.batch_len = args->batch_len; 1744 exec2.DR1 = args->DR1; 1745 exec2.DR4 = args->DR4; 1746 exec2.num_cliprects = args->num_cliprects; 1747 exec2.cliprects_ptr = args->cliprects_ptr; 1748 exec2.flags = I915_EXEC_RENDER; 1749 i915_execbuffer2_set_context_id(exec2, 0); 1750 1751 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); 1752 if (!ret) { 1753 struct drm_i915_gem_exec_object __user *user_exec_list = 1754 to_user_ptr(args->buffers_ptr); 1755 1756 /* Copy the new buffer offsets back to the user's exec list. */ 1757 for (i = 0; i < args->buffer_count; i++) { 1758 ret = __copy_to_user(&user_exec_list[i].offset, 1759 &exec2_list[i].offset, 1760 sizeof(user_exec_list[i].offset)); 1761 if (ret) { 1762 ret = -EFAULT; 1763 DRM_DEBUG("failed to copy %d exec entries " 1764 "back to user (%d)\n", 1765 args->buffer_count, ret); 1766 break; 1767 } 1768 } 1769 } 1770 1771 drm_free_large(exec_list); 1772 drm_free_large(exec2_list); 1773 return ret; 1774 } 1775 1776 int 1777 i915_gem_execbuffer2(struct drm_device *dev, void *data, 1778 struct drm_file *file) 1779 { 1780 struct drm_i915_gem_execbuffer2 *args = data; 1781 struct drm_i915_gem_exec_object2 *exec2_list = NULL; 1782 int ret; 1783 1784 if (args->buffer_count < 1 || 1785 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { 1786 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count); 1787 return -EINVAL; 1788 } 1789 1790 if (args->rsvd2 != 0) { 1791 DRM_DEBUG("dirty rvsd2 field\n"); 1792 return -EINVAL; 1793 } 1794 1795 exec2_list = kmalloc(sizeof(*exec2_list)*args->buffer_count, 1796 M_DRM, M_NOWAIT); 1797 if (exec2_list == NULL) 1798 exec2_list = drm_malloc_ab(sizeof(*exec2_list), 1799 args->buffer_count); 1800 if (exec2_list == NULL) { 1801 DRM_DEBUG("Failed to allocate exec list for %d buffers\n", 1802 args->buffer_count); 1803 return -ENOMEM; 1804 } 1805 ret = copy_from_user(exec2_list, 1806 to_user_ptr(args->buffers_ptr), 1807 sizeof(*exec2_list) * args->buffer_count); 1808 if (ret != 0) { 1809 DRM_DEBUG("copy %d exec entries failed %d\n", 1810 args->buffer_count, ret); 1811 drm_free_large(exec2_list); 1812 return -EFAULT; 1813 } 1814 1815 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); 1816 if (!ret) { 1817 /* Copy the new buffer offsets back to the user's exec list. */ 1818 struct drm_i915_gem_exec_object2 __user *user_exec_list = 1819 to_user_ptr(args->buffers_ptr); 1820 int i; 1821 1822 for (i = 0; i < args->buffer_count; i++) { 1823 ret = __copy_to_user(&user_exec_list[i].offset, 1824 &exec2_list[i].offset, 1825 sizeof(user_exec_list[i].offset)); 1826 if (ret) { 1827 ret = -EFAULT; 1828 DRM_DEBUG("failed to copy %d exec entries " 1829 "back to user\n", 1830 args->buffer_count); 1831 break; 1832 } 1833 } 1834 } 1835 1836 drm_free_large(exec2_list); 1837 return ret; 1838 } 1839