1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 struct drm_i915_file_private; 38 39 typedef uint32_t gen6_pte_t; 40 typedef uint64_t gen8_pte_t; 41 typedef uint64_t gen8_pde_t; 42 typedef uint64_t gen8_ppgtt_pdpe_t; 43 typedef uint64_t gen8_ppgtt_pml4e_t; 44 45 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 46 47 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 48 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 49 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 50 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 51 #define GEN6_PTE_CACHE_LLC (2 << 1) 52 #define GEN6_PTE_UNCACHED (1 << 1) 53 #define GEN6_PTE_VALID (1 << 0) 54 55 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 56 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 57 #define I915_PDES 512 58 #define I915_PDE_MASK (I915_PDES - 1) 59 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 60 61 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 62 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 63 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 64 #define GEN6_PDE_SHIFT 22 65 #define GEN6_PDE_VALID (1 << 0) 66 67 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 68 69 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 70 #define BYT_PTE_WRITEABLE (1 << 1) 71 72 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 73 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 74 */ 75 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 76 (((bits) & 0x8) << (11 - 3))) 77 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 78 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 79 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 80 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 81 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 82 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 83 #define HSW_PTE_UNCACHED (0) 84 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 85 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 86 87 /* GEN8 legacy style address is defined as a 3 level page table: 88 * 31:30 | 29:21 | 20:12 | 11:0 89 * PDPE | PDE | PTE | offset 90 * The difference as compared to normal x86 3 level page table is the PDPEs are 91 * programmed via register. 92 * 93 * GEN8 48b legacy style address is defined as a 4 level page table: 94 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 95 * PML4E | PDPE | PDE | PTE | offset 96 */ 97 #define GEN8_PML4ES_PER_PML4 512 98 #define GEN8_PML4E_SHIFT 39 99 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 100 #define GEN8_PDPE_SHIFT 30 101 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 102 * tables */ 103 #define GEN8_PDPE_MASK 0x1ff 104 #define GEN8_PDE_SHIFT 21 105 #define GEN8_PDE_MASK 0x1ff 106 #define GEN8_PTE_SHIFT 12 107 #define GEN8_PTE_MASK 0x1ff 108 #define GEN8_LEGACY_PDPES 4 109 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 110 111 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ 112 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 113 114 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 115 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 116 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 117 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 118 119 #define CHV_PPAT_SNOOP (1<<6) 120 #define GEN8_PPAT_AGE(x) (x<<4) 121 #define GEN8_PPAT_LLCeLLC (3<<2) 122 #define GEN8_PPAT_LLCELLC (2<<2) 123 #define GEN8_PPAT_LLC (1<<2) 124 #define GEN8_PPAT_WB (3<<0) 125 #define GEN8_PPAT_WT (2<<0) 126 #define GEN8_PPAT_WC (1<<0) 127 #define GEN8_PPAT_UC (0<<0) 128 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 129 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 130 131 enum i915_ggtt_view_type { 132 I915_GGTT_VIEW_NORMAL = 0, 133 I915_GGTT_VIEW_ROTATED, 134 I915_GGTT_VIEW_PARTIAL, 135 }; 136 137 struct intel_rotation_info { 138 unsigned int uv_offset; 139 uint32_t pixel_format; 140 unsigned int uv_start_page; 141 struct { 142 /* tiles */ 143 unsigned int width, height; 144 } plane[2]; 145 }; 146 147 struct i915_ggtt_view { 148 enum i915_ggtt_view_type type; 149 150 union { 151 struct { 152 u64 offset; 153 unsigned int size; 154 } partial; 155 struct intel_rotation_info rotated; 156 } params; 157 158 struct sg_table *pages; 159 }; 160 161 extern const struct i915_ggtt_view i915_ggtt_view_normal; 162 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 163 164 enum i915_cache_level; 165 166 /** 167 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 168 * VMA's presence cannot be guaranteed before binding, or after unbinding the 169 * object into/from the address space. 170 * 171 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 172 * will always be <= an objects lifetime. So object refcounting should cover us. 173 */ 174 struct i915_vma { 175 struct drm_mm_node node; 176 struct drm_i915_gem_object *obj; 177 struct i915_address_space *vm; 178 179 /** Flags and address space this VMA is bound to */ 180 #define GLOBAL_BIND (1<<0) 181 #define LOCAL_BIND (1<<1) 182 unsigned int bound : 4; 183 bool is_ggtt : 1; 184 185 /** 186 * Support different GGTT views into the same object. 187 * This means there can be multiple VMA mappings per object and per VM. 188 * i915_ggtt_view_type is used to distinguish between those entries. 189 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 190 * assumed in GEM functions which take no ggtt view parameter. 191 */ 192 struct i915_ggtt_view ggtt_view; 193 194 /** This object's place on the active/inactive lists */ 195 struct list_head vm_link; 196 197 struct list_head obj_link; /* Link in the object's VMA list */ 198 199 /** This vma's place in the batchbuffer or on the eviction list */ 200 struct list_head exec_list; 201 202 /** 203 * Used for performing relocations during execbuffer insertion. 204 */ 205 struct hlist_node exec_node; 206 unsigned long exec_handle; 207 struct drm_i915_gem_exec_object2 *exec_entry; 208 209 /** 210 * How many users have pinned this object in GTT space. The following 211 * users can each hold at most one reference: pwrite/pread, execbuffer 212 * (objects are not allowed multiple times for the same batchbuffer), 213 * and the framebuffer code. When switching/pageflipping, the 214 * framebuffer code has at most two buffers pinned per crtc. 215 * 216 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 217 * bits with absolutely no headroom. So use 4 bits. */ 218 unsigned int pin_count:4; 219 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 220 }; 221 222 struct i915_page_dma { 223 struct vm_page *page; 224 union { 225 dma_addr_t daddr; 226 227 /* For gen6/gen7 only. This is the offset in the GGTT 228 * where the page directory entries for PPGTT begin 229 */ 230 uint32_t ggtt_offset; 231 }; 232 }; 233 234 #define px_base(px) (&(px)->base) 235 #define px_page(px) (px_base(px)->page) 236 #define px_dma(px) (px_base(px)->daddr) 237 238 struct i915_page_scratch { 239 struct i915_page_dma base; 240 }; 241 242 struct i915_page_table { 243 struct i915_page_dma base; 244 245 unsigned long *used_ptes; 246 }; 247 248 struct i915_page_directory { 249 struct i915_page_dma base; 250 251 unsigned long *used_pdes; 252 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 253 }; 254 255 struct i915_page_directory_pointer { 256 struct i915_page_dma base; 257 258 unsigned long *used_pdpes; 259 struct i915_page_directory **page_directory; 260 }; 261 262 struct i915_pml4 { 263 struct i915_page_dma base; 264 265 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 266 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 267 }; 268 269 struct i915_address_space { 270 struct drm_mm mm; 271 struct drm_device *dev; 272 struct list_head global_link; 273 u64 start; /* Start offset always 0 for dri2 */ 274 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 275 276 bool is_ggtt; 277 278 struct i915_page_scratch *scratch_page; 279 struct i915_page_table *scratch_pt; 280 struct i915_page_directory *scratch_pd; 281 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 282 283 /** 284 * List of objects currently involved in rendering. 285 * 286 * Includes buffers having the contents of their GPU caches 287 * flushed, not necessarily primitives. last_read_req 288 * represents when the rendering involved will be completed. 289 * 290 * A reference is held on the buffer while on this list. 291 */ 292 struct list_head active_list; 293 294 /** 295 * LRU list of objects which are not in the ringbuffer and 296 * are ready to unbind, but are still in the GTT. 297 * 298 * last_read_req is NULL while an object is in this list. 299 * 300 * A reference is not held on the buffer while on this list, 301 * as merely being GTT-bound shouldn't prevent its being 302 * freed, and we'll pull it off the list in the free path. 303 */ 304 struct list_head inactive_list; 305 306 /* FIXME: Need a more generic return type */ 307 gen6_pte_t (*pte_encode)(dma_addr_t addr, 308 enum i915_cache_level level, 309 bool valid, u32 flags); /* Create a valid PTE */ 310 /* flags for pte_encode */ 311 #define PTE_READ_ONLY (1<<0) 312 int (*allocate_va_range)(struct i915_address_space *vm, 313 uint64_t start, 314 uint64_t length); 315 void (*clear_range)(struct i915_address_space *vm, 316 uint64_t start, 317 uint64_t length, 318 bool use_scratch); 319 void (*insert_entries)(struct i915_address_space *vm, 320 struct sg_table *st, 321 uint64_t start, 322 enum i915_cache_level cache_level, u32 flags); 323 void (*cleanup)(struct i915_address_space *vm); 324 /** Unmap an object from an address space. This usually consists of 325 * setting the valid PTE entries to a reserved scratch page. */ 326 void (*unbind_vma)(struct i915_vma *vma); 327 /* Map an object into an address space with the given cache flags. */ 328 int (*bind_vma)(struct i915_vma *vma, 329 enum i915_cache_level cache_level, 330 u32 flags); 331 }; 332 333 #define i915_is_ggtt(V) ((V)->is_ggtt) 334 335 /* The Graphics Translation Table is the way in which GEN hardware translates a 336 * Graphics Virtual Address into a Physical Address. In addition to the normal 337 * collateral associated with any va->pa translations GEN hardware also has a 338 * portion of the GTT which can be mapped by the CPU and remain both coherent 339 * and correct (in cases like swizzling). That region is referred to as GMADR in 340 * the spec. 341 */ 342 struct i915_ggtt { 343 struct i915_address_space base; 344 345 size_t stolen_size; /* Total size of stolen memory */ 346 size_t stolen_usable_size; /* Total size minus BIOS reserved */ 347 size_t stolen_reserved_base; 348 size_t stolen_reserved_size; 349 size_t size; /* Total size of Global GTT */ 350 u64 mappable_end; /* End offset that we can CPU map */ 351 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 352 phys_addr_t mappable_base; /* PA of our GMADR */ 353 354 /** "Graphics Stolen Memory" holds the global PTEs */ 355 void __iomem *gsm; 356 357 bool do_idle_maps; 358 359 int mtrr; 360 361 int (*probe)(struct i915_ggtt *ggtt); 362 }; 363 364 struct i915_hw_ppgtt { 365 struct i915_address_space base; 366 struct kref ref; 367 struct drm_mm_node node; 368 unsigned long pd_dirty_rings; 369 union { 370 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 371 struct i915_page_directory_pointer pdp; /* GEN8+ */ 372 struct i915_page_directory pd; /* GEN6-7 */ 373 }; 374 375 struct drm_i915_file_private *file_priv; 376 377 gen6_pte_t __iomem *pd_addr; 378 379 int (*enable)(struct i915_hw_ppgtt *ppgtt); 380 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 381 struct drm_i915_gem_request *req); 382 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 383 }; 384 385 /* For each pde iterates over every pde between from start until start + length. 386 * If start, and start+length are not perfectly divisible, the macro will round 387 * down, and up as needed. The macro modifies pde, start, and length. Dev is 388 * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, 389 * and length = 2G effectively iterates over every PDE in the system. 390 * 391 * XXX: temp is not actually needed, but it saves doing the ALIGN operation. 392 */ 393 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ 394 for (iter = gen6_pde_index(start); \ 395 length > 0 && iter < I915_PDES ? \ 396 (pt = (pd)->page_table[iter]), 1 : 0; \ 397 iter++, \ 398 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ 399 temp = min_t(unsigned, temp, length), \ 400 start += temp, length -= temp) 401 402 #define gen6_for_all_pdes(pt, ppgtt, iter) \ 403 for (iter = 0; \ 404 pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ 405 iter++) 406 407 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 408 { 409 const uint32_t mask = NUM_PTE(pde_shift) - 1; 410 411 return (address >> PAGE_SHIFT) & mask; 412 } 413 414 /* Helper to counts the number of PTEs within the given length. This count 415 * does not cross a page table boundary, so the max value would be 416 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 417 */ 418 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 419 uint32_t pde_shift) 420 { 421 const uint64_t mask = ~((1ULL << pde_shift) - 1); 422 uint64_t end; 423 424 WARN_ON(length == 0); 425 WARN_ON(offset_in_page(addr|length)); 426 427 end = addr + length; 428 429 if ((addr & mask) != (end & mask)) 430 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 431 432 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 433 } 434 435 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 436 { 437 return (addr >> shift) & I915_PDE_MASK; 438 } 439 440 static inline uint32_t gen6_pte_index(uint32_t addr) 441 { 442 return i915_pte_index(addr, GEN6_PDE_SHIFT); 443 } 444 445 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 446 { 447 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 448 } 449 450 static inline uint32_t gen6_pde_index(uint32_t addr) 451 { 452 return i915_pde_index(addr, GEN6_PDE_SHIFT); 453 } 454 455 /* Equivalent to the gen6 version, For each pde iterates over every pde 456 * between from start until start + length. On gen8+ it simply iterates 457 * over every page directory entry in a page directory. 458 */ 459 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 460 for (iter = gen8_pde_index(start); \ 461 length > 0 && iter < I915_PDES && \ 462 (pt = (pd)->page_table[iter], true); \ 463 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 464 temp = min(temp - start, length); \ 465 start += temp, length -= temp; }), ++iter) 466 467 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 468 for (iter = gen8_pdpe_index(start); \ 469 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ 470 (pd = (pdp)->page_directory[iter], true); \ 471 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 472 temp = min(temp - start, length); \ 473 start += temp, length -= temp; }), ++iter) 474 475 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 476 for (iter = gen8_pml4e_index(start); \ 477 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 478 (pdp = (pml4)->pdps[iter], true); \ 479 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 480 temp = min(temp - start, length); \ 481 start += temp, length -= temp; }), ++iter) 482 483 static inline uint32_t gen8_pte_index(uint64_t address) 484 { 485 return i915_pte_index(address, GEN8_PDE_SHIFT); 486 } 487 488 static inline uint32_t gen8_pde_index(uint64_t address) 489 { 490 return i915_pde_index(address, GEN8_PDE_SHIFT); 491 } 492 493 static inline uint32_t gen8_pdpe_index(uint64_t address) 494 { 495 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 496 } 497 498 static inline uint32_t gen8_pml4e_index(uint64_t address) 499 { 500 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 501 } 502 503 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 504 { 505 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 506 } 507 508 static inline dma_addr_t 509 i915_page_dir_dma_addr(struct i915_hw_ppgtt *ppgtt, const unsigned n) 510 { 511 return test_bit(n, ppgtt->pdp.used_pdpes) ? 512 px_dma(ppgtt->pdp.page_directory[n]) : 513 px_dma(ppgtt->base.scratch_pd); 514 } 515 516 int i915_ggtt_init_hw(struct drm_device *dev); 517 int i915_ggtt_enable_hw(struct drm_device *dev); 518 void i915_gem_init_ggtt(struct drm_device *dev); 519 void i915_ggtt_cleanup_hw(struct drm_device *dev); 520 521 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); 522 int i915_ppgtt_init_hw(struct drm_device *dev); 523 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req); 524 void i915_ppgtt_release(struct kref *kref); 525 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, 526 struct drm_i915_file_private *fpriv); 527 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 528 { 529 if (ppgtt) 530 kref_get(&ppgtt->ref); 531 } 532 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 533 { 534 if (ppgtt) 535 kref_put(&ppgtt->ref, i915_ppgtt_release); 536 } 537 538 void i915_check_and_clear_faults(struct drm_device *dev); 539 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 540 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 541 542 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 543 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 544 545 static inline bool 546 i915_ggtt_view_equal(const struct i915_ggtt_view *a, 547 const struct i915_ggtt_view *b) 548 { 549 if (WARN_ON(!a || !b)) 550 return false; 551 552 if (a->type != b->type) 553 return false; 554 if (a->type != I915_GGTT_VIEW_NORMAL) 555 return !memcmp(&a->params, &b->params, sizeof(a->params)); 556 return true; 557 } 558 559 size_t 560 i915_ggtt_view_size(struct drm_i915_gem_object *obj, 561 const struct i915_ggtt_view *view); 562 563 #endif 564