1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 struct drm_i915_file_private; 38 39 typedef uint32_t gen6_pte_t; 40 typedef uint64_t gen8_pte_t; 41 typedef uint64_t gen8_pde_t; 42 typedef uint64_t gen8_ppgtt_pdpe_t; 43 typedef uint64_t gen8_ppgtt_pml4e_t; 44 45 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 46 47 #define I915_GTT_PAGE_SIZE_4K (1ULL << 12) 48 #define I915_GTT_PAGE_MASK -I915_GTT_PAGE_SIZE_4K 49 50 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 51 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 52 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 53 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 54 #define GEN6_PTE_CACHE_LLC (2 << 1) 55 #define GEN6_PTE_UNCACHED (1 << 1) 56 #define GEN6_PTE_VALID (1 << 0) 57 58 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 59 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 60 #define I915_PDES 512 61 #define I915_PDE_MASK (I915_PDES - 1) 62 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 63 64 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 65 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 66 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 67 #define GEN6_PDE_SHIFT 22 68 #define GEN6_PDE_VALID (1 << 0) 69 70 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 71 72 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 73 #define BYT_PTE_WRITEABLE (1 << 1) 74 75 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 76 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 77 */ 78 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 79 (((bits) & 0x8) << (11 - 3))) 80 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 81 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 82 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 83 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 84 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 85 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 86 #define HSW_PTE_UNCACHED (0) 87 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 88 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 89 90 /* GEN8 legacy style address is defined as a 3 level page table: 91 * 31:30 | 29:21 | 20:12 | 11:0 92 * PDPE | PDE | PTE | offset 93 * The difference as compared to normal x86 3 level page table is the PDPEs are 94 * programmed via register. 95 * 96 * GEN8 48b legacy style address is defined as a 4 level page table: 97 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 98 * PML4E | PDPE | PDE | PTE | offset 99 */ 100 #define GEN8_PML4ES_PER_PML4 512 101 #define GEN8_PML4E_SHIFT 39 102 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 103 #define GEN8_PDPE_SHIFT 30 104 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 105 * tables */ 106 #define GEN8_PDPE_MASK 0x1ff 107 #define GEN8_PDE_SHIFT 21 108 #define GEN8_PDE_MASK 0x1ff 109 #define GEN8_PTE_SHIFT 12 110 #define GEN8_PTE_MASK 0x1ff 111 #define GEN8_LEGACY_PDPES 4 112 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 113 114 #define I915_PDPES_PER_PDP(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ 115 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 116 117 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 118 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 119 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 120 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 121 122 #define CHV_PPAT_SNOOP (1<<6) 123 #define GEN8_PPAT_AGE(x) (x<<4) 124 #define GEN8_PPAT_LLCeLLC (3<<2) 125 #define GEN8_PPAT_LLCELLC (2<<2) 126 #define GEN8_PPAT_LLC (1<<2) 127 #define GEN8_PPAT_WB (3<<0) 128 #define GEN8_PPAT_WT (2<<0) 129 #define GEN8_PPAT_WC (1<<0) 130 #define GEN8_PPAT_UC (0<<0) 131 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 132 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 133 134 enum i915_ggtt_view_type { 135 I915_GGTT_VIEW_NORMAL = 0, 136 I915_GGTT_VIEW_ROTATED, 137 I915_GGTT_VIEW_PARTIAL, 138 }; 139 140 struct intel_rotation_info { 141 unsigned int uv_offset; 142 uint32_t pixel_format; 143 unsigned int uv_start_page; 144 struct { 145 /* tiles */ 146 unsigned int width, height; 147 } plane[2]; 148 }; 149 150 struct i915_ggtt_view { 151 enum i915_ggtt_view_type type; 152 153 union { 154 struct { 155 u64 offset; 156 unsigned int size; 157 } partial; 158 struct intel_rotation_info rotated; 159 } params; 160 161 struct sg_table *pages; 162 }; 163 164 extern const struct i915_ggtt_view i915_ggtt_view_normal; 165 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 166 167 enum i915_cache_level; 168 169 /** 170 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 171 * VMA's presence cannot be guaranteed before binding, or after unbinding the 172 * object into/from the address space. 173 * 174 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 175 * will always be <= an objects lifetime. So object refcounting should cover us. 176 */ 177 struct i915_vma { 178 struct drm_mm_node node; 179 struct drm_i915_gem_object *obj; 180 struct i915_address_space *vm; 181 182 /** Flags and address space this VMA is bound to */ 183 #define GLOBAL_BIND (1<<0) 184 #define LOCAL_BIND (1<<1) 185 unsigned int bound : 4; 186 bool is_ggtt : 1; 187 188 /** 189 * Support different GGTT views into the same object. 190 * This means there can be multiple VMA mappings per object and per VM. 191 * i915_ggtt_view_type is used to distinguish between those entries. 192 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 193 * assumed in GEM functions which take no ggtt view parameter. 194 */ 195 struct i915_ggtt_view ggtt_view; 196 197 /** This object's place on the active/inactive lists */ 198 struct list_head vm_link; 199 200 struct list_head obj_link; /* Link in the object's VMA list */ 201 202 /** This vma's place in the batchbuffer or on the eviction list */ 203 struct list_head exec_list; 204 205 /** 206 * Used for performing relocations during execbuffer insertion. 207 */ 208 struct hlist_node exec_node; 209 unsigned long exec_handle; 210 struct drm_i915_gem_exec_object2 *exec_entry; 211 212 /** 213 * How many users have pinned this object in GTT space. The following 214 * users can each hold at most one reference: pwrite/pread, execbuffer 215 * (objects are not allowed multiple times for the same batchbuffer), 216 * and the framebuffer code. When switching/pageflipping, the 217 * framebuffer code has at most two buffers pinned per crtc. 218 * 219 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 220 * bits with absolutely no headroom. So use 4 bits. */ 221 unsigned int pin_count:4; 222 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 223 }; 224 225 struct i915_page_dma { 226 struct page *page; 227 union { 228 dma_addr_t daddr; 229 230 /* For gen6/gen7 only. This is the offset in the GGTT 231 * where the page directory entries for PPGTT begin 232 */ 233 uint32_t ggtt_offset; 234 }; 235 }; 236 237 #define px_base(px) (&(px)->base) 238 #define px_page(px) (px_base(px)->page) 239 #define px_dma(px) (px_base(px)->daddr) 240 241 struct i915_page_scratch { 242 struct i915_page_dma base; 243 }; 244 245 struct i915_page_table { 246 struct i915_page_dma base; 247 248 unsigned long *used_ptes; 249 }; 250 251 struct i915_page_directory { 252 struct i915_page_dma base; 253 254 unsigned long *used_pdes; 255 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 256 }; 257 258 struct i915_page_directory_pointer { 259 struct i915_page_dma base; 260 261 unsigned long *used_pdpes; 262 struct i915_page_directory **page_directory; 263 }; 264 265 struct i915_pml4 { 266 struct i915_page_dma base; 267 268 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 269 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 270 }; 271 272 struct i915_address_space { 273 struct drm_mm mm; 274 struct drm_device *dev; 275 struct list_head global_link; 276 u64 start; /* Start offset always 0 for dri2 */ 277 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 278 279 bool is_ggtt; 280 281 struct i915_page_scratch *scratch_page; 282 struct i915_page_table *scratch_pt; 283 struct i915_page_directory *scratch_pd; 284 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 285 286 /** 287 * List of objects currently involved in rendering. 288 * 289 * Includes buffers having the contents of their GPU caches 290 * flushed, not necessarily primitives. last_read_req 291 * represents when the rendering involved will be completed. 292 * 293 * A reference is held on the buffer while on this list. 294 */ 295 struct list_head active_list; 296 297 /** 298 * LRU list of objects which are not in the ringbuffer and 299 * are ready to unbind, but are still in the GTT. 300 * 301 * last_read_req is NULL while an object is in this list. 302 * 303 * A reference is not held on the buffer while on this list, 304 * as merely being GTT-bound shouldn't prevent its being 305 * freed, and we'll pull it off the list in the free path. 306 */ 307 struct list_head inactive_list; 308 309 /* FIXME: Need a more generic return type */ 310 gen6_pte_t (*pte_encode)(dma_addr_t addr, 311 enum i915_cache_level level, 312 bool valid, u32 flags); /* Create a valid PTE */ 313 /* flags for pte_encode */ 314 #define PTE_READ_ONLY (1<<0) 315 int (*allocate_va_range)(struct i915_address_space *vm, 316 uint64_t start, 317 uint64_t length); 318 void (*clear_range)(struct i915_address_space *vm, 319 uint64_t start, 320 uint64_t length, 321 bool use_scratch); 322 void (*insert_entries)(struct i915_address_space *vm, 323 struct sg_table *st, 324 uint64_t start, 325 enum i915_cache_level cache_level, u32 flags); 326 void (*cleanup)(struct i915_address_space *vm); 327 /** Unmap an object from an address space. This usually consists of 328 * setting the valid PTE entries to a reserved scratch page. */ 329 void (*unbind_vma)(struct i915_vma *vma); 330 /* Map an object into an address space with the given cache flags. */ 331 int (*bind_vma)(struct i915_vma *vma, 332 enum i915_cache_level cache_level, 333 u32 flags); 334 }; 335 336 #define i915_is_ggtt(V) ((V)->is_ggtt) 337 338 /* The Graphics Translation Table is the way in which GEN hardware translates a 339 * Graphics Virtual Address into a Physical Address. In addition to the normal 340 * collateral associated with any va->pa translations GEN hardware also has a 341 * portion of the GTT which can be mapped by the CPU and remain both coherent 342 * and correct (in cases like swizzling). That region is referred to as GMADR in 343 * the spec. 344 */ 345 struct i915_ggtt { 346 struct i915_address_space base; 347 348 size_t stolen_size; /* Total size of stolen memory */ 349 size_t stolen_usable_size; /* Total size minus BIOS reserved */ 350 size_t stolen_reserved_base; 351 size_t stolen_reserved_size; 352 size_t size; /* Total size of Global GTT */ 353 u64 mappable_end; /* End offset that we can CPU map */ 354 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 355 phys_addr_t mappable_base; /* PA of our GMADR */ 356 357 /** "Graphics Stolen Memory" holds the global PTEs */ 358 void __iomem *gsm; 359 360 bool do_idle_maps; 361 362 int mtrr; 363 364 int (*probe)(struct i915_ggtt *ggtt); 365 }; 366 367 struct i915_hw_ppgtt { 368 struct i915_address_space base; 369 struct kref ref; 370 struct drm_mm_node node; 371 unsigned long pd_dirty_rings; 372 union { 373 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 374 struct i915_page_directory_pointer pdp; /* GEN8+ */ 375 struct i915_page_directory pd; /* GEN6-7 */ 376 }; 377 378 struct drm_i915_file_private *file_priv; 379 380 gen6_pte_t __iomem *pd_addr; 381 382 int (*enable)(struct i915_hw_ppgtt *ppgtt); 383 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 384 struct drm_i915_gem_request *req); 385 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 386 }; 387 388 /* For each pde iterates over every pde between from start until start + length. 389 * If start, and start+length are not perfectly divisible, the macro will round 390 * down, and up as needed. The macro modifies pde, start, and length. Dev is 391 * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, 392 * and length = 2G effectively iterates over every PDE in the system. 393 * 394 * XXX: temp is not actually needed, but it saves doing the ALIGN operation. 395 */ 396 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ 397 for (iter = gen6_pde_index(start); \ 398 length > 0 && iter < I915_PDES ? \ 399 (pt = (pd)->page_table[iter]), 1 : 0; \ 400 iter++, \ 401 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ 402 temp = min_t(unsigned, temp, length), \ 403 start += temp, length -= temp) 404 405 #define gen6_for_all_pdes(pt, ppgtt, iter) \ 406 for (iter = 0; \ 407 pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ 408 iter++) 409 410 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 411 { 412 const uint32_t mask = NUM_PTE(pde_shift) - 1; 413 414 return (address >> PAGE_SHIFT) & mask; 415 } 416 417 /* Helper to counts the number of PTEs within the given length. This count 418 * does not cross a page table boundary, so the max value would be 419 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 420 */ 421 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 422 uint32_t pde_shift) 423 { 424 const uint64_t mask = ~((1ULL << pde_shift) - 1); 425 uint64_t end; 426 427 WARN_ON(length == 0); 428 WARN_ON(offset_in_page(addr|length)); 429 430 end = addr + length; 431 432 if ((addr & mask) != (end & mask)) 433 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 434 435 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 436 } 437 438 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 439 { 440 return (addr >> shift) & I915_PDE_MASK; 441 } 442 443 static inline uint32_t gen6_pte_index(uint32_t addr) 444 { 445 return i915_pte_index(addr, GEN6_PDE_SHIFT); 446 } 447 448 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 449 { 450 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 451 } 452 453 static inline uint32_t gen6_pde_index(uint32_t addr) 454 { 455 return i915_pde_index(addr, GEN6_PDE_SHIFT); 456 } 457 458 /* Equivalent to the gen6 version, For each pde iterates over every pde 459 * between from start until start + length. On gen8+ it simply iterates 460 * over every page directory entry in a page directory. 461 */ 462 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 463 for (iter = gen8_pde_index(start); \ 464 length > 0 && iter < I915_PDES && \ 465 (pt = (pd)->page_table[iter], true); \ 466 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 467 temp = min(temp - start, length); \ 468 start += temp, length -= temp; }), ++iter) 469 470 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 471 for (iter = gen8_pdpe_index(start); \ 472 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ 473 (pd = (pdp)->page_directory[iter], true); \ 474 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 475 temp = min(temp - start, length); \ 476 start += temp, length -= temp; }), ++iter) 477 478 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 479 for (iter = gen8_pml4e_index(start); \ 480 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 481 (pdp = (pml4)->pdps[iter], true); \ 482 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 483 temp = min(temp - start, length); \ 484 start += temp, length -= temp; }), ++iter) 485 486 static inline uint32_t gen8_pte_index(uint64_t address) 487 { 488 return i915_pte_index(address, GEN8_PDE_SHIFT); 489 } 490 491 static inline uint32_t gen8_pde_index(uint64_t address) 492 { 493 return i915_pde_index(address, GEN8_PDE_SHIFT); 494 } 495 496 static inline uint32_t gen8_pdpe_index(uint64_t address) 497 { 498 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 499 } 500 501 static inline uint32_t gen8_pml4e_index(uint64_t address) 502 { 503 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 504 } 505 506 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 507 { 508 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 509 } 510 511 static inline dma_addr_t 512 i915_page_dir_dma_addr(struct i915_hw_ppgtt *ppgtt, const unsigned n) 513 { 514 return test_bit(n, ppgtt->pdp.used_pdpes) ? 515 px_dma(ppgtt->pdp.page_directory[n]) : 516 px_dma(ppgtt->base.scratch_pd); 517 } 518 519 int i915_ggtt_init_hw(struct drm_device *dev); 520 int i915_ggtt_enable_hw(struct drm_device *dev); 521 void i915_gem_init_ggtt(struct drm_device *dev); 522 void i915_ggtt_cleanup_hw(struct drm_device *dev); 523 524 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); 525 int i915_ppgtt_init_hw(struct drm_device *dev); 526 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req); 527 void i915_ppgtt_release(struct kref *kref); 528 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, 529 struct drm_i915_file_private *fpriv); 530 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 531 { 532 if (ppgtt) 533 kref_get(&ppgtt->ref); 534 } 535 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 536 { 537 if (ppgtt) 538 kref_put(&ppgtt->ref, i915_ppgtt_release); 539 } 540 541 void i915_check_and_clear_faults(struct drm_device *dev); 542 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 543 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 544 545 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 546 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 547 548 static inline bool 549 i915_ggtt_view_equal(const struct i915_ggtt_view *a, 550 const struct i915_ggtt_view *b) 551 { 552 if (WARN_ON(!a || !b)) 553 return false; 554 555 if (a->type != b->type) 556 return false; 557 if (a->type != I915_GGTT_VIEW_NORMAL) 558 return !memcmp(&a->params, &b->params, sizeof(a->params)); 559 return true; 560 } 561 562 size_t 563 i915_ggtt_view_size(struct drm_i915_gem_object *obj, 564 const struct i915_ggtt_view *view); 565 566 #endif 567