1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/io-mapping.h> 38 #include <linux/mm.h> 39 40 #include "i915_gem_timeline.h" 41 #include "i915_gem_request.h" 42 43 #define I915_FENCE_REG_NONE -1 44 #define I915_MAX_NUM_FENCES 32 45 /* 32 fences + sign bit for FENCE_REG_NONE */ 46 #define I915_MAX_NUM_FENCE_BITS 6 47 48 struct drm_i915_file_private; 49 struct drm_i915_fence_reg; 50 51 typedef uint32_t gen6_pte_t; 52 typedef uint64_t gen8_pte_t; 53 typedef uint64_t gen8_pde_t; 54 typedef uint64_t gen8_ppgtt_pdpe_t; 55 typedef uint64_t gen8_ppgtt_pml4e_t; 56 57 #define ggtt_total_entries(ggtt) ((ggtt)->base.total >> PAGE_SHIFT) 58 59 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 60 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 61 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 62 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 63 #define GEN6_PTE_CACHE_LLC (2 << 1) 64 #define GEN6_PTE_UNCACHED (1 << 1) 65 #define GEN6_PTE_VALID (1 << 0) 66 67 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 68 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 69 #define I915_PDES 512 70 #define I915_PDE_MASK (I915_PDES - 1) 71 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 72 73 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 74 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 75 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 76 #define GEN6_PDE_SHIFT 22 77 #define GEN6_PDE_VALID (1 << 0) 78 79 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 80 81 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 82 #define BYT_PTE_WRITEABLE (1 << 1) 83 84 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 85 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 86 */ 87 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 88 (((bits) & 0x8) << (11 - 3))) 89 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 90 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 91 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 92 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 93 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 94 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 95 #define HSW_PTE_UNCACHED (0) 96 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 97 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 98 99 /* GEN8 legacy style address is defined as a 3 level page table: 100 * 31:30 | 29:21 | 20:12 | 11:0 101 * PDPE | PDE | PTE | offset 102 * The difference as compared to normal x86 3 level page table is the PDPEs are 103 * programmed via register. 104 * 105 * GEN8 48b legacy style address is defined as a 4 level page table: 106 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0 107 * PML4E | PDPE | PDE | PTE | offset 108 */ 109 #define GEN8_PML4ES_PER_PML4 512 110 #define GEN8_PML4E_SHIFT 39 111 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1) 112 #define GEN8_PDPE_SHIFT 30 113 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page 114 * tables */ 115 #define GEN8_PDPE_MASK 0x1ff 116 #define GEN8_PDE_SHIFT 21 117 #define GEN8_PDE_MASK 0x1ff 118 #define GEN8_PTE_SHIFT 12 119 #define GEN8_PTE_MASK 0x1ff 120 #define GEN8_LEGACY_PDPES 4 121 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 122 123 #define I915_PDPES_PER_PDP(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\ 124 GEN8_PML4ES_PER_PML4 : GEN8_LEGACY_PDPES) 125 126 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 127 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 128 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 129 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 130 131 #define CHV_PPAT_SNOOP (1<<6) 132 #define GEN8_PPAT_AGE(x) (x<<4) 133 #define GEN8_PPAT_LLCeLLC (3<<2) 134 #define GEN8_PPAT_LLCELLC (2<<2) 135 #define GEN8_PPAT_LLC (1<<2) 136 #define GEN8_PPAT_WB (3<<0) 137 #define GEN8_PPAT_WT (2<<0) 138 #define GEN8_PPAT_WC (1<<0) 139 #define GEN8_PPAT_UC (0<<0) 140 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 141 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 142 143 struct sg_table; 144 145 enum i915_ggtt_view_type { 146 I915_GGTT_VIEW_NORMAL = 0, 147 I915_GGTT_VIEW_ROTATED, 148 I915_GGTT_VIEW_PARTIAL, 149 }; 150 151 struct intel_rotation_info { 152 struct { 153 /* tiles */ 154 unsigned int width, height, stride, offset; 155 } plane[2]; 156 }; 157 158 struct i915_ggtt_view { 159 enum i915_ggtt_view_type type; 160 161 union { 162 struct { 163 u64 offset; 164 unsigned int size; 165 } partial; 166 struct intel_rotation_info rotated; 167 } params; 168 }; 169 170 extern const struct i915_ggtt_view i915_ggtt_view_normal; 171 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 172 173 enum i915_cache_level; 174 175 struct i915_vma; 176 177 struct i915_page_dma { 178 struct page *page; 179 union { 180 dma_addr_t daddr; 181 182 /* For gen6/gen7 only. This is the offset in the GGTT 183 * where the page directory entries for PPGTT begin 184 */ 185 uint32_t ggtt_offset; 186 }; 187 }; 188 189 #define px_base(px) (&(px)->base) 190 #define px_page(px) (px_base(px)->page) 191 #define px_dma(px) (px_base(px)->daddr) 192 193 struct i915_page_table { 194 struct i915_page_dma base; 195 196 unsigned long *used_ptes; 197 }; 198 199 struct i915_page_directory { 200 struct i915_page_dma base; 201 202 unsigned long *used_pdes; 203 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 204 }; 205 206 struct i915_page_directory_pointer { 207 struct i915_page_dma base; 208 209 unsigned long *used_pdpes; 210 struct i915_page_directory **page_directory; 211 }; 212 213 struct i915_pml4 { 214 struct i915_page_dma base; 215 216 DECLARE_BITMAP(used_pml4es, GEN8_PML4ES_PER_PML4); 217 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4]; 218 }; 219 220 struct i915_address_space { 221 struct drm_mm mm; 222 struct i915_gem_timeline timeline; 223 struct drm_device *dev; 224 /* Every address space belongs to a struct file - except for the global 225 * GTT that is owned by the driver (and so @file is set to NULL). In 226 * principle, no information should leak from one context to another 227 * (or between files/processes etc) unless explicitly shared by the 228 * owner. Tracking the owner is important in order to free up per-file 229 * objects along with the file, to aide resource tracking, and to 230 * assign blame. 231 */ 232 struct drm_i915_file_private *file; 233 struct list_head global_link; 234 u64 start; /* Start offset always 0 for dri2 */ 235 u64 total; /* size addr space maps (ex. 2GB for ggtt) */ 236 237 bool closed; 238 239 struct i915_page_dma scratch_page; 240 struct i915_page_table *scratch_pt; 241 struct i915_page_directory *scratch_pd; 242 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */ 243 244 /** 245 * List of objects currently involved in rendering. 246 * 247 * Includes buffers having the contents of their GPU caches 248 * flushed, not necessarily primitives. last_read_req 249 * represents when the rendering involved will be completed. 250 * 251 * A reference is held on the buffer while on this list. 252 */ 253 struct list_head active_list; 254 255 /** 256 * LRU list of objects which are not in the ringbuffer and 257 * are ready to unbind, but are still in the GTT. 258 * 259 * last_read_req is NULL while an object is in this list. 260 * 261 * A reference is not held on the buffer while on this list, 262 * as merely being GTT-bound shouldn't prevent its being 263 * freed, and we'll pull it off the list in the free path. 264 */ 265 struct list_head inactive_list; 266 267 /** 268 * List of vma that have been unbound. 269 * 270 * A reference is not held on the buffer while on this list. 271 */ 272 struct list_head unbound_list; 273 274 /* FIXME: Need a more generic return type */ 275 gen6_pte_t (*pte_encode)(dma_addr_t addr, 276 enum i915_cache_level level, 277 u32 flags); /* Create a valid PTE */ 278 /* flags for pte_encode */ 279 #define PTE_READ_ONLY (1<<0) 280 int (*allocate_va_range)(struct i915_address_space *vm, 281 uint64_t start, 282 uint64_t length); 283 void (*clear_range)(struct i915_address_space *vm, 284 uint64_t start, 285 uint64_t length); 286 void (*insert_page)(struct i915_address_space *vm, 287 dma_addr_t addr, 288 uint64_t offset, 289 enum i915_cache_level cache_level, 290 u32 flags); 291 void (*insert_entries)(struct i915_address_space *vm, 292 struct sg_table *st, 293 uint64_t start, 294 enum i915_cache_level cache_level, u32 flags); 295 void (*cleanup)(struct i915_address_space *vm); 296 /** Unmap an object from an address space. This usually consists of 297 * setting the valid PTE entries to a reserved scratch page. */ 298 void (*unbind_vma)(struct i915_vma *vma); 299 /* Map an object into an address space with the given cache flags. */ 300 int (*bind_vma)(struct i915_vma *vma, 301 enum i915_cache_level cache_level, 302 u32 flags); 303 }; 304 305 #define i915_is_ggtt(V) (!(V)->file) 306 307 /* The Graphics Translation Table is the way in which GEN hardware translates a 308 * Graphics Virtual Address into a Physical Address. In addition to the normal 309 * collateral associated with any va->pa translations GEN hardware also has a 310 * portion of the GTT which can be mapped by the CPU and remain both coherent 311 * and correct (in cases like swizzling). That region is referred to as GMADR in 312 * the spec. 313 */ 314 struct i915_ggtt { 315 struct i915_address_space base; 316 struct io_mapping mappable; /* Mapping to our CPU mappable region */ 317 318 size_t stolen_size; /* Total size of stolen memory */ 319 size_t stolen_usable_size; /* Total size minus BIOS reserved */ 320 size_t stolen_reserved_base; 321 size_t stolen_reserved_size; 322 u64 mappable_end; /* End offset that we can CPU map */ 323 phys_addr_t mappable_base; /* PA of our GMADR */ 324 325 /** "Graphics Stolen Memory" holds the global PTEs */ 326 void __iomem *gsm; 327 328 bool do_idle_maps; 329 330 int mtrr; 331 332 struct drm_mm_node error_capture; 333 }; 334 335 struct i915_hw_ppgtt { 336 struct i915_address_space base; 337 struct kref ref; 338 struct drm_mm_node node; 339 unsigned long pd_dirty_rings; 340 union { 341 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */ 342 struct i915_page_directory_pointer pdp; /* GEN8+ */ 343 struct i915_page_directory pd; /* GEN6-7 */ 344 }; 345 346 gen6_pte_t __iomem *pd_addr; 347 348 int (*enable)(struct i915_hw_ppgtt *ppgtt); 349 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 350 struct drm_i915_gem_request *req); 351 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 352 }; 353 354 /* 355 * gen6_for_each_pde() iterates over every pde from start until start+length. 356 * If start and start+length are not perfectly divisible, the macro will round 357 * down and up as needed. Start=0 and length=2G effectively iterates over 358 * every PDE in the system. The macro modifies ALL its parameters except 'pd', 359 * so each of the other parameters should preferably be a simple variable, or 360 * at most an lvalue with no side-effects! 361 */ 362 #define gen6_for_each_pde(pt, pd, start, length, iter) \ 363 for (iter = gen6_pde_index(start); \ 364 length > 0 && iter < I915_PDES && \ 365 (pt = (pd)->page_table[iter], true); \ 366 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \ 367 temp = min(temp - start, length); \ 368 start += temp, length -= temp; }), ++iter) 369 370 #define gen6_for_all_pdes(pt, pd, iter) \ 371 for (iter = 0; \ 372 iter < I915_PDES && \ 373 (pt = (pd)->page_table[iter], true); \ 374 ++iter) 375 376 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 377 { 378 const uint32_t mask = NUM_PTE(pde_shift) - 1; 379 380 return (address >> PAGE_SHIFT) & mask; 381 } 382 383 /* Helper to counts the number of PTEs within the given length. This count 384 * does not cross a page table boundary, so the max value would be 385 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 386 */ 387 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 388 uint32_t pde_shift) 389 { 390 const uint64_t mask = ~((1ULL << pde_shift) - 1); 391 uint64_t end; 392 393 WARN_ON(length == 0); 394 WARN_ON(offset_in_page(addr|length)); 395 396 end = addr + length; 397 398 if ((addr & mask) != (end & mask)) 399 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 400 401 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 402 } 403 404 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 405 { 406 return (addr >> shift) & I915_PDE_MASK; 407 } 408 409 static inline uint32_t gen6_pte_index(uint32_t addr) 410 { 411 return i915_pte_index(addr, GEN6_PDE_SHIFT); 412 } 413 414 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 415 { 416 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 417 } 418 419 static inline uint32_t gen6_pde_index(uint32_t addr) 420 { 421 return i915_pde_index(addr, GEN6_PDE_SHIFT); 422 } 423 424 /* Equivalent to the gen6 version, For each pde iterates over every pde 425 * between from start until start + length. On gen8+ it simply iterates 426 * over every page directory entry in a page directory. 427 */ 428 #define gen8_for_each_pde(pt, pd, start, length, iter) \ 429 for (iter = gen8_pde_index(start); \ 430 length > 0 && iter < I915_PDES && \ 431 (pt = (pd)->page_table[iter], true); \ 432 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \ 433 temp = min(temp - start, length); \ 434 start += temp, length -= temp; }), ++iter) 435 436 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \ 437 for (iter = gen8_pdpe_index(start); \ 438 length > 0 && iter < I915_PDPES_PER_PDP(dev) && \ 439 (pd = (pdp)->page_directory[iter], true); \ 440 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \ 441 temp = min(temp - start, length); \ 442 start += temp, length -= temp; }), ++iter) 443 444 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \ 445 for (iter = gen8_pml4e_index(start); \ 446 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \ 447 (pdp = (pml4)->pdps[iter], true); \ 448 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \ 449 temp = min(temp - start, length); \ 450 start += temp, length -= temp; }), ++iter) 451 452 static inline uint32_t gen8_pte_index(uint64_t address) 453 { 454 return i915_pte_index(address, GEN8_PDE_SHIFT); 455 } 456 457 static inline uint32_t gen8_pde_index(uint64_t address) 458 { 459 return i915_pde_index(address, GEN8_PDE_SHIFT); 460 } 461 462 static inline uint32_t gen8_pdpe_index(uint64_t address) 463 { 464 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 465 } 466 467 static inline uint32_t gen8_pml4e_index(uint64_t address) 468 { 469 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK; 470 } 471 472 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 473 { 474 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 475 } 476 477 static inline dma_addr_t 478 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n) 479 { 480 return test_bit(n, ppgtt->pdp.used_pdpes) ? 481 px_dma(ppgtt->pdp.page_directory[n]) : 482 px_dma(ppgtt->base.scratch_pd); 483 } 484 485 static inline struct i915_ggtt * 486 i915_vm_to_ggtt(struct i915_address_space *vm) 487 { 488 GEM_BUG_ON(!i915_is_ggtt(vm)); 489 return container_of(vm, struct i915_ggtt, base); 490 } 491 492 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); 493 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); 494 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); 495 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv); 496 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv); 497 498 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv); 499 void i915_ppgtt_release(struct kref *kref); 500 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv, 501 struct drm_i915_file_private *fpriv, 502 const char *name); 503 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 504 { 505 if (ppgtt) 506 kref_get(&ppgtt->ref); 507 } 508 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 509 { 510 if (ppgtt) 511 kref_put(&ppgtt->ref, i915_ppgtt_release); 512 } 513 514 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv); 515 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv); 516 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv); 517 518 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, 519 struct sg_table *pages); 520 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, 521 struct sg_table *pages); 522 523 /* Flags used by pin/bind&friends. */ 524 #define PIN_NONBLOCK BIT(0) 525 #define PIN_MAPPABLE BIT(1) 526 #define PIN_ZONE_4G BIT(2) 527 #define PIN_NONFAULT BIT(3) 528 529 #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ 530 #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ 531 #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ 532 #define PIN_UPDATE BIT(8) 533 534 #define PIN_HIGH BIT(9) 535 #define PIN_OFFSET_BIAS BIT(10) 536 #define PIN_OFFSET_FIXED BIT(11) 537 #define PIN_OFFSET_MASK (~4095) 538 539 #endif 540