1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 #include <linux/seq_file.h> 38 39 struct drm_i915_file_private; 40 41 typedef uint32_t gen6_gtt_pte_t; 42 typedef uint64_t gen8_gtt_pte_t; 43 typedef gen8_gtt_pte_t gen8_ppgtt_pde_t; 44 45 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) 46 47 #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) 48 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 49 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 50 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 51 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 52 #define GEN6_PTE_CACHE_LLC (2 << 1) 53 #define GEN6_PTE_UNCACHED (1 << 1) 54 #define GEN6_PTE_VALID (1 << 0) 55 56 #define GEN6_PPGTT_PD_ENTRIES 512 57 #define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE) 58 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 59 #define GEN6_PDE_VALID (1 << 0) 60 61 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 62 63 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 64 #define BYT_PTE_WRITEABLE (1 << 1) 65 66 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 67 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 68 */ 69 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 70 (((bits) & 0x8) << (11 - 3))) 71 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 72 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 73 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 74 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 75 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 76 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 77 #define HSW_PTE_UNCACHED (0) 78 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 79 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 80 81 /* GEN8 legacy style address is defined as a 3 level page table: 82 * 31:30 | 29:21 | 20:12 | 11:0 83 * PDPE | PDE | PTE | offset 84 * The difference as compared to normal x86 3 level page table is the PDPEs are 85 * programmed via register. 86 */ 87 #define GEN8_PDPE_SHIFT 30 88 #define GEN8_PDPE_MASK 0x3 89 #define GEN8_PDE_SHIFT 21 90 #define GEN8_PDE_MASK 0x1ff 91 #define GEN8_PTE_SHIFT 12 92 #define GEN8_PTE_MASK 0x1ff 93 #define GEN8_LEGACY_PDPS 4 94 #define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t)) 95 #define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t)) 96 97 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 98 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 99 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 100 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 101 102 #define CHV_PPAT_SNOOP (1<<6) 103 #define GEN8_PPAT_AGE(x) (x<<4) 104 #define GEN8_PPAT_LLCeLLC (3<<2) 105 #define GEN8_PPAT_LLCELLC (2<<2) 106 #define GEN8_PPAT_LLC (1<<2) 107 #define GEN8_PPAT_WB (3<<0) 108 #define GEN8_PPAT_WT (2<<0) 109 #define GEN8_PPAT_WC (1<<0) 110 #define GEN8_PPAT_UC (0<<0) 111 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 112 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 113 114 enum i915_cache_level; 115 /** 116 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 117 * VMA's presence cannot be guaranteed before binding, or after unbinding the 118 * object into/from the address space. 119 * 120 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 121 * will always be <= an objects lifetime. So object refcounting should cover us. 122 */ 123 struct i915_vma { 124 struct drm_mm_node node; 125 struct drm_i915_gem_object *obj; 126 struct i915_address_space *vm; 127 128 /** This object's place on the active/inactive lists */ 129 struct list_head mm_list; 130 131 struct list_head vma_link; /* Link in the object's VMA list */ 132 133 /** This vma's place in the batchbuffer or on the eviction list */ 134 struct list_head exec_list; 135 136 /** 137 * Used for performing relocations during execbuffer insertion. 138 */ 139 struct hlist_node exec_node; 140 unsigned long exec_handle; 141 struct drm_i915_gem_exec_object2 *exec_entry; 142 143 /** 144 * How many users have pinned this object in GTT space. The following 145 * users can each hold at most one reference: pwrite/pread, pin_ioctl 146 * (via user_pin_count), execbuffer (objects are not allowed multiple 147 * times for the same batchbuffer), and the framebuffer code. When 148 * switching/pageflipping, the framebuffer code has at most two buffers 149 * pinned per crtc. 150 * 151 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 152 * bits with absolutely no headroom. So use 4 bits. */ 153 unsigned int pin_count:4; 154 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 155 156 /** Unmap an object from an address space. This usually consists of 157 * setting the valid PTE entries to a reserved scratch page. */ 158 void (*unbind_vma)(struct i915_vma *vma); 159 /* Map an object into an address space with the given cache flags. */ 160 #define GLOBAL_BIND (1<<0) 161 #define PTE_READ_ONLY (1<<1) 162 void (*bind_vma)(struct i915_vma *vma, 163 enum i915_cache_level cache_level, 164 u32 flags); 165 }; 166 167 struct i915_address_space { 168 struct drm_mm mm; 169 struct drm_device *dev; 170 struct list_head global_link; 171 unsigned long start; /* Start offset always 0 for dri2 */ 172 size_t total; /* size addr space maps (ex. 2GB for ggtt) */ 173 174 struct { 175 dma_addr_t addr; 176 struct vm_page *page; 177 } scratch; 178 179 /** 180 * List of objects currently involved in rendering. 181 * 182 * Includes buffers having the contents of their GPU caches 183 * flushed, not necessarily primitives. last_rendering_seqno 184 * represents when the rendering involved will be completed. 185 * 186 * A reference is held on the buffer while on this list. 187 */ 188 struct list_head active_list; 189 190 /** 191 * LRU list of objects which are not in the ringbuffer and 192 * are ready to unbind, but are still in the GTT. 193 * 194 * last_rendering_seqno is 0 while an object is in this list. 195 * 196 * A reference is not held on the buffer while on this list, 197 * as merely being GTT-bound shouldn't prevent its being 198 * freed, and we'll pull it off the list in the free path. 199 */ 200 struct list_head inactive_list; 201 202 /* FIXME: Need a more generic return type */ 203 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, 204 enum i915_cache_level level, 205 bool valid, u32 flags); /* Create a valid PTE */ 206 void (*clear_range)(struct i915_address_space *vm, 207 uint64_t start, 208 uint64_t length, 209 bool use_scratch); 210 void (*insert_entries)(struct i915_address_space *vm, 211 vm_page_t *pages, 212 uint64_t start, 213 unsigned int num_entries, 214 enum i915_cache_level cache_level, u32 flags); 215 void (*cleanup)(struct i915_address_space *vm); 216 }; 217 218 /* The Graphics Translation Table is the way in which GEN hardware translates a 219 * Graphics Virtual Address into a Physical Address. In addition to the normal 220 * collateral associated with any va->pa translations GEN hardware also has a 221 * portion of the GTT which can be mapped by the CPU and remain both coherent 222 * and correct (in cases like swizzling). That region is referred to as GMADR in 223 * the spec. 224 */ 225 struct i915_gtt { 226 struct i915_address_space base; 227 size_t stolen_size; /* Total size of stolen memory */ 228 229 unsigned long mappable_end; /* End offset that we can CPU map */ 230 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 231 phys_addr_t mappable_base; /* PA of our GMADR */ 232 233 /** "Graphics Stolen Memory" holds the global PTEs */ 234 void __iomem *gsm; 235 236 bool do_idle_maps; 237 238 int mtrr; 239 240 /* global gtt ops */ 241 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, 242 size_t *stolen, phys_addr_t *mappable_base, 243 unsigned long *mappable_end); 244 }; 245 246 struct i915_hw_ppgtt { 247 struct i915_address_space base; 248 struct kref ref; 249 struct drm_mm_node node; 250 unsigned num_pd_entries; 251 unsigned num_pd_pages; /* gen8+ */ 252 union { 253 struct vm_page **pt_pages; 254 struct vm_page **gen8_pt_pages[GEN8_LEGACY_PDPS]; 255 }; 256 struct vm_page *pd_pages; 257 union { 258 uint32_t pd_offset; 259 dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS]; 260 }; 261 union { 262 dma_addr_t *pt_dma_addr; 263 dma_addr_t *gen8_pt_dma_addr[4]; 264 }; 265 266 struct drm_i915_file_private *file_priv; 267 268 int (*enable)(struct i915_hw_ppgtt *ppgtt); 269 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 270 struct intel_engine_cs *ring); 271 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 272 }; 273 274 int i915_gem_gtt_init(struct drm_device *dev); 275 void i915_gem_init_global_gtt(struct drm_device *dev); 276 int i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, 277 unsigned long mappable_end, unsigned long end); 278 void i915_global_gtt_cleanup(struct drm_device *dev); 279 280 281 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); 282 int i915_ppgtt_init_hw(struct drm_device *dev); 283 void i915_ppgtt_release(struct kref *kref); 284 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, 285 struct drm_i915_file_private *fpriv); 286 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 287 { 288 if (ppgtt) 289 kref_get(&ppgtt->ref); 290 } 291 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 292 { 293 if (ppgtt) 294 kref_put(&ppgtt->ref, i915_ppgtt_release); 295 } 296 297 void i915_check_and_clear_faults(struct drm_device *dev); 298 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 299 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 300 301 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 302 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 303 304 #endif 305