1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Please try to maintain the following order within this file unless it makes 24 * sense to do otherwise. From top to bottom: 25 * 1. typedefs 26 * 2. #defines, and macros 27 * 3. structure definitions 28 * 4. function prototypes 29 * 30 * Within each section, please try to order by generation in ascending order, 31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom). 32 */ 33 34 #ifndef __I915_GEM_GTT_H__ 35 #define __I915_GEM_GTT_H__ 36 37 struct drm_i915_file_private; 38 39 typedef uint32_t gen6_pte_t; 40 typedef uint64_t gen8_pte_t; 41 typedef uint64_t gen8_pde_t; 42 43 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) 44 45 46 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */ 47 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) 48 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 49 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) 50 #define GEN6_PTE_CACHE_LLC (2 << 1) 51 #define GEN6_PTE_UNCACHED (1 << 1) 52 #define GEN6_PTE_VALID (1 << 0) 53 54 #define I915_PTES(pte_len) (PAGE_SIZE / (pte_len)) 55 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1) 56 #define I915_PDES 512 57 #define I915_PDE_MASK (I915_PDES - 1) 58 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT)) 59 60 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t)) 61 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE) 62 #define GEN6_PD_ALIGN (PAGE_SIZE * 16) 63 #define GEN6_PDE_SHIFT 22 64 #define GEN6_PDE_VALID (1 << 0) 65 66 #define GEN7_PTE_CACHE_L3_LLC (3 << 1) 67 68 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) 69 #define BYT_PTE_WRITEABLE (1 << 1) 70 71 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits 72 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. 73 */ 74 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ 75 (((bits) & 0x8) << (11 - 3))) 76 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2) 77 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) 78 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8) 79 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) 80 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7) 81 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6) 82 #define HSW_PTE_UNCACHED (0) 83 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) 84 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) 85 86 /* GEN8 legacy style address is defined as a 3 level page table: 87 * 31:30 | 29:21 | 20:12 | 11:0 88 * PDPE | PDE | PTE | offset 89 * The difference as compared to normal x86 3 level page table is the PDPEs are 90 * programmed via register. 91 */ 92 #define GEN8_PDPE_SHIFT 30 93 #define GEN8_PDPE_MASK 0x3 94 #define GEN8_PDE_SHIFT 21 95 #define GEN8_PDE_MASK 0x1ff 96 #define GEN8_PTE_SHIFT 12 97 #define GEN8_PTE_MASK 0x1ff 98 #define GEN8_LEGACY_PDPES 4 99 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t)) 100 101 #define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD) 102 #define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */ 103 #define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */ 104 #define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */ 105 106 #define CHV_PPAT_SNOOP (1<<6) 107 #define GEN8_PPAT_AGE(x) (x<<4) 108 #define GEN8_PPAT_LLCeLLC (3<<2) 109 #define GEN8_PPAT_LLCELLC (2<<2) 110 #define GEN8_PPAT_LLC (1<<2) 111 #define GEN8_PPAT_WB (3<<0) 112 #define GEN8_PPAT_WT (2<<0) 113 #define GEN8_PPAT_WC (1<<0) 114 #define GEN8_PPAT_UC (0<<0) 115 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) 116 #define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8)) 117 118 enum i915_ggtt_view_type { 119 I915_GGTT_VIEW_NORMAL = 0, 120 I915_GGTT_VIEW_ROTATED, 121 I915_GGTT_VIEW_PARTIAL, 122 }; 123 124 struct intel_rotation_info { 125 unsigned int height; 126 unsigned int pitch; 127 uint32_t pixel_format; 128 uint64_t fb_modifier; 129 }; 130 131 struct i915_ggtt_view { 132 enum i915_ggtt_view_type type; 133 134 union { 135 struct { 136 unsigned long offset; 137 unsigned int size; 138 } partial; 139 } params; 140 141 struct vm_page **pages; 142 143 union { 144 struct intel_rotation_info rotation_info; 145 }; 146 }; 147 148 extern const struct i915_ggtt_view i915_ggtt_view_normal; 149 extern const struct i915_ggtt_view i915_ggtt_view_rotated; 150 151 enum i915_cache_level; 152 153 /** 154 * A VMA represents a GEM BO that is bound into an address space. Therefore, a 155 * VMA's presence cannot be guaranteed before binding, or after unbinding the 156 * object into/from the address space. 157 * 158 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime 159 * will always be <= an objects lifetime. So object refcounting should cover us. 160 */ 161 struct i915_vma { 162 struct drm_mm_node node; 163 struct drm_i915_gem_object *obj; 164 struct i915_address_space *vm; 165 166 /** Flags and address space this VMA is bound to */ 167 #define GLOBAL_BIND (1<<0) 168 #define LOCAL_BIND (1<<1) 169 unsigned int bound : 4; 170 171 /** 172 * Support different GGTT views into the same object. 173 * This means there can be multiple VMA mappings per object and per VM. 174 * i915_ggtt_view_type is used to distinguish between those entries. 175 * The default one of zero (I915_GGTT_VIEW_NORMAL) is default and also 176 * assumed in GEM functions which take no ggtt view parameter. 177 */ 178 struct i915_ggtt_view ggtt_view; 179 180 /** This object's place on the active/inactive lists */ 181 struct list_head mm_list; 182 183 struct list_head vma_link; /* Link in the object's VMA list */ 184 185 /** This vma's place in the batchbuffer or on the eviction list */ 186 struct list_head exec_list; 187 188 /** 189 * Used for performing relocations during execbuffer insertion. 190 */ 191 struct hlist_node exec_node; 192 unsigned long exec_handle; 193 struct drm_i915_gem_exec_object2 *exec_entry; 194 195 /** 196 * How many users have pinned this object in GTT space. The following 197 * users can each hold at most one reference: pwrite/pread, execbuffer 198 * (objects are not allowed multiple times for the same batchbuffer), 199 * and the framebuffer code. When switching/pageflipping, the 200 * framebuffer code has at most two buffers pinned per crtc. 201 * 202 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 203 * bits with absolutely no headroom. So use 4 bits. */ 204 unsigned int pin_count:4; 205 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 206 }; 207 208 struct i915_page_table { 209 struct vm_page *page; 210 dma_addr_t daddr; 211 212 unsigned long *used_ptes; 213 }; 214 215 struct i915_page_directory { 216 struct vm_page *page; /* NULL for GEN6-GEN7 */ 217 union { 218 uint32_t pd_offset; 219 dma_addr_t daddr; 220 }; 221 222 unsigned long *used_pdes; 223 struct i915_page_table *page_table[I915_PDES]; /* PDEs */ 224 }; 225 226 struct i915_page_directory_pointer { 227 /* struct page *page; */ 228 DECLARE_BITMAP(used_pdpes, GEN8_LEGACY_PDPES); 229 struct i915_page_directory *page_directory[GEN8_LEGACY_PDPES]; 230 }; 231 232 struct i915_address_space { 233 struct drm_mm mm; 234 struct drm_device *dev; 235 struct list_head global_link; 236 unsigned long start; /* Start offset always 0 for dri2 */ 237 size_t total; /* size addr space maps (ex. 2GB for ggtt) */ 238 239 struct { 240 dma_addr_t addr; 241 struct vm_page *page; 242 } scratch; 243 244 /** 245 * List of objects currently involved in rendering. 246 * 247 * Includes buffers having the contents of their GPU caches 248 * flushed, not necessarily primitives. last_read_req 249 * represents when the rendering involved will be completed. 250 * 251 * A reference is held on the buffer while on this list. 252 */ 253 struct list_head active_list; 254 255 /** 256 * LRU list of objects which are not in the ringbuffer and 257 * are ready to unbind, but are still in the GTT. 258 * 259 * last_read_req is NULL while an object is in this list. 260 * 261 * A reference is not held on the buffer while on this list, 262 * as merely being GTT-bound shouldn't prevent its being 263 * freed, and we'll pull it off the list in the free path. 264 */ 265 struct list_head inactive_list; 266 267 /* FIXME: Need a more generic return type */ 268 gen6_pte_t (*pte_encode)(dma_addr_t addr, 269 enum i915_cache_level level, 270 bool valid, u32 flags); /* Create a valid PTE */ 271 /* flags for pte_encode */ 272 #define PTE_READ_ONLY (1<<0) 273 int (*allocate_va_range)(struct i915_address_space *vm, 274 uint64_t start, 275 uint64_t length); 276 void (*clear_range)(struct i915_address_space *vm, 277 uint64_t start, 278 uint64_t length, 279 bool use_scratch); 280 void (*insert_entries)(struct i915_address_space *vm, 281 vm_page_t *pages, 282 uint64_t start, 283 unsigned int num_entries, 284 enum i915_cache_level cache_level, u32 flags); 285 void (*cleanup)(struct i915_address_space *vm); 286 /** Unmap an object from an address space. This usually consists of 287 * setting the valid PTE entries to a reserved scratch page. */ 288 void (*unbind_vma)(struct i915_vma *vma); 289 /* Map an object into an address space with the given cache flags. */ 290 int (*bind_vma)(struct i915_vma *vma, 291 enum i915_cache_level cache_level, 292 u32 flags); 293 }; 294 295 /* The Graphics Translation Table is the way in which GEN hardware translates a 296 * Graphics Virtual Address into a Physical Address. In addition to the normal 297 * collateral associated with any va->pa translations GEN hardware also has a 298 * portion of the GTT which can be mapped by the CPU and remain both coherent 299 * and correct (in cases like swizzling). That region is referred to as GMADR in 300 * the spec. 301 */ 302 struct i915_gtt { 303 struct i915_address_space base; 304 size_t stolen_size; /* Total size of stolen memory */ 305 306 unsigned long mappable_end; /* End offset that we can CPU map */ 307 struct io_mapping *mappable; /* Mapping to our CPU mappable region */ 308 phys_addr_t mappable_base; /* PA of our GMADR */ 309 310 /** "Graphics Stolen Memory" holds the global PTEs */ 311 void __iomem *gsm; 312 313 bool do_idle_maps; 314 315 int mtrr; 316 317 /* global gtt ops */ 318 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, 319 size_t *stolen, phys_addr_t *mappable_base, 320 unsigned long *mappable_end); 321 }; 322 323 struct i915_hw_ppgtt { 324 struct i915_address_space base; 325 struct kref ref; 326 struct drm_mm_node node; 327 unsigned long pd_dirty_rings; 328 union { 329 struct i915_page_directory_pointer pdp; 330 struct i915_page_directory pd; 331 }; 332 333 struct i915_page_table *scratch_pt; 334 struct i915_page_directory *scratch_pd; 335 336 struct drm_i915_file_private *file_priv; 337 338 gen6_pte_t __iomem *pd_addr; 339 340 int (*enable)(struct i915_hw_ppgtt *ppgtt); 341 int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, 342 struct intel_engine_cs *ring); 343 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); 344 }; 345 346 /* For each pde iterates over every pde between from start until start + length. 347 * If start, and start+length are not perfectly divisible, the macro will round 348 * down, and up as needed. The macro modifies pde, start, and length. Dev is 349 * only used to differentiate shift values. Temp is temp. On gen6/7, start = 0, 350 * and length = 2G effectively iterates over every PDE in the system. 351 * 352 * XXX: temp is not actually needed, but it saves doing the ALIGN operation. 353 */ 354 #define gen6_for_each_pde(pt, pd, start, length, temp, iter) \ 355 for (iter = gen6_pde_index(start); \ 356 pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ 357 iter++, \ 358 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT) - start, \ 359 temp = min_t(unsigned, temp, length), \ 360 start += temp, length -= temp) 361 362 #define gen6_for_all_pdes(pt, ppgtt, iter) \ 363 for (iter = 0; \ 364 pt = ppgtt->pd.page_table[iter], iter < I915_PDES; \ 365 iter++) 366 367 static inline uint32_t i915_pte_index(uint64_t address, uint32_t pde_shift) 368 { 369 const uint32_t mask = NUM_PTE(pde_shift) - 1; 370 371 return (address >> PAGE_SHIFT) & mask; 372 } 373 374 /* Helper to counts the number of PTEs within the given length. This count 375 * does not cross a page table boundary, so the max value would be 376 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8. 377 */ 378 static inline uint32_t i915_pte_count(uint64_t addr, size_t length, 379 uint32_t pde_shift) 380 { 381 const uint64_t mask = ~((1 << pde_shift) - 1); 382 uint64_t end; 383 384 WARN_ON(length == 0); 385 WARN_ON(offset_in_page(addr|length)); 386 387 end = addr + length; 388 389 if ((addr & mask) != (end & mask)) 390 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift); 391 392 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift); 393 } 394 395 static inline uint32_t i915_pde_index(uint64_t addr, uint32_t shift) 396 { 397 return (addr >> shift) & I915_PDE_MASK; 398 } 399 400 static inline uint32_t gen6_pte_index(uint32_t addr) 401 { 402 return i915_pte_index(addr, GEN6_PDE_SHIFT); 403 } 404 405 static inline size_t gen6_pte_count(uint32_t addr, uint32_t length) 406 { 407 return i915_pte_count(addr, length, GEN6_PDE_SHIFT); 408 } 409 410 static inline uint32_t gen6_pde_index(uint32_t addr) 411 { 412 return i915_pde_index(addr, GEN6_PDE_SHIFT); 413 } 414 415 /* Equivalent to the gen6 version, For each pde iterates over every pde 416 * between from start until start + length. On gen8+ it simply iterates 417 * over every page directory entry in a page directory. 418 */ 419 #define gen8_for_each_pde(pt, pd, start, length, temp, iter) \ 420 for (iter = gen8_pde_index(start); \ 421 pt = (pd)->page_table[iter], length > 0 && iter < I915_PDES; \ 422 iter++, \ 423 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT) - start, \ 424 temp = min(temp, length), \ 425 start += temp, length -= temp) 426 427 #define gen8_for_each_pdpe(pd, pdp, start, length, temp, iter) \ 428 for (iter = gen8_pdpe_index(start); \ 429 pd = (pdp)->page_directory[iter], length > 0 && iter < GEN8_LEGACY_PDPES; \ 430 iter++, \ 431 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT) - start, \ 432 temp = min(temp, length), \ 433 start += temp, length -= temp) 434 435 /* Clamp length to the next page_directory boundary */ 436 static inline uint64_t gen8_clamp_pd(uint64_t start, uint64_t length) 437 { 438 uint64_t next_pd = ALIGN(start + 1, 1 << GEN8_PDPE_SHIFT); 439 440 if (next_pd > (start + length)) 441 return length; 442 443 return next_pd - start; 444 } 445 446 static inline uint32_t gen8_pte_index(uint64_t address) 447 { 448 return i915_pte_index(address, GEN8_PDE_SHIFT); 449 } 450 451 static inline uint32_t gen8_pde_index(uint64_t address) 452 { 453 return i915_pde_index(address, GEN8_PDE_SHIFT); 454 } 455 456 static inline uint32_t gen8_pdpe_index(uint64_t address) 457 { 458 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK; 459 } 460 461 static inline uint32_t gen8_pml4e_index(uint64_t address) 462 { 463 WARN_ON(1); /* For 64B */ 464 return 0; 465 } 466 467 static inline size_t gen8_pte_count(uint64_t address, uint64_t length) 468 { 469 return i915_pte_count(address, length, GEN8_PDE_SHIFT); 470 } 471 472 int i915_gem_gtt_init(struct drm_device *dev); 473 void i915_gem_init_global_gtt(struct drm_device *dev); 474 void i915_global_gtt_cleanup(struct drm_device *dev); 475 476 477 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); 478 int i915_ppgtt_init_hw(struct drm_device *dev); 479 void i915_ppgtt_release(struct kref *kref); 480 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_device *dev, 481 struct drm_i915_file_private *fpriv); 482 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt) 483 { 484 if (ppgtt) 485 kref_get(&ppgtt->ref); 486 } 487 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt) 488 { 489 if (ppgtt) 490 kref_put(&ppgtt->ref, i915_ppgtt_release); 491 } 492 493 void i915_check_and_clear_faults(struct drm_device *dev); 494 void i915_gem_suspend_gtt_mappings(struct drm_device *dev); 495 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 496 497 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); 498 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); 499 500 static inline bool 501 i915_ggtt_view_equal(const struct i915_ggtt_view *a, 502 const struct i915_ggtt_view *b) 503 { 504 if (WARN_ON(!a || !b)) 505 return false; 506 507 if (a->type != b->type) 508 return false; 509 if (a->type == I915_GGTT_VIEW_PARTIAL) 510 return !memcmp(&a->params, &b->params, sizeof(a->params)); 511 return true; 512 } 513 514 size_t 515 i915_ggtt_view_size(struct drm_i915_gem_object *obj, 516 const struct i915_ggtt_view *view); 517 518 #endif 519